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author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2015-08-05 17:04:01 -0300 |
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committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2015-08-05 17:04:01 -0300 |
commit | 57f0f512b273f60d52568b8c6b77e17f5636edc0 (patch) | |
tree | 5e910f0e82173f4ef4f51111366a3f1299037a7b /arch/arm/mach-orion5x/include/mach/bridge-regs.h |
Initial import
Diffstat (limited to 'arch/arm/mach-orion5x/include/mach/bridge-regs.h')
-rw-r--r-- | arch/arm/mach-orion5x/include/mach/bridge-regs.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h new file mode 100644 index 000000000..5766e3fbf --- /dev/null +++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-orion5x/include/mach/bridge-regs.h + * + * Orion CPU Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include <mach/orion5x.h> + +#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) + +#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) + +#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) +#define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) + +#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) + +#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) + +#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) + +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) + +#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) + +#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) +#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) +#endif |