diff options
| author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-09-11 04:34:46 -0300 |
|---|---|---|
| committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-09-11 04:34:46 -0300 |
| commit | 863981e96738983919de841ec669e157e6bdaeb0 (patch) | |
| tree | d6d89a12e7eb8017837c057935a2271290907f76 /arch/mips/boot/dts | |
| parent | 8dec7c70575785729a6a9e6719a955e9c545bcab (diff) | |
Linux-libre 4.7.1-gnupck-4.7.1-gnu
Diffstat (limited to 'arch/mips/boot/dts')
41 files changed, 1805 insertions, 586 deletions
diff --git a/arch/mips/boot/dts/brcm/Makefile b/arch/mips/boot/dts/brcm/Makefile index eabeb603e..fda9d387c 100644 --- a/arch/mips/boot/dts/brcm/Makefile +++ b/arch/mips/boot/dts/brcm/Makefile @@ -1,5 +1,6 @@ dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb +dtb-$(CONFIG_DT_BCM96358NB4SER) += bcm96358nb4ser.dtb dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb @@ -14,6 +15,7 @@ dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb dtb-$(CONFIG_DT_NONE) += \ bcm93384wvg.dtb \ bcm93384wvg_viper.dtb \ + bcm96358nb4ser.dtb \ bcm96368mvwg.dtb \ bcm9ejtagprb.dtb \ bcm97125cbmb.dtb \ diff --git a/arch/mips/boot/dts/brcm/bcm6328.dtsi b/arch/mips/boot/dts/brcm/bcm6328.dtsi index 9d19236f5..5633b9d90 100644 --- a/arch/mips/boot/dts/brcm/bcm6328.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi @@ -23,7 +23,7 @@ }; clocks { - periph_clk: periph_clk { + periph_clk: periph-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; @@ -31,11 +31,11 @@ }; aliases { - leds0 = &leds0; - uart0 = &uart0; + serial0 = &uart0; + serial1 = &uart1; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -50,16 +50,16 @@ compatible = "simple-bus"; ranges; - periph_intc: periph_intc@10000020 { - compatible = "brcm,bcm3380-l2-intc"; - reg = <0x10000024 0x4 0x1000002c 0x4>, - <0x10000020 0x4 0x10000028 0x4>; + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&cpu_intc>; - interrupts = <2>; + interrupts = <2>, <3>; }; uart0: serial@10000100 { @@ -71,13 +71,22 @@ status = "disabled"; }; - timer: timer@10000040 { + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + interrupt-parent = <&periph_intc>; + interrupts = <39>; + clocks = <&periph_clk>; + status = "disabled"; + }; + + timer: syscon@10000040 { compatible = "syscon"; reg = <0x10000040 0x2c>; native-endian; }; - reboot { + reboot: syscon-reboot@10000068 { compatible = "syscon-reboot"; regmap = <&timer>; offset = <0x28>; @@ -91,5 +100,24 @@ reg = <0x10000800 0x24>; status = "disabled"; }; + + ehci: usb@10002500 { + compatible = "brcm,bcm6328-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + big-endian; + interrupt-parent = <&periph_intc>; + interrupts = <42>; + status = "disabled"; + }; + + ohci: usb@10002600 { + compatible = "brcm,bcm6328-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + big-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <41>; + status = "disabled"; + }; }; }; diff --git a/arch/mips/boot/dts/brcm/bcm6358.dtsi b/arch/mips/boot/dts/brcm/bcm6358.dtsi new file mode 100644 index 000000000..f9d8d3921 --- /dev/null +++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi @@ -0,0 +1,130 @@ +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "brcm,bcm6358"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + mips-hpt-frequency = <150000000>; + + cpu@0 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "brcm,bmips4350"; + device_type = "cpu"; + reg = <1>; + }; + }; + + clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpu_intc: interrupt-controller { + #address-cells = <0>; + compatible = "mti,cpu-interrupt-controller"; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + ubus { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "simple-bus"; + ranges; + + periph_cntl: syscon@fffe0000 { + compatible = "syscon"; + reg = <0xfffe0000 0xc>; + native-endian; + }; + + reboot: syscon-reboot@fffe0008 { + compatible = "syscon-reboot"; + regmap = <&periph_cntl>; + offset = <0x8>; + mask = <0x1>; + }; + + periph_intc: interrupt-controller@fffe000c { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0xfffe000c 0x8>, + <0xfffe0038 0x8>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpu_intc>; + interrupts = <2>, <3>; + }; + + leds0: led-controller@fffe00d0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6358-leds"; + reg = <0xfffe00d0 0x8>; + + status = "disabled"; + }; + + uart0: serial@fffe0100 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0100 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <2>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + uart1: serial@fffe0120 { + compatible = "brcm,bcm6345-uart"; + reg = <0xfffe0120 0x18>; + + interrupt-parent = <&periph_intc>; + interrupts = <3>; + + clocks = <&periph_clk>; + + status = "disabled"; + }; + + ehci: usb@fffe1300 { + compatible = "brcm,bcm6358-ehci", "generic-ehci"; + reg = <0xfffe1300 0x100>; + big-endian; + interrupt-parent = <&periph_intc>; + interrupts = <10>; + status = "disabled"; + }; + + ohci: usb@fffe1400 { + compatible = "brcm,bcm6358-ohci", "generic-ohci"; + reg = <0xfffe1400 0x100>; + big-endian; + no-big-frame-no; + interrupt-parent = <&periph_intc>; + interrupts = <5>; + status = "disabled"; + }; + }; +}; diff --git a/arch/mips/boot/dts/brcm/bcm6368.dtsi b/arch/mips/boot/dts/brcm/bcm6368.dtsi index 1f6b9b5cd..d0e3a70b3 100644 --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi @@ -20,11 +20,10 @@ device_type = "cpu"; reg = <1>; }; - }; clocks { - periph_clk: periph_clk { + periph_clk: periph-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; @@ -32,11 +31,11 @@ }; aliases { - leds0 = &leds0; - uart0 = &uart0; + serial0 = &uart0; + serial1 = &uart1; }; - cpu_intc: cpu_intc { + cpu_intc: interrupt-controller { #address-cells = <0>; compatible = "mti,cpu-interrupt-controller"; @@ -64,16 +63,16 @@ mask = <0x1>; }; - periph_intc: periph_intc@10000020 { - compatible = "brcm,bcm3380-l2-intc"; - reg = <0x10000024 0x4 0x1000002c 0x4>, - <0x10000020 0x4 0x10000028 0x4>; + periph_intc: interrupt-controller@10000020 { + compatible = "brcm,bcm6345-l1-intc"; + reg = <0x10000020 0x10>, + <0x10000030 0x10>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&cpu_intc>; - interrupts = <2>; + interrupts = <2>, <3>; }; leds0: led-controller@100000d0 { @@ -93,7 +92,16 @@ status = "disabled"; }; - ehci0: usb@10001500 { + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + interrupt-parent = <&periph_intc>; + interrupts = <3>; + clocks = <&periph_clk>; + status = "disabled"; + }; + + ehci: usb@10001500 { compatible = "brcm,bcm6368-ehci", "generic-ehci"; reg = <0x10001500 0x100>; big-endian; @@ -102,7 +110,7 @@ status = "disabled"; }; - ohci0: usb@10001600 { + ohci: usb@10001600 { compatible = "brcm,bcm6368-ohci", "generic-ohci"; reg = <0x10001600 0x100>; big-endian; diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi index 3ae16053a..550e1d9e3 100644 --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi @@ -85,14 +85,15 @@ compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; - brcm,int-map-mask = <0x44>; + brcm,int-map-mask = <0x44>, <0xf000000>; brcm,int-fwd-mask = <0x70000>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&periph_intc>; - interrupts = <18>; + interrupts = <18>, <19>; + interrupt-names = "upg_main", "upg_bsc"; }; sun_top_ctrl: syscon@404000 { @@ -118,6 +119,70 @@ status = "disabled"; }; + uart1: serial@406b40 { + compatible = "ns16550a"; + reg = <0x406b40 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <64>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406b80 { + compatible = "ns16550a"; + reg = <0x406b80 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + native-endian; + interrupt-parent = <&periph_intc>; + interrupts = <65>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + bsca: i2c@406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406200 0x58>; + interrupts = <24>; + interrupt-names = "upg_bsca"; + status = "disabled"; + }; + + bscb: i2c@406280 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406280 0x58>; + interrupts = <25>; + interrupt-names = "upg_bscb"; + status = "disabled"; + }; + + bscc: i2c@406300 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406300 0x58>; + interrupts = <26>; + interrupt-names = "upg_bscc"; + status = "disabled"; + }; + + bscd: i2c@406380 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406380 0x58>; + interrupts = <27>; + interrupt-names = "upg_bscd"; + status = "disabled"; + }; + ehci0: usb@488300 { compatible = "brcm,bcm7125-ehci", "generic-ehci"; reg = <0x488300 0x100>; diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi index be7991917..ec959061d 100644 --- a/arch/mips/boot/dts/brcm/bcm7346.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi @@ -24,8 +24,6 @@ aliases { uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -323,8 +321,6 @@ interrupts = <40>; #address-cells = <1>; #size-cells = <0>; - brcm,broken-ncq; - brcm,broken-phy; status = "disabled"; sata0: sata-port@0 { @@ -338,7 +334,7 @@ }; }; - sata_phy: sata-phy@1800000 { + sata_phy: sata-phy@180100 { compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; reg = <0x180100 0x0eff>; reg-names = "phy"; diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi index 060805be6..ca57fb5eb 100644 --- a/arch/mips/boot/dts/brcm/bcm7358.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi @@ -18,8 +18,6 @@ aliases { uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; }; cpu_intc: cpu_intc { diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi index bcdb09bfe..1c0c3d438 100644 --- a/arch/mips/boot/dts/brcm/bcm7360.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi @@ -18,8 +18,6 @@ aliases { uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -241,5 +239,45 @@ interrupts = <66>; status = "disabled"; }; + + sata: sata@181000 { + compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x181000 0xa9c>, <0x180020 0x1c>; + interrupt-parent = <&periph_intc>; + interrupts = <86>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + }; + }; + + sata_phy: sata-phy@180100 { + compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; + reg = <0x180100 0x0eff>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; }; }; diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi index d3b1b762e..6b4713add 100644 --- a/arch/mips/boot/dts/brcm/bcm7362.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi @@ -24,8 +24,6 @@ aliases { uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; }; cpu_intc: cpu_intc { @@ -246,8 +244,6 @@ interrupts = <86>; #address-cells = <1>; #size-cells = <0>; - brcm,broken-ncq; - brcm,broken-phy; status = "disabled"; sata0: sata-port@0 { @@ -261,7 +257,7 @@ }; }; - sata_phy: sata-phy@1800000 { + sata_phy: sata-phy@180100 { compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; reg = <0x180100 0x0eff>; reg-names = "phy"; diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi index 3302a1b8a..0586bf662 100644 --- a/arch/mips/boot/dts/brcm/bcm7420.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi @@ -86,14 +86,15 @@ compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; - brcm,int-map-mask = <0x44>; + brcm,int-map-mask = <0x44>, <0x1f000000>; brcm,int-fwd-mask = <0x70000>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&periph_intc>; - interrupts = <18>; + interrupts = <18>, <19>; + interrupt-names = "upg_main", "upg_bsc"; }; sun_top_ctrl: syscon@404000 { @@ -118,6 +119,78 @@ status = "disabled"; }; + uart1: serial@406b40 { + compatible = "ns16550a"; + reg = <0x406b40 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <64>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406b80 { + compatible = "ns16550a"; + reg = <0x406b80 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <65>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + bsca: i2c@406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406200 0x58>; + interrupts = <24>; + interrupt-names = "upg_bsca"; + status = "disabled"; + }; + + bscb: i2c@406280 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406280 0x58>; + interrupts = <25>; + interrupt-names = "upg_bscb"; + status = "disabled"; + }; + + bscc: i2c@406300 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406300 0x58>; + interrupts = <26>; + interrupt-names = "upg_bscc"; + status = "disabled"; + }; + + bscd: i2c@406380 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406380 0x58>; + interrupts = <27>; + interrupt-names = "upg_bscd"; + status = "disabled"; + }; + + bsce: i2c@406800 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406800 0x58>; + interrupts = <28>; + interrupt-names = "upg_bsce"; + status = "disabled"; + }; + enet0: ethernet@468000 { phy-mode = "internal"; phy-handle = <&phy1>; diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi index 15b27aae1..c1c15edaf 100644 --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi @@ -87,14 +87,32 @@ compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; - brcm,int-map-mask = <0x44>; + brcm,int-map-mask = <0x44>, <0x7000000>; brcm,int-fwd-mask = <0x70000>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&periph_intc>; - interrupts = <55>; + interrupts = <55>, <53>; + interrupt-names = "upg_main", "upg_bsc"; + }; + + upg_aon_irq0_intc: upg_aon_irq0_intc@409480 { + compatible = "brcm,bcm7120-l2-intc"; + reg = <0x409480 0x8>; + + brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>; + brcm,int-fwd-mask = <0>; + brcm,irq-can-wake; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&periph_intc>; + interrupts = <56>, <54>, <59>; + interrupt-names = "upg_main_aon", "upg_bsc_aon", + "upg_spi"; }; sun_top_ctrl: syscon@404000 { @@ -119,6 +137,78 @@ status = "disabled"; }; + uart1: serial@406b40 { + compatible = "ns16550a"; + reg = <0x406b40 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <62>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406b80 { + compatible = "ns16550a"; + reg = <0x406b80 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <63>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + bsca: i2c@409180 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_aon_irq0_intc>; + reg = <0x409180 0x58>; + interrupts = <27>; + interrupt-names = "upg_bsca"; + status = "disabled"; + }; + + bscb: i2c@409400 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_aon_irq0_intc>; + reg = <0x409400 0x58>; + interrupts = <28>; + interrupt-names = "upg_bscb"; + status = "disabled"; + }; + + bscc: i2c@406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406200 0x58>; + interrupts = <24>; + interrupt-names = "upg_bscc"; + status = "disabled"; + }; + + bscd: i2c@406280 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406280 0x58>; + interrupts = <25>; + interrupt-names = "upg_bscd"; + status = "disabled"; + }; + + bsce: i2c@406300 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406300 0x58>; + interrupts = <26>; + interrupt-names = "upg_bsce"; + status = "disabled"; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -227,11 +317,9 @@ reg-names = "ahci", "top-ctrl"; reg = <0x181000 0xa9c>, <0x180020 0x1c>; interrupt-parent = <&periph_intc>; - interrupts = <40>; + interrupts = <41>; #address-cells = <1>; #size-cells = <0>; - brcm,broken-ncq; - brcm,broken-phy; status = "disabled"; sata0: sata-port@0 { @@ -245,7 +333,7 @@ }; }; - sata_phy: sata-phy@1800000 { + sata_phy: sata-phy@180100 { compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; reg = <0x180100 0x0eff>; reg-names = "phy"; diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi index 56035e5b7..a874d3a0e 100644 --- a/arch/mips/boot/dts/brcm/bcm7435.dtsi +++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi @@ -7,7 +7,7 @@ #address-cells = <1>; #size-cells = <0>; - mips-hpt-frequency = <163125000>; + mips-hpt-frequency = <175625000>; cpu@0 { compatible = "brcm,bmips5200"; @@ -63,13 +63,14 @@ periph_intc: periph_intc@41b500 { compatible = "brcm,bcm7038-l1-intc"; - reg = <0x41b500 0x40>, <0x41b600 0x40>; + reg = <0x41b500 0x40>, <0x41b600 0x40>, + <0x41b700 0x40>, <0x41b800 0x40>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&cpu_intc>; - interrupts = <2>, <3>; + interrupts = <2>, <3>, <2>, <3>; }; sun_l2_intc: sun_l2_intc@403000 { @@ -101,14 +102,32 @@ compatible = "brcm,bcm7120-l2-intc"; reg = <0x406780 0x8>; - brcm,int-map-mask = <0x44>; + brcm,int-map-mask = <0x44>, <0x7000000>; brcm,int-fwd-mask = <0x70000>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&periph_intc>; - interrupts = <60>; + interrupts = <60>, <58>; + interrupt-names = "upg_main", "upg_bsc"; + }; + + upg_aon_irq0_intc: upg_aon_irq0_intc@409480 { + compatible = "brcm,bcm7120-l2-intc"; + reg = <0x409480 0x8>; + + brcm,int-map-mask = <0x40>, <0x18000000>, <0x100000>; + brcm,int-fwd-mask = <0>; + brcm,irq-can-wake; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&periph_intc>; + interrupts = <61>, <59>, <64>; + interrupt-names = "upg_main_aon", "upg_bsc_aon", + "upg_spi"; }; sun_top_ctrl: syscon@404000 { @@ -133,6 +152,78 @@ status = "disabled"; }; + uart1: serial@406b40 { + compatible = "ns16550a"; + reg = <0x406b40 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <67>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@406b80 { + compatible = "ns16550a"; + reg = <0x406b80 0x20>; + reg-io-width = <0x4>; + reg-shift = <0x2>; + interrupt-parent = <&periph_intc>; + interrupts = <68>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + bsca: i2c@406300 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406300 0x58>; + interrupts = <26>; + interrupt-names = "upg_bsca"; + status = "disabled"; + }; + + bscb: i2c@409400 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_aon_irq0_intc>; + reg = <0x409400 0x58>; + interrupts = <28>; + interrupt-names = "upg_bscb"; + status = "disabled"; + }; + + bscc: i2c@406200 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406200 0x58>; + interrupts = <24>; + interrupt-names = "upg_bscc"; + status = "disabled"; + }; + + bscd: i2c@406280 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_irq0_intc>; + reg = <0x406280 0x58>; + interrupts = <25>; + interrupt-names = "upg_bscd"; + status = "disabled"; + }; + + bsce: i2c@409180 { + clock-frequency = <390000>; + compatible = "brcm,brcmstb-i2c"; + interrupt-parent = <&upg_aon_irq0_intc>; + reg = <0x409180 0x58>; + interrupts = <27>; + interrupt-names = "upg_bsce"; + status = "disabled"; + }; + enet0: ethernet@b80000 { phy-mode = "internal"; phy-handle = <&phy1>; @@ -235,5 +326,45 @@ interrupts = <78>; status = "disabled"; }; + + sata: sata@181000 { + compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; + reg-names = "ahci", "top-ctrl"; + reg = <0x181000 0xa9c>, <0x180020 0x1c>; + interrupt-parent = <&periph_intc>; + interrupts = <45>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy0>; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy1>; + }; + }; + + sata_phy: sata-phy@180100 { + compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; + reg = <0x180100 0x0eff>; + reg-names = "phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata_phy0: sata-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + sata_phy1: sata-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; }; }; diff --git a/arch/mips/boot/dts/brcm/bcm96358nb4ser.dts b/arch/mips/boot/dts/brcm/bcm96358nb4ser.dts new file mode 100644 index 000000000..f41211797 --- /dev/null +++ b/arch/mips/boot/dts/brcm/bcm96358nb4ser.dts @@ -0,0 +1,46 @@ +/dts-v1/; + +/include/ "bcm6358.dtsi" + +/ { + compatible = "sfr,nb4-ser", "brcm,bcm6358"; + model = "SFR Neufbox 4 (Sercomm)"; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&leds0 { + status = "ok"; + + led@0 { + reg = <0>; + active-low; + label = "nb4-ser:white:alarm"; + }; + led@2 { + reg = <2>; + active-low; + label = "nb4-ser:white:tv"; + }; + led@3 { + reg = <3>; + active-low; + label = "nb4-ser:white:tel"; + }; + led@4 { + reg = <4>; + active-low; + label = "nb4-ser:white:adsl"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/mips/boot/dts/brcm/bcm96368mvwg.dts b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts index 0e890c28f..8c71c6845 100644 --- a/arch/mips/boot/dts/brcm/bcm96368mvwg.dts +++ b/arch/mips/boot/dts/brcm/bcm96368mvwg.dts @@ -22,10 +22,10 @@ }; /* FIXME: need to set up USB_CTRL registers first */ -&ehci0 { +&ehci { status = "disabled"; }; -&ohci0 { +&ohci { status = "disabled"; }; diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts index e046b1109..f2449d147 100644 --- a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts @@ -21,6 +21,30 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&bsca { + status = "okay"; +}; + +&bscb { + status = "okay"; +}; + +&bscc { + status = "okay"; +}; + +&bscd { + status = "okay"; +}; + /* FIXME: USB is wonky; disable it for now */ &ehci0 { status = "disabled"; diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts index d48462e09..73124be95 100644 --- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts @@ -56,3 +56,11 @@ &ohci0 { status = "okay"; }; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts index 67fe1f3a3..600d57abe 100644 --- a/arch/mips/boot/dts/brcm/bcm97420c.dts +++ b/arch/mips/boot/dts/brcm/bcm97420c.dts @@ -23,6 +23,34 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&bsca { + status = "okay"; +}; + +&bscb { + status = "okay"; +}; + +&bscc { + status = "okay"; +}; + +&bscd { + status = "okay"; +}; + +&bsce { + status = "okay"; +}; + /* FIXME: MAC driver comes up but cannot attach to PHY */ &enet0 { status = "disabled"; diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts index 689c68a4f..119c71480 100644 --- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts @@ -23,6 +23,34 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&bsca { + status = "okay"; +}; + +&bscb { + status = "okay"; +}; + +&bscc { + status = "okay"; +}; + +&bscd { + status = "okay"; +}; + +&bsce { + status = "okay"; +}; + &enet0 { status = "okay"; }; diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts index 1df088183..43e3ba27f 100644 --- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts +++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts @@ -14,7 +14,7 @@ }; chosen { - bootargs = "console=ttyS0,115200 maxcpus=1"; + bootargs = "console=ttyS0,115200"; stdout-path = &uart0; }; }; @@ -23,6 +23,34 @@ status = "okay"; }; +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&bsca { + status = "okay"; +}; + +&bscb { + status = "okay"; +}; + +&bscc { + status = "okay"; +}; + +&bscd { + status = "okay"; +}; + +&bsce { + status = "okay"; +}; + &enet0 { status = "okay"; }; @@ -58,3 +86,11 @@ &ohci3 { status = "okay"; }; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; diff --git a/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts new file mode 100644 index 000000000..d6bc994f7 --- /dev/null +++ b/arch/mips/boot/dts/cavium-octeon/dlink_dsr-1000n.dts @@ -0,0 +1,78 @@ +/* + * Device tree source for D-Link DSR-1000N. + * + * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "octeon_3xxx.dtsi" + +/ { + model = "dlink,dsr-1000n"; + + soc@0 { + smi0: mdio@1180000001800 { + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + pip: pip@11800a0000000 { + interface@0 { + ethernet@0 { + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + ethernet@1 { + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + ethernet@2 { + phy-handle = <&phy8>; + }; + }; + }; + + twsi0: i2c@1180000001000 { + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; + }; + + uart0: serial@1180000000800 { + clock-frequency = <500000000>; + }; + + usbn: usbn@1180068000000 { + refclk-frequency = <12000000>; + refclk-type = "crystal"; + }; + }; + + leds { + compatible = "gpio-leds"; + + usb1 { + label = "usb1"; + gpios = <&gpio 9 1>; /* Active low */ + }; + + usb2 { + label = "usb2"; + gpios = <&gpio 10 1>; /* Active low */ + }; + }; + + aliases { + pip = &pip; + }; +}; diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts index 9c48e0586..de61f02d3 100644 --- a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts +++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dts @@ -1,4 +1,3 @@ -/dts-v1/; /* * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. * @@ -6,56 +5,12 @@ * use. Because of this, it contains a super-set of the available * devices and properties. */ -/ { - compatible = "cavium,octeon-3860"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&ciu>; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; /* Direct mapping */ - - ciu: interrupt-controller@1070000000000 { - compatible = "cavium,octeon-3860-ciu"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 1) - * 2) Bit within the register (0..63) - */ - #interrupt-cells = <2>; - reg = <0x10700 0x00000000 0x0 0x7000>; - }; - gpio: gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pin connect to 16 consecutive CUI bits */ - interrupts = <0 16>, <0 17>, <0 18>, <0 19>, - <0 20>, <0 21>, <0 22>, <0 23>, - <0 24>, <0 25>, <0 26>, <0 27>, - <0 28>, <0 29>, <0 30>, <0 31>; - }; +/include/ "octeon_3xxx.dtsi" +/ { + soc@0 { smi0: mdio@1180000001800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001800 0x0 0x40>; - phy0: ethernet-phy@0 { compatible = "marvell,88e1118"; marvell,reg-init = @@ -220,35 +175,16 @@ }; pip: pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* interface */ - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; phy-handle = <&phy2>; cavium,alt-phy-handle = <&phy100>; }; ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; phy-handle = <&phy3>; cavium,alt-phy-handle = <&phy101>; }; ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; phy-handle = <&phy4>; cavium,alt-phy-handle = <&phy102>; }; @@ -322,11 +258,6 @@ }; interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* interface */ - ethernet@0 { compatible = "cavium,octeon-3860-pip-port"; reg = <0x0>; /* Port */ @@ -355,13 +286,6 @@ }; twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <0 45>; - clock-frequency = <100000>; - rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; @@ -381,15 +305,6 @@ clock-frequency = <100000>; }; - uart0: serial@1180000000800 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000800 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <0 34>; - }; - uart1: serial@1180000000c00 { compatible = "cavium,octeon-3860-uart","ns16550"; reg = <0x11800 0x00000c00 0x0 0x400>; @@ -409,98 +324,6 @@ }; bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0x0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0x0 0x1d020000 0x10000>, - <5 0 0x0 0x1d040000 0x10000>, - <6 0 0x0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <20>; - cavium,t-ce = <60>; - cavium,t-oe = <60>; - cavium,t-we = <45>; - cavium,t-rd-hld = <35>; - cavium,t-wr-hld = <45>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <35>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@4 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <4>; - cavium,t-adr = <320>; - cavium,t-ce = <320>; - cavium,t-oe = <320>; - cavium,t-we = <320>; - cavium,t-rd-hld = <320>; - cavium,t-wr-hld = <320>; - cavium,t-pause = <320>; - cavium,t-wait = <320>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@5 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <5>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <30>; - cavium,t-pause = <0>; - cavium,t-wait = <30>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <16>; - }; - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <270>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <70>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - - flash0: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - }; - led0: led-display@4,0 { compatible = "avago,hdsp-253x"; reg = <4 0x20 0x20>, <4 0 0x20>; @@ -515,17 +338,6 @@ }; }; - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; - dma1: dma-engine@1180000000108 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000108 0x0 0x8>; - interrupts = <0 63>; - }; - uctl: uctl@118006f000000 { compatible = "cavium,octeon-6335-uctl"; reg = <0x11800 0x6f000000 0x0 0x100>; @@ -552,21 +364,10 @@ }; usbn: usbn@1180068000000 { - compatible = "cavium,octeon-5750-usbn"; - reg = <0x11800 0x68000000 0x0 0x1000>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; /* 12MHz, 24MHz and 48MHz allowed */ refclk-frequency = <12000000>; /* Either "crystal" or "external" */ refclk-type = "crystal"; - - usbc@16f0010000000 { - compatible = "cavium,octeon-5750-usbc"; - reg = <0x16f00 0x10000000 0x0 0x80000>; - interrupts = <0 56>; - }; }; }; diff --git a/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi new file mode 100644 index 000000000..5302148e0 --- /dev/null +++ b/arch/mips/boot/dts/cavium-octeon/octeon_3xxx.dtsi @@ -0,0 +1,231 @@ +/* OCTEON 3XXX DTS common parts. */ + +/dts-v1/; + +/ { + compatible = "cavium,octeon-3860"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&ciu>; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; /* Direct mapping */ + + ciu: interrupt-controller@1070000000000 { + compatible = "cavium,octeon-3860-ciu"; + interrupt-controller; + /* Interrupts are specified by two parts: + * 1) Controller register (0 or 1) + * 2) Bit within the register (0..63) + */ + #interrupt-cells = <2>; + reg = <0x10700 0x00000000 0x0 0x7000>; + }; + + gpio: gpio-controller@1070000000800 { + #gpio-cells = <2>; + compatible = "cavium,octeon-3860-gpio"; + reg = <0x10700 0x00000800 0x0 0x100>; + gpio-controller; + /* Interrupts are specified by two parts: + * 1) GPIO pin number (0..15) + * 2) Triggering (1 - edge rising + * 2 - edge falling + * 4 - level active high + * 8 - level active low) + */ + interrupt-controller; + #interrupt-cells = <2>; + /* The GPIO pin connect to 16 consecutive CUI bits */ + interrupts = <0 16>, <0 17>, <0 18>, <0 19>, + <0 20>, <0 21>, <0 22>, <0 23>, + <0 24>, <0 25>, <0 26>, <0 27>, + <0 28>, <0 29>, <0 30>, <0 31>; + }; + + smi0: mdio@1180000001800 { + compatible = "cavium,octeon-3860-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0x00001800 0x0 0x40>; + }; + + pip: pip@11800a0000000 { + compatible = "cavium,octeon-3860-pip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11800 0xa0000000 0x0 0x2000>; + + interface@0 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* interface */ + + ethernet@0 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x0>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@1 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x1>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + ethernet@2 { + compatible = "cavium,octeon-3860-pip-port"; + reg = <0x2>; /* Port */ + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + interface@1 { + compatible = "cavium,octeon-3860-pip-interface"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* interface */ + }; + }; + + twsi0: i2c@1180000001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-3860-twsi"; + reg = <0x11800 0x00001000 0x0 0x200>; + interrupts = <0 45>; + clock-frequency = <100000>; + }; + + uart0: serial@1180000000800 { + compatible = "cavium,octeon-3860-uart","ns16550"; + reg = <0x11800 0x00000800 0x0 0x400>; + clock-frequency = <0>; + current-speed = <115200>; + reg-shift = <3>; + interrupts = <0 34>; + }; + + bootbus: bootbus@1180000000000 { + compatible = "cavium,octeon-3860-bootbus"; + reg = <0x11800 0x00000000 0x0 0x200>; + /* The chip select number and offset */ + #address-cells = <2>; + /* The size of the chip select region */ + #size-cells = <1>; + ranges = <0 0 0x0 0x1f400000 0xc00000>, + <1 0 0x10000 0x30000000 0>, + <2 0 0x10000 0x40000000 0>, + <3 0 0x10000 0x50000000 0>, + <4 0 0x0 0x1d020000 0x10000>, + <5 0 0x0 0x1d040000 0x10000>, + <6 0 0x0 0x1d050000 0x10000>, + <7 0 0x10000 0x90000000 0>; + + cavium,cs-config@0 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <0>; + cavium,t-adr = <20>; + cavium,t-ce = <60>; + cavium,t-oe = <60>; + cavium,t-we = <45>; + cavium,t-rd-hld = <35>; + cavium,t-wr-hld = <45>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <35>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@4 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <4>; + cavium,t-adr = <320>; + cavium,t-ce = <320>; + cavium,t-oe = <320>; + cavium,t-we = <320>; + cavium,t-rd-hld = <320>; + cavium,t-wr-hld = <320>; + cavium,t-pause = <320>; + cavium,t-wait = <320>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <8>; + }; + cavium,cs-config@5 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <5>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <125>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <30>; + cavium,t-pause = <0>; + cavium,t-wait = <30>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,bus-width = <16>; + }; + cavium,cs-config@6 { + compatible = "cavium,octeon-3860-bootbus-config"; + cavium,cs-index = <6>; + cavium,t-adr = <5>; + cavium,t-ce = <300>; + cavium,t-oe = <270>; + cavium,t-we = <150>; + cavium,t-rd-hld = <100>; + cavium,t-wr-hld = <70>; + cavium,t-pause = <0>; + cavium,t-wait = <0>; + cavium,t-page = <320>; + cavium,t-rd-dly = <0>; + + cavium,pages = <0>; + cavium,wait-mode; + cavium,bus-width = <16>; + }; + + flash0: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + dma0: dma-engine@1180000000100 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000100 0x0 0x8>; + interrupts = <0 63>; + }; + + dma1: dma-engine@1180000000108 { + compatible = "cavium,octeon-5750-bootbus-dma"; + reg = <0x11800 0x00000108 0x0 0x8>; + interrupts = <0 63>; + }; + + usbn: usbn@1180068000000 { + compatible = "cavium,octeon-5750-usbn"; + reg = <0x11800 0x68000000 0x0 0x1000>; + ranges; /* Direct mapping */ + #address-cells = <2>; + #size-cells = <2>; + + usbc@16f0010000000 { + compatible = "cavium,octeon-5750-usbc"; + reg = <0x16f00 0x10000000 0x0 0x80000>; + interrupts = <0 56>; + }; + }; + }; +}; diff --git a/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts new file mode 100644 index 000000000..243e5dc44 --- /dev/null +++ b/arch/mips/boot/dts/cavium-octeon/ubnt_e100.dts @@ -0,0 +1,59 @@ +/* + * Device tree source for EdgeRouter Lite. + * + * Written by: Aaro Koskinen <aaro.koskinen@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/include/ "octeon_3xxx.dtsi" + +/ { + model = "ubnt,e100"; + + soc@0 { + smi0: mdio@1180000001800 { + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy6: ethernet-phy@6 { + reg = <6>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + phy7: ethernet-phy@7 { + reg = <7>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; + + pip: pip@11800a0000000 { + interface@0 { + ethernet@0 { + phy-handle = <&phy7>; + }; + ethernet@1 { + phy-handle = <&phy6>; + }; + ethernet@2 { + phy-handle = <&phy5>; + }; + }; + }; + + uart0: serial@1180000000800 { + clock-frequency = <500000000>; + }; + + usbn: usbn@1180068000000 { + refclk-frequency = <12000000>; + refclk-type = "crystal"; + }; + }; + + aliases { + pip = &pip; + }; +}; diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 8b2437cd0..f6ae6ed9c 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -5,7 +5,7 @@ #size-cells = <1>; compatible = "ingenic,jz4740"; - cpuintc: interrupt-controller@0 { + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; @@ -65,4 +65,18 @@ clocks = <&ext>, <&cgu JZ4740_CLK_UART1>; clock-names = "baud", "module"; }; + + uhc: uhc@13030000 { + compatible = "ingenic,jz4740-ohci", "generic-ohci"; + reg = <0x13030000 0x1000>; + + clocks = <&cgu JZ4740_CLK_UHC>; + assigned-clocks = <&cgu JZ4740_CLK_UHC>; + assigned-clock-rates = <48000000>; + + interrupt-parent = <&intc>; + interrupts = <3>; + + status = "disabled"; + }; }; diff --git a/arch/mips/boot/dts/lantiq/easy50712.dts b/arch/mips/boot/dts/lantiq/easy50712.dts index 143b8a37b..b59962585 100644 --- a/arch/mips/boot/dts/lantiq/easy50712.dts +++ b/arch/mips/boot/dts/lantiq/easy50712.dts @@ -52,7 +52,7 @@ }; gpio: pinmux@E100B10 { - compatible = "lantiq,pinctrl-xway"; + compatible = "lantiq,danube-pinctrl"; pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi b/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi deleted file mode 100644 index ef1335012..000000000 --- a/arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi +++ /dev/null @@ -1,236 +0,0 @@ -/* - * Device Tree Source for PIC32MZDA clock data - * - * Purna Chandra Mandal <purna.mandal@microchip.com> - * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. - * - * Licensed under GPLv2 or later. - */ - -/* all fixed rate clocks */ - -/ { - POSC:posc_clk { /* On-chip primary oscillator */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - FRC:frc_clk { /* internal FRC oscillator */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <8000000>; - }; - - BFRC:bfrc_clk { /* internal backup FRC oscillator */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <8000000>; - }; - - LPRC:lprc_clk { /* internal low-power FRC oscillator */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - /* UPLL provides clock to USBCORE */ - UPLL:usb_phy_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "usbphy_clk"; - }; - - TxCKI:txcki_clk { /* external clock input on TxCLKI pin */ - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - status = "disabled"; - }; - - /* external clock input on REFCLKIx pin */ - REFIx:refix_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - status = "disabled"; - }; - - /* PIC32 specific clks */ - pic32_clktree { - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1f801200 0x200>; - compatible = "microchip,pic32mzda-clk"; - ranges = <0 0x1f801200 0x200>; - - /* secondary oscillator; external input on SOSCI pin */ - SOSC:sosc_clk@0 { - #clock-cells = <0>; - compatible = "microchip,pic32mzda-sosc"; - clock-frequency = <32768>; - reg = <0x000 0x10>, /* enable reg */ - <0x1d0 0x10>; /* status reg */ - microchip,bit-mask = <0x02>; /* enable mask */ - microchip,status-bit-mask = <0x10>; /* status-mask*/ - }; - - FRCDIV:frcdiv_clk { - #clock-cells = <0>; - compatible = "microchip,pic32mzda-frcdivclk"; - clocks = <&FRC>; - clock-output-names = "frcdiv_clk"; - }; - - /* System PLL clock */ - SYSPLL:spll_clk@020 { - #clock-cells = <0>; - compatible = "microchip,pic32mzda-syspll"; - reg = <0x020 0x10>, /* SPLL register */ - <0x1d0 0x10>; /* CLKSTAT register */ - clocks = <&POSC>, <&FRC>; - clock-output-names = "sys_pll"; - microchip,status-bit-mask = <0x80>; /* SPLLRDY */ - }; - - /* system clock; mux with postdiv & slew */ - SYSCLK:sys_clk@1c0 { - #clock-cells = <0>; - compatible = "microchip,pic32mzda-sysclk-v2"; - reg = <0x1c0 0x04>; /* SLEWCON */ - clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>, - <&LPRC>, <&FRCDIV>; - microchip,clock-indices = <0>, <1>, <2>, <4>, - <5>, <7>; - clock-output-names = "sys_clk"; - }; - - /* Peripheral bus1 clock */ - PBCLK1:pb1_clk@140 { - reg = <0x140 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - clock-output-names = "pb1_clk"; - /* used by system modules, not gateable */ - microchip,ignore-unused; - }; - - /* Peripheral bus2 clock */ - PBCLK2:pb2_clk@150 { - reg = <0x150 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - clock-output-names = "pb2_clk"; - /* avoid gating even if unused */ - microchip,ignore-unused; - }; - - /* Peripheral bus3 clock */ - PBCLK3:pb3_clk@160 { - reg = <0x160 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - clock-output-names = "pb3_clk"; - }; - - /* Peripheral bus4 clock(I/O ports, GPIO) */ - PBCLK4:pb4_clk@170 { - reg = <0x170 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - clock-output-names = "pb4_clk"; - }; - - /* Peripheral bus clock */ - PBCLK5:pb5_clk@180 { - reg = <0x180 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - clock-output-names = "pb5_clk"; - }; - - /* Peripheral Bus6 clock; */ - PBCLK6:pb6_clk@190 { - reg = <0x190 0x10>; - compatible = "microchip,pic32mzda-pbclk"; - clocks = <&SYSCLK>; - #clock-cells = <0>; - }; - - /* Peripheral bus7 clock */ - PBCLK7:pb7_clk@1a0 { - reg = <0x1a0 0x10>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-pbclk"; - /* CPU is driven by this clock; so named */ - clock-output-names = "cpu_clk"; - clocks = <&SYSCLK>; - }; - - /* Reference Oscillator clock for SPI/I2S */ - REFCLKO1:refo1_clk@80 { - reg = <0x080 0x20>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-refoclk"; - clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>, - <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>; - microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, - <5>, <7>, <8>, <9>; - clock-output-names = "refo1_clk"; - }; - - /* Reference Oscillator clock for SQI */ - REFCLKO2:refo2_clk@a0 { - reg = <0x0a0 0x20>; - #clock-cells = <0>; - compatible = "microchip,pic32mzda-refoclk"; - clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>, - <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>; - microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, - <5>, <7>, <8>, <9>; - clock-output-names = "refo2_clk"; - }; - - /* Reference Oscillator clock, ADC */ - REFCLKO3:refo3_clk@c0 { - reg = <0x0c0 0x20>; - compatible = "microchip,pic32mzda-refoclk"; - clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>, - <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>; - microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, - <5>, <7>, <8>, <9>; - #clock-cells = <0>; - clock-output-names = "refo3_clk"; - }; - - /* Reference Oscillator clock */ - REFCLKO4:refo4_clk@e0 { - reg = <0x0e0 0x20>; - compatible = "microchip,pic32mzda-refoclk"; - clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>, - <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>; - microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, - <5>, <7>, <8>, <9>; - #clock-cells = <0>; - clock-output-names = "refo4_clk"; - }; - - /* Reference Oscillator clock, LCD */ - REFCLKO5:refo5_clk@100 { - reg = <0x100 0x20>; - compatible = "microchip,pic32mzda-refoclk"; - clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>, - <&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>; - microchip,clock-indices = <0>, <1>, <2>, <3>, <4>, - <5>, <7>, <8>, <9>; - #clock-cells = <0>; - clock-output-names = "refo5_clk"; - }; - }; -}; diff --git a/arch/mips/boot/dts/pic32/pic32mzda.dtsi b/arch/mips/boot/dts/pic32/pic32mzda.dtsi index ad9e3318c..5353a639c 100644 --- a/arch/mips/boot/dts/pic32/pic32mzda.dtsi +++ b/arch/mips/boot/dts/pic32/pic32mzda.dtsi @@ -6,11 +6,9 @@ * published by the Free Software Foundation. * */ - +#include <dt-bindings/clock/microchip,pic32-clock.h> #include <dt-bindings/interrupt-controller/irq.h> -#include "pic32mzda-clk.dtsi" - / { #address-cells = <1>; #size-cells = <1>; @@ -50,6 +48,29 @@ interrupts = <0 IRQ_TYPE_EDGE_RISING>; }; + /* external clock input on TxCLKI pin */ + txcki: txcki_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + status = "disabled"; + }; + + /* external input on REFCLKIx pin */ + refix: refix_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + status = "disabled"; + }; + + rootclk: clock-controller@1f801200 { + compatible = "microchip,pic32mzda-clk"; + reg = <0x1f801200 0x200>; + #clock-cells = <1>; + microchip,pic32mzda-sosc; + }; + evic: interrupt-controller@1f810000 { compatible = "microchip,pic32mzda-evic"; interrupt-controller; @@ -63,7 +84,7 @@ #size-cells = <1>; compatible = "microchip,pic32mzda-pinctrl"; reg = <0x1f801400 0x400>; - clocks = <&PBCLK1>; + clocks = <&rootclk PB1CLK>; }; /* PORTA */ @@ -75,7 +96,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <0>; gpio-ranges = <&pic32_pinctrl 0 0 16>; }; @@ -89,7 +110,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <1>; gpio-ranges = <&pic32_pinctrl 0 16 16>; }; @@ -103,7 +124,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <2>; gpio-ranges = <&pic32_pinctrl 0 32 16>; }; @@ -117,7 +138,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <3>; gpio-ranges = <&pic32_pinctrl 0 48 16>; }; @@ -131,7 +152,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <4>; gpio-ranges = <&pic32_pinctrl 0 64 16>; }; @@ -145,7 +166,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <5>; gpio-ranges = <&pic32_pinctrl 0 80 16>; }; @@ -159,7 +180,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <6>; gpio-ranges = <&pic32_pinctrl 0 96 16>; }; @@ -173,7 +194,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <7>; gpio-ranges = <&pic32_pinctrl 0 112 16>; }; @@ -189,7 +210,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <8>; gpio-ranges = <&pic32_pinctrl 0 128 16>; }; @@ -203,7 +224,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&PBCLK4>; + clocks = <&rootclk PB4CLK>; microchip,gpio-bank = <9>; gpio-ranges = <&pic32_pinctrl 0 144 16>; }; @@ -212,7 +233,7 @@ compatible = "microchip,pic32mzda-sdhci"; reg = <0x1f8ec000 0x100>; interrupts = <191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&REFCLKO4>, <&PBCLK5>; + clocks = <&rootclk REF4CLK>, <&rootclk PB5CLK>; clock-names = "base_clk", "sys_clk"; bus-width = <4>; cap-sd-highspeed; @@ -225,7 +246,7 @@ interrupts = <112 IRQ_TYPE_LEVEL_HIGH>, <113 IRQ_TYPE_LEVEL_HIGH>, <114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; @@ -235,7 +256,7 @@ interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, <146 IRQ_TYPE_LEVEL_HIGH>, <147 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; @@ -245,7 +266,7 @@ interrupts = <157 IRQ_TYPE_LEVEL_HIGH>, <158 IRQ_TYPE_LEVEL_HIGH>, <159 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; @@ -255,7 +276,7 @@ interrupts = <170 IRQ_TYPE_LEVEL_HIGH>, <171 IRQ_TYPE_LEVEL_HIGH>, <172 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; @@ -265,7 +286,7 @@ interrupts = <179 IRQ_TYPE_LEVEL_HIGH>, <180 IRQ_TYPE_LEVEL_HIGH>, <181 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; @@ -275,7 +296,7 @@ interrupts = <188 IRQ_TYPE_LEVEL_HIGH>, <189 IRQ_TYPE_LEVEL_HIGH>, <190 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&PBCLK2>; + clocks = <&rootclk PB2CLK>; status = "disabled"; }; }; diff --git a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts index 5d434a50e..fc7401028 100644 --- a/arch/mips/boot/dts/pic32/pic32mzda_sk.dts +++ b/arch/mips/boot/dts/pic32/pic32mzda_sk.dts @@ -95,8 +95,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhc1>; status = "okay"; - assigned-clocks = <&REFCLKO2>,<&REFCLKO4>,<&REFCLKO5>; - assigned-clock-rates = <50000000>,<25000000>,<40000000>; + assigned-clocks = <&rootclk REF2CLK>, <&rootclk REF4CLK>, + <&rootclk REF5CLK>; + assigned-clock-rates = <50000000>, <25000000>, <40000000>; }; &pic32_pinctrl { diff --git a/arch/mips/boot/dts/qca/Makefile b/arch/mips/boot/dts/qca/Makefile index 2d61455d5..63a9ddf04 100644 --- a/arch/mips/boot/dts/qca/Makefile +++ b/arch/mips/boot/dts/qca/Makefile @@ -1,8 +1,9 @@ # All DTBs dtb-$(CONFIG_ATH79) += ar9132_tl_wr1043nd_v1.dtb - -# Select a DTB to build in the kernel -obj-$(CONFIG_DTB_TL_WR1043ND_V1) += ar9132_tl_wr1043nd_v1.dtb.o +dtb-$(CONFIG_ATH79) += ar9331_dpt_module.dtb +dtb-$(CONFIG_ATH79) += ar9331_dragino_ms14.dtb +dtb-$(CONFIG_ATH79) += ar9331_omega.dtb +dtb-$(CONFIG_ATH79) += ar9331_tl_mr3020.dtb # Force kbuild to make empty built-in.o if necessary obj- += dummy.o diff --git a/arch/mips/boot/dts/qca/ar9132.dtsi b/arch/mips/boot/dts/qca/ar9132.dtsi index 3c2ed9ee5..302f0a8d2 100644 --- a/arch/mips/boot/dts/qca/ar9132.dtsi +++ b/arch/mips/boot/dts/qca/ar9132.dtsi @@ -1,3 +1,5 @@ +#include <dt-bindings/clock/ath79-clk.h> + / { compatible = "qca,ar9132"; @@ -11,6 +13,7 @@ cpu@0 { device_type = "cpu"; compatible = "mips,mips24Kc"; + clocks = <&pll ATH79_CLK_CPU>; reg = <0>; }; }; @@ -52,12 +55,12 @@ #qca,ddr-wb-channel-cells = <1>; }; - uart@18020000 { + uart: uart@18020000 { compatible = "ns8250"; reg = <0x18020000 0x20>; interrupts = <3>; - clocks = <&pll 2>; + clocks = <&pll ATH79_CLK_AHB>; clock-names = "uart"; reg-io-width = <4>; @@ -94,13 +97,13 @@ clock-output-names = "cpu", "ddr", "ahb"; }; - wdt@18060008 { + wdt: wdt@18060008 { compatible = "qca,ar7130-wdt"; reg = <0x18060008 0x8>; interrupts = <4>; - clocks = <&pll 2>; + clocks = <&pll ATH79_CLK_AHB>; clock-names = "wdt"; }; @@ -125,7 +128,7 @@ }; }; - usb@1b000100 { + usb: usb@1b000100 { compatible = "qca,ar7100-ehci", "generic-ehci"; reg = <0x1b000100 0x100>; @@ -140,11 +143,11 @@ status = "disabled"; }; - spi@1f000000 { + spi: spi@1f000000 { compatible = "qca,ar9132-spi", "qca,ar7100-spi"; reg = <0x1f000000 0x10>; - clocks = <&pll 2>; + clocks = <&pll ATH79_CLK_AHB>; clock-names = "ahb"; status = "disabled"; diff --git a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts index 4f1540e5f..3c3b7ce57 100644 --- a/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts +++ b/arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts @@ -9,10 +9,6 @@ compatible = "tplink,tl-wr1043nd-v1", "qca,ar9132"; model = "TP-Link TL-WR1043ND Version 1"; - alias { - serial0 = "/ahb/apb/uart@18020000"; - }; - memory@0 { device_type = "memory"; reg = <0x0 0x2000000>; @@ -24,55 +20,6 @@ clock-frequency = <40000000>; }; - ahb { - apb { - uart@18020000 { - status = "okay"; - }; - - pll-controller@18050000 { - clocks = <&extosc>; - }; - }; - - usb@1b000100 { - status = "okay"; - }; - - spi@1f000000 { - status = "okay"; - num-cs = <1>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "s25sl064a"; - reg = <0>; - spi-max-frequency = <25000000>; - - partition@0 { - label = "u-boot"; - reg = <0x000000 0x020000>; - }; - - partition@1 { - label = "firmware"; - reg = <0x020000 0x7D0000>; - }; - - partition@2 { - label = "art"; - reg = <0x7F0000 0x010000>; - read-only; - }; - }; - }; - }; - - usb-phy { - status = "okay"; - }; - gpio-keys { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -118,3 +65,48 @@ }; }; }; + +&uart { + status = "okay"; +}; + +&pll { + clocks = <&extosc>; +}; + +&usb { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <1>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25sl064a"; + reg = <0>; + spi-max-frequency = <25000000>; + + partition@0 { + label = "u-boot"; + reg = <0x000000 0x020000>; + }; + + partition@1 { + label = "firmware"; + reg = <0x020000 0x7D0000>; + }; + + partition@2 { + label = "art"; + reg = <0x7F0000 0x010000>; + read-only; + }; + }; +}; diff --git a/arch/mips/boot/dts/qca/ar9331.dtsi b/arch/mips/boot/dts/qca/ar9331.dtsi new file mode 100644 index 000000000..cf47ed4d8 --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331.dtsi @@ -0,0 +1,155 @@ +#include <dt-bindings/clock/ath79-clk.h> + +/ { + compatible = "qca,ar9331"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips24Kc"; + clocks = <&pll ATH79_CLK_CPU>; + reg = <0>; + }; + }; + + cpuintc: interrupt-controller { + compatible = "qca,ar7100-cpu-intc"; + + interrupt-controller; + #interrupt-cells = <1>; + + qca,ddr-wb-channel-interrupts = <2>, <3>; + qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>; + }; + + ref: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&cpuintc>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&miscintc>; + + ddr_ctrl: memory-controller@18000000 { + compatible = "qca,ar7240-ddr-controller"; + reg = <0x18000000 0x100>; + + #qca,ddr-wb-channel-cells = <1>; + }; + + uart: uart@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + + interrupts = <3>; + + clocks = <&ref>; + clock-names = "uart"; + + status = "disabled"; + }; + + gpio: gpio@18040000 { + compatible = "qca,ar7100-gpio"; + reg = <0x18040000 0x34>; + interrupts = <2>; + + ngpios = <30>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + status = "disabled"; + }; + + pll: pll-controller@18050000 { + compatible = "qca,ar9330-pll"; + reg = <0x18050000 0x100>; + + clocks = <&ref>; + clock-names = "ref"; + + #clock-cells = <1>; + }; + + miscintc: interrupt-controller@18060010 { + compatible = "qca,ar7240-misc-intc"; + reg = <0x18060010 0x4>; + + interrupt-parent = <&cpuintc>; + interrupts = <6>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + + rst: reset-controller@1806001c { + compatible = "qca,ar7100-reset"; + reg = <0x1806001c 0x4>; + + #reset-cells = <1>; + }; + }; + + usb: usb@1b000100 { + compatible = "chipidea,usb2"; + reg = <0x1b000000 0x200>; + + interrupts = <3>; + resets = <&rst 5>; + + phy-names = "usb-phy"; + phys = <&usb_phy>; + + status = "disabled"; + }; + + spi: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + clocks = <&pll ATH79_CLK_AHB>; + clock-names = "ahb"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + usb_phy: usb-phy { + compatible = "qca,ar7100-usb-phy"; + + reset-names = "usb-phy", "usb-suspend-override"; + resets = <&rst 4>, <&rst 3>; + + #phy-cells = <0>; + + status = "disabled"; + }; +}; diff --git a/arch/mips/boot/dts/qca/ar9331_dpt_module.dts b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts new file mode 100644 index 000000000..98e74500e --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331_dpt_module.dts @@ -0,0 +1,78 @@ +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "ar9331.dtsi" + +/ { + model = "DPTechnics DPT-Module"; + compatible = "dptechnics,dpt-module"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + system { + label = "dpt-module:green:system"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond 25Q128FVSG SPI flash */ + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts new file mode 100644 index 000000000..56f832076 --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts @@ -0,0 +1,102 @@ +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "ar9331.dtsi" + +/ { + model = "Dragino MS14 (Dragino 2)"; + compatible = "dragino,ms14"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "dragino2:red:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + lan { + label = "dragino2:red:lan"; + gpios = <&gpio 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wan { + label = "dragino2:red:wan"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + system { + label = "dragino2:red:system"; + gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "jumpstart"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + }; + + button@1 { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond 25Q128BVFG SPI flash */ + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/boot/dts/qca/ar9331_omega.dts b/arch/mips/boot/dts/qca/ar9331_omega.dts new file mode 100644 index 000000000..b2be3b044 --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331_omega.dts @@ -0,0 +1,78 @@ +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "ar9331.dtsi" + +/ { + model = "Onion Omega"; + compatible = "onion,omega"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x4000000>; + }; + + leds { + compatible = "gpio-leds"; + + system { + label = "onion:amber:system"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond 25Q128FVSG SPI flash */ + spiflash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts new file mode 100644 index 000000000..919cf3b85 --- /dev/null +++ b/arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts @@ -0,0 +1,118 @@ +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "ar9331.dtsi" + +/ { + model = "TP-Link TL-MR3020"; + compatible = "tplink,tl-mr3020"; + + aliases { + serial0 = &uart; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x2000000>; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "tp-link:green:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + lan { + label = "tp-link:green:lan"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wps { + label = "tp-link:green:wps"; + gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3g { + label = "tp-link:green:3g"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + button@0 { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + + button@1 { + label = "sw1"; + linux,code = <BTN_0>; + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + }; + + button@2 { + label = "sw2"; + linux,code = <BTN_1>; + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_vbus: reg_usb_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ref { + clock-frequency = <25000000>; +}; + +&uart { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&usb { + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Spansion S25FL032PIF SPI flash */ + spiflash: s25sl032p@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25sl032p", "jedec,spi-nor"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi index 08bf24fef..793c0c7ca 100644 --- a/arch/mips/boot/dts/ralink/mt7620a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi @@ -9,7 +9,7 @@ }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; diff --git a/arch/mips/boot/dts/ralink/rt2880.dtsi b/arch/mips/boot/dts/ralink/rt2880.dtsi index 182afde2f..fb2faef0a 100644 --- a/arch/mips/boot/dts/ralink/rt2880.dtsi +++ b/arch/mips/boot/dts/ralink/rt2880.dtsi @@ -9,7 +9,7 @@ }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; diff --git a/arch/mips/boot/dts/ralink/rt3050.dtsi b/arch/mips/boot/dts/ralink/rt3050.dtsi index e3203d414..d3cb57f98 100644 --- a/arch/mips/boot/dts/ralink/rt3050.dtsi +++ b/arch/mips/boot/dts/ralink/rt3050.dtsi @@ -9,7 +9,7 @@ }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; diff --git a/arch/mips/boot/dts/ralink/rt3883.dtsi b/arch/mips/boot/dts/ralink/rt3883.dtsi index 3b131dd0d..3d6fc9afd 100644 --- a/arch/mips/boot/dts/ralink/rt3883.dtsi +++ b/arch/mips/boot/dts/ralink/rt3883.dtsi @@ -9,7 +9,7 @@ }; }; - cpuintc: cpuintc@0 { + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts index 686ebd113..48d21127c 100644 --- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts +++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts @@ -10,7 +10,7 @@ reg = <0x0 0x08000000>; }; - cpuintc: interrupt-controller@0 { + cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; |