diff options
| author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-03-25 03:53:42 -0300 |
|---|---|---|
| committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-03-25 03:53:42 -0300 |
| commit | 03dd4cb26d967f9588437b0fc9cc0e8353322bb7 (patch) | |
| tree | fa581f6dc1c0596391690d1f67eceef3af8246dc /drivers/net/wireless/b43 | |
| parent | d4e493caf788ef44982e131ff9c786546904d934 (diff) | |
Linux-libre 4.5-gnu
Diffstat (limited to 'drivers/net/wireless/b43')
63 files changed, 0 insertions, 58112 deletions
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig deleted file mode 100644 index fba856032..000000000 --- a/drivers/net/wireless/b43/Kconfig +++ /dev/null @@ -1,187 +0,0 @@ -config B43 - tristate "Broadcom 43xx wireless support (mac80211 stack)" - depends on (BCMA_POSSIBLE || SSB_POSSIBLE) && MAC80211 && HAS_DMA - select BCMA if B43_BCMA - select SSB if B43_SSB - select FW_LOADER - ---help--- - b43 is a driver for the Broadcom 43xx series wireless devices. - - Check "lspci" for something like - "Broadcom Corporation BCM43XX 802.11 Wireless LAN Controller" - to determine whether you own such a device. - - This driver supports the new BCM43xx IEEE 802.11G devices, but not - the old IEEE 802.11B devices. Old devices are supported by - the b43legacy driver. - Note that this has nothing to do with the standard that your AccessPoint - supports (A, B, G or a combination). - IEEE 802.11G devices can talk to IEEE 802.11B AccessPoints. - - It is safe to include both b43 and b43legacy as the underlying glue - layer will automatically load the correct version for your device. - - This driver uses V4 firmware, which must be installed separately using - b43-fwcutter. - - This driver can be built as a module (recommended) that will be called "b43". - If unsure, say M. - -config B43_BCMA - bool - -config B43_SSB - bool - -choice - prompt "Supported bus types" - depends on B43 - default B43_BUSES_BCMA_AND_SSB - -config B43_BUSES_BCMA_AND_SSB - bool "BCMA and SSB" - depends on BCMA_POSSIBLE && SSB_POSSIBLE - select B43_BCMA - select B43_SSB - -config B43_BUSES_BCMA - bool "BCMA only" - depends on BCMA_POSSIBLE - select B43_BCMA - -config B43_BUSES_SSB - bool "SSB only" - depends on SSB_POSSIBLE - select B43_SSB - -endchoice - -# Auto-select SSB PCI-HOST support, if possible -config B43_PCI_AUTOSELECT - bool - depends on B43 && SSB_PCIHOST_POSSIBLE - select SSB_PCIHOST - select SSB_B43_PCI_BRIDGE - default y - -# Auto-select SSB PCICORE driver, if possible -config B43_PCICORE_AUTOSELECT - bool - depends on B43 && SSB_DRIVER_PCICORE_POSSIBLE - select SSB_DRIVER_PCICORE - default y - -config B43_SDIO - bool "Broadcom 43xx SDIO device support" - depends on B43 && B43_SSB && SSB_SDIOHOST_POSSIBLE - select SSB_SDIOHOST - ---help--- - Broadcom 43xx device support for Soft-MAC SDIO devices. - - With this config option you can drive Soft-MAC b43 cards with a - Secure Digital I/O interface. - This includes the WLAN daughter card found on the Nintendo Wii - video game console. - Note that this does not support Broadcom 43xx Full-MAC devices. - - It's safe to select Y here, even if you don't have a B43 SDIO device. - - If unsure, say N. - -#Data transfers to the device via PIO. We want it as a fallback even -# if we can do DMA. -config B43_BCMA_PIO - bool - depends on B43 && B43_BCMA - select BCMA_BLOCKIO - default y - -config B43_PIO - bool - depends on B43 && B43_SSB - select SSB_BLOCKIO - default y - -config B43_PHY_G - bool "Support for G-PHY (802.11g) devices" - depends on B43 && B43_SSB - default y - ---help--- - This PHY type can be found in the following chipsets: - PCI: BCM4306, BCM4311, BCM4318 - SoC: BCM4712, BCM5352E - -config B43_PHY_N - bool "Support for N-PHY (the main 802.11n series) devices" - depends on B43 - default y - ---help--- - This PHY type can be found in the following chipsets: - PCI: BCM4321, BCM4322, - BCM43222, BCM43224, BCM43225, - BCM43131, BCM43217, BCM43227, BCM43228 - SoC: BCM4716, BCM4717, BCM4718, BCM5356, BCM5357, BCM5358 - -config B43_PHY_LP - bool "Support for LP-PHY (low-power 802.11g) devices" - depends on B43 && B43_SSB - default y - ---help--- - The LP-PHY is a low-power PHY built into some notebooks - and embedded devices. It supports 802.11a/b/g - (802.11a support is optional, and currently disabled). - -config B43_PHY_HT - bool "Support for HT-PHY (high throughput 802.11n) devices" - depends on B43 && B43_BCMA - default y - ---help--- - This PHY type with 3x3:3 MIMO can be found in the BCM4331 PCI chipset. - -config B43_PHY_LCN - bool "Support for LCN-PHY devices (BROKEN)" - depends on B43 && BROKEN - ---help--- - Support for the LCN-PHY. - - Say N, this is BROKEN and crashes driver. - -config B43_PHY_AC - bool "Support for AC-PHY (802.11ac) devices (BROKEN)" - depends on B43 && B43_BCMA && BROKEN - ---help--- - This PHY type can be found in the following chipsets: - PCI: BCM4352, BCM4360 - - Say N, this is BROKEN and crashes driver. - -# This config option automatically enables b43 LEDS support, -# if it's possible. -config B43_LEDS - bool - depends on B43 && MAC80211_LEDS && (LEDS_CLASS = y || LEDS_CLASS = B43) - default y - -# This config option automatically enables b43 HW-RNG support, -# if the HW-RNG core is enabled. -config B43_HWRNG - bool - depends on B43 && (HW_RANDOM = y || HW_RANDOM = B43) - default y - -config B43_DEBUG - bool "Broadcom 43xx debugging" - depends on B43 - ---help--- - Broadcom 43xx debugging. - - This adds additional runtime sanity checks and statistics to the driver. - These checks and statistics might be expensive and hurt the runtime - performance of your system. - This also adds the b43 debugfs interface. - - Do not enable this, unless you are debugging the driver. - - Say N, if you are a distributor or user building a release kernel - for production use. - Only say Y, if you are debugging a problem in the b43 driver sourcecode. diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile deleted file mode 100644 index ddc4df466..000000000 --- a/drivers/net/wireless/b43/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -b43-y += main.o -b43-y += bus.o -b43-$(CONFIG_B43_PHY_G) += phy_a.o phy_g.o tables.o lo.o wa.o -b43-$(CONFIG_B43_PHY_N) += tables_nphy.o -b43-$(CONFIG_B43_PHY_N) += radio_2055.o -b43-$(CONFIG_B43_PHY_N) += radio_2056.o -b43-$(CONFIG_B43_PHY_N) += radio_2057.o -b43-y += phy_common.o -b43-$(CONFIG_B43_PHY_N) += phy_n.o -b43-$(CONFIG_B43_PHY_LP) += phy_lp.o -b43-$(CONFIG_B43_PHY_LP) += tables_lpphy.o -b43-$(CONFIG_B43_PHY_HT) += phy_ht.o -b43-$(CONFIG_B43_PHY_HT) += tables_phy_ht.o -b43-$(CONFIG_B43_PHY_HT) += radio_2059.o -b43-$(CONFIG_B43_PHY_LCN) += phy_lcn.o tables_phy_lcn.o -b43-$(CONFIG_B43_PHY_AC) += phy_ac.o -b43-y += sysfs.o -b43-y += xmit.o -b43-y += dma.o -b43-y += pio.o -b43-y += rfkill.o -b43-y += ppr.o -b43-$(CONFIG_B43_LEDS) += leds.o -b43-$(CONFIG_B43_SDIO) += sdio.o -b43-$(CONFIG_B43_DEBUG) += debugfs.o - -obj-$(CONFIG_B43) += b43.o diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h deleted file mode 100644 index 036552439..000000000 --- a/drivers/net/wireless/b43/b43.h +++ /dev/null @@ -1,1108 +0,0 @@ -#ifndef B43_H_ -#define B43_H_ - -#include <linux/kernel.h> -#include <linux/spinlock.h> -#include <linux/interrupt.h> -#include <linux/hw_random.h> -#include <linux/bcma/bcma.h> -#include <linux/ssb/ssb.h> -#include <linux/completion.h> -#include <net/mac80211.h> - -#include "debugfs.h" -#include "leds.h" -#include "rfkill.h" -#include "bus.h" -#include "lo.h" -#include "phy_common.h" - - -#ifdef CONFIG_B43_DEBUG -# define B43_DEBUG 1 -#else -# define B43_DEBUG 0 -#endif - -/* MMIO offsets */ -#define B43_MMIO_DMA0_REASON 0x20 -#define B43_MMIO_DMA0_IRQ_MASK 0x24 -#define B43_MMIO_DMA1_REASON 0x28 -#define B43_MMIO_DMA1_IRQ_MASK 0x2C -#define B43_MMIO_DMA2_REASON 0x30 -#define B43_MMIO_DMA2_IRQ_MASK 0x34 -#define B43_MMIO_DMA3_REASON 0x38 -#define B43_MMIO_DMA3_IRQ_MASK 0x3C -#define B43_MMIO_DMA4_REASON 0x40 -#define B43_MMIO_DMA4_IRQ_MASK 0x44 -#define B43_MMIO_DMA5_REASON 0x48 -#define B43_MMIO_DMA5_IRQ_MASK 0x4C -#define B43_MMIO_MACCTL 0x120 /* MAC control */ -#define B43_MMIO_MACCMD 0x124 /* MAC command */ -#define B43_MMIO_GEN_IRQ_REASON 0x128 -#define B43_MMIO_GEN_IRQ_MASK 0x12C -#define B43_MMIO_RAM_CONTROL 0x130 -#define B43_MMIO_RAM_DATA 0x134 -#define B43_MMIO_PS_STATUS 0x140 -#define B43_MMIO_RADIO_HWENABLED_HI 0x158 -#define B43_MMIO_MAC_HW_CAP 0x15C /* MAC capabilities (corerev >= 13) */ -#define B43_MMIO_SHM_CONTROL 0x160 -#define B43_MMIO_SHM_DATA 0x164 -#define B43_MMIO_SHM_DATA_UNALIGNED 0x166 -#define B43_MMIO_XMITSTAT_0 0x170 -#define B43_MMIO_XMITSTAT_1 0x174 -#define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ -#define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ -#define B43_MMIO_TSF_CFP_REP 0x188 -#define B43_MMIO_TSF_CFP_START 0x18C -#define B43_MMIO_TSF_CFP_MAXDUR 0x190 - -/* 32-bit DMA */ -#define B43_MMIO_DMA32_BASE0 0x200 -#define B43_MMIO_DMA32_BASE1 0x220 -#define B43_MMIO_DMA32_BASE2 0x240 -#define B43_MMIO_DMA32_BASE3 0x260 -#define B43_MMIO_DMA32_BASE4 0x280 -#define B43_MMIO_DMA32_BASE5 0x2A0 -/* 64-bit DMA */ -#define B43_MMIO_DMA64_BASE0 0x200 -#define B43_MMIO_DMA64_BASE1 0x240 -#define B43_MMIO_DMA64_BASE2 0x280 -#define B43_MMIO_DMA64_BASE3 0x2C0 -#define B43_MMIO_DMA64_BASE4 0x300 -#define B43_MMIO_DMA64_BASE5 0x340 - -/* PIO on core rev < 11 */ -#define B43_MMIO_PIO_BASE0 0x300 -#define B43_MMIO_PIO_BASE1 0x310 -#define B43_MMIO_PIO_BASE2 0x320 -#define B43_MMIO_PIO_BASE3 0x330 -#define B43_MMIO_PIO_BASE4 0x340 -#define B43_MMIO_PIO_BASE5 0x350 -#define B43_MMIO_PIO_BASE6 0x360 -#define B43_MMIO_PIO_BASE7 0x370 -/* PIO on core rev >= 11 */ -#define B43_MMIO_PIO11_BASE0 0x200 -#define B43_MMIO_PIO11_BASE1 0x240 -#define B43_MMIO_PIO11_BASE2 0x280 -#define B43_MMIO_PIO11_BASE3 0x2C0 -#define B43_MMIO_PIO11_BASE4 0x300 -#define B43_MMIO_PIO11_BASE5 0x340 - -#define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */ -#define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */ -#define B43_MMIO_PHY_VER 0x3E0 -#define B43_MMIO_PHY_RADIO 0x3E2 -#define B43_MMIO_PHY0 0x3E6 -#define B43_MMIO_ANTENNA 0x3E8 -#define B43_MMIO_CHANNEL 0x3F0 -#define B43_MMIO_CHANNEL_EXT 0x3F4 -#define B43_MMIO_RADIO_CONTROL 0x3F6 -#define B43_MMIO_RADIO_DATA_HIGH 0x3F8 -#define B43_MMIO_RADIO_DATA_LOW 0x3FA -#define B43_MMIO_PHY_CONTROL 0x3FC -#define B43_MMIO_PHY_DATA 0x3FE -#define B43_MMIO_MACFILTER_CONTROL 0x420 -#define B43_MMIO_MACFILTER_DATA 0x422 -#define B43_MMIO_RCMTA_COUNT 0x43C -#define B43_MMIO_PSM_PHY_HDR 0x492 -#define B43_MMIO_RADIO_HWENABLED_LO 0x49A -#define B43_MMIO_GPIO_CONTROL 0x49C -#define B43_MMIO_GPIO_MASK 0x49E -#define B43_MMIO_TXE0_CTL 0x500 -#define B43_MMIO_TXE0_AUX 0x502 -#define B43_MMIO_TXE0_TS_LOC 0x504 -#define B43_MMIO_TXE0_TIME_OUT 0x506 -#define B43_MMIO_TXE0_WM_0 0x508 -#define B43_MMIO_TXE0_WM_1 0x50A -#define B43_MMIO_TXE0_PHYCTL 0x50C -#define B43_MMIO_TXE0_STATUS 0x50E -#define B43_MMIO_TXE0_MMPLCP0 0x510 -#define B43_MMIO_TXE0_MMPLCP1 0x512 -#define B43_MMIO_TXE0_PHYCTL1 0x514 -#define B43_MMIO_XMTFIFODEF 0x520 -#define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */ -#define B43_MMIO_XMTFIFOCMD 0x540 -#define B43_MMIO_XMTFIFOFLUSH 0x542 -#define B43_MMIO_XMTFIFOTHRESH 0x544 -#define B43_MMIO_XMTFIFORDY 0x546 -#define B43_MMIO_XMTFIFOPRIRDY 0x548 -#define B43_MMIO_XMTFIFORQPRI 0x54A -#define B43_MMIO_XMTTPLATETXPTR 0x54C -#define B43_MMIO_XMTTPLATEPTR 0x550 -#define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */ -#define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */ -#define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */ -#define B43_MMIO_XMTTPLATEDATALO 0x560 -#define B43_MMIO_XMTTPLATEDATAHI 0x562 -#define B43_MMIO_XMTSEL 0x568 -#define B43_MMIO_XMTTXCNT 0x56A -#define B43_MMIO_XMTTXSHMADDR 0x56C -#define B43_MMIO_TSF_CFP_START_LOW 0x604 -#define B43_MMIO_TSF_CFP_START_HIGH 0x606 -#define B43_MMIO_TSF_CFP_PRETBTT 0x612 -#define B43_MMIO_TSF_CLK_FRAC_LOW 0x62E -#define B43_MMIO_TSF_CLK_FRAC_HIGH 0x630 -#define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ -#define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ -#define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ -#define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ -#define B43_MMIO_RNG 0x65A -#define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ -#define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ -#define B43_MMIO_IFSSTAT 0x690 -#define B43_MMIO_IFSMEDBUSYCTL 0x692 -#define B43_MMIO_IFTXDUR 0x694 -#define B43_MMIO_IFSCTL_USE_EDCF 0x0004 -#define B43_MMIO_POWERUP_DELAY 0x6A8 -#define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ -#define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ -#define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ -#define B43_MMIO_WEPCTL 0x7C0 - -/* SPROM boardflags_lo values */ -#define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ -#define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ -#define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ -#define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ -#define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ -#define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ -#define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ -#define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */ -#define B43_BFL_ENETVLAN 0x0100 /* can do vlan */ -#define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ -#define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */ -#define B43_BFL_FEM 0x0800 /* supports the Front End Module */ -#define B43_BFL_EXTLNA 0x1000 /* has an external LNA */ -#define B43_BFL_HGPA 0x2000 /* had high gain PA */ -#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ -#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ - -/* SPROM boardflags_hi values */ -#define B43_BFH_NOPA 0x0001 /* has no PA */ -#define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ -#define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */ -#define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared - * with bluetooth */ -#define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ -#define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */ -#define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna - * with bluetooth */ -#define B43_BFH_NOCBUCK 0x0080 -#define B43_BFH_PALDO 0x0200 -#define B43_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */ - -/* SPROM boardflags2_lo values */ -#define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ -#define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ -#define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ -#define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ -#define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ -#define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ -#define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ -#define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ -#define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ -#define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ -#define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ -#define B43_BFL2_SINGLEANT_CCK 0x1000 -#define B43_BFL2_2G_SPUR_WAR 0x2000 - -/* SPROM boardflags2_hi values */ -#define B43_BFH2_GPLL_WAR2 0x0001 -#define B43_BFH2_IPALVLSHIFT_3P3 0x0002 -#define B43_BFH2_INTERNDET_TXIQCAL 0x0004 -#define B43_BFH2_XTALBUFOUTEN 0x0008 - -/* GPIO register offset, in both ChipCommon and PCI core. */ -#define B43_GPIO_CONTROL 0x6c - -/* SHM Routing */ -enum { - B43_SHM_UCODE, /* Microcode memory */ - B43_SHM_SHARED, /* Shared memory */ - B43_SHM_SCRATCH, /* Scratch memory */ - B43_SHM_HW, /* Internal hardware register */ - B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */ -}; -/* SHM Routing modifiers */ -#define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */ -#define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */ -#define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \ - B43_SHM_AUTOINC_W) - -/* Misc SHM_SHARED offsets */ -#define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ -#define B43_SHM_SH_PCTLWDPOS 0x0008 -#define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */ -#define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */ -#define B43_SHM_SH_PHYVER 0x0050 /* PHY version */ -#define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */ -#define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */ -#define B43_SHM_SH_HOSTF1 0x005E /* Hostflags 1 for ucode options */ -#define B43_SHM_SH_HOSTF2 0x0060 /* Hostflags 2 for ucode options */ -#define B43_SHM_SH_HOSTF3 0x0062 /* Hostflags 3 for ucode options */ -#define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */ -#define B43_SHM_SH_RADAR 0x0066 /* Radar register */ -#define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ -#define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ -#define B43_SHM_SH_HOSTF4 0x0078 /* Hostflags 4 for ucode options */ -#define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ -#define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */ -#define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */ -#define B43_SHM_SH_MACHW_L 0x00C0 /* Location where the ucode expects the MAC capabilities */ -#define B43_SHM_SH_MACHW_H 0x00C2 /* Location where the ucode expects the MAC capabilities */ -#define B43_SHM_SH_HOSTF5 0x00D4 /* Hostflags 5 for ucode options */ -#define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ -/* TSSI information */ -#define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ -#define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */ -#define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */ -#define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */ -/* SHM_SHARED TX FIFO variables */ -#define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */ -#define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */ -#define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */ -#define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */ -/* SHM_SHARED background noise */ -#define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */ -#define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */ -#define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */ -/* SHM_SHARED crypto engine */ -#define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */ -#define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */ -#define B43_SHM_SH_KTP 0x0056 /* Key table pointer */ -#define B43_SHM_SH_TKIPTSCTTAK 0x0318 -#define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */ -#define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */ -/* SHM_SHARED WME variables */ -#define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */ -#define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */ -#define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */ -/* SHM_SHARED powersave mode related */ -#define B43_SHM_SH_SLOTT 0x0010 /* Slot time */ -#define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */ -#define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */ -/* SHM_SHARED beacon/AP variables */ -#define B43_SHM_SH_BT_BASE0 0x0068 /* Beacon template base 0 */ -#define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ -#define B43_SHM_SH_BT_BASE1 0x0468 /* Beacon template base 1 */ -#define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ -#define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ -#define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */ -#define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */ -#define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */ -#define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */ -#define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */ -#define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */ -#define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */ -#define B43_SHM_SH_BCN_LI 0x00B6 /* beacon listen interval */ -/* SHM_SHARED ACK/CTS control */ -#define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */ -/* SHM_SHARED probe response variables */ -#define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */ -#define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */ -#define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ -#define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ -#define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */ -/* SHM_SHARED rate tables */ -#define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */ -#define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */ -#define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */ -#define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */ -/* SHM_SHARED microcode soft registers */ -#define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ -#define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ -#define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ -#define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */ -#define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */ -#define B43_SHM_SH_UCODESTAT_INVALID 0 -#define B43_SHM_SH_UCODESTAT_INIT 1 -#define B43_SHM_SH_UCODESTAT_ACTIVE 2 -#define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */ -#define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */ -#define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */ -#define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ -#define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ -/* SHM_SHARED tx iq workarounds */ -#define B43_SHM_SH_NPHY_TXIQW0 0x0700 -#define B43_SHM_SH_NPHY_TXIQW1 0x0702 -#define B43_SHM_SH_NPHY_TXIQW2 0x0704 -#define B43_SHM_SH_NPHY_TXIQW3 0x0706 -/* SHM_SHARED tx pwr ctrl */ -#define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708 -#define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E - -/* SHM_SCRATCH offsets */ -#define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */ -#define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */ -#define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */ -#define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */ -#define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */ -#define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */ -#define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */ -#define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */ -#define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */ -#define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */ - -/* Hardware Radio Enable masks */ -#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) -#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) - -/* HostFlags. See b43_hf_read/write() */ -#define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */ -#define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */ -#define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */ -#define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */ -#define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */ -#define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */ -#define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */ -#define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */ -#define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */ -#define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */ -#define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */ -#define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */ -#define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */ -#define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */ -#define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */ -#define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */ -#define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */ -#define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */ -#define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */ -#define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */ -#define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */ -#define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */ -#define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */ -#define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */ -#define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */ -#define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */ -#define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */ -#define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */ -#define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */ -#define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */ -#define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */ -#define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */ -#define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */ -#define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */ -#define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */ - -/* Firmware capabilities field in SHM (Opensource firmware only) */ -#define B43_FWCAPA_HWCRYPTO 0x0001 -#define B43_FWCAPA_QOS 0x0002 - -/* MacFilter offsets. */ -#define B43_MACFILTER_SELF 0x0000 -#define B43_MACFILTER_BSSID 0x0003 - -/* PowerControl */ -#define B43_PCTL_IN 0xB0 -#define B43_PCTL_OUT 0xB4 -#define B43_PCTL_OUTENABLE 0xB8 -#define B43_PCTL_XTAL_POWERUP 0x40 -#define B43_PCTL_PLL_POWERDOWN 0x80 - -/* PowerControl Clock Modes */ -#define B43_PCTL_CLK_FAST 0x00 -#define B43_PCTL_CLK_SLOW 0x01 -#define B43_PCTL_CLK_DYNAMIC 0x02 - -#define B43_PCTL_FORCE_SLOW 0x0800 -#define B43_PCTL_FORCE_PLL 0x1000 -#define B43_PCTL_DYN_XTAL 0x2000 - -/* PHYVersioning */ -#define B43_PHYTYPE_A 0x00 -#define B43_PHYTYPE_B 0x01 -#define B43_PHYTYPE_G 0x02 -#define B43_PHYTYPE_N 0x04 -#define B43_PHYTYPE_LP 0x05 -#define B43_PHYTYPE_SSLPN 0x06 -#define B43_PHYTYPE_HT 0x07 -#define B43_PHYTYPE_LCN 0x08 -#define B43_PHYTYPE_LCNXN 0x09 -#define B43_PHYTYPE_LCN40 0x0a -#define B43_PHYTYPE_AC 0x0b - -/* PHYRegisters */ -#define B43_PHY_ILT_A_CTRL 0x0072 -#define B43_PHY_ILT_A_DATA1 0x0073 -#define B43_PHY_ILT_A_DATA2 0x0074 -#define B43_PHY_G_LO_CONTROL 0x0810 -#define B43_PHY_ILT_G_CTRL 0x0472 -#define B43_PHY_ILT_G_DATA1 0x0473 -#define B43_PHY_ILT_G_DATA2 0x0474 -#define B43_PHY_A_PCTL 0x007B -#define B43_PHY_G_PCTL 0x0029 -#define B43_PHY_A_CRS 0x0029 -#define B43_PHY_RADIO_BITFIELD 0x0401 -#define B43_PHY_G_CRS 0x0429 -#define B43_PHY_NRSSILT_CTRL 0x0803 -#define B43_PHY_NRSSILT_DATA 0x0804 - -/* RadioRegisters */ -#define B43_RADIOCTL_ID 0x01 - -/* MAC Control bitfield */ -#define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ -#define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ -#define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ -#define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ -#define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */ -#define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ -#define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */ -#define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */ -#define B43_MACCTL_BE 0x00010000 /* Big Endian mode */ -#define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ -#define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */ -#define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ -#define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ -#define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */ -#define B43_MACCTL_PHY_LOCK 0x00200000 -#define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ -#define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ -#define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ -#define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ -#define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */ -#define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */ -#define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ -#define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */ -#define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */ -#define B43_MACCTL_GMODE 0x80000000 /* G Mode */ - -/* MAC Command bitfield */ -#define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ -#define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ -#define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ -#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ -#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ - -/* B43_MMIO_PSM_PHY_HDR bits */ -#define B43_PSM_HDR_MAC_PHY_RESET 0x00000001 -#define B43_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002 -#define B43_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004 - -/* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */ -#define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100 -#define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200 -#define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000 -#define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000 - -/* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ -#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */ -#define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */ -#define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */ -#define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */ -#define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */ -#define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ -#define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */ -#define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */ -#define B43_BCMA_IOCTL_PHY_BW_80MHZ 0x000000C0 /* 80 MHz bandwidth */ -#define B43_BCMA_IOCTL_DAC 0x00000300 /* Highspeed DAC mode control field */ -#define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */ - -/* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ -#define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */ -#define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */ -#define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */ -#define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */ - -/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ -#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ -#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ -#define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ -#define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */ -#define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */ -#define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ -#define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ -#define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ -#define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ - -/* 802.11 core specific TM State High (SSB_TMSHIGH) flags */ -#define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */ -#define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */ -#define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */ -#define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */ - -/* Generic-Interrupt reasons. */ -#define B43_IRQ_MAC_SUSPENDED 0x00000001 -#define B43_IRQ_BEACON 0x00000002 -#define B43_IRQ_TBTT_INDI 0x00000004 -#define B43_IRQ_BEACON_TX_OK 0x00000008 -#define B43_IRQ_BEACON_CANCEL 0x00000010 -#define B43_IRQ_ATIM_END 0x00000020 -#define B43_IRQ_PMQ 0x00000040 -#define B43_IRQ_PIO_WORKAROUND 0x00000100 -#define B43_IRQ_MAC_TXERR 0x00000200 -#define B43_IRQ_PHY_TXERR 0x00000800 -#define B43_IRQ_PMEVENT 0x00001000 -#define B43_IRQ_TIMER0 0x00002000 -#define B43_IRQ_TIMER1 0x00004000 -#define B43_IRQ_DMA 0x00008000 -#define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000 -#define B43_IRQ_CCA_MEASURE_OK 0x00020000 -#define B43_IRQ_NOISESAMPLE_OK 0x00040000 -#define B43_IRQ_UCODE_DEBUG 0x08000000 -#define B43_IRQ_RFKILL 0x10000000 -#define B43_IRQ_TX_OK 0x20000000 -#define B43_IRQ_PHY_G_CHANGED 0x40000000 -#define B43_IRQ_TIMEOUT 0x80000000 - -#define B43_IRQ_ALL 0xFFFFFFFF -#define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \ - B43_IRQ_ATIM_END | \ - B43_IRQ_PMQ | \ - B43_IRQ_MAC_TXERR | \ - B43_IRQ_PHY_TXERR | \ - B43_IRQ_DMA | \ - B43_IRQ_TXFIFO_FLUSH_OK | \ - B43_IRQ_NOISESAMPLE_OK | \ - B43_IRQ_UCODE_DEBUG | \ - B43_IRQ_RFKILL | \ - B43_IRQ_TX_OK) - -/* The firmware register to fetch the debug-IRQ reason from. */ -#define B43_DEBUGIRQ_REASON_REG 63 -/* Debug-IRQ reasons. */ -#define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */ -#define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */ -#define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */ -#define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */ -#define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */ - -/* The firmware register that contains the "marker" line. */ -#define B43_MARKER_ID_REG 2 -#define B43_MARKER_LINE_REG 3 - -/* The firmware register to fetch the panic reason from. */ -#define B43_FWPANIC_REASON_REG 3 -/* Firmware panic reason codes */ -#define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */ -#define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */ - -/* The firmware register that contains the watchdog counter. */ -#define B43_WATCHDOG_REG 1 - -/* Device specific rate values. - * The actual values defined here are (rate_in_mbps * 2). - * Some code depends on this. Don't change it. */ -#define B43_CCK_RATE_1MB 0x02 -#define B43_CCK_RATE_2MB 0x04 -#define B43_CCK_RATE_5MB 0x0B -#define B43_CCK_RATE_11MB 0x16 -#define B43_OFDM_RATE_6MB 0x0C -#define B43_OFDM_RATE_9MB 0x12 -#define B43_OFDM_RATE_12MB 0x18 -#define B43_OFDM_RATE_18MB 0x24 -#define B43_OFDM_RATE_24MB 0x30 -#define B43_OFDM_RATE_36MB 0x48 -#define B43_OFDM_RATE_48MB 0x60 -#define B43_OFDM_RATE_54MB 0x6C -/* Convert a b43 rate value to a rate in 100kbps */ -#define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2) - -#define B43_DEFAULT_SHORT_RETRY_LIMIT 7 -#define B43_DEFAULT_LONG_RETRY_LIMIT 4 - -#define B43_PHY_TX_BADNESS_LIMIT 1000 - -/* Max size of a security key */ -#define B43_SEC_KEYSIZE 16 -/* Max number of group keys */ -#define B43_NR_GROUP_KEYS 4 -/* Max number of pairwise keys */ -#define B43_NR_PAIRWISE_KEYS 50 -/* Security algorithms. */ -enum { - B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ - B43_SEC_ALGO_WEP40, - B43_SEC_ALGO_TKIP, - B43_SEC_ALGO_AES, - B43_SEC_ALGO_WEP104, - B43_SEC_ALGO_AES_LEGACY, -}; - -struct b43_dmaring; - -/* The firmware file header */ -#define B43_FW_TYPE_UCODE 'u' -#define B43_FW_TYPE_PCM 'p' -#define B43_FW_TYPE_IV 'i' -struct b43_fw_header { - /* File type */ - u8 type; - /* File format version */ - u8 ver; - u8 __padding[2]; - /* Size of the data. For ucode and PCM this is in bytes. - * For IV this is number-of-ivs. */ - __be32 size; -} __packed; - -/* Initial Value file format */ -#define B43_IV_OFFSET_MASK 0x7FFF -#define B43_IV_32BIT 0x8000 -struct b43_iv { - __be16 offset_size; - union { - __be16 d16; - __be32 d32; - } data __packed; -} __packed; - - -/* Data structures for DMA transmission, per 80211 core. */ -struct b43_dma { - struct b43_dmaring *tx_ring_AC_BK; /* Background */ - struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */ - struct b43_dmaring *tx_ring_AC_VI; /* Video */ - struct b43_dmaring *tx_ring_AC_VO; /* Voice */ - struct b43_dmaring *tx_ring_mcast; /* Multicast */ - - struct b43_dmaring *rx_ring; - - u32 translation; /* Routing bits */ - bool translation_in_low; /* Should translation bit go into low addr? */ - bool parity; /* Check for parity */ -}; - -struct b43_pio_txqueue; -struct b43_pio_rxqueue; - -/* Data structures for PIO transmission, per 80211 core. */ -struct b43_pio { - struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */ - struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */ - struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */ - struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */ - struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */ - - struct b43_pio_rxqueue *rx_queue; -}; - -/* Context information for a noise calculation (Link Quality). */ -struct b43_noise_calculation { - bool calculation_running; - u8 nr_samples; - s8 samples[8][4]; -}; - -struct b43_stats { - u8 link_noise; -}; - -struct b43_key { - /* If keyconf is NULL, this key is disabled. - * keyconf is a cookie. Don't derefenrence it outside of the set_key - * path, because b43 doesn't own it. */ - struct ieee80211_key_conf *keyconf; - u8 algorithm; -}; - -/* SHM offsets to the QOS data structures for the 4 different queues. */ -#define B43_QOS_QUEUE_NUM 4 -#define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \ - (B43_NR_QOSPARAMS * sizeof(u16) * (queue))) -#define B43_QOS_BACKGROUND B43_QOS_PARAMS(0) -#define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1) -#define B43_QOS_VIDEO B43_QOS_PARAMS(2) -#define B43_QOS_VOICE B43_QOS_PARAMS(3) - -/* QOS parameter hardware data structure offsets. */ -#define B43_NR_QOSPARAMS 16 -enum { - B43_QOSPARAM_TXOP = 0, - B43_QOSPARAM_CWMIN, - B43_QOSPARAM_CWMAX, - B43_QOSPARAM_CWCUR, - B43_QOSPARAM_AIFS, - B43_QOSPARAM_BSLOTS, - B43_QOSPARAM_REGGAP, - B43_QOSPARAM_STATUS, -}; - -/* QOS parameters for a queue. */ -struct b43_qos_params { - /* The QOS parameters */ - struct ieee80211_tx_queue_params p; -}; - -struct b43_wl; - -/* The type of the firmware file. */ -enum b43_firmware_file_type { - B43_FWTYPE_PROPRIETARY, - B43_FWTYPE_OPENSOURCE, - B43_NR_FWTYPES, -}; - -/* Context data for fetching firmware. */ -struct b43_request_fw_context { - /* The device we are requesting the fw for. */ - struct b43_wldev *dev; - /* a pointer to the firmware object */ - const struct firmware *blob; - /* The type of firmware to request. */ - enum b43_firmware_file_type req_type; - /* Error messages for each firmware type. */ - char errors[B43_NR_FWTYPES][128]; - /* Temporary buffer for storing the firmware name. */ - char fwname[64]; - /* A fatal error occurred while requesting. Firmware request - * can not continue, as any other request will also fail. */ - int fatal_failure; -}; - -/* In-memory representation of a cached microcode file. */ -struct b43_firmware_file { - const char *filename; - const struct firmware *data; - /* Type of the firmware file name. Note that this does only indicate - * the type by the firmware name. NOT the file contents. - * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource - * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware - * binary code, not just the filename. - */ - enum b43_firmware_file_type type; -}; - -enum b43_firmware_hdr_format { - B43_FW_HDR_598, - B43_FW_HDR_410, - B43_FW_HDR_351, -}; - -/* Pointers to the firmware data and meta information about it. */ -struct b43_firmware { - /* Microcode */ - struct b43_firmware_file ucode; - /* PCM code */ - struct b43_firmware_file pcm; - /* Initial MMIO values for the firmware */ - struct b43_firmware_file initvals; - /* Initial MMIO values for the firmware, band-specific */ - struct b43_firmware_file initvals_band; - - /* Firmware revision */ - u16 rev; - /* Firmware patchlevel */ - u16 patch; - - /* Format of header used by firmware */ - enum b43_firmware_hdr_format hdr_format; - - /* Set to true, if we are using an opensource firmware. - * Use this to check for proprietary vs opensource. */ - bool opensource; - /* Set to true, if the core needs a PCM firmware, but - * we failed to load one. This is always false for - * core rev > 10, as these don't need PCM firmware. */ - bool pcm_request_failed; -}; - -enum b43_band { - B43_BAND_2G = 0, - B43_BAND_5G_LO = 1, - B43_BAND_5G_MI = 2, - B43_BAND_5G_HI = 3, -}; - -/* Device (802.11 core) initialization status. */ -enum { - B43_STAT_UNINIT = 0, /* Uninitialized. */ - B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */ - B43_STAT_STARTED = 2, /* Up and running. */ -}; -#define b43_status(wldev) atomic_read(&(wldev)->__init_status) -#define b43_set_status(wldev, stat) do { \ - atomic_set(&(wldev)->__init_status, (stat)); \ - smp_wmb(); \ - } while (0) - -/* Data structure for one wireless device (802.11 core) */ -struct b43_wldev { - struct b43_bus_dev *dev; - struct b43_wl *wl; - /* a completion event structure needed if this call is asynchronous */ - struct completion fw_load_complete; - - /* The device initialization status. - * Use b43_status() to query. */ - atomic_t __init_status; - - bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */ - bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */ - bool radio_hw_enable; /* saved state of radio hardware enabled state */ - bool qos_enabled; /* TRUE, if QoS is used. */ - bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */ - bool use_pio; /* TRUE if next init should use PIO */ - - /* PHY/Radio device. */ - struct b43_phy phy; - - union { - /* DMA engines. */ - struct b43_dma dma; - /* PIO engines. */ - struct b43_pio pio; - }; - /* Use b43_using_pio_transfers() to check whether we are using - * DMA or PIO data transfers. */ - bool __using_pio_transfers; - - /* Various statistics about the physical device. */ - struct b43_stats stats; - - /* Reason code of the last interrupt. */ - u32 irq_reason; - u32 dma_reason[6]; - /* The currently active generic-interrupt mask. */ - u32 irq_mask; - - /* Link Quality calculation context. */ - struct b43_noise_calculation noisecalc; - /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ - int mac_suspended; - - /* Periodic tasks */ - struct delayed_work periodic_work; - unsigned int periodic_state; - - struct work_struct restart_work; - - /* encryption/decryption */ - u16 ktp; /* Key table pointer */ - struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS]; - - /* Firmware data */ - struct b43_firmware fw; - - /* Devicelist in struct b43_wl (all 802.11 cores) */ - struct list_head list; - - /* Debugging stuff follows. */ -#ifdef CONFIG_B43_DEBUG - struct b43_dfsentry *dfsentry; - unsigned int irq_count; - unsigned int irq_bit_count[32]; - unsigned int tx_count; - unsigned int rx_count; -#endif -}; - -/* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */ -struct b43_wl { - /* Pointer to the active wireless device on this chip */ - struct b43_wldev *current_dev; - /* Pointer to the ieee80211 hardware data structure */ - struct ieee80211_hw *hw; - - /* Global driver mutex. Every operation must run with this mutex locked. */ - struct mutex mutex; - /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ - * handler, only. This basically is just the IRQ mask register. */ - spinlock_t hardirq_lock; - - /* Set this if we call ieee80211_register_hw() and check if we call - * ieee80211_unregister_hw(). */ - bool hw_registred; - - /* We can only have one operating interface (802.11 core) - * at a time. General information about this interface follows. - */ - - struct ieee80211_vif *vif; - /* The MAC address of the operating interface. */ - u8 mac_addr[ETH_ALEN]; - /* Current BSSID */ - u8 bssid[ETH_ALEN]; - /* Interface type. (NL80211_IFTYPE_XXX) */ - int if_type; - /* Is the card operating in AP, STA or IBSS mode? */ - bool operating; - /* filter flags */ - unsigned int filter_flags; - /* Stats about the wireless interface */ - struct ieee80211_low_level_stats ieee_stats; - -#ifdef CONFIG_B43_HWRNG - struct hwrng rng; - bool rng_initialized; - char rng_name[30 + 1]; -#endif /* CONFIG_B43_HWRNG */ - - bool radiotap_enabled; - bool radio_enabled; - - /* The beacon we are currently using (AP or IBSS mode). */ - struct sk_buff *current_beacon; - bool beacon0_uploaded; - bool beacon1_uploaded; - bool beacon_templates_virgin; /* Never wrote the templates? */ - struct work_struct beacon_update_trigger; - spinlock_t beacon_lock; - - /* The current QOS parameters for the 4 queues. */ - struct b43_qos_params qos_params[B43_QOS_QUEUE_NUM]; - - /* Work for adjustment of the transmission power. - * This is scheduled when we determine that the actual TX output - * power doesn't match what we want. */ - struct work_struct txpower_adjust_work; - - /* Packet transmit work */ - struct work_struct tx_work; - - /* Queue of packets to be transmitted. */ - struct sk_buff_head tx_queue[B43_QOS_QUEUE_NUM]; - - /* Flag that implement the queues stopping. */ - bool tx_queue_stopped[B43_QOS_QUEUE_NUM]; - - /* firmware loading work */ - struct work_struct firmware_load; - - /* The device LEDs. */ - struct b43_leds leds; - - /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */ - u8 pio_scratchspace[118] __attribute__((__aligned__(8))); - u8 pio_tailspace[4] __attribute__((__aligned__(8))); -}; - -static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw) -{ - return hw->priv; -} - -static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev) -{ - struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); - return ssb_get_drvdata(ssb_dev); -} - -/* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */ -static inline int b43_is_mode(struct b43_wl *wl, int type) -{ - return (wl->operating && wl->if_type == type); -} - -/** - * b43_current_band - Returns the currently used band. - * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ. - */ -static inline enum ieee80211_band b43_current_band(struct b43_wl *wl) -{ - return wl->hw->conf.chandef.chan->band; -} - -static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) -{ - return wldev->dev->bus_may_powerdown(wldev->dev); -} -static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl) -{ - return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl); -} -static inline int b43_device_is_enabled(struct b43_wldev *wldev) -{ - return wldev->dev->device_is_enabled(wldev->dev); -} -static inline void b43_device_enable(struct b43_wldev *wldev, - u32 core_specific_flags) -{ - wldev->dev->device_enable(wldev->dev, core_specific_flags); -} -static inline void b43_device_disable(struct b43_wldev *wldev, - u32 core_specific_flags) -{ - wldev->dev->device_disable(wldev->dev, core_specific_flags); -} - -static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) -{ - return dev->dev->read16(dev->dev, offset); -} - -static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) -{ - dev->dev->write16(dev->dev, offset, value); -} - -/* To optimize this check for flush_writes on BCM47XX_BCMA only. */ -static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value) -{ - b43_write16(dev, offset, value); -#if defined(CONFIG_BCM47XX_BCMA) - if (dev->dev->flush_writes) - b43_read16(dev, offset); -#endif -} - -static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask, - u16 set) -{ - b43_write16(dev, offset, (b43_read16(dev, offset) & mask) | set); -} - -static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) -{ - return dev->dev->read32(dev->dev, offset); -} - -static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) -{ - dev->dev->write32(dev->dev, offset, value); -} - -static inline void b43_maskset32(struct b43_wldev *dev, u16 offset, u32 mask, - u32 set) -{ - b43_write32(dev, offset, (b43_read32(dev, offset) & mask) | set); -} - -static inline void b43_block_read(struct b43_wldev *dev, void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - dev->dev->block_read(dev->dev, buffer, count, offset, reg_width); -} - -static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - dev->dev->block_write(dev->dev, buffer, count, offset, reg_width); -} - -static inline bool b43_using_pio_transfers(struct b43_wldev *dev) -{ - return dev->__using_pio_transfers; -} - -/* Message printing */ -__printf(2, 3) void b43info(struct b43_wl *wl, const char *fmt, ...); -__printf(2, 3) void b43err(struct b43_wl *wl, const char *fmt, ...); -__printf(2, 3) void b43warn(struct b43_wl *wl, const char *fmt, ...); -__printf(2, 3) void b43dbg(struct b43_wl *wl, const char *fmt, ...); - - -/* A WARN_ON variant that vanishes when b43 debugging is disabled. - * This _also_ evaluates the arg with debugging disabled. */ -#if B43_DEBUG -# define B43_WARN_ON(x) WARN_ON(x) -#else -static inline bool __b43_warn_on_dummy(bool x) { return x; } -# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x))) -#endif - -/* Convert an integer to a Q5.2 value */ -#define INT_TO_Q52(i) ((i) << 2) -/* Convert a Q5.2 value to an integer (precision loss!) */ -#define Q52_TO_INT(q52) ((q52) >> 2) -/* Macros for printing a value in Q5.2 format */ -#define Q52_FMT "%u.%u" -#define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4) - -#endif /* B43_H_ */ diff --git a/drivers/net/wireless/b43/bus.c b/drivers/net/wireless/b43/bus.c deleted file mode 100644 index 17d16a391..000000000 --- a/drivers/net/wireless/b43/bus.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - - Broadcom B43 wireless driver - Bus abstraction layer - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#ifdef CONFIG_BCM47XX_BCMA -#include <asm/mach-bcm47xx/bcm47xx.h> -#endif - -#include "b43.h" -#include "bus.h" - -/* BCMA */ -#ifdef CONFIG_B43_BCMA -static int b43_bus_bcma_bus_may_powerdown(struct b43_bus_dev *dev) -{ - return 0; /* bcma_bus_may_powerdown(dev->bdev->bus); */ -} -static int b43_bus_bcma_bus_powerup(struct b43_bus_dev *dev, - bool dynamic_pctl) -{ - return 0; /* bcma_bus_powerup(dev->sdev->bus, dynamic_pctl); */ -} -static int b43_bus_bcma_device_is_enabled(struct b43_bus_dev *dev) -{ - return bcma_core_is_enabled(dev->bdev); -} -static void b43_bus_bcma_device_enable(struct b43_bus_dev *dev, - u32 core_specific_flags) -{ - bcma_core_enable(dev->bdev, core_specific_flags); -} -static void b43_bus_bcma_device_disable(struct b43_bus_dev *dev, - u32 core_specific_flags) -{ - bcma_core_disable(dev->bdev, core_specific_flags); -} -static u16 b43_bus_bcma_read16(struct b43_bus_dev *dev, u16 offset) -{ - return bcma_read16(dev->bdev, offset); -} -static u32 b43_bus_bcma_read32(struct b43_bus_dev *dev, u16 offset) -{ - return bcma_read32(dev->bdev, offset); -} -static -void b43_bus_bcma_write16(struct b43_bus_dev *dev, u16 offset, u16 value) -{ - bcma_write16(dev->bdev, offset, value); -} -static -void b43_bus_bcma_write32(struct b43_bus_dev *dev, u16 offset, u32 value) -{ - bcma_write32(dev->bdev, offset, value); -} -static -void b43_bus_bcma_block_read(struct b43_bus_dev *dev, void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - bcma_block_read(dev->bdev, buffer, count, offset, reg_width); -} -static -void b43_bus_bcma_block_write(struct b43_bus_dev *dev, const void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - bcma_block_write(dev->bdev, buffer, count, offset, reg_width); -} - -struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core) -{ - struct b43_bus_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL); - if (!dev) - return NULL; - - dev->bus_type = B43_BUS_BCMA; - dev->bdev = core; - - dev->bus_may_powerdown = b43_bus_bcma_bus_may_powerdown; - dev->bus_powerup = b43_bus_bcma_bus_powerup; - dev->device_is_enabled = b43_bus_bcma_device_is_enabled; - dev->device_enable = b43_bus_bcma_device_enable; - dev->device_disable = b43_bus_bcma_device_disable; - - dev->read16 = b43_bus_bcma_read16; - dev->read32 = b43_bus_bcma_read32; - dev->write16 = b43_bus_bcma_write16; - dev->write32 = b43_bus_bcma_write32; - dev->block_read = b43_bus_bcma_block_read; - dev->block_write = b43_bus_bcma_block_write; -#ifdef CONFIG_BCM47XX_BCMA - if (b43_bus_host_is_pci(dev) && - bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA && - bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4716) - dev->flush_writes = true; -#endif - - dev->dev = &core->dev; - dev->dma_dev = core->dma_dev; - dev->irq = core->irq; - - dev->board_vendor = core->bus->boardinfo.vendor; - dev->board_type = core->bus->boardinfo.type; - dev->board_rev = core->bus->sprom.board_rev; - - dev->chip_id = core->bus->chipinfo.id; - dev->chip_rev = core->bus->chipinfo.rev; - dev->chip_pkg = core->bus->chipinfo.pkg; - - dev->bus_sprom = &core->bus->sprom; - - dev->core_id = core->id.id; - dev->core_rev = core->id.rev; - - return dev; -} -#endif /* CONFIG_B43_BCMA */ - -/* SSB */ -#ifdef CONFIG_B43_SSB -static int b43_bus_ssb_bus_may_powerdown(struct b43_bus_dev *dev) -{ - return ssb_bus_may_powerdown(dev->sdev->bus); -} -static int b43_bus_ssb_bus_powerup(struct b43_bus_dev *dev, - bool dynamic_pctl) -{ - return ssb_bus_powerup(dev->sdev->bus, dynamic_pctl); -} -static int b43_bus_ssb_device_is_enabled(struct b43_bus_dev *dev) -{ - return ssb_device_is_enabled(dev->sdev); -} -static void b43_bus_ssb_device_enable(struct b43_bus_dev *dev, - u32 core_specific_flags) -{ - ssb_device_enable(dev->sdev, core_specific_flags); -} -static void b43_bus_ssb_device_disable(struct b43_bus_dev *dev, - u32 core_specific_flags) -{ - ssb_device_disable(dev->sdev, core_specific_flags); -} - -static u16 b43_bus_ssb_read16(struct b43_bus_dev *dev, u16 offset) -{ - return ssb_read16(dev->sdev, offset); -} -static u32 b43_bus_ssb_read32(struct b43_bus_dev *dev, u16 offset) -{ - return ssb_read32(dev->sdev, offset); -} -static void b43_bus_ssb_write16(struct b43_bus_dev *dev, u16 offset, u16 value) -{ - ssb_write16(dev->sdev, offset, value); -} -static void b43_bus_ssb_write32(struct b43_bus_dev *dev, u16 offset, u32 value) -{ - ssb_write32(dev->sdev, offset, value); -} -static void b43_bus_ssb_block_read(struct b43_bus_dev *dev, void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - ssb_block_read(dev->sdev, buffer, count, offset, reg_width); -} -static -void b43_bus_ssb_block_write(struct b43_bus_dev *dev, const void *buffer, - size_t count, u16 offset, u8 reg_width) -{ - ssb_block_write(dev->sdev, buffer, count, offset, reg_width); -} - -struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev) -{ - struct b43_bus_dev *dev; - - dev = kzalloc(sizeof(*dev), GFP_KERNEL); - if (!dev) - return NULL; - - dev->bus_type = B43_BUS_SSB; - dev->sdev = sdev; - - dev->bus_may_powerdown = b43_bus_ssb_bus_may_powerdown; - dev->bus_powerup = b43_bus_ssb_bus_powerup; - dev->device_is_enabled = b43_bus_ssb_device_is_enabled; - dev->device_enable = b43_bus_ssb_device_enable; - dev->device_disable = b43_bus_ssb_device_disable; - - dev->read16 = b43_bus_ssb_read16; - dev->read32 = b43_bus_ssb_read32; - dev->write16 = b43_bus_ssb_write16; - dev->write32 = b43_bus_ssb_write32; - dev->block_read = b43_bus_ssb_block_read; - dev->block_write = b43_bus_ssb_block_write; - - dev->dev = sdev->dev; - dev->dma_dev = sdev->dma_dev; - dev->irq = sdev->irq; - - dev->board_vendor = sdev->bus->boardinfo.vendor; - dev->board_type = sdev->bus->boardinfo.type; - dev->board_rev = sdev->bus->sprom.board_rev; - - dev->chip_id = sdev->bus->chip_id; - dev->chip_rev = sdev->bus->chip_rev; - dev->chip_pkg = sdev->bus->chip_package; - - dev->bus_sprom = &sdev->bus->sprom; - - dev->core_id = sdev->id.coreid; - dev->core_rev = sdev->id.revision; - - return dev; -} -#endif /* CONFIG_B43_SSB */ - -void *b43_bus_get_wldev(struct b43_bus_dev *dev) -{ - switch (dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - return bcma_get_drvdata(dev->bdev); -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - return ssb_get_drvdata(dev->sdev); -#endif - } - return NULL; -} - -void b43_bus_set_wldev(struct b43_bus_dev *dev, void *wldev) -{ - switch (dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_set_drvdata(dev->bdev, wldev); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - ssb_set_drvdata(dev->sdev, wldev); - break; -#endif - } -} diff --git a/drivers/net/wireless/b43/bus.h b/drivers/net/wireless/b43/bus.h deleted file mode 100644 index 256c2c179..000000000 --- a/drivers/net/wireless/b43/bus.h +++ /dev/null @@ -1,95 +0,0 @@ -#ifndef B43_BUS_H_ -#define B43_BUS_H_ - -enum b43_bus_type { -#ifdef CONFIG_B43_BCMA - B43_BUS_BCMA, -#endif -#ifdef CONFIG_B43_SSB - B43_BUS_SSB, -#endif -}; - -struct b43_bus_dev { - enum b43_bus_type bus_type; - union { - struct bcma_device *bdev; - struct ssb_device *sdev; - }; - - int (*bus_may_powerdown)(struct b43_bus_dev *dev); - int (*bus_powerup)(struct b43_bus_dev *dev, bool dynamic_pctl); - int (*device_is_enabled)(struct b43_bus_dev *dev); - void (*device_enable)(struct b43_bus_dev *dev, - u32 core_specific_flags); - void (*device_disable)(struct b43_bus_dev *dev, - u32 core_specific_flags); - - u16 (*read16)(struct b43_bus_dev *dev, u16 offset); - u32 (*read32)(struct b43_bus_dev *dev, u16 offset); - void (*write16)(struct b43_bus_dev *dev, u16 offset, u16 value); - void (*write32)(struct b43_bus_dev *dev, u16 offset, u32 value); - void (*block_read)(struct b43_bus_dev *dev, void *buffer, - size_t count, u16 offset, u8 reg_width); - void (*block_write)(struct b43_bus_dev *dev, const void *buffer, - size_t count, u16 offset, u8 reg_width); - bool flush_writes; - - struct device *dev; - struct device *dma_dev; - unsigned int irq; - - u16 board_vendor; - u16 board_type; - u16 board_rev; - - u16 chip_id; - u8 chip_rev; - u8 chip_pkg; - - struct ssb_sprom *bus_sprom; - - u16 core_id; - u8 core_rev; -}; - -static inline bool b43_bus_host_is_pcmcia(struct b43_bus_dev *dev) -{ -#ifdef CONFIG_B43_SSB - return (dev->bus_type == B43_BUS_SSB && - dev->sdev->bus->bustype == SSB_BUSTYPE_PCMCIA); -#else - return false; -#endif -}; - -static inline bool b43_bus_host_is_pci(struct b43_bus_dev *dev) -{ -#ifdef CONFIG_B43_BCMA - if (dev->bus_type == B43_BUS_BCMA) - return (dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI); -#endif -#ifdef CONFIG_B43_SSB - if (dev->bus_type == B43_BUS_SSB) - return (dev->sdev->bus->bustype == SSB_BUSTYPE_PCI); -#endif - return false; -} - -static inline bool b43_bus_host_is_sdio(struct b43_bus_dev *dev) -{ -#ifdef CONFIG_B43_SSB - return (dev->bus_type == B43_BUS_SSB && - dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO); -#else - return false; -#endif -} - -struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core); -struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev); - -void *b43_bus_get_wldev(struct b43_bus_dev *dev); -void b43_bus_set_wldev(struct b43_bus_dev *dev, void *data); - -#endif /* B43_BUS_H_ */ diff --git a/drivers/net/wireless/b43/debugfs.c b/drivers/net/wireless/b43/debugfs.c deleted file mode 100644 index b4bcd94af..000000000 --- a/drivers/net/wireless/b43/debugfs.c +++ /dev/null @@ -1,826 +0,0 @@ -/* - - Broadcom B43 wireless driver - - debugfs driver debugging code - - Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/fs.h> -#include <linux/debugfs.h> -#include <linux/slab.h> -#include <linux/netdevice.h> -#include <linux/pci.h> -#include <linux/mutex.h> - -#include "b43.h" -#include "main.h" -#include "debugfs.h" -#include "dma.h" -#include "xmit.h" - - -/* The root directory. */ -static struct dentry *rootdir; - -struct b43_debugfs_fops { - ssize_t (*read)(struct b43_wldev *dev, char *buf, size_t bufsize); - int (*write)(struct b43_wldev *dev, const char *buf, size_t count); - struct file_operations fops; - /* Offset of struct b43_dfs_file in struct b43_dfsentry */ - size_t file_struct_offset; -}; - -static inline -struct b43_dfs_file *fops_to_dfs_file(struct b43_wldev *dev, - const struct b43_debugfs_fops *dfops) -{ - void *p; - - p = dev->dfsentry; - p += dfops->file_struct_offset; - - return p; -} - - -#define fappend(fmt, x...) \ - do { \ - if (bufsize - count) \ - count += snprintf(buf + count, \ - bufsize - count, \ - fmt , ##x); \ - else \ - printk(KERN_ERR "b43: fappend overflow\n"); \ - } while (0) - - -/* The biggest address values for SHM access from the debugfs files. */ -#define B43_MAX_SHM_ROUTING 4 -#define B43_MAX_SHM_ADDR 0xFFFF - -static ssize_t shm16read__read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - ssize_t count = 0; - unsigned int routing, addr; - u16 val; - - routing = dev->dfsentry->shm16read_routing_next; - addr = dev->dfsentry->shm16read_addr_next; - if ((routing > B43_MAX_SHM_ROUTING) || - (addr > B43_MAX_SHM_ADDR)) - return -EDESTADDRREQ; - - val = b43_shm_read16(dev, routing, addr); - fappend("0x%04X\n", val); - - return count; -} - -static int shm16read__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int routing, addr; - int res; - - res = sscanf(buf, "0x%X 0x%X", &routing, &addr); - if (res != 2) - return -EINVAL; - if (routing > B43_MAX_SHM_ROUTING) - return -EADDRNOTAVAIL; - if (addr > B43_MAX_SHM_ADDR) - return -EADDRNOTAVAIL; - if (routing == B43_SHM_SHARED) { - if ((addr % 2) != 0) - return -EADDRNOTAVAIL; - } - - dev->dfsentry->shm16read_routing_next = routing; - dev->dfsentry->shm16read_addr_next = addr; - - return 0; -} - -static int shm16write__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int routing, addr, mask, set; - u16 val; - int res; - - res = sscanf(buf, "0x%X 0x%X 0x%X 0x%X", - &routing, &addr, &mask, &set); - if (res != 4) - return -EINVAL; - if (routing > B43_MAX_SHM_ROUTING) - return -EADDRNOTAVAIL; - if (addr > B43_MAX_SHM_ADDR) - return -EADDRNOTAVAIL; - if (routing == B43_SHM_SHARED) { - if ((addr % 2) != 0) - return -EADDRNOTAVAIL; - } - if ((mask > 0xFFFF) || (set > 0xFFFF)) - return -E2BIG; - - if (mask == 0) - val = 0; - else - val = b43_shm_read16(dev, routing, addr); - val &= mask; - val |= set; - b43_shm_write16(dev, routing, addr, val); - - return 0; -} - -static ssize_t shm32read__read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - ssize_t count = 0; - unsigned int routing, addr; - u32 val; - - routing = dev->dfsentry->shm32read_routing_next; - addr = dev->dfsentry->shm32read_addr_next; - if ((routing > B43_MAX_SHM_ROUTING) || - (addr > B43_MAX_SHM_ADDR)) - return -EDESTADDRREQ; - - val = b43_shm_read32(dev, routing, addr); - fappend("0x%08X\n", val); - - return count; -} - -static int shm32read__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int routing, addr; - int res; - - res = sscanf(buf, "0x%X 0x%X", &routing, &addr); - if (res != 2) - return -EINVAL; - if (routing > B43_MAX_SHM_ROUTING) - return -EADDRNOTAVAIL; - if (addr > B43_MAX_SHM_ADDR) - return -EADDRNOTAVAIL; - if (routing == B43_SHM_SHARED) { - if ((addr % 2) != 0) - return -EADDRNOTAVAIL; - } - - dev->dfsentry->shm32read_routing_next = routing; - dev->dfsentry->shm32read_addr_next = addr; - - return 0; -} - -static int shm32write__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int routing, addr, mask, set; - u32 val; - int res; - - res = sscanf(buf, "0x%X 0x%X 0x%X 0x%X", - &routing, &addr, &mask, &set); - if (res != 4) - return -EINVAL; - if (routing > B43_MAX_SHM_ROUTING) - return -EADDRNOTAVAIL; - if (addr > B43_MAX_SHM_ADDR) - return -EADDRNOTAVAIL; - if (routing == B43_SHM_SHARED) { - if ((addr % 2) != 0) - return -EADDRNOTAVAIL; - } - if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF)) - return -E2BIG; - - if (mask == 0) - val = 0; - else - val = b43_shm_read32(dev, routing, addr); - val &= mask; - val |= set; - b43_shm_write32(dev, routing, addr, val); - - return 0; -} - -/* The biggest MMIO address that we allow access to from the debugfs files. */ -#define B43_MAX_MMIO_ACCESS (0xF00 - 1) - -static ssize_t mmio16read__read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - ssize_t count = 0; - unsigned int addr; - u16 val; - - addr = dev->dfsentry->mmio16read_next; - if (addr > B43_MAX_MMIO_ACCESS) - return -EDESTADDRREQ; - - val = b43_read16(dev, addr); - fappend("0x%04X\n", val); - - return count; -} - -static int mmio16read__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int addr; - int res; - - res = sscanf(buf, "0x%X", &addr); - if (res != 1) - return -EINVAL; - if (addr > B43_MAX_MMIO_ACCESS) - return -EADDRNOTAVAIL; - if ((addr % 2) != 0) - return -EINVAL; - - dev->dfsentry->mmio16read_next = addr; - - return 0; -} - -static int mmio16write__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int addr, mask, set; - int res; - u16 val; - - res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set); - if (res != 3) - return -EINVAL; - if (addr > B43_MAX_MMIO_ACCESS) - return -EADDRNOTAVAIL; - if ((mask > 0xFFFF) || (set > 0xFFFF)) - return -E2BIG; - if ((addr % 2) != 0) - return -EINVAL; - - if (mask == 0) - val = 0; - else - val = b43_read16(dev, addr); - val &= mask; - val |= set; - b43_write16(dev, addr, val); - - return 0; -} - -static ssize_t mmio32read__read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - ssize_t count = 0; - unsigned int addr; - u32 val; - - addr = dev->dfsentry->mmio32read_next; - if (addr > B43_MAX_MMIO_ACCESS) - return -EDESTADDRREQ; - - val = b43_read32(dev, addr); - fappend("0x%08X\n", val); - - return count; -} - -static int mmio32read__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int addr; - int res; - - res = sscanf(buf, "0x%X", &addr); - if (res != 1) - return -EINVAL; - if (addr > B43_MAX_MMIO_ACCESS) - return -EADDRNOTAVAIL; - if ((addr % 4) != 0) - return -EINVAL; - - dev->dfsentry->mmio32read_next = addr; - - return 0; -} - -static int mmio32write__write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - unsigned int addr, mask, set; - int res; - u32 val; - - res = sscanf(buf, "0x%X 0x%X 0x%X", &addr, &mask, &set); - if (res != 3) - return -EINVAL; - if (addr > B43_MAX_MMIO_ACCESS) - return -EADDRNOTAVAIL; - if ((mask > 0xFFFFFFFF) || (set > 0xFFFFFFFF)) - return -E2BIG; - if ((addr % 4) != 0) - return -EINVAL; - - if (mask == 0) - val = 0; - else - val = b43_read32(dev, addr); - val &= mask; - val |= set; - b43_write32(dev, addr, val); - - return 0; -} - -static ssize_t txstat_read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - struct b43_txstatus_log *log = &dev->dfsentry->txstatlog; - ssize_t count = 0; - int i, idx; - struct b43_txstatus *stat; - - if (log->end < 0) { - fappend("Nothing transmitted, yet\n"); - goto out; - } - fappend("b43 TX status reports:\n\n" - "index | cookie | seq | phy_stat | frame_count | " - "rts_count | supp_reason | pm_indicated | " - "intermediate | for_ampdu | acked\n" "---\n"); - i = log->end + 1; - idx = 0; - while (1) { - if (i == B43_NR_LOGGED_TXSTATUS) - i = 0; - stat = &(log->log[i]); - if (stat->cookie) { - fappend("%03d | " - "0x%04X | 0x%04X | 0x%02X | " - "0x%X | 0x%X | " - "%u | %u | " - "%u | %u | %u\n", - idx, - stat->cookie, stat->seq, stat->phy_stat, - stat->frame_count, stat->rts_count, - stat->supp_reason, stat->pm_indicated, - stat->intermediate, stat->for_ampdu, - stat->acked); - idx++; - } - if (i == log->end) - break; - i++; - } -out: - - return count; -} - -static int restart_write_file(struct b43_wldev *dev, - const char *buf, size_t count) -{ - int err = 0; - - if (count > 0 && buf[0] == '1') { - b43_controller_restart(dev, "manually restarted"); - } else - err = -EINVAL; - - return err; -} - -static unsigned long calc_expire_secs(unsigned long now, - unsigned long time, - unsigned long expire) -{ - expire = time + expire; - - if (time_after(now, expire)) - return 0; /* expired */ - if (expire < now) { - /* jiffies wrapped */ - expire -= MAX_JIFFY_OFFSET; - now -= MAX_JIFFY_OFFSET; - } - B43_WARN_ON(expire < now); - - return (expire - now) / HZ; -} - -static ssize_t loctls_read_file(struct b43_wldev *dev, - char *buf, size_t bufsize) -{ - ssize_t count = 0; - struct b43_txpower_lo_control *lo; - int i, err = 0; - struct b43_lo_calib *cal; - unsigned long now = jiffies; - struct b43_phy *phy = &dev->phy; - - if (phy->type != B43_PHYTYPE_G) { - fappend("Device is not a G-PHY\n"); - err = -ENODEV; - goto out; - } - lo = phy->g->lo_control; - fappend("-- Local Oscillator calibration data --\n\n"); - fappend("HW-power-control enabled: %d\n", - dev->phy.hardware_power_control); - fappend("TX Bias: 0x%02X, TX Magn: 0x%02X (expire in %lu sec)\n", - lo->tx_bias, lo->tx_magn, - calc_expire_secs(now, lo->txctl_measured_time, - B43_LO_TXCTL_EXPIRE)); - fappend("Power Vector: 0x%08X%08X (expires in %lu sec)\n", - (unsigned int)((lo->power_vector & 0xFFFFFFFF00000000ULL) >> 32), - (unsigned int)(lo->power_vector & 0x00000000FFFFFFFFULL), - calc_expire_secs(now, lo->pwr_vec_read_time, - B43_LO_PWRVEC_EXPIRE)); - - fappend("\nCalibrated settings:\n"); - list_for_each_entry(cal, &lo->calib_list, list) { - bool active; - - active = (b43_compare_bbatt(&cal->bbatt, &phy->g->bbatt) && - b43_compare_rfatt(&cal->rfatt, &phy->g->rfatt)); - fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d " - "(expires in %lu sec)%s\n", - cal->bbatt.att, - cal->rfatt.att, cal->rfatt.with_padmix, - cal->ctl.i, cal->ctl.q, - calc_expire_secs(now, cal->calib_time, - B43_LO_CALIB_EXPIRE), - active ? " ACTIVE" : ""); - } - - fappend("\nUsed RF attenuation values: Value(WithPadmix flag)\n"); - for (i = 0; i < lo->rfatt_list.len; i++) { - fappend("%u(%d), ", - lo->rfatt_list.list[i].att, - lo->rfatt_list.list[i].with_padmix); - } - fappend("\n"); - fappend("\nUsed Baseband attenuation values:\n"); - for (i = 0; i < lo->bbatt_list.len; i++) { - fappend("%u, ", - lo->bbatt_list.list[i].att); - } - fappend("\n"); - -out: - return err ? err : count; -} - -#undef fappend - -static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct b43_wldev *dev; - struct b43_debugfs_fops *dfops; - struct b43_dfs_file *dfile; - ssize_t uninitialized_var(ret); - char *buf; - const size_t bufsize = 1024 * 16; /* 16 kiB buffer */ - const size_t buforder = get_order(bufsize); - int err = 0; - - if (!count) - return 0; - dev = file->private_data; - if (!dev) - return -ENODEV; - - mutex_lock(&dev->wl->mutex); - if (b43_status(dev) < B43_STAT_INITIALIZED) { - err = -ENODEV; - goto out_unlock; - } - - dfops = container_of(file->f_op, struct b43_debugfs_fops, fops); - if (!dfops->read) { - err = -ENOSYS; - goto out_unlock; - } - dfile = fops_to_dfs_file(dev, dfops); - - if (!dfile->buffer) { - buf = (char *)__get_free_pages(GFP_KERNEL, buforder); - if (!buf) { - err = -ENOMEM; - goto out_unlock; - } - memset(buf, 0, bufsize); - ret = dfops->read(dev, buf, bufsize); - if (ret <= 0) { - free_pages((unsigned long)buf, buforder); - err = ret; - goto out_unlock; - } - dfile->data_len = ret; - dfile->buffer = buf; - } - - ret = simple_read_from_buffer(userbuf, count, ppos, - dfile->buffer, - dfile->data_len); - if (*ppos >= dfile->data_len) { - free_pages((unsigned long)dfile->buffer, buforder); - dfile->buffer = NULL; - dfile->data_len = 0; - } -out_unlock: - mutex_unlock(&dev->wl->mutex); - - return err ? err : ret; -} - -static ssize_t b43_debugfs_write(struct file *file, - const char __user *userbuf, - size_t count, loff_t *ppos) -{ - struct b43_wldev *dev; - struct b43_debugfs_fops *dfops; - char *buf; - int err = 0; - - if (!count) - return 0; - if (count > PAGE_SIZE) - return -E2BIG; - dev = file->private_data; - if (!dev) - return -ENODEV; - - mutex_lock(&dev->wl->mutex); - if (b43_status(dev) < B43_STAT_INITIALIZED) { - err = -ENODEV; - goto out_unlock; - } - - dfops = container_of(file->f_op, struct b43_debugfs_fops, fops); - if (!dfops->write) { - err = -ENOSYS; - goto out_unlock; - } - - buf = (char *)get_zeroed_page(GFP_KERNEL); - if (!buf) { - err = -ENOMEM; - goto out_unlock; - } - if (copy_from_user(buf, userbuf, count)) { - err = -EFAULT; - goto out_freepage; - } - err = dfops->write(dev, buf, count); - if (err) - goto out_freepage; - -out_freepage: - free_page((unsigned long)buf); -out_unlock: - mutex_unlock(&dev->wl->mutex); - - return err ? err : count; -} - - -#define B43_DEBUGFS_FOPS(name, _read, _write) \ - static struct b43_debugfs_fops fops_##name = { \ - .read = _read, \ - .write = _write, \ - .fops = { \ - .open = simple_open, \ - .read = b43_debugfs_read, \ - .write = b43_debugfs_write, \ - .llseek = generic_file_llseek, \ - }, \ - .file_struct_offset = offsetof(struct b43_dfsentry, \ - file_##name), \ - } - -B43_DEBUGFS_FOPS(shm16read, shm16read__read_file, shm16read__write_file); -B43_DEBUGFS_FOPS(shm16write, NULL, shm16write__write_file); -B43_DEBUGFS_FOPS(shm32read, shm32read__read_file, shm32read__write_file); -B43_DEBUGFS_FOPS(shm32write, NULL, shm32write__write_file); -B43_DEBUGFS_FOPS(mmio16read, mmio16read__read_file, mmio16read__write_file); -B43_DEBUGFS_FOPS(mmio16write, NULL, mmio16write__write_file); -B43_DEBUGFS_FOPS(mmio32read, mmio32read__read_file, mmio32read__write_file); -B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file); -B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL); -B43_DEBUGFS_FOPS(restart, NULL, restart_write_file); -B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL); - - -bool b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature) -{ - bool enabled; - - enabled = (dev->dfsentry && dev->dfsentry->dyn_debug[feature]); - if (unlikely(enabled)) { - /* Force full debugging messages, if the user enabled - * some dynamic debugging feature. */ - b43_modparam_verbose = B43_VERBOSITY_MAX; - } - - return enabled; -} - -static void b43_remove_dynamic_debug(struct b43_wldev *dev) -{ - struct b43_dfsentry *e = dev->dfsentry; - int i; - - for (i = 0; i < __B43_NR_DYNDBG; i++) - debugfs_remove(e->dyn_debug_dentries[i]); -} - -static void b43_add_dynamic_debug(struct b43_wldev *dev) -{ - struct b43_dfsentry *e = dev->dfsentry; - struct dentry *d; - -#define add_dyn_dbg(name, id, initstate) do { \ - e->dyn_debug[id] = (initstate); \ - d = debugfs_create_bool(name, 0600, e->subdir, \ - &(e->dyn_debug[id])); \ - if (!IS_ERR(d)) \ - e->dyn_debug_dentries[id] = d; \ - } while (0) - - add_dyn_dbg("debug_xmitpower", B43_DBG_XMITPOWER, false); - add_dyn_dbg("debug_dmaoverflow", B43_DBG_DMAOVERFLOW, false); - add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, false); - add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, false); - add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, false); - add_dyn_dbg("debug_lo", B43_DBG_LO, false); - add_dyn_dbg("debug_firmware", B43_DBG_FIRMWARE, false); - add_dyn_dbg("debug_keys", B43_DBG_KEYS, false); - add_dyn_dbg("debug_verbose_stats", B43_DBG_VERBOSESTATS, false); - -#undef add_dyn_dbg -} - -void b43_debugfs_add_device(struct b43_wldev *dev) -{ - struct b43_dfsentry *e; - struct b43_txstatus_log *log; - char devdir[16]; - - B43_WARN_ON(!dev); - e = kzalloc(sizeof(*e), GFP_KERNEL); - if (!e) { - b43err(dev->wl, "debugfs: add device OOM\n"); - return; - } - e->dev = dev; - log = &e->txstatlog; - log->log = kcalloc(B43_NR_LOGGED_TXSTATUS, - sizeof(struct b43_txstatus), GFP_KERNEL); - if (!log->log) { - b43err(dev->wl, "debugfs: add device txstatus OOM\n"); - kfree(e); - return; - } - log->end = -1; - - dev->dfsentry = e; - - snprintf(devdir, sizeof(devdir), "%s", wiphy_name(dev->wl->hw->wiphy)); - e->subdir = debugfs_create_dir(devdir, rootdir); - if (!e->subdir || IS_ERR(e->subdir)) { - if (e->subdir == ERR_PTR(-ENODEV)) { - b43dbg(dev->wl, "DebugFS (CONFIG_DEBUG_FS) not " - "enabled in kernel config\n"); - } else { - b43err(dev->wl, "debugfs: cannot create %s directory\n", - devdir); - } - dev->dfsentry = NULL; - kfree(log->log); - kfree(e); - return; - } - - e->mmio16read_next = 0xFFFF; /* invalid address */ - e->mmio32read_next = 0xFFFF; /* invalid address */ - e->shm16read_routing_next = 0xFFFFFFFF; /* invalid routing */ - e->shm16read_addr_next = 0xFFFFFFFF; /* invalid address */ - e->shm32read_routing_next = 0xFFFFFFFF; /* invalid routing */ - e->shm32read_addr_next = 0xFFFFFFFF; /* invalid address */ - -#define ADD_FILE(name, mode) \ - do { \ - struct dentry *d; \ - d = debugfs_create_file(__stringify(name), \ - mode, e->subdir, dev, \ - &fops_##name.fops); \ - e->file_##name.dentry = NULL; \ - if (!IS_ERR(d)) \ - e->file_##name.dentry = d; \ - } while (0) - - - ADD_FILE(shm16read, 0600); - ADD_FILE(shm16write, 0200); - ADD_FILE(shm32read, 0600); - ADD_FILE(shm32write, 0200); - ADD_FILE(mmio16read, 0600); - ADD_FILE(mmio16write, 0200); - ADD_FILE(mmio32read, 0600); - ADD_FILE(mmio32write, 0200); - ADD_FILE(txstat, 0400); - ADD_FILE(restart, 0200); - ADD_FILE(loctls, 0400); - -#undef ADD_FILE - - b43_add_dynamic_debug(dev); -} - -void b43_debugfs_remove_device(struct b43_wldev *dev) -{ - struct b43_dfsentry *e; - - if (!dev) - return; - e = dev->dfsentry; - if (!e) - return; - b43_remove_dynamic_debug(dev); - - debugfs_remove(e->file_shm16read.dentry); - debugfs_remove(e->file_shm16write.dentry); - debugfs_remove(e->file_shm32read.dentry); - debugfs_remove(e->file_shm32write.dentry); - debugfs_remove(e->file_mmio16read.dentry); - debugfs_remove(e->file_mmio16write.dentry); - debugfs_remove(e->file_mmio32read.dentry); - debugfs_remove(e->file_mmio32write.dentry); - debugfs_remove(e->file_txstat.dentry); - debugfs_remove(e->file_restart.dentry); - debugfs_remove(e->file_loctls.dentry); - - debugfs_remove(e->subdir); - kfree(e->txstatlog.log); - kfree(e); -} - -void b43_debugfs_log_txstat(struct b43_wldev *dev, - const struct b43_txstatus *status) -{ - struct b43_dfsentry *e = dev->dfsentry; - struct b43_txstatus_log *log; - struct b43_txstatus *cur; - int i; - - if (!e) - return; - log = &e->txstatlog; - i = log->end + 1; - if (i == B43_NR_LOGGED_TXSTATUS) - i = 0; - log->end = i; - cur = &(log->log[i]); - memcpy(cur, status, sizeof(*cur)); -} - -void b43_debugfs_init(void) -{ - rootdir = debugfs_create_dir(KBUILD_MODNAME, NULL); - if (IS_ERR(rootdir)) - rootdir = NULL; -} - -void b43_debugfs_exit(void) -{ - debugfs_remove(rootdir); -} diff --git a/drivers/net/wireless/b43/debugfs.h b/drivers/net/wireless/b43/debugfs.h deleted file mode 100644 index d05377745..000000000 --- a/drivers/net/wireless/b43/debugfs.h +++ /dev/null @@ -1,111 +0,0 @@ -#ifndef B43_DEBUGFS_H_ -#define B43_DEBUGFS_H_ - -struct b43_wldev; -struct b43_txstatus; - -enum b43_dyndbg { /* Dynamic debugging features */ - B43_DBG_XMITPOWER, - B43_DBG_DMAOVERFLOW, - B43_DBG_DMAVERBOSE, - B43_DBG_PWORK_FAST, - B43_DBG_PWORK_STOP, - B43_DBG_LO, - B43_DBG_FIRMWARE, - B43_DBG_KEYS, - B43_DBG_VERBOSESTATS, - __B43_NR_DYNDBG, -}; - -#ifdef CONFIG_B43_DEBUG - -struct dentry; - -#define B43_NR_LOGGED_TXSTATUS 100 - -struct b43_txstatus_log { - /* This structure is protected by wl->mutex */ - - struct b43_txstatus *log; - int end; -}; - -struct b43_dfs_file { - struct dentry *dentry; - char *buffer; - size_t data_len; -}; - -struct b43_dfsentry { - struct b43_wldev *dev; - struct dentry *subdir; - - struct b43_dfs_file file_shm16read; - struct b43_dfs_file file_shm16write; - struct b43_dfs_file file_shm32read; - struct b43_dfs_file file_shm32write; - struct b43_dfs_file file_mmio16read; - struct b43_dfs_file file_mmio16write; - struct b43_dfs_file file_mmio32read; - struct b43_dfs_file file_mmio32write; - struct b43_dfs_file file_txstat; - struct b43_dfs_file file_txpower_g; - struct b43_dfs_file file_restart; - struct b43_dfs_file file_loctls; - - struct b43_txstatus_log txstatlog; - - /* The cached address for the next mmio16read file read */ - u16 mmio16read_next; - /* The cached address for the next mmio32read file read */ - u16 mmio32read_next; - - /* The cached address for the next shm16read file read */ - u32 shm16read_routing_next; - u32 shm16read_addr_next; - /* The cached address for the next shm32read file read */ - u32 shm32read_routing_next; - u32 shm32read_addr_next; - - /* Enabled/Disabled list for the dynamic debugging features. */ - bool dyn_debug[__B43_NR_DYNDBG]; - /* Dentries for the dynamic debugging entries. */ - struct dentry *dyn_debug_dentries[__B43_NR_DYNDBG]; -}; - -bool b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature); - -void b43_debugfs_init(void); -void b43_debugfs_exit(void); -void b43_debugfs_add_device(struct b43_wldev *dev); -void b43_debugfs_remove_device(struct b43_wldev *dev); -void b43_debugfs_log_txstat(struct b43_wldev *dev, - const struct b43_txstatus *status); - -#else /* CONFIG_B43_DEBUG */ - -static inline bool b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature) -{ - return false; -} - -static inline void b43_debugfs_init(void) -{ -} -static inline void b43_debugfs_exit(void) -{ -} -static inline void b43_debugfs_add_device(struct b43_wldev *dev) -{ -} -static inline void b43_debugfs_remove_device(struct b43_wldev *dev) -{ -} -static inline void b43_debugfs_log_txstat(struct b43_wldev *dev, - const struct b43_txstatus *status) -{ -} - -#endif /* CONFIG_B43_DEBUG */ - -#endif /* B43_DEBUGFS_H_ */ diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c deleted file mode 100644 index 683706490..000000000 --- a/drivers/net/wireless/b43/dma.c +++ /dev/null @@ -1,1831 +0,0 @@ -/* - - Broadcom B43 wireless driver - - DMA ringbuffer and descriptor allocation/management - - Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch> - - Some code in this file is derived from the b44.c driver - Copyright (C) 2002 David S. Miller - Copyright (C) Pekka Pietikainen - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "dma.h" -#include "main.h" -#include "debugfs.h" -#include "xmit.h" - -#include <linux/dma-mapping.h> -#include <linux/pci.h> -#include <linux/delay.h> -#include <linux/skbuff.h> -#include <linux/etherdevice.h> -#include <linux/slab.h> -#include <asm/div64.h> - - -/* Required number of TX DMA slots per TX frame. - * This currently is 2, because we put the header and the ieee80211 frame - * into separate slots. */ -#define TX_SLOTS_PER_FRAME 2 - -static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr, - enum b43_addrtype addrtype) -{ - u32 uninitialized_var(addr); - - switch (addrtype) { - case B43_DMA_ADDR_LOW: - addr = lower_32_bits(dmaaddr); - if (dma->translation_in_low) { - addr &= ~SSB_DMA_TRANSLATION_MASK; - addr |= dma->translation; - } - break; - case B43_DMA_ADDR_HIGH: - addr = upper_32_bits(dmaaddr); - if (!dma->translation_in_low) { - addr &= ~SSB_DMA_TRANSLATION_MASK; - addr |= dma->translation; - } - break; - case B43_DMA_ADDR_EXT: - if (dma->translation_in_low) - addr = lower_32_bits(dmaaddr); - else - addr = upper_32_bits(dmaaddr); - addr &= SSB_DMA_TRANSLATION_MASK; - addr >>= SSB_DMA_TRANSLATION_SHIFT; - break; - } - - return addr; -} - -/* 32bit DMA ops. */ -static -struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring, - int slot, - struct b43_dmadesc_meta **meta) -{ - struct b43_dmadesc32 *desc; - - *meta = &(ring->meta[slot]); - desc = ring->descbase; - desc = &(desc[slot]); - - return (struct b43_dmadesc_generic *)desc; -} - -static void op32_fill_descriptor(struct b43_dmaring *ring, - struct b43_dmadesc_generic *desc, - dma_addr_t dmaaddr, u16 bufsize, - int start, int end, int irq) -{ - struct b43_dmadesc32 *descbase = ring->descbase; - int slot; - u32 ctl; - u32 addr; - u32 addrext; - - slot = (int)(&(desc->dma32) - descbase); - B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); - - addr = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW); - addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT); - - ctl = bufsize & B43_DMA32_DCTL_BYTECNT; - if (slot == ring->nr_slots - 1) - ctl |= B43_DMA32_DCTL_DTABLEEND; - if (start) - ctl |= B43_DMA32_DCTL_FRAMESTART; - if (end) - ctl |= B43_DMA32_DCTL_FRAMEEND; - if (irq) - ctl |= B43_DMA32_DCTL_IRQ; - ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT) - & B43_DMA32_DCTL_ADDREXT_MASK; - - desc->dma32.control = cpu_to_le32(ctl); - desc->dma32.address = cpu_to_le32(addr); -} - -static void op32_poke_tx(struct b43_dmaring *ring, int slot) -{ - b43_dma_write(ring, B43_DMA32_TXINDEX, - (u32) (slot * sizeof(struct b43_dmadesc32))); -} - -static void op32_tx_suspend(struct b43_dmaring *ring) -{ - b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) - | B43_DMA32_TXSUSPEND); -} - -static void op32_tx_resume(struct b43_dmaring *ring) -{ - b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) - & ~B43_DMA32_TXSUSPEND); -} - -static int op32_get_current_rxslot(struct b43_dmaring *ring) -{ - u32 val; - - val = b43_dma_read(ring, B43_DMA32_RXSTATUS); - val &= B43_DMA32_RXDPTR; - - return (val / sizeof(struct b43_dmadesc32)); -} - -static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot) -{ - b43_dma_write(ring, B43_DMA32_RXINDEX, - (u32) (slot * sizeof(struct b43_dmadesc32))); -} - -static const struct b43_dma_ops dma32_ops = { - .idx2desc = op32_idx2desc, - .fill_descriptor = op32_fill_descriptor, - .poke_tx = op32_poke_tx, - .tx_suspend = op32_tx_suspend, - .tx_resume = op32_tx_resume, - .get_current_rxslot = op32_get_current_rxslot, - .set_current_rxslot = op32_set_current_rxslot, -}; - -/* 64bit DMA ops. */ -static -struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring, - int slot, - struct b43_dmadesc_meta **meta) -{ - struct b43_dmadesc64 *desc; - - *meta = &(ring->meta[slot]); - desc = ring->descbase; - desc = &(desc[slot]); - - return (struct b43_dmadesc_generic *)desc; -} - -static void op64_fill_descriptor(struct b43_dmaring *ring, - struct b43_dmadesc_generic *desc, - dma_addr_t dmaaddr, u16 bufsize, - int start, int end, int irq) -{ - struct b43_dmadesc64 *descbase = ring->descbase; - int slot; - u32 ctl0 = 0, ctl1 = 0; - u32 addrlo, addrhi; - u32 addrext; - - slot = (int)(&(desc->dma64) - descbase); - B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); - - addrlo = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_LOW); - addrhi = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_HIGH); - addrext = b43_dma_address(&ring->dev->dma, dmaaddr, B43_DMA_ADDR_EXT); - - if (slot == ring->nr_slots - 1) - ctl0 |= B43_DMA64_DCTL0_DTABLEEND; - if (start) - ctl0 |= B43_DMA64_DCTL0_FRAMESTART; - if (end) - ctl0 |= B43_DMA64_DCTL0_FRAMEEND; - if (irq) - ctl0 |= B43_DMA64_DCTL0_IRQ; - ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT; - ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) - & B43_DMA64_DCTL1_ADDREXT_MASK; - - desc->dma64.control0 = cpu_to_le32(ctl0); - desc->dma64.control1 = cpu_to_le32(ctl1); - desc->dma64.address_low = cpu_to_le32(addrlo); - desc->dma64.address_high = cpu_to_le32(addrhi); -} - -static void op64_poke_tx(struct b43_dmaring *ring, int slot) -{ - b43_dma_write(ring, B43_DMA64_TXINDEX, - (u32) (slot * sizeof(struct b43_dmadesc64))); -} - -static void op64_tx_suspend(struct b43_dmaring *ring) -{ - b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) - | B43_DMA64_TXSUSPEND); -} - -static void op64_tx_resume(struct b43_dmaring *ring) -{ - b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) - & ~B43_DMA64_TXSUSPEND); -} - -static int op64_get_current_rxslot(struct b43_dmaring *ring) -{ - u32 val; - - val = b43_dma_read(ring, B43_DMA64_RXSTATUS); - val &= B43_DMA64_RXSTATDPTR; - - return (val / sizeof(struct b43_dmadesc64)); -} - -static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot) -{ - b43_dma_write(ring, B43_DMA64_RXINDEX, - (u32) (slot * sizeof(struct b43_dmadesc64))); -} - -static const struct b43_dma_ops dma64_ops = { - .idx2desc = op64_idx2desc, - .fill_descriptor = op64_fill_descriptor, - .poke_tx = op64_poke_tx, - .tx_suspend = op64_tx_suspend, - .tx_resume = op64_tx_resume, - .get_current_rxslot = op64_get_current_rxslot, - .set_current_rxslot = op64_set_current_rxslot, -}; - -static inline int free_slots(struct b43_dmaring *ring) -{ - return (ring->nr_slots - ring->used_slots); -} - -static inline int next_slot(struct b43_dmaring *ring, int slot) -{ - B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); - if (slot == ring->nr_slots - 1) - return 0; - return slot + 1; -} - -static inline int prev_slot(struct b43_dmaring *ring, int slot) -{ - B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); - if (slot == 0) - return ring->nr_slots - 1; - return slot - 1; -} - -#ifdef CONFIG_B43_DEBUG -static void update_max_used_slots(struct b43_dmaring *ring, - int current_used_slots) -{ - if (current_used_slots <= ring->max_used_slots) - return; - ring->max_used_slots = current_used_slots; - if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) { - b43dbg(ring->dev->wl, - "max_used_slots increased to %d on %s ring %d\n", - ring->max_used_slots, - ring->tx ? "TX" : "RX", ring->index); - } -} -#else -static inline - void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots) -{ -} -#endif /* DEBUG */ - -/* Request a slot for usage. */ -static inline int request_slot(struct b43_dmaring *ring) -{ - int slot; - - B43_WARN_ON(!ring->tx); - B43_WARN_ON(ring->stopped); - B43_WARN_ON(free_slots(ring) == 0); - - slot = next_slot(ring, ring->current_slot); - ring->current_slot = slot; - ring->used_slots++; - - update_max_used_slots(ring, ring->used_slots); - - return slot; -} - -static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx) -{ - static const u16 map64[] = { - B43_MMIO_DMA64_BASE0, - B43_MMIO_DMA64_BASE1, - B43_MMIO_DMA64_BASE2, - B43_MMIO_DMA64_BASE3, - B43_MMIO_DMA64_BASE4, - B43_MMIO_DMA64_BASE5, - }; - static const u16 map32[] = { - B43_MMIO_DMA32_BASE0, - B43_MMIO_DMA32_BASE1, - B43_MMIO_DMA32_BASE2, - B43_MMIO_DMA32_BASE3, - B43_MMIO_DMA32_BASE4, - B43_MMIO_DMA32_BASE5, - }; - - if (type == B43_DMA_64BIT) { - B43_WARN_ON(!(controller_idx >= 0 && - controller_idx < ARRAY_SIZE(map64))); - return map64[controller_idx]; - } - B43_WARN_ON(!(controller_idx >= 0 && - controller_idx < ARRAY_SIZE(map32))); - return map32[controller_idx]; -} - -static inline - dma_addr_t map_descbuffer(struct b43_dmaring *ring, - unsigned char *buf, size_t len, int tx) -{ - dma_addr_t dmaaddr; - - if (tx) { - dmaaddr = dma_map_single(ring->dev->dev->dma_dev, - buf, len, DMA_TO_DEVICE); - } else { - dmaaddr = dma_map_single(ring->dev->dev->dma_dev, - buf, len, DMA_FROM_DEVICE); - } - - return dmaaddr; -} - -static inline - void unmap_descbuffer(struct b43_dmaring *ring, - dma_addr_t addr, size_t len, int tx) -{ - if (tx) { - dma_unmap_single(ring->dev->dev->dma_dev, - addr, len, DMA_TO_DEVICE); - } else { - dma_unmap_single(ring->dev->dev->dma_dev, - addr, len, DMA_FROM_DEVICE); - } -} - -static inline - void sync_descbuffer_for_cpu(struct b43_dmaring *ring, - dma_addr_t addr, size_t len) -{ - B43_WARN_ON(ring->tx); - dma_sync_single_for_cpu(ring->dev->dev->dma_dev, - addr, len, DMA_FROM_DEVICE); -} - -static inline - void sync_descbuffer_for_device(struct b43_dmaring *ring, - dma_addr_t addr, size_t len) -{ - B43_WARN_ON(ring->tx); - dma_sync_single_for_device(ring->dev->dev->dma_dev, - addr, len, DMA_FROM_DEVICE); -} - -static inline - void free_descriptor_buffer(struct b43_dmaring *ring, - struct b43_dmadesc_meta *meta) -{ - if (meta->skb) { - if (ring->tx) - ieee80211_free_txskb(ring->dev->wl->hw, meta->skb); - else - dev_kfree_skb_any(meta->skb); - meta->skb = NULL; - } -} - -static int alloc_ringmemory(struct b43_dmaring *ring) -{ - /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K - * alignment and 8K buffers for 64-bit DMA with 8K alignment. - * In practice we could use smaller buffers for the latter, but the - * alignment is really important because of the hardware bug. If bit - * 0x00001000 is used in DMA address, some hardware (like BCM4331) - * copies that bit into B43_DMA64_RXSTATUS and we get false values from - * B43_DMA64_RXSTATDPTR. Let's just use 8K buffers even if we don't use - * more than 256 slots for ring. - */ - u16 ring_mem_size = (ring->type == B43_DMA_64BIT) ? - B43_DMA64_RINGMEMSIZE : B43_DMA32_RINGMEMSIZE; - - ring->descbase = dma_zalloc_coherent(ring->dev->dev->dma_dev, - ring_mem_size, &(ring->dmabase), - GFP_KERNEL); - if (!ring->descbase) - return -ENOMEM; - - return 0; -} - -static void free_ringmemory(struct b43_dmaring *ring) -{ - u16 ring_mem_size = (ring->type == B43_DMA_64BIT) ? - B43_DMA64_RINGMEMSIZE : B43_DMA32_RINGMEMSIZE; - dma_free_coherent(ring->dev->dev->dma_dev, ring_mem_size, - ring->descbase, ring->dmabase); -} - -/* Reset the RX DMA channel */ -static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, - enum b43_dmatype type) -{ - int i; - u32 value; - u16 offset; - - might_sleep(); - - offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL; - b43_write32(dev, mmio_base + offset, 0); - for (i = 0; i < 10; i++) { - offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS : - B43_DMA32_RXSTATUS; - value = b43_read32(dev, mmio_base + offset); - if (type == B43_DMA_64BIT) { - value &= B43_DMA64_RXSTAT; - if (value == B43_DMA64_RXSTAT_DISABLED) { - i = -1; - break; - } - } else { - value &= B43_DMA32_RXSTATE; - if (value == B43_DMA32_RXSTAT_DISABLED) { - i = -1; - break; - } - } - msleep(1); - } - if (i != -1) { - b43err(dev->wl, "DMA RX reset timed out\n"); - return -ENODEV; - } - - return 0; -} - -/* Reset the TX DMA channel */ -static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, - enum b43_dmatype type) -{ - int i; - u32 value; - u16 offset; - - might_sleep(); - - for (i = 0; i < 10; i++) { - offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : - B43_DMA32_TXSTATUS; - value = b43_read32(dev, mmio_base + offset); - if (type == B43_DMA_64BIT) { - value &= B43_DMA64_TXSTAT; - if (value == B43_DMA64_TXSTAT_DISABLED || - value == B43_DMA64_TXSTAT_IDLEWAIT || - value == B43_DMA64_TXSTAT_STOPPED) - break; - } else { - value &= B43_DMA32_TXSTATE; - if (value == B43_DMA32_TXSTAT_DISABLED || - value == B43_DMA32_TXSTAT_IDLEWAIT || - value == B43_DMA32_TXSTAT_STOPPED) - break; - } - msleep(1); - } - offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL; - b43_write32(dev, mmio_base + offset, 0); - for (i = 0; i < 10; i++) { - offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : - B43_DMA32_TXSTATUS; - value = b43_read32(dev, mmio_base + offset); - if (type == B43_DMA_64BIT) { - value &= B43_DMA64_TXSTAT; - if (value == B43_DMA64_TXSTAT_DISABLED) { - i = -1; - break; - } - } else { - value &= B43_DMA32_TXSTATE; - if (value == B43_DMA32_TXSTAT_DISABLED) { - i = -1; - break; - } - } - msleep(1); - } - if (i != -1) { - b43err(dev->wl, "DMA TX reset timed out\n"); - return -ENODEV; - } - /* ensure the reset is completed. */ - msleep(1); - - return 0; -} - -/* Check if a DMA mapping address is invalid. */ -static bool b43_dma_mapping_error(struct b43_dmaring *ring, - dma_addr_t addr, - size_t buffersize, bool dma_to_device) -{ - if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr))) - return true; - - switch (ring->type) { - case B43_DMA_30BIT: - if ((u64)addr + buffersize > (1ULL << 30)) - goto address_error; - break; - case B43_DMA_32BIT: - if ((u64)addr + buffersize > (1ULL << 32)) - goto address_error; - break; - case B43_DMA_64BIT: - /* Currently we can't have addresses beyond - * 64bit in the kernel. */ - break; - } - - /* The address is OK. */ - return false; - -address_error: - /* We can't support this address. Unmap it again. */ - unmap_descbuffer(ring, addr, buffersize, dma_to_device); - - return true; -} - -static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb) -{ - unsigned char *f = skb->data + ring->frameoffset; - - return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF); -} - -static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb) -{ - struct b43_rxhdr_fw4 *rxhdr; - unsigned char *frame; - - /* This poisons the RX buffer to detect DMA failures. */ - - rxhdr = (struct b43_rxhdr_fw4 *)(skb->data); - rxhdr->frame_len = 0; - - B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2); - frame = skb->data + ring->frameoffset; - memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */); -} - -static int setup_rx_descbuffer(struct b43_dmaring *ring, - struct b43_dmadesc_generic *desc, - struct b43_dmadesc_meta *meta, gfp_t gfp_flags) -{ - dma_addr_t dmaaddr; - struct sk_buff *skb; - - B43_WARN_ON(ring->tx); - - skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); - if (unlikely(!skb)) - return -ENOMEM; - b43_poison_rx_buffer(ring, skb); - dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0); - if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { - /* ugh. try to realloc in zone_dma */ - gfp_flags |= GFP_DMA; - - dev_kfree_skb_any(skb); - - skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); - if (unlikely(!skb)) - return -ENOMEM; - b43_poison_rx_buffer(ring, skb); - dmaaddr = map_descbuffer(ring, skb->data, - ring->rx_buffersize, 0); - if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { - b43err(ring->dev->wl, "RX DMA buffer allocation failed\n"); - dev_kfree_skb_any(skb); - return -EIO; - } - } - - meta->skb = skb; - meta->dmaaddr = dmaaddr; - ring->ops->fill_descriptor(ring, desc, dmaaddr, - ring->rx_buffersize, 0, 0, 0); - - return 0; -} - -/* Allocate the initial descbuffers. - * This is used for an RX ring only. - */ -static int alloc_initial_descbuffers(struct b43_dmaring *ring) -{ - int i, err = -ENOMEM; - struct b43_dmadesc_generic *desc; - struct b43_dmadesc_meta *meta; - - for (i = 0; i < ring->nr_slots; i++) { - desc = ring->ops->idx2desc(ring, i, &meta); - - err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); - if (err) { - b43err(ring->dev->wl, - "Failed to allocate initial descbuffers\n"); - goto err_unwind; - } - } - mb(); - ring->used_slots = ring->nr_slots; - err = 0; - out: - return err; - - err_unwind: - for (i--; i >= 0; i--) { - desc = ring->ops->idx2desc(ring, i, &meta); - - unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); - dev_kfree_skb(meta->skb); - } - goto out; -} - -/* Do initial setup of the DMA controller. - * Reset the controller, write the ring busaddress - * and switch the "enable" bit on. - */ -static int dmacontroller_setup(struct b43_dmaring *ring) -{ - int err = 0; - u32 value; - u32 addrext; - bool parity = ring->dev->dma.parity; - u32 addrlo; - u32 addrhi; - - if (ring->tx) { - if (ring->type == B43_DMA_64BIT) { - u64 ringbase = (u64) (ring->dmabase); - addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT); - addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW); - addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH); - - value = B43_DMA64_TXENABLE; - value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) - & B43_DMA64_TXADDREXT_MASK; - if (!parity) - value |= B43_DMA64_TXPARITYDISABLE; - b43_dma_write(ring, B43_DMA64_TXCTL, value); - b43_dma_write(ring, B43_DMA64_TXRINGLO, addrlo); - b43_dma_write(ring, B43_DMA64_TXRINGHI, addrhi); - } else { - u32 ringbase = (u32) (ring->dmabase); - addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT); - addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW); - - value = B43_DMA32_TXENABLE; - value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) - & B43_DMA32_TXADDREXT_MASK; - if (!parity) - value |= B43_DMA32_TXPARITYDISABLE; - b43_dma_write(ring, B43_DMA32_TXCTL, value); - b43_dma_write(ring, B43_DMA32_TXRING, addrlo); - } - } else { - err = alloc_initial_descbuffers(ring); - if (err) - goto out; - if (ring->type == B43_DMA_64BIT) { - u64 ringbase = (u64) (ring->dmabase); - addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT); - addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW); - addrhi = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_HIGH); - - value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT); - value |= B43_DMA64_RXENABLE; - value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) - & B43_DMA64_RXADDREXT_MASK; - if (!parity) - value |= B43_DMA64_RXPARITYDISABLE; - b43_dma_write(ring, B43_DMA64_RXCTL, value); - b43_dma_write(ring, B43_DMA64_RXRINGLO, addrlo); - b43_dma_write(ring, B43_DMA64_RXRINGHI, addrhi); - b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * - sizeof(struct b43_dmadesc64)); - } else { - u32 ringbase = (u32) (ring->dmabase); - addrext = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_EXT); - addrlo = b43_dma_address(&ring->dev->dma, ringbase, B43_DMA_ADDR_LOW); - - value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT); - value |= B43_DMA32_RXENABLE; - value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) - & B43_DMA32_RXADDREXT_MASK; - if (!parity) - value |= B43_DMA32_RXPARITYDISABLE; - b43_dma_write(ring, B43_DMA32_RXCTL, value); - b43_dma_write(ring, B43_DMA32_RXRING, addrlo); - b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots * - sizeof(struct b43_dmadesc32)); - } - } - -out: - return err; -} - -/* Shutdown the DMA controller. */ -static void dmacontroller_cleanup(struct b43_dmaring *ring) -{ - if (ring->tx) { - b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base, - ring->type); - if (ring->type == B43_DMA_64BIT) { - b43_dma_write(ring, B43_DMA64_TXRINGLO, 0); - b43_dma_write(ring, B43_DMA64_TXRINGHI, 0); - } else - b43_dma_write(ring, B43_DMA32_TXRING, 0); - } else { - b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base, - ring->type); - if (ring->type == B43_DMA_64BIT) { - b43_dma_write(ring, B43_DMA64_RXRINGLO, 0); - b43_dma_write(ring, B43_DMA64_RXRINGHI, 0); - } else - b43_dma_write(ring, B43_DMA32_RXRING, 0); - } -} - -static void free_all_descbuffers(struct b43_dmaring *ring) -{ - struct b43_dmadesc_meta *meta; - int i; - - if (!ring->used_slots) - return; - for (i = 0; i < ring->nr_slots; i++) { - /* get meta - ignore returned value */ - ring->ops->idx2desc(ring, i, &meta); - - if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) { - B43_WARN_ON(!ring->tx); - continue; - } - if (ring->tx) { - unmap_descbuffer(ring, meta->dmaaddr, - meta->skb->len, 1); - } else { - unmap_descbuffer(ring, meta->dmaaddr, - ring->rx_buffersize, 0); - } - free_descriptor_buffer(ring, meta); - } -} - -static u64 supported_dma_mask(struct b43_wldev *dev) -{ - u32 tmp; - u16 mmio_base; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); - if (tmp & BCMA_IOST_DMA64) - return DMA_BIT_MASK(64); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); - if (tmp & SSB_TMSHIGH_DMA64) - return DMA_BIT_MASK(64); - break; -#endif - } - - mmio_base = b43_dmacontroller_base(0, 0); - b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK); - tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL); - if (tmp & B43_DMA32_TXADDREXT_MASK) - return DMA_BIT_MASK(32); - - return DMA_BIT_MASK(30); -} - -static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask) -{ - if (dmamask == DMA_BIT_MASK(30)) - return B43_DMA_30BIT; - if (dmamask == DMA_BIT_MASK(32)) - return B43_DMA_32BIT; - if (dmamask == DMA_BIT_MASK(64)) - return B43_DMA_64BIT; - B43_WARN_ON(1); - return B43_DMA_30BIT; -} - -/* Main initialization function. */ -static -struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev, - int controller_index, - int for_tx, - enum b43_dmatype type) -{ - struct b43_dmaring *ring; - int i, err; - dma_addr_t dma_test; - - ring = kzalloc(sizeof(*ring), GFP_KERNEL); - if (!ring) - goto out; - - ring->nr_slots = B43_RXRING_SLOTS; - if (for_tx) - ring->nr_slots = B43_TXRING_SLOTS; - - ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta), - GFP_KERNEL); - if (!ring->meta) - goto err_kfree_ring; - for (i = 0; i < ring->nr_slots; i++) - ring->meta->skb = B43_DMA_PTR_POISON; - - ring->type = type; - ring->dev = dev; - ring->mmio_base = b43_dmacontroller_base(type, controller_index); - ring->index = controller_index; - if (type == B43_DMA_64BIT) - ring->ops = &dma64_ops; - else - ring->ops = &dma32_ops; - if (for_tx) { - ring->tx = true; - ring->current_slot = -1; - } else { - if (ring->index == 0) { - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - ring->rx_buffersize = B43_DMA0_RX_FW598_BUFSIZE; - ring->frameoffset = B43_DMA0_RX_FW598_FO; - break; - case B43_FW_HDR_410: - case B43_FW_HDR_351: - ring->rx_buffersize = B43_DMA0_RX_FW351_BUFSIZE; - ring->frameoffset = B43_DMA0_RX_FW351_FO; - break; - } - } else - B43_WARN_ON(1); - } -#ifdef CONFIG_B43_DEBUG - ring->last_injected_overflow = jiffies; -#endif - - if (for_tx) { - /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */ - BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0); - - ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME, - b43_txhdr_size(dev), - GFP_KERNEL); - if (!ring->txhdr_cache) - goto err_kfree_meta; - - /* test for ability to dma to txhdr_cache */ - dma_test = dma_map_single(dev->dev->dma_dev, - ring->txhdr_cache, - b43_txhdr_size(dev), - DMA_TO_DEVICE); - - if (b43_dma_mapping_error(ring, dma_test, - b43_txhdr_size(dev), 1)) { - /* ugh realloc */ - kfree(ring->txhdr_cache); - ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME, - b43_txhdr_size(dev), - GFP_KERNEL | GFP_DMA); - if (!ring->txhdr_cache) - goto err_kfree_meta; - - dma_test = dma_map_single(dev->dev->dma_dev, - ring->txhdr_cache, - b43_txhdr_size(dev), - DMA_TO_DEVICE); - - if (b43_dma_mapping_error(ring, dma_test, - b43_txhdr_size(dev), 1)) { - - b43err(dev->wl, - "TXHDR DMA allocation failed\n"); - goto err_kfree_txhdr_cache; - } - } - - dma_unmap_single(dev->dev->dma_dev, - dma_test, b43_txhdr_size(dev), - DMA_TO_DEVICE); - } - - err = alloc_ringmemory(ring); - if (err) - goto err_kfree_txhdr_cache; - err = dmacontroller_setup(ring); - if (err) - goto err_free_ringmemory; - - out: - return ring; - - err_free_ringmemory: - free_ringmemory(ring); - err_kfree_txhdr_cache: - kfree(ring->txhdr_cache); - err_kfree_meta: - kfree(ring->meta); - err_kfree_ring: - kfree(ring); - ring = NULL; - goto out; -} - -#define divide(a, b) ({ \ - typeof(a) __a = a; \ - do_div(__a, b); \ - __a; \ - }) - -#define modulo(a, b) ({ \ - typeof(a) __a = a; \ - do_div(__a, b); \ - }) - -/* Main cleanup function. */ -static void b43_destroy_dmaring(struct b43_dmaring *ring, - const char *ringname) -{ - if (!ring) - return; - -#ifdef CONFIG_B43_DEBUG - { - /* Print some statistics. */ - u64 failed_packets = ring->nr_failed_tx_packets; - u64 succeed_packets = ring->nr_succeed_tx_packets; - u64 nr_packets = failed_packets + succeed_packets; - u64 permille_failed = 0, average_tries = 0; - - if (nr_packets) - permille_failed = divide(failed_packets * 1000, nr_packets); - if (nr_packets) - average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets); - - b43dbg(ring->dev->wl, "DMA-%u %s: " - "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, " - "Average tries %llu.%02llu\n", - (unsigned int)(ring->type), ringname, - ring->max_used_slots, - ring->nr_slots, - (unsigned long long)failed_packets, - (unsigned long long)nr_packets, - (unsigned long long)divide(permille_failed, 10), - (unsigned long long)modulo(permille_failed, 10), - (unsigned long long)divide(average_tries, 100), - (unsigned long long)modulo(average_tries, 100)); - } -#endif /* DEBUG */ - - /* Device IRQs are disabled prior entering this function, - * so no need to take care of concurrency with rx handler stuff. - */ - dmacontroller_cleanup(ring); - free_all_descbuffers(ring); - free_ringmemory(ring); - - kfree(ring->txhdr_cache); - kfree(ring->meta); - kfree(ring); -} - -#define destroy_ring(dma, ring) do { \ - b43_destroy_dmaring((dma)->ring, __stringify(ring)); \ - (dma)->ring = NULL; \ - } while (0) - -void b43_dma_free(struct b43_wldev *dev) -{ - struct b43_dma *dma; - - if (b43_using_pio_transfers(dev)) - return; - dma = &dev->dma; - - destroy_ring(dma, rx_ring); - destroy_ring(dma, tx_ring_AC_BK); - destroy_ring(dma, tx_ring_AC_BE); - destroy_ring(dma, tx_ring_AC_VI); - destroy_ring(dma, tx_ring_AC_VO); - destroy_ring(dma, tx_ring_mcast); -} - -static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask) -{ - u64 orig_mask = mask; - bool fallback = false; - int err; - - /* Try to set the DMA mask. If it fails, try falling back to a - * lower mask, as we can always also support a lower one. */ - while (1) { - err = dma_set_mask_and_coherent(dev->dev->dma_dev, mask); - if (!err) - break; - if (mask == DMA_BIT_MASK(64)) { - mask = DMA_BIT_MASK(32); - fallback = true; - continue; - } - if (mask == DMA_BIT_MASK(32)) { - mask = DMA_BIT_MASK(30); - fallback = true; - continue; - } - b43err(dev->wl, "The machine/kernel does not support " - "the required %u-bit DMA mask\n", - (unsigned int)dma_mask_to_engine_type(orig_mask)); - return -EOPNOTSUPP; - } - if (fallback) { - b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n", - (unsigned int)dma_mask_to_engine_type(orig_mask), - (unsigned int)dma_mask_to_engine_type(mask)); - } - - return 0; -} - -/* Some hardware with 64-bit DMA seems to be bugged and looks for translation - * bit in low address word instead of high one. - */ -static bool b43_dma_translation_in_low_word(struct b43_wldev *dev, - enum b43_dmatype type) -{ - if (type != B43_DMA_64BIT) - return true; - -#ifdef CONFIG_B43_SSB - if (dev->dev->bus_type == B43_BUS_SSB && - dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && - !(pci_is_pcie(dev->dev->sdev->bus->host_pci) && - ssb_read32(dev->dev->sdev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)) - return true; -#endif - return false; -} - -int b43_dma_init(struct b43_wldev *dev) -{ - struct b43_dma *dma = &dev->dma; - int err; - u64 dmamask; - enum b43_dmatype type; - - dmamask = supported_dma_mask(dev); - type = dma_mask_to_engine_type(dmamask); - err = b43_dma_set_mask(dev, dmamask); - if (err) - return err; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - dma->translation = bcma_core_dma_translation(dev->dev->bdev); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - dma->translation = ssb_dma_translation(dev->dev->sdev); - break; -#endif - } - dma->translation_in_low = b43_dma_translation_in_low_word(dev, type); - - dma->parity = true; -#ifdef CONFIG_B43_BCMA - /* TODO: find out which SSB devices need disabling parity */ - if (dev->dev->bus_type == B43_BUS_BCMA) - dma->parity = false; -#endif - - err = -ENOMEM; - /* setup TX DMA channels. */ - dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type); - if (!dma->tx_ring_AC_BK) - goto out; - - dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type); - if (!dma->tx_ring_AC_BE) - goto err_destroy_bk; - - dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type); - if (!dma->tx_ring_AC_VI) - goto err_destroy_be; - - dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type); - if (!dma->tx_ring_AC_VO) - goto err_destroy_vi; - - dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type); - if (!dma->tx_ring_mcast) - goto err_destroy_vo; - - /* setup RX DMA channel. */ - dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type); - if (!dma->rx_ring) - goto err_destroy_mcast; - - /* No support for the TX status DMA ring. */ - B43_WARN_ON(dev->dev->core_rev < 5); - - b43dbg(dev->wl, "%u-bit DMA initialized\n", - (unsigned int)type); - err = 0; -out: - return err; - -err_destroy_mcast: - destroy_ring(dma, tx_ring_mcast); -err_destroy_vo: - destroy_ring(dma, tx_ring_AC_VO); -err_destroy_vi: - destroy_ring(dma, tx_ring_AC_VI); -err_destroy_be: - destroy_ring(dma, tx_ring_AC_BE); -err_destroy_bk: - destroy_ring(dma, tx_ring_AC_BK); - return err; -} - -/* Generate a cookie for the TX header. */ -static u16 generate_cookie(struct b43_dmaring *ring, int slot) -{ - u16 cookie; - - /* Use the upper 4 bits of the cookie as - * DMA controller ID and store the slot number - * in the lower 12 bits. - * Note that the cookie must never be 0, as this - * is a special value used in RX path. - * It can also not be 0xFFFF because that is special - * for multicast frames. - */ - cookie = (((u16)ring->index + 1) << 12); - B43_WARN_ON(slot & ~0x0FFF); - cookie |= (u16)slot; - - return cookie; -} - -/* Inspect a cookie and find out to which controller/slot it belongs. */ -static -struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot) -{ - struct b43_dma *dma = &dev->dma; - struct b43_dmaring *ring = NULL; - - switch (cookie & 0xF000) { - case 0x1000: - ring = dma->tx_ring_AC_BK; - break; - case 0x2000: - ring = dma->tx_ring_AC_BE; - break; - case 0x3000: - ring = dma->tx_ring_AC_VI; - break; - case 0x4000: - ring = dma->tx_ring_AC_VO; - break; - case 0x5000: - ring = dma->tx_ring_mcast; - break; - } - *slot = (cookie & 0x0FFF); - if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) { - b43dbg(dev->wl, "TX-status contains " - "invalid cookie: 0x%04X\n", cookie); - return NULL; - } - - return ring; -} - -static int dma_tx_fragment(struct b43_dmaring *ring, - struct sk_buff *skb) -{ - const struct b43_dma_ops *ops = ring->ops; - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info); - u8 *header; - int slot, old_top_slot, old_used_slots; - int err; - struct b43_dmadesc_generic *desc; - struct b43_dmadesc_meta *meta; - struct b43_dmadesc_meta *meta_hdr; - u16 cookie; - size_t hdrsize = b43_txhdr_size(ring->dev); - - /* Important note: If the number of used DMA slots per TX frame - * is changed here, the TX_SLOTS_PER_FRAME definition at the top of - * the file has to be updated, too! - */ - - old_top_slot = ring->current_slot; - old_used_slots = ring->used_slots; - - /* Get a slot for the header. */ - slot = request_slot(ring); - desc = ops->idx2desc(ring, slot, &meta_hdr); - memset(meta_hdr, 0, sizeof(*meta_hdr)); - - header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]); - cookie = generate_cookie(ring, slot); - err = b43_generate_txhdr(ring->dev, header, - skb, info, cookie); - if (unlikely(err)) { - ring->current_slot = old_top_slot; - ring->used_slots = old_used_slots; - return err; - } - - meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, - hdrsize, 1); - if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) { - ring->current_slot = old_top_slot; - ring->used_slots = old_used_slots; - return -EIO; - } - ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr, - hdrsize, 1, 0, 0); - - /* Get a slot for the payload. */ - slot = request_slot(ring); - desc = ops->idx2desc(ring, slot, &meta); - memset(meta, 0, sizeof(*meta)); - - meta->skb = skb; - meta->is_last_fragment = true; - priv_info->bouncebuffer = NULL; - - meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); - /* create a bounce buffer in zone_dma on mapping failure. */ - if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { - priv_info->bouncebuffer = kmemdup(skb->data, skb->len, - GFP_ATOMIC | GFP_DMA); - if (!priv_info->bouncebuffer) { - ring->current_slot = old_top_slot; - ring->used_slots = old_used_slots; - err = -ENOMEM; - goto out_unmap_hdr; - } - - meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1); - if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { - kfree(priv_info->bouncebuffer); - priv_info->bouncebuffer = NULL; - ring->current_slot = old_top_slot; - ring->used_slots = old_used_slots; - err = -EIO; - goto out_unmap_hdr; - } - } - - ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); - - if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { - /* Tell the firmware about the cookie of the last - * mcast frame, so it can clear the more-data bit in it. */ - b43_shm_write16(ring->dev, B43_SHM_SHARED, - B43_SHM_SH_MCASTCOOKIE, cookie); - } - /* Now transfer the whole frame. */ - wmb(); - ops->poke_tx(ring, next_slot(ring, slot)); - return 0; - -out_unmap_hdr: - unmap_descbuffer(ring, meta_hdr->dmaaddr, - hdrsize, 1); - return err; -} - -static inline int should_inject_overflow(struct b43_dmaring *ring) -{ -#ifdef CONFIG_B43_DEBUG - if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) { - /* Check if we should inject another ringbuffer overflow - * to test handling of this situation in the stack. */ - unsigned long next_overflow; - - next_overflow = ring->last_injected_overflow + HZ; - if (time_after(jiffies, next_overflow)) { - ring->last_injected_overflow = jiffies; - b43dbg(ring->dev->wl, - "Injecting TX ring overflow on " - "DMA controller %d\n", ring->index); - return 1; - } - } -#endif /* CONFIG_B43_DEBUG */ - return 0; -} - -/* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */ -static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev, - u8 queue_prio) -{ - struct b43_dmaring *ring; - - if (dev->qos_enabled) { - /* 0 = highest priority */ - switch (queue_prio) { - default: - B43_WARN_ON(1); - /* fallthrough */ - case 0: - ring = dev->dma.tx_ring_AC_VO; - break; - case 1: - ring = dev->dma.tx_ring_AC_VI; - break; - case 2: - ring = dev->dma.tx_ring_AC_BE; - break; - case 3: - ring = dev->dma.tx_ring_AC_BK; - break; - } - } else - ring = dev->dma.tx_ring_AC_BE; - - return ring; -} - -int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb) -{ - struct b43_dmaring *ring; - struct ieee80211_hdr *hdr; - int err = 0; - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - - hdr = (struct ieee80211_hdr *)skb->data; - if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { - /* The multicast ring will be sent after the DTIM */ - ring = dev->dma.tx_ring_mcast; - /* Set the more-data bit. Ucode will clear it on - * the last frame for us. */ - hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); - } else { - /* Decide by priority where to put this frame. */ - ring = select_ring_by_priority( - dev, skb_get_queue_mapping(skb)); - } - - B43_WARN_ON(!ring->tx); - - if (unlikely(ring->stopped)) { - /* We get here only because of a bug in mac80211. - * Because of a race, one packet may be queued after - * the queue is stopped, thus we got called when we shouldn't. - * For now, just refuse the transmit. */ - if (b43_debug(dev, B43_DBG_DMAVERBOSE)) - b43err(dev->wl, "Packet after queue stopped\n"); - err = -ENOSPC; - goto out; - } - - if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) { - /* If we get here, we have a real error with the queue - * full, but queues not stopped. */ - b43err(dev->wl, "DMA queue overflow\n"); - err = -ENOSPC; - goto out; - } - - /* Assign the queue number to the ring (if not already done before) - * so TX status handling can use it. The queue to ring mapping is - * static, so we don't need to store it per frame. */ - ring->queue_prio = skb_get_queue_mapping(skb); - - err = dma_tx_fragment(ring, skb); - if (unlikely(err == -ENOKEY)) { - /* Drop this packet, as we don't have the encryption key - * anymore and must not transmit it unencrypted. */ - ieee80211_free_txskb(dev->wl->hw, skb); - err = 0; - goto out; - } - if (unlikely(err)) { - b43err(dev->wl, "DMA tx mapping failure\n"); - goto out; - } - if ((free_slots(ring) < TX_SLOTS_PER_FRAME) || - should_inject_overflow(ring)) { - /* This TX ring is full. */ - unsigned int skb_mapping = skb_get_queue_mapping(skb); - ieee80211_stop_queue(dev->wl->hw, skb_mapping); - dev->wl->tx_queue_stopped[skb_mapping] = 1; - ring->stopped = true; - if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { - b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); - } - } -out: - - return err; -} - -void b43_dma_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status) -{ - const struct b43_dma_ops *ops; - struct b43_dmaring *ring; - struct b43_dmadesc_meta *meta; - static const struct b43_txstatus fake; /* filled with 0 */ - const struct b43_txstatus *txstat; - int slot, firstused; - bool frame_succeed; - int skip; - static u8 err_out1, err_out2; - - ring = parse_cookie(dev, status->cookie, &slot); - if (unlikely(!ring)) - return; - B43_WARN_ON(!ring->tx); - - /* Sanity check: TX packets are processed in-order on one ring. - * Check if the slot deduced from the cookie really is the first - * used slot. */ - firstused = ring->current_slot - ring->used_slots + 1; - if (firstused < 0) - firstused = ring->nr_slots + firstused; - - skip = 0; - if (unlikely(slot != firstused)) { - /* This possibly is a firmware bug and will result in - * malfunction, memory leaks and/or stall of DMA functionality. - */ - if (slot == next_slot(ring, next_slot(ring, firstused))) { - /* If a single header/data pair was missed, skip over - * the first two slots in an attempt to recover. - */ - slot = firstused; - skip = 2; - if (!err_out1) { - /* Report the error once. */ - b43dbg(dev->wl, - "Skip on DMA ring %d slot %d.\n", - ring->index, slot); - err_out1 = 1; - } - } else { - /* More than a single header/data pair were missed. - * Report this error once. - */ - if (!err_out2) - b43dbg(dev->wl, - "Out of order TX status report on DMA ring %d. Expected %d, but got %d\n", - ring->index, firstused, slot); - err_out2 = 1; - return; - } - } - - ops = ring->ops; - while (1) { - B43_WARN_ON(slot < 0 || slot >= ring->nr_slots); - /* get meta - ignore returned value */ - ops->idx2desc(ring, slot, &meta); - - if (b43_dma_ptr_is_poisoned(meta->skb)) { - b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) " - "on ring %d\n", - slot, firstused, ring->index); - break; - } - - if (meta->skb) { - struct b43_private_tx_info *priv_info = - b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb)); - - unmap_descbuffer(ring, meta->dmaaddr, - meta->skb->len, 1); - kfree(priv_info->bouncebuffer); - priv_info->bouncebuffer = NULL; - } else { - unmap_descbuffer(ring, meta->dmaaddr, - b43_txhdr_size(dev), 1); - } - - if (meta->is_last_fragment) { - struct ieee80211_tx_info *info; - - if (unlikely(!meta->skb)) { - /* This is a scatter-gather fragment of a frame, - * so the skb pointer must not be NULL. - */ - b43dbg(dev->wl, "TX status unexpected NULL skb " - "at slot %d (first=%d) on ring %d\n", - slot, firstused, ring->index); - break; - } - - info = IEEE80211_SKB_CB(meta->skb); - - /* - * Call back to inform the ieee80211 subsystem about - * the status of the transmission. When skipping over - * a missed TX status report, use a status structure - * filled with zeros to indicate that the frame was not - * sent (frame_count 0) and not acknowledged - */ - if (unlikely(skip)) - txstat = &fake; - else - txstat = status; - - frame_succeed = b43_fill_txstatus_report(dev, info, - txstat); -#ifdef CONFIG_B43_DEBUG - if (frame_succeed) - ring->nr_succeed_tx_packets++; - else - ring->nr_failed_tx_packets++; - ring->nr_total_packet_tries += status->frame_count; -#endif /* DEBUG */ - ieee80211_tx_status(dev->wl->hw, meta->skb); - - /* skb will be freed by ieee80211_tx_status(). - * Poison our pointer. */ - meta->skb = B43_DMA_PTR_POISON; - } else { - /* No need to call free_descriptor_buffer here, as - * this is only the txhdr, which is not allocated. - */ - if (unlikely(meta->skb)) { - b43dbg(dev->wl, "TX status unexpected non-NULL skb " - "at slot %d (first=%d) on ring %d\n", - slot, firstused, ring->index); - break; - } - } - - /* Everything unmapped and free'd. So it's not used anymore. */ - ring->used_slots--; - - if (meta->is_last_fragment && !skip) { - /* This is the last scatter-gather - * fragment of the frame. We are done. */ - break; - } - slot = next_slot(ring, slot); - if (skip > 0) - --skip; - } - if (ring->stopped) { - B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME); - ring->stopped = false; - } - - if (dev->wl->tx_queue_stopped[ring->queue_prio]) { - dev->wl->tx_queue_stopped[ring->queue_prio] = 0; - } else { - /* If the driver queue is running wake the corresponding - * mac80211 queue. */ - ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); - if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { - b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index); - } - } - /* Add work to the queue. */ - ieee80211_queue_work(dev->wl->hw, &dev->wl->tx_work); -} - -static void dma_rx(struct b43_dmaring *ring, int *slot) -{ - const struct b43_dma_ops *ops = ring->ops; - struct b43_dmadesc_generic *desc; - struct b43_dmadesc_meta *meta; - struct b43_rxhdr_fw4 *rxhdr; - struct sk_buff *skb; - u16 len; - int err; - dma_addr_t dmaaddr; - - desc = ops->idx2desc(ring, *slot, &meta); - - sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); - skb = meta->skb; - - rxhdr = (struct b43_rxhdr_fw4 *)skb->data; - len = le16_to_cpu(rxhdr->frame_len); - if (len == 0) { - int i = 0; - - do { - udelay(2); - barrier(); - len = le16_to_cpu(rxhdr->frame_len); - } while (len == 0 && i++ < 5); - if (unlikely(len == 0)) { - dmaaddr = meta->dmaaddr; - goto drop_recycle_buffer; - } - } - if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) { - /* Something went wrong with the DMA. - * The device did not touch the buffer and did not overwrite the poison. */ - b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n"); - dmaaddr = meta->dmaaddr; - goto drop_recycle_buffer; - } - if (unlikely(len + ring->frameoffset > ring->rx_buffersize)) { - /* The data did not fit into one descriptor buffer - * and is split over multiple buffers. - * This should never happen, as we try to allocate buffers - * big enough. So simply ignore this packet. - */ - int cnt = 0; - s32 tmp = len; - - while (1) { - desc = ops->idx2desc(ring, *slot, &meta); - /* recycle the descriptor buffer. */ - b43_poison_rx_buffer(ring, meta->skb); - sync_descbuffer_for_device(ring, meta->dmaaddr, - ring->rx_buffersize); - *slot = next_slot(ring, *slot); - cnt++; - tmp -= ring->rx_buffersize; - if (tmp <= 0) - break; - } - b43err(ring->dev->wl, "DMA RX buffer too small " - "(len: %u, buffer: %u, nr-dropped: %d)\n", - len, ring->rx_buffersize, cnt); - goto drop; - } - - dmaaddr = meta->dmaaddr; - err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); - if (unlikely(err)) { - b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n"); - goto drop_recycle_buffer; - } - - unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); - skb_put(skb, len + ring->frameoffset); - skb_pull(skb, ring->frameoffset); - - b43_rx(ring->dev, skb, rxhdr); -drop: - return; - -drop_recycle_buffer: - /* Poison and recycle the RX buffer. */ - b43_poison_rx_buffer(ring, skb); - sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize); -} - -void b43_dma_handle_rx_overflow(struct b43_dmaring *ring) -{ - int current_slot, previous_slot; - - B43_WARN_ON(ring->tx); - - /* Device has filled all buffers, drop all packets and let TCP - * decrease speed. - * Decrement RX index by one will let the device to see all slots - * as free again - */ - /* - *TODO: How to increase rx_drop in mac80211? - */ - current_slot = ring->ops->get_current_rxslot(ring); - previous_slot = prev_slot(ring, current_slot); - ring->ops->set_current_rxslot(ring, previous_slot); -} - -void b43_dma_rx(struct b43_dmaring *ring) -{ - const struct b43_dma_ops *ops = ring->ops; - int slot, current_slot; - int used_slots = 0; - - B43_WARN_ON(ring->tx); - current_slot = ops->get_current_rxslot(ring); - B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots)); - - slot = ring->current_slot; - for (; slot != current_slot; slot = next_slot(ring, slot)) { - dma_rx(ring, &slot); - update_max_used_slots(ring, ++used_slots); - } - wmb(); - ops->set_current_rxslot(ring, slot); - ring->current_slot = slot; -} - -static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring) -{ - B43_WARN_ON(!ring->tx); - ring->ops->tx_suspend(ring); -} - -static void b43_dma_tx_resume_ring(struct b43_dmaring *ring) -{ - B43_WARN_ON(!ring->tx); - ring->ops->tx_resume(ring); -} - -void b43_dma_tx_suspend(struct b43_wldev *dev) -{ - b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); - b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK); - b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE); - b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI); - b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO); - b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast); -} - -void b43_dma_tx_resume(struct b43_wldev *dev) -{ - b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast); - b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO); - b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI); - b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE); - b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK); - b43_power_saving_ctl_bits(dev, 0); -} - -static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type, - u16 mmio_base, bool enable) -{ - u32 ctl; - - if (type == B43_DMA_64BIT) { - ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL); - ctl &= ~B43_DMA64_RXDIRECTFIFO; - if (enable) - ctl |= B43_DMA64_RXDIRECTFIFO; - b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl); - } else { - ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL); - ctl &= ~B43_DMA32_RXDIRECTFIFO; - if (enable) - ctl |= B43_DMA32_RXDIRECTFIFO; - b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl); - } -} - -/* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine. - * This is called from PIO code, so DMA structures are not available. */ -void b43_dma_direct_fifo_rx(struct b43_wldev *dev, - unsigned int engine_index, bool enable) -{ - enum b43_dmatype type; - u16 mmio_base; - - type = dma_mask_to_engine_type(supported_dma_mask(dev)); - - mmio_base = b43_dmacontroller_base(type, engine_index); - direct_fifo_rx(dev, type, mmio_base, enable); -} diff --git a/drivers/net/wireless/b43/dma.h b/drivers/net/wireless/b43/dma.h deleted file mode 100644 index df8c8cdcb..000000000 --- a/drivers/net/wireless/b43/dma.h +++ /dev/null @@ -1,305 +0,0 @@ -#ifndef B43_DMA_H_ -#define B43_DMA_H_ - -#include <linux/err.h> - -#include "b43.h" - - -/* DMA-Interrupt reasons. */ -#define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \ - | (1 << 14) | (1 << 15)) -#define B43_DMAIRQ_RDESC_UFLOW (1 << 13) -#define B43_DMAIRQ_RX_DONE (1 << 16) - -/*** 32-bit DMA Engine. ***/ - -/* 32-bit DMA controller registers. */ -#define B43_DMA32_TXCTL 0x00 -#define B43_DMA32_TXENABLE 0x00000001 -#define B43_DMA32_TXSUSPEND 0x00000002 -#define B43_DMA32_TXLOOPBACK 0x00000004 -#define B43_DMA32_TXFLUSH 0x00000010 -#define B43_DMA32_TXPARITYDISABLE 0x00000800 -#define B43_DMA32_TXADDREXT_MASK 0x00030000 -#define B43_DMA32_TXADDREXT_SHIFT 16 -#define B43_DMA32_TXRING 0x04 -#define B43_DMA32_TXINDEX 0x08 -#define B43_DMA32_TXSTATUS 0x0C -#define B43_DMA32_TXDPTR 0x00000FFF -#define B43_DMA32_TXSTATE 0x0000F000 -#define B43_DMA32_TXSTAT_DISABLED 0x00000000 -#define B43_DMA32_TXSTAT_ACTIVE 0x00001000 -#define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000 -#define B43_DMA32_TXSTAT_STOPPED 0x00003000 -#define B43_DMA32_TXSTAT_SUSP 0x00004000 -#define B43_DMA32_TXERROR 0x000F0000 -#define B43_DMA32_TXERR_NOERR 0x00000000 -#define B43_DMA32_TXERR_PROT 0x00010000 -#define B43_DMA32_TXERR_UNDERRUN 0x00020000 -#define B43_DMA32_TXERR_BUFREAD 0x00030000 -#define B43_DMA32_TXERR_DESCREAD 0x00040000 -#define B43_DMA32_TXACTIVE 0xFFF00000 -#define B43_DMA32_RXCTL 0x10 -#define B43_DMA32_RXENABLE 0x00000001 -#define B43_DMA32_RXFROFF_MASK 0x000000FE -#define B43_DMA32_RXFROFF_SHIFT 1 -#define B43_DMA32_RXDIRECTFIFO 0x00000100 -#define B43_DMA32_RXPARITYDISABLE 0x00000800 -#define B43_DMA32_RXADDREXT_MASK 0x00030000 -#define B43_DMA32_RXADDREXT_SHIFT 16 -#define B43_DMA32_RXRING 0x14 -#define B43_DMA32_RXINDEX 0x18 -#define B43_DMA32_RXSTATUS 0x1C -#define B43_DMA32_RXDPTR 0x00000FFF -#define B43_DMA32_RXSTATE 0x0000F000 -#define B43_DMA32_RXSTAT_DISABLED 0x00000000 -#define B43_DMA32_RXSTAT_ACTIVE 0x00001000 -#define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000 -#define B43_DMA32_RXSTAT_STOPPED 0x00003000 -#define B43_DMA32_RXERROR 0x000F0000 -#define B43_DMA32_RXERR_NOERR 0x00000000 -#define B43_DMA32_RXERR_PROT 0x00010000 -#define B43_DMA32_RXERR_OVERFLOW 0x00020000 -#define B43_DMA32_RXERR_BUFWRITE 0x00030000 -#define B43_DMA32_RXERR_DESCREAD 0x00040000 -#define B43_DMA32_RXACTIVE 0xFFF00000 - -/* 32-bit DMA descriptor. */ -struct b43_dmadesc32 { - __le32 control; - __le32 address; -} __packed; -#define B43_DMA32_DCTL_BYTECNT 0x00001FFF -#define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000 -#define B43_DMA32_DCTL_ADDREXT_SHIFT 16 -#define B43_DMA32_DCTL_DTABLEEND 0x10000000 -#define B43_DMA32_DCTL_IRQ 0x20000000 -#define B43_DMA32_DCTL_FRAMEEND 0x40000000 -#define B43_DMA32_DCTL_FRAMESTART 0x80000000 - -/*** 64-bit DMA Engine. ***/ - -/* 64-bit DMA controller registers. */ -#define B43_DMA64_TXCTL 0x00 -#define B43_DMA64_TXENABLE 0x00000001 -#define B43_DMA64_TXSUSPEND 0x00000002 -#define B43_DMA64_TXLOOPBACK 0x00000004 -#define B43_DMA64_TXFLUSH 0x00000010 -#define B43_DMA64_TXPARITYDISABLE 0x00000800 -#define B43_DMA64_TXADDREXT_MASK 0x00030000 -#define B43_DMA64_TXADDREXT_SHIFT 16 -#define B43_DMA64_TXINDEX 0x04 -#define B43_DMA64_TXRINGLO 0x08 -#define B43_DMA64_TXRINGHI 0x0C -#define B43_DMA64_TXSTATUS 0x10 -#define B43_DMA64_TXSTATDPTR 0x00001FFF -#define B43_DMA64_TXSTAT 0xF0000000 -#define B43_DMA64_TXSTAT_DISABLED 0x00000000 -#define B43_DMA64_TXSTAT_ACTIVE 0x10000000 -#define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000 -#define B43_DMA64_TXSTAT_STOPPED 0x30000000 -#define B43_DMA64_TXSTAT_SUSP 0x40000000 -#define B43_DMA64_TXERROR 0x14 -#define B43_DMA64_TXERRDPTR 0x0001FFFF -#define B43_DMA64_TXERR 0xF0000000 -#define B43_DMA64_TXERR_NOERR 0x00000000 -#define B43_DMA64_TXERR_PROT 0x10000000 -#define B43_DMA64_TXERR_UNDERRUN 0x20000000 -#define B43_DMA64_TXERR_TRANSFER 0x30000000 -#define B43_DMA64_TXERR_DESCREAD 0x40000000 -#define B43_DMA64_TXERR_CORE 0x50000000 -#define B43_DMA64_RXCTL 0x20 -#define B43_DMA64_RXENABLE 0x00000001 -#define B43_DMA64_RXFROFF_MASK 0x000000FE -#define B43_DMA64_RXFROFF_SHIFT 1 -#define B43_DMA64_RXDIRECTFIFO 0x00000100 -#define B43_DMA64_RXPARITYDISABLE 0x00000800 -#define B43_DMA64_RXADDREXT_MASK 0x00030000 -#define B43_DMA64_RXADDREXT_SHIFT 16 -#define B43_DMA64_RXINDEX 0x24 -#define B43_DMA64_RXRINGLO 0x28 -#define B43_DMA64_RXRINGHI 0x2C -#define B43_DMA64_RXSTATUS 0x30 -#define B43_DMA64_RXSTATDPTR 0x00001FFF -#define B43_DMA64_RXSTAT 0xF0000000 -#define B43_DMA64_RXSTAT_DISABLED 0x00000000 -#define B43_DMA64_RXSTAT_ACTIVE 0x10000000 -#define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000 -#define B43_DMA64_RXSTAT_STOPPED 0x30000000 -#define B43_DMA64_RXSTAT_SUSP 0x40000000 -#define B43_DMA64_RXERROR 0x34 -#define B43_DMA64_RXERRDPTR 0x0001FFFF -#define B43_DMA64_RXERR 0xF0000000 -#define B43_DMA64_RXERR_NOERR 0x00000000 -#define B43_DMA64_RXERR_PROT 0x10000000 -#define B43_DMA64_RXERR_UNDERRUN 0x20000000 -#define B43_DMA64_RXERR_TRANSFER 0x30000000 -#define B43_DMA64_RXERR_DESCREAD 0x40000000 -#define B43_DMA64_RXERR_CORE 0x50000000 - -/* 64-bit DMA descriptor. */ -struct b43_dmadesc64 { - __le32 control0; - __le32 control1; - __le32 address_low; - __le32 address_high; -} __packed; -#define B43_DMA64_DCTL0_DTABLEEND 0x10000000 -#define B43_DMA64_DCTL0_IRQ 0x20000000 -#define B43_DMA64_DCTL0_FRAMEEND 0x40000000 -#define B43_DMA64_DCTL0_FRAMESTART 0x80000000 -#define B43_DMA64_DCTL1_BYTECNT 0x00001FFF -#define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000 -#define B43_DMA64_DCTL1_ADDREXT_SHIFT 16 - -struct b43_dmadesc_generic { - union { - struct b43_dmadesc32 dma32; - struct b43_dmadesc64 dma64; - } __packed; -} __packed; - -/* Misc DMA constants */ -#define B43_DMA32_RINGMEMSIZE 4096 -#define B43_DMA64_RINGMEMSIZE 8192 -/* Offset of frame with actual data */ -#define B43_DMA0_RX_FW598_FO 38 -#define B43_DMA0_RX_FW351_FO 30 - -/* DMA engine tuning knobs */ -#define B43_TXRING_SLOTS 256 -#define B43_RXRING_SLOTS 256 -#define B43_DMA0_RX_FW598_BUFSIZE (B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN) -#define B43_DMA0_RX_FW351_BUFSIZE (B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN) - -/* Pointer poison */ -#define B43_DMA_PTR_POISON ((void *)ERR_PTR(-ENOMEM)) -#define b43_dma_ptr_is_poisoned(ptr) (unlikely((ptr) == B43_DMA_PTR_POISON)) - - -struct sk_buff; -struct b43_private; -struct b43_txstatus; - -struct b43_dmadesc_meta { - /* The kernel DMA-able buffer. */ - struct sk_buff *skb; - /* DMA base bus-address of the descriptor buffer. */ - dma_addr_t dmaaddr; - /* ieee80211 TX status. Only used once per 802.11 frag. */ - bool is_last_fragment; -}; - -struct b43_dmaring; - -/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */ -struct b43_dma_ops { - struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring, - int slot, - struct b43_dmadesc_meta ** - meta); - void (*fill_descriptor) (struct b43_dmaring * ring, - struct b43_dmadesc_generic * desc, - dma_addr_t dmaaddr, u16 bufsize, int start, - int end, int irq); - void (*poke_tx) (struct b43_dmaring * ring, int slot); - void (*tx_suspend) (struct b43_dmaring * ring); - void (*tx_resume) (struct b43_dmaring * ring); - int (*get_current_rxslot) (struct b43_dmaring * ring); - void (*set_current_rxslot) (struct b43_dmaring * ring, int slot); -}; - -enum b43_dmatype { - B43_DMA_30BIT = 30, - B43_DMA_32BIT = 32, - B43_DMA_64BIT = 64, -}; - -enum b43_addrtype { - B43_DMA_ADDR_LOW, - B43_DMA_ADDR_HIGH, - B43_DMA_ADDR_EXT, -}; - -struct b43_dmaring { - /* Lowlevel DMA ops. */ - const struct b43_dma_ops *ops; - /* Kernel virtual base address of the ring memory. */ - void *descbase; - /* Meta data about all descriptors. */ - struct b43_dmadesc_meta *meta; - /* Cache of TX headers for each TX frame. - * This is to avoid an allocation on each TX. - * This is NULL for an RX ring. - */ - u8 *txhdr_cache; - /* (Unadjusted) DMA base bus-address of the ring memory. */ - dma_addr_t dmabase; - /* Number of descriptor slots in the ring. */ - int nr_slots; - /* Number of used descriptor slots. */ - int used_slots; - /* Currently used slot in the ring. */ - int current_slot; - /* Frameoffset in octets. */ - u32 frameoffset; - /* Descriptor buffer size. */ - u16 rx_buffersize; - /* The MMIO base register of the DMA controller. */ - u16 mmio_base; - /* DMA controller index number (0-5). */ - int index; - /* Boolean. Is this a TX ring? */ - bool tx; - /* The type of DMA engine used. */ - enum b43_dmatype type; - /* Boolean. Is this ring stopped at ieee80211 level? */ - bool stopped; - /* The QOS priority assigned to this ring. Only used for TX rings. - * This is the mac80211 "queue" value. */ - u8 queue_prio; - struct b43_wldev *dev; -#ifdef CONFIG_B43_DEBUG - /* Maximum number of used slots. */ - int max_used_slots; - /* Last time we injected a ring overflow. */ - unsigned long last_injected_overflow; - /* Statistics: Number of successfully transmitted packets */ - u64 nr_succeed_tx_packets; - /* Statistics: Number of failed TX packets */ - u64 nr_failed_tx_packets; - /* Statistics: Total number of TX plus all retries. */ - u64 nr_total_packet_tries; -#endif /* CONFIG_B43_DEBUG */ -}; - -static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset) -{ - return b43_read32(ring->dev, ring->mmio_base + offset); -} - -static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value) -{ - b43_write32(ring->dev, ring->mmio_base + offset, value); -} - -int b43_dma_init(struct b43_wldev *dev); -void b43_dma_free(struct b43_wldev *dev); - -void b43_dma_tx_suspend(struct b43_wldev *dev); -void b43_dma_tx_resume(struct b43_wldev *dev); - -int b43_dma_tx(struct b43_wldev *dev, - struct sk_buff *skb); -void b43_dma_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status); - -void b43_dma_handle_rx_overflow(struct b43_dmaring *ring); - -void b43_dma_rx(struct b43_dmaring *ring); - -void b43_dma_direct_fifo_rx(struct b43_wldev *dev, - unsigned int engine_index, bool enable); - -#endif /* B43_DMA_H_ */ diff --git a/drivers/net/wireless/b43/leds.c b/drivers/net/wireless/b43/leds.c deleted file mode 100644 index d79ab2a22..000000000 --- a/drivers/net/wireless/b43/leds.c +++ /dev/null @@ -1,359 +0,0 @@ -/* - - Broadcom B43 wireless driver - LED control - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> - Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "leds.h" -#include "rfkill.h" - - -static void b43_led_turn_on(struct b43_wldev *dev, u8 led_index, - bool activelow) -{ - u16 ctl; - - ctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL); - if (activelow) - ctl &= ~(1 << led_index); - else - ctl |= (1 << led_index); - b43_write16(dev, B43_MMIO_GPIO_CONTROL, ctl); -} - -static void b43_led_turn_off(struct b43_wldev *dev, u8 led_index, - bool activelow) -{ - u16 ctl; - - ctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL); - if (activelow) - ctl |= (1 << led_index); - else - ctl &= ~(1 << led_index); - b43_write16(dev, B43_MMIO_GPIO_CONTROL, ctl); -} - -static void b43_led_update(struct b43_wldev *dev, - struct b43_led *led) -{ - bool radio_enabled; - bool turn_on; - - if (!led->wl) - return; - - radio_enabled = (dev->phy.radio_on && dev->radio_hw_enable); - - /* The led->state read is racy, but we don't care. In case we raced - * with the brightness_set handler, we will be called again soon - * to fixup our state. */ - if (radio_enabled) - turn_on = atomic_read(&led->state) != LED_OFF; - else - turn_on = false; - if (turn_on == led->hw_state) - return; - led->hw_state = turn_on; - - if (turn_on) - b43_led_turn_on(dev, led->index, led->activelow); - else - b43_led_turn_off(dev, led->index, led->activelow); -} - -static void b43_leds_work(struct work_struct *work) -{ - struct b43_leds *leds = container_of(work, struct b43_leds, work); - struct b43_wl *wl = container_of(leds, struct b43_wl, leds); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) - goto out_unlock; - - b43_led_update(dev, &wl->leds.led_tx); - b43_led_update(dev, &wl->leds.led_rx); - b43_led_update(dev, &wl->leds.led_radio); - b43_led_update(dev, &wl->leds.led_assoc); - -out_unlock: - mutex_unlock(&wl->mutex); -} - -/* Callback from the LED subsystem. */ -static void b43_led_brightness_set(struct led_classdev *led_dev, - enum led_brightness brightness) -{ - struct b43_led *led = container_of(led_dev, struct b43_led, led_dev); - struct b43_wl *wl = led->wl; - - if (likely(!wl->leds.stop)) { - atomic_set(&led->state, brightness); - ieee80211_queue_work(wl->hw, &wl->leds.work); - } -} - -static int b43_register_led(struct b43_wldev *dev, struct b43_led *led, - const char *name, const char *default_trigger, - u8 led_index, bool activelow) -{ - int err; - - if (led->wl) - return -EEXIST; - if (!default_trigger) - return -EINVAL; - led->wl = dev->wl; - led->index = led_index; - led->activelow = activelow; - strncpy(led->name, name, sizeof(led->name)); - atomic_set(&led->state, 0); - - led->led_dev.name = led->name; - led->led_dev.default_trigger = default_trigger; - led->led_dev.brightness_set = b43_led_brightness_set; - - err = led_classdev_register(dev->dev->dev, &led->led_dev); - if (err) { - b43warn(dev->wl, "LEDs: Failed to register %s\n", name); - led->wl = NULL; - return err; - } - - return 0; -} - -static void b43_unregister_led(struct b43_led *led) -{ - if (!led->wl) - return; - led_classdev_unregister(&led->led_dev); - led->wl = NULL; -} - -static void b43_map_led(struct b43_wldev *dev, - u8 led_index, - enum b43_led_behaviour behaviour, - bool activelow) -{ - struct ieee80211_hw *hw = dev->wl->hw; - char name[B43_LED_MAX_NAME_LEN + 1]; - - /* Map the b43 specific LED behaviour value to the - * generic LED triggers. */ - switch (behaviour) { - case B43_LED_INACTIVE: - case B43_LED_OFF: - case B43_LED_ON: - break; - case B43_LED_ACTIVITY: - case B43_LED_TRANSFER: - case B43_LED_APTRANSFER: - snprintf(name, sizeof(name), - "b43-%s::tx", wiphy_name(hw->wiphy)); - b43_register_led(dev, &dev->wl->leds.led_tx, name, - ieee80211_get_tx_led_name(hw), - led_index, activelow); - snprintf(name, sizeof(name), - "b43-%s::rx", wiphy_name(hw->wiphy)); - b43_register_led(dev, &dev->wl->leds.led_rx, name, - ieee80211_get_rx_led_name(hw), - led_index, activelow); - break; - case B43_LED_RADIO_ALL: - case B43_LED_RADIO_A: - case B43_LED_RADIO_B: - case B43_LED_MODE_BG: - snprintf(name, sizeof(name), - "b43-%s::radio", wiphy_name(hw->wiphy)); - b43_register_led(dev, &dev->wl->leds.led_radio, name, - ieee80211_get_radio_led_name(hw), - led_index, activelow); - break; - case B43_LED_WEIRD: - case B43_LED_ASSOC: - snprintf(name, sizeof(name), - "b43-%s::assoc", wiphy_name(hw->wiphy)); - b43_register_led(dev, &dev->wl->leds.led_assoc, name, - ieee80211_get_assoc_led_name(hw), - led_index, activelow); - break; - default: - b43warn(dev->wl, "LEDs: Unknown behaviour 0x%02X\n", - behaviour); - break; - } -} - -static void b43_led_get_sprominfo(struct b43_wldev *dev, - unsigned int led_index, - enum b43_led_behaviour *behaviour, - bool *activelow) -{ - u8 sprom[4]; - - sprom[0] = dev->dev->bus_sprom->gpio0; - sprom[1] = dev->dev->bus_sprom->gpio1; - sprom[2] = dev->dev->bus_sprom->gpio2; - sprom[3] = dev->dev->bus_sprom->gpio3; - - if (sprom[led_index] == 0xFF) { - /* There is no LED information in the SPROM - * for this LED. Hardcode it here. */ - *activelow = false; - switch (led_index) { - case 0: - *behaviour = B43_LED_ACTIVITY; - *activelow = true; - if (dev->dev->board_vendor == PCI_VENDOR_ID_COMPAQ) - *behaviour = B43_LED_RADIO_ALL; - break; - case 1: - *behaviour = B43_LED_RADIO_B; - if (dev->dev->board_vendor == PCI_VENDOR_ID_ASUSTEK) - *behaviour = B43_LED_ASSOC; - break; - case 2: - *behaviour = B43_LED_RADIO_A; - break; - case 3: - *behaviour = B43_LED_OFF; - break; - default: - *behaviour = B43_LED_OFF; - B43_WARN_ON(1); - return; - } - } else { - *behaviour = sprom[led_index] & B43_LED_BEHAVIOUR; - *activelow = !!(sprom[led_index] & B43_LED_ACTIVELOW); - } -} - -void b43_leds_init(struct b43_wldev *dev) -{ - struct b43_led *led; - unsigned int i; - enum b43_led_behaviour behaviour; - bool activelow; - - /* Sync the RF-kill LED state (if we have one) with radio and switch states. */ - led = &dev->wl->leds.led_radio; - if (led->wl) { - if (dev->phy.radio_on && b43_is_hw_radio_enabled(dev)) { - b43_led_turn_on(dev, led->index, led->activelow); - led->hw_state = true; - atomic_set(&led->state, 1); - } else { - b43_led_turn_off(dev, led->index, led->activelow); - led->hw_state = false; - atomic_set(&led->state, 0); - } - } - - /* Initialize TX/RX/ASSOC leds */ - led = &dev->wl->leds.led_tx; - if (led->wl) { - b43_led_turn_off(dev, led->index, led->activelow); - led->hw_state = false; - atomic_set(&led->state, 0); - } - led = &dev->wl->leds.led_rx; - if (led->wl) { - b43_led_turn_off(dev, led->index, led->activelow); - led->hw_state = false; - atomic_set(&led->state, 0); - } - led = &dev->wl->leds.led_assoc; - if (led->wl) { - b43_led_turn_off(dev, led->index, led->activelow); - led->hw_state = false; - atomic_set(&led->state, 0); - } - - /* Initialize other LED states. */ - for (i = 0; i < B43_MAX_NR_LEDS; i++) { - b43_led_get_sprominfo(dev, i, &behaviour, &activelow); - switch (behaviour) { - case B43_LED_OFF: - b43_led_turn_off(dev, i, activelow); - break; - case B43_LED_ON: - b43_led_turn_on(dev, i, activelow); - break; - default: - /* Leave others as-is. */ - break; - } - } - - dev->wl->leds.stop = 0; -} - -void b43_leds_exit(struct b43_wldev *dev) -{ - struct b43_leds *leds = &dev->wl->leds; - - b43_led_turn_off(dev, leds->led_tx.index, leds->led_tx.activelow); - b43_led_turn_off(dev, leds->led_rx.index, leds->led_rx.activelow); - b43_led_turn_off(dev, leds->led_assoc.index, leds->led_assoc.activelow); - b43_led_turn_off(dev, leds->led_radio.index, leds->led_radio.activelow); -} - -void b43_leds_stop(struct b43_wldev *dev) -{ - struct b43_leds *leds = &dev->wl->leds; - - leds->stop = 1; - cancel_work_sync(&leds->work); -} - -void b43_leds_register(struct b43_wldev *dev) -{ - unsigned int i; - enum b43_led_behaviour behaviour; - bool activelow; - - INIT_WORK(&dev->wl->leds.work, b43_leds_work); - - /* Register the LEDs to the LED subsystem. */ - for (i = 0; i < B43_MAX_NR_LEDS; i++) { - b43_led_get_sprominfo(dev, i, &behaviour, &activelow); - b43_map_led(dev, i, behaviour, activelow); - } -} - -void b43_leds_unregister(struct b43_wl *wl) -{ - struct b43_leds *leds = &wl->leds; - - b43_unregister_led(&leds->led_tx); - b43_unregister_led(&leds->led_rx); - b43_unregister_led(&leds->led_assoc); - b43_unregister_led(&leds->led_radio); -} diff --git a/drivers/net/wireless/b43/leds.h b/drivers/net/wireless/b43/leds.h deleted file mode 100644 index 32b66d53c..000000000 --- a/drivers/net/wireless/b43/leds.h +++ /dev/null @@ -1,94 +0,0 @@ -#ifndef B43_LEDS_H_ -#define B43_LEDS_H_ - -struct b43_wl; -struct b43_wldev; - -#ifdef CONFIG_B43_LEDS - -#include <linux/types.h> -#include <linux/leds.h> -#include <linux/workqueue.h> - - -#define B43_LED_MAX_NAME_LEN 31 - -struct b43_led { - struct b43_wl *wl; - /* The LED class device */ - struct led_classdev led_dev; - /* The index number of the LED. */ - u8 index; - /* If activelow is true, the LED is ON if the - * bit is switched off. */ - bool activelow; - /* The unique name string for this LED device. */ - char name[B43_LED_MAX_NAME_LEN + 1]; - /* The current status of the LED. This is updated locklessly. */ - atomic_t state; - /* The active state in hardware. */ - bool hw_state; -}; - -struct b43_leds { - struct b43_led led_tx; - struct b43_led led_rx; - struct b43_led led_radio; - struct b43_led led_assoc; - - bool stop; - struct work_struct work; -}; - -#define B43_MAX_NR_LEDS 4 - -#define B43_LED_BEHAVIOUR 0x7F -#define B43_LED_ACTIVELOW 0x80 -/* LED behaviour values */ -enum b43_led_behaviour { - B43_LED_OFF, - B43_LED_ON, - B43_LED_ACTIVITY, - B43_LED_RADIO_ALL, - B43_LED_RADIO_A, - B43_LED_RADIO_B, - B43_LED_MODE_BG, - B43_LED_TRANSFER, - B43_LED_APTRANSFER, - B43_LED_WEIRD, //FIXME - B43_LED_ASSOC, - B43_LED_INACTIVE, -}; - -void b43_leds_register(struct b43_wldev *dev); -void b43_leds_unregister(struct b43_wl *wl); -void b43_leds_init(struct b43_wldev *dev); -void b43_leds_exit(struct b43_wldev *dev); -void b43_leds_stop(struct b43_wldev *dev); - - -#else /* CONFIG_B43_LEDS */ -/* LED support disabled */ - -struct b43_leds { - /* empty */ -}; - -static inline void b43_leds_register(struct b43_wldev *dev) -{ -} -static inline void b43_leds_unregister(struct b43_wl *wl) -{ -} -static inline void b43_leds_init(struct b43_wldev *dev) -{ -} -static inline void b43_leds_exit(struct b43_wldev *dev) -{ -} -static inline void b43_leds_stop(struct b43_wldev *dev) -{ -} -#endif /* CONFIG_B43_LEDS */ - -#endif /* B43_LEDS_H_ */ diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c deleted file mode 100644 index a335f94c7..000000000 --- a/drivers/net/wireless/b43/lo.c +++ /dev/null @@ -1,1016 +0,0 @@ -/* - - Broadcom B43 wireless driver - - G PHY LO (LocalOscillator) Measuring and Control routines - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005, 2006 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> - Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "lo.h" -#include "phy_g.h" -#include "main.h" - -#include <linux/delay.h> -#include <linux/sched.h> -#include <linux/slab.h> - - -static struct b43_lo_calib *b43_find_lo_calib(struct b43_txpower_lo_control *lo, - const struct b43_bbatt *bbatt, - const struct b43_rfatt *rfatt) -{ - struct b43_lo_calib *c; - - list_for_each_entry(c, &lo->calib_list, list) { - if (!b43_compare_bbatt(&c->bbatt, bbatt)) - continue; - if (!b43_compare_rfatt(&c->rfatt, rfatt)) - continue; - return c; - } - - return NULL; -} - -/* Write the LocalOscillator Control (adjust) value-pair. */ -static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control) -{ - struct b43_phy *phy = &dev->phy; - u16 value; - - if (B43_DEBUG) { - if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) { - b43dbg(dev->wl, "Invalid LO control pair " - "(I: %d, Q: %d)\n", control->i, control->q); - dump_stack(); - return; - } - } - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - - value = (u8) (control->q); - value |= ((u8) (control->i)) << 8; - b43_phy_write(dev, B43_PHY_LO_CTL, value); -} - -static u16 lo_measure_feedthrough(struct b43_wldev *dev, - u16 lna, u16 pga, u16 trsw_rx) -{ - struct b43_phy *phy = &dev->phy; - u16 rfover; - u16 feedthrough; - - if (phy->gmode) { - lna <<= B43_PHY_RFOVERVAL_LNA_SHIFT; - pga <<= B43_PHY_RFOVERVAL_PGA_SHIFT; - - B43_WARN_ON(lna & ~B43_PHY_RFOVERVAL_LNA); - B43_WARN_ON(pga & ~B43_PHY_RFOVERVAL_PGA); -/*FIXME This assertion fails B43_WARN_ON(trsw_rx & ~(B43_PHY_RFOVERVAL_TRSWRX | - B43_PHY_RFOVERVAL_BW)); -*/ - trsw_rx &= (B43_PHY_RFOVERVAL_TRSWRX | B43_PHY_RFOVERVAL_BW); - - /* Construct the RF Override Value */ - rfover = B43_PHY_RFOVERVAL_UNK; - rfover |= pga; - rfover |= lna; - rfover |= trsw_rx; - if ((dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) - && phy->rev > 6) - rfover |= B43_PHY_RFOVERVAL_EXTLNA; - - b43_phy_write(dev, B43_PHY_PGACTL, 0xE300); - b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover); - udelay(10); - rfover |= B43_PHY_RFOVERVAL_BW_LBW; - b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover); - udelay(10); - rfover |= B43_PHY_RFOVERVAL_BW_LPF; - b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover); - udelay(10); - b43_phy_write(dev, B43_PHY_PGACTL, 0xF300); - } else { - pga |= B43_PHY_PGACTL_UNKNOWN; - b43_phy_write(dev, B43_PHY_PGACTL, pga); - udelay(10); - pga |= B43_PHY_PGACTL_LOWBANDW; - b43_phy_write(dev, B43_PHY_PGACTL, pga); - udelay(10); - pga |= B43_PHY_PGACTL_LPF; - b43_phy_write(dev, B43_PHY_PGACTL, pga); - } - udelay(21); - feedthrough = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); - - /* This is a good place to check if we need to relax a bit, - * as this is the main function called regularly - * in the LO calibration. */ - cond_resched(); - - return feedthrough; -} - -/* TXCTL Register and Value Table. - * Returns the "TXCTL Register". - * "value" is the "TXCTL Value". - * "pad_mix_gain" is the PAD Mixer Gain. - */ -static u16 lo_txctl_register_table(struct b43_wldev *dev, - u16 *value, u16 *pad_mix_gain) -{ - struct b43_phy *phy = &dev->phy; - u16 reg, v, padmix; - - if (phy->type == B43_PHYTYPE_B) { - v = 0x30; - if (phy->radio_rev <= 5) { - reg = 0x43; - padmix = 0; - } else { - reg = 0x52; - padmix = 5; - } - } else { - if (phy->rev >= 2 && phy->radio_rev == 8) { - reg = 0x43; - v = 0x10; - padmix = 2; - } else { - reg = 0x52; - v = 0x30; - padmix = 5; - } - } - if (value) - *value = v; - if (pad_mix_gain) - *pad_mix_gain = padmix; - - return reg; -} - -static void lo_measure_txctl_values(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - u16 reg, mask; - u16 trsw_rx, pga; - u16 radio_pctl_reg; - - static const u8 tx_bias_values[] = { - 0x09, 0x08, 0x0A, 0x01, 0x00, - 0x02, 0x05, 0x04, 0x06, - }; - static const u8 tx_magn_values[] = { - 0x70, 0x40, - }; - - if (!has_loopback_gain(phy)) { - radio_pctl_reg = 6; - trsw_rx = 2; - pga = 0; - } else { - int lb_gain; /* Loopback gain (in dB) */ - - trsw_rx = 0; - lb_gain = gphy->max_lb_gain / 2; - if (lb_gain > 10) { - radio_pctl_reg = 0; - pga = abs(10 - lb_gain) / 6; - pga = clamp_val(pga, 0, 15); - } else { - int cmp_val; - int tmp; - - pga = 0; - cmp_val = 0x24; - if ((phy->rev >= 2) && - (phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) - cmp_val = 0x3C; - tmp = lb_gain; - if ((10 - lb_gain) < cmp_val) - tmp = (10 - lb_gain); - if (tmp < 0) - tmp += 6; - else - tmp += 3; - cmp_val /= 4; - tmp /= 4; - if (tmp >= cmp_val) - radio_pctl_reg = cmp_val; - else - radio_pctl_reg = tmp; - } - } - b43_radio_maskset(dev, 0x43, 0xFFF0, radio_pctl_reg); - b43_gphy_set_baseband_attenuation(dev, 2); - - reg = lo_txctl_register_table(dev, &mask, NULL); - mask = ~mask; - b43_radio_mask(dev, reg, mask); - - if (has_tx_magnification(phy)) { - int i, j; - int feedthrough; - int min_feedth = 0xFFFF; - u8 tx_magn, tx_bias; - - for (i = 0; i < ARRAY_SIZE(tx_magn_values); i++) { - tx_magn = tx_magn_values[i]; - b43_radio_maskset(dev, 0x52, 0xFF0F, tx_magn); - for (j = 0; j < ARRAY_SIZE(tx_bias_values); j++) { - tx_bias = tx_bias_values[j]; - b43_radio_maskset(dev, 0x52, 0xFFF0, tx_bias); - feedthrough = - lo_measure_feedthrough(dev, 0, pga, - trsw_rx); - if (feedthrough < min_feedth) { - lo->tx_bias = tx_bias; - lo->tx_magn = tx_magn; - min_feedth = feedthrough; - } - if (lo->tx_bias == 0) - break; - } - b43_radio_write16(dev, 0x52, - (b43_radio_read16(dev, 0x52) - & 0xFF00) | lo->tx_bias | lo-> - tx_magn); - } - } else { - lo->tx_magn = 0; - lo->tx_bias = 0; - b43_radio_mask(dev, 0x52, 0xFFF0); /* TX bias == 0 */ - } - lo->txctl_measured_time = jiffies; -} - -static void lo_read_power_vector(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - int i; - u64 tmp; - u64 power_vector = 0; - - for (i = 0; i < 8; i += 2) { - tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x310 + i); - power_vector |= (tmp << (i * 8)); - /* Clear the vector on the device. */ - b43_shm_write16(dev, B43_SHM_SHARED, 0x310 + i, 0); - } - if (power_vector) - lo->power_vector = power_vector; - lo->pwr_vec_read_time = jiffies; -} - -/* 802.11/LO/GPHY/MeasuringGains */ -static void lo_measure_gain_values(struct b43_wldev *dev, - s16 max_rx_gain, int use_trsw_rx) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 tmp; - - if (max_rx_gain < 0) - max_rx_gain = 0; - - if (has_loopback_gain(phy)) { - int trsw_rx_gain; - - if (use_trsw_rx) { - trsw_rx_gain = gphy->trsw_rx_gain / 2; - if (max_rx_gain >= trsw_rx_gain) { - trsw_rx_gain = max_rx_gain - trsw_rx_gain; - } - } else - trsw_rx_gain = max_rx_gain; - if (trsw_rx_gain < 9) { - gphy->lna_lod_gain = 0; - } else { - gphy->lna_lod_gain = 1; - trsw_rx_gain -= 8; - } - trsw_rx_gain = clamp_val(trsw_rx_gain, 0, 0x2D); - gphy->pga_gain = trsw_rx_gain / 3; - if (gphy->pga_gain >= 5) { - gphy->pga_gain -= 5; - gphy->lna_gain = 2; - } else - gphy->lna_gain = 0; - } else { - gphy->lna_gain = 0; - gphy->trsw_rx_gain = 0x20; - if (max_rx_gain >= 0x14) { - gphy->lna_lod_gain = 1; - gphy->pga_gain = 2; - } else if (max_rx_gain >= 0x12) { - gphy->lna_lod_gain = 1; - gphy->pga_gain = 1; - } else if (max_rx_gain >= 0xF) { - gphy->lna_lod_gain = 1; - gphy->pga_gain = 0; - } else { - gphy->lna_lod_gain = 0; - gphy->pga_gain = 0; - } - } - - tmp = b43_radio_read16(dev, 0x7A); - if (gphy->lna_lod_gain == 0) - tmp &= ~0x0008; - else - tmp |= 0x0008; - b43_radio_write16(dev, 0x7A, tmp); -} - -struct lo_g_saved_values { - u8 old_channel; - - /* Core registers */ - u16 reg_3F4; - u16 reg_3E2; - - /* PHY registers */ - u16 phy_lo_mask; - u16 phy_extg_01; - u16 phy_dacctl_hwpctl; - u16 phy_dacctl; - u16 phy_cck_14; - u16 phy_hpwr_tssictl; - u16 phy_analogover; - u16 phy_analogoverval; - u16 phy_rfover; - u16 phy_rfoverval; - u16 phy_classctl; - u16 phy_cck_3E; - u16 phy_crs0; - u16 phy_pgactl; - u16 phy_cck_2A; - u16 phy_syncctl; - u16 phy_cck_30; - u16 phy_cck_06; - - /* Radio registers */ - u16 radio_43; - u16 radio_7A; - u16 radio_52; -}; - -static void lo_measure_setup(struct b43_wldev *dev, - struct lo_g_saved_values *sav) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - u16 tmp; - - if (b43_has_hardware_pctl(dev)) { - sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); - sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01)); - sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL); - sav->phy_cck_14 = b43_phy_read(dev, B43_PHY_CCK(0x14)); - sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL); - - b43_phy_set(dev, B43_PHY_HPWR_TSSICTL, 0x100); - b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x40); - b43_phy_set(dev, B43_PHY_DACCTL, 0x40); - b43_phy_set(dev, B43_PHY_CCK(0x14), 0x200); - } - if (phy->type == B43_PHYTYPE_B && - phy->radio_ver == 0x2050 && phy->radio_rev < 6) { - b43_phy_write(dev, B43_PHY_CCK(0x16), 0x410); - b43_phy_write(dev, B43_PHY_CCK(0x17), 0x820); - } - if (phy->rev >= 2) { - sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); - sav->phy_analogoverval = - b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); - sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); - sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); - sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); - sav->phy_cck_3E = b43_phy_read(dev, B43_PHY_CCK(0x3E)); - sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); - - b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); - b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); - b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); - b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); - if (phy->type == B43_PHYTYPE_G) { - if ((phy->rev >= 7) && - (sprom->boardflags_lo & B43_BFL_EXTLNA)) { - b43_phy_write(dev, B43_PHY_RFOVER, 0x933); - } else { - b43_phy_write(dev, B43_PHY_RFOVER, 0x133); - } - } else { - b43_phy_write(dev, B43_PHY_RFOVER, 0); - } - b43_phy_write(dev, B43_PHY_CCK(0x3E), 0); - } - sav->reg_3F4 = b43_read16(dev, 0x3F4); - sav->reg_3E2 = b43_read16(dev, 0x3E2); - sav->radio_43 = b43_radio_read16(dev, 0x43); - sav->radio_7A = b43_radio_read16(dev, 0x7A); - sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); - sav->phy_cck_2A = b43_phy_read(dev, B43_PHY_CCK(0x2A)); - sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); - sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL); - - if (!has_tx_magnification(phy)) { - sav->radio_52 = b43_radio_read16(dev, 0x52); - sav->radio_52 &= 0x00F0; - } - if (phy->type == B43_PHYTYPE_B) { - sav->phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); - sav->phy_cck_06 = b43_phy_read(dev, B43_PHY_CCK(0x06)); - b43_phy_write(dev, B43_PHY_CCK(0x30), 0x00FF); - b43_phy_write(dev, B43_PHY_CCK(0x06), 0x3F3F); - } else { - b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) - | 0x8000); - } - b43_write16(dev, 0x3F4, b43_read16(dev, 0x3F4) - & 0xF000); - - tmp = - (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_CCK(0x2E); - b43_phy_write(dev, tmp, 0x007F); - - tmp = sav->phy_syncctl; - b43_phy_write(dev, B43_PHY_SYNCCTL, tmp & 0xFF7F); - tmp = sav->radio_7A; - b43_radio_write16(dev, 0x007A, tmp & 0xFFF0); - - b43_phy_write(dev, B43_PHY_CCK(0x2A), 0x8A3); - if (phy->type == B43_PHYTYPE_G || - (phy->type == B43_PHYTYPE_B && - phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) { - b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1003); - } else - b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802); - if (phy->rev >= 2) - b43_dummy_transmission(dev, false, true); - b43_gphy_channel_switch(dev, 6, 0); - b43_radio_read16(dev, 0x51); /* dummy read */ - if (phy->type == B43_PHYTYPE_G) - b43_phy_write(dev, B43_PHY_CCK(0x2F), 0); - - /* Re-measure the txctl values, if needed. */ - if (time_before(lo->txctl_measured_time, - jiffies - B43_LO_TXCTL_EXPIRE)) - lo_measure_txctl_values(dev); - - if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) { - b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078); - } else { - if (phy->type == B43_PHYTYPE_B) - b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078); - else - b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); - } -} - -static void lo_measure_restore(struct b43_wldev *dev, - struct lo_g_saved_values *sav) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 tmp; - - if (phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_PGACTL, 0xE300); - tmp = (gphy->pga_gain << 8); - b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0); - udelay(5); - b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2); - udelay(2); - b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3); - } else { - tmp = (gphy->pga_gain | 0xEFA0); - b43_phy_write(dev, B43_PHY_PGACTL, tmp); - } - if (phy->type == B43_PHYTYPE_G) { - if (phy->rev >= 3) - b43_phy_write(dev, B43_PHY_CCK(0x2E), 0xC078); - else - b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8078); - if (phy->rev >= 2) - b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0202); - else - b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x0101); - } - b43_write16(dev, 0x3F4, sav->reg_3F4); - b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl); - b43_phy_write(dev, B43_PHY_CCK(0x2A), sav->phy_cck_2A); - b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl); - b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl); - b43_radio_write16(dev, 0x43, sav->radio_43); - b43_radio_write16(dev, 0x7A, sav->radio_7A); - if (!has_tx_magnification(phy)) { - tmp = sav->radio_52; - b43_radio_maskset(dev, 0x52, 0xFF0F, tmp); - } - b43_write16(dev, 0x3E2, sav->reg_3E2); - if (phy->type == B43_PHYTYPE_B && - phy->radio_ver == 0x2050 && phy->radio_rev <= 5) { - b43_phy_write(dev, B43_PHY_CCK(0x30), sav->phy_cck_30); - b43_phy_write(dev, B43_PHY_CCK(0x06), sav->phy_cck_06); - } - if (phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover); - b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, - sav->phy_analogoverval); - b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl); - b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover); - b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval); - b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E); - b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0); - } - if (b43_has_hardware_pctl(dev)) { - tmp = (sav->phy_lo_mask & 0xBFFF); - b43_phy_write(dev, B43_PHY_LO_MASK, tmp); - b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01); - b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl); - b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14); - b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl); - } - b43_gphy_channel_switch(dev, sav->old_channel, 1); -} - -struct b43_lo_g_statemachine { - int current_state; - int nr_measured; - int state_val_multiplier; - u16 lowest_feedth; - struct b43_loctl min_loctl; -}; - -/* Loop over each possible value in this state. */ -static int lo_probe_possible_loctls(struct b43_wldev *dev, - struct b43_loctl *probe_loctl, - struct b43_lo_g_statemachine *d) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_loctl test_loctl; - struct b43_loctl orig_loctl; - struct b43_loctl prev_loctl = { - .i = -100, - .q = -100, - }; - int i; - int begin, end; - int found_lower = 0; - u16 feedth; - - static const struct b43_loctl modifiers[] = { - {.i = 1,.q = 1,}, - {.i = 1,.q = 0,}, - {.i = 1,.q = -1,}, - {.i = 0,.q = -1,}, - {.i = -1,.q = -1,}, - {.i = -1,.q = 0,}, - {.i = -1,.q = 1,}, - {.i = 0,.q = 1,}, - }; - - if (d->current_state == 0) { - begin = 1; - end = 8; - } else if (d->current_state % 2 == 0) { - begin = d->current_state - 1; - end = d->current_state + 1; - } else { - begin = d->current_state - 2; - end = d->current_state + 2; - } - if (begin < 1) - begin += 8; - if (end > 8) - end -= 8; - - memcpy(&orig_loctl, probe_loctl, sizeof(struct b43_loctl)); - i = begin; - d->current_state = i; - while (1) { - B43_WARN_ON(!(i >= 1 && i <= 8)); - memcpy(&test_loctl, &orig_loctl, sizeof(struct b43_loctl)); - test_loctl.i += modifiers[i - 1].i * d->state_val_multiplier; - test_loctl.q += modifiers[i - 1].q * d->state_val_multiplier; - if ((test_loctl.i != prev_loctl.i || - test_loctl.q != prev_loctl.q) && - (abs(test_loctl.i) <= 16 && abs(test_loctl.q) <= 16)) { - b43_lo_write(dev, &test_loctl); - feedth = lo_measure_feedthrough(dev, gphy->lna_gain, - gphy->pga_gain, - gphy->trsw_rx_gain); - if (feedth < d->lowest_feedth) { - memcpy(probe_loctl, &test_loctl, - sizeof(struct b43_loctl)); - found_lower = 1; - d->lowest_feedth = feedth; - if ((d->nr_measured < 2) && - !has_loopback_gain(phy)) - break; - } - } - memcpy(&prev_loctl, &test_loctl, sizeof(prev_loctl)); - if (i == end) - break; - if (i == 8) - i = 1; - else - i++; - d->current_state = i; - } - - return found_lower; -} - -static void lo_probe_loctls_statemachine(struct b43_wldev *dev, - struct b43_loctl *loctl, - int *max_rx_gain) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_lo_g_statemachine d; - u16 feedth; - int found_lower; - struct b43_loctl probe_loctl; - int max_repeat = 1, repeat_cnt = 0; - - d.nr_measured = 0; - d.state_val_multiplier = 1; - if (has_loopback_gain(phy)) - d.state_val_multiplier = 3; - - memcpy(&d.min_loctl, loctl, sizeof(struct b43_loctl)); - if (has_loopback_gain(phy)) - max_repeat = 4; - do { - b43_lo_write(dev, &d.min_loctl); - feedth = lo_measure_feedthrough(dev, gphy->lna_gain, - gphy->pga_gain, - gphy->trsw_rx_gain); - if (feedth < 0x258) { - if (feedth >= 0x12C) - *max_rx_gain += 6; - else - *max_rx_gain += 3; - feedth = lo_measure_feedthrough(dev, gphy->lna_gain, - gphy->pga_gain, - gphy->trsw_rx_gain); - } - d.lowest_feedth = feedth; - - d.current_state = 0; - do { - B43_WARN_ON(! - (d.current_state >= 0 - && d.current_state <= 8)); - memcpy(&probe_loctl, &d.min_loctl, - sizeof(struct b43_loctl)); - found_lower = - lo_probe_possible_loctls(dev, &probe_loctl, &d); - if (!found_lower) - break; - if ((probe_loctl.i == d.min_loctl.i) && - (probe_loctl.q == d.min_loctl.q)) - break; - memcpy(&d.min_loctl, &probe_loctl, - sizeof(struct b43_loctl)); - d.nr_measured++; - } while (d.nr_measured < 24); - memcpy(loctl, &d.min_loctl, sizeof(struct b43_loctl)); - - if (has_loopback_gain(phy)) { - if (d.lowest_feedth > 0x1194) - *max_rx_gain -= 6; - else if (d.lowest_feedth < 0x5DC) - *max_rx_gain += 3; - if (repeat_cnt == 0) { - if (d.lowest_feedth <= 0x5DC) { - d.state_val_multiplier = 1; - repeat_cnt++; - } else - d.state_val_multiplier = 2; - } else if (repeat_cnt == 2) - d.state_val_multiplier = 1; - } - lo_measure_gain_values(dev, *max_rx_gain, - has_loopback_gain(phy)); - } while (++repeat_cnt < max_repeat); -} - -static -struct b43_lo_calib *b43_calibrate_lo_setting(struct b43_wldev *dev, - const struct b43_bbatt *bbatt, - const struct b43_rfatt *rfatt) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_loctl loctl = { - .i = 0, - .q = 0, - }; - int max_rx_gain; - struct b43_lo_calib *cal; - struct lo_g_saved_values uninitialized_var(saved_regs); - /* Values from the "TXCTL Register and Value Table" */ - u16 txctl_reg; - u16 txctl_value; - u16 pad_mix_gain; - - saved_regs.old_channel = phy->channel; - b43_mac_suspend(dev); - lo_measure_setup(dev, &saved_regs); - - txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain); - - b43_radio_maskset(dev, 0x43, 0xFFF0, rfatt->att); - b43_radio_maskset(dev, txctl_reg, ~txctl_value, (rfatt->with_padmix ? txctl_value :0)); - - max_rx_gain = rfatt->att * 2; - max_rx_gain += bbatt->att / 2; - if (rfatt->with_padmix) - max_rx_gain -= pad_mix_gain; - if (has_loopback_gain(phy)) - max_rx_gain += gphy->max_lb_gain; - lo_measure_gain_values(dev, max_rx_gain, - has_loopback_gain(phy)); - - b43_gphy_set_baseband_attenuation(dev, bbatt->att); - lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain); - - lo_measure_restore(dev, &saved_regs); - b43_mac_enable(dev); - - if (b43_debug(dev, B43_DBG_LO)) { - b43dbg(dev->wl, "LO: Calibrated for BB(%u), RF(%u,%u) " - "=> I=%d Q=%d\n", - bbatt->att, rfatt->att, rfatt->with_padmix, - loctl.i, loctl.q); - } - - cal = kmalloc(sizeof(*cal), GFP_KERNEL); - if (!cal) { - b43warn(dev->wl, "LO calib: out of memory\n"); - return NULL; - } - memcpy(&cal->bbatt, bbatt, sizeof(*bbatt)); - memcpy(&cal->rfatt, rfatt, sizeof(*rfatt)); - memcpy(&cal->ctl, &loctl, sizeof(loctl)); - cal->calib_time = jiffies; - INIT_LIST_HEAD(&cal->list); - - return cal; -} - -/* Get a calibrated LO setting for the given attenuation values. - * Might return a NULL pointer under OOM! */ -static -struct b43_lo_calib *b43_get_calib_lo_settings(struct b43_wldev *dev, - const struct b43_bbatt *bbatt, - const struct b43_rfatt *rfatt) -{ - struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; - struct b43_lo_calib *c; - - c = b43_find_lo_calib(lo, bbatt, rfatt); - if (c) - return c; - /* Not in the list of calibrated LO settings. - * Calibrate it now. */ - c = b43_calibrate_lo_setting(dev, bbatt, rfatt); - if (!c) - return NULL; - list_add(&c->list, &lo->calib_list); - - return c; -} - -void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - int i; - int rf_offset, bb_offset; - const struct b43_rfatt *rfatt; - const struct b43_bbatt *bbatt; - u64 power_vector; - bool table_changed = false; - - BUILD_BUG_ON(B43_DC_LT_SIZE != 32); - B43_WARN_ON(lo->rfatt_list.len * lo->bbatt_list.len > 64); - - power_vector = lo->power_vector; - if (!update_all && !power_vector) - return; /* Nothing to do. */ - - /* Suspend the MAC now to avoid continuous suspend/enable - * cycles in the loop. */ - b43_mac_suspend(dev); - - for (i = 0; i < B43_DC_LT_SIZE * 2; i++) { - struct b43_lo_calib *cal; - int idx; - u16 val; - - if (!update_all && !(power_vector & (((u64)1ULL) << i))) - continue; - /* Update the table entry for this power_vector bit. - * The table rows are RFatt entries and columns are BBatt. */ - bb_offset = i / lo->rfatt_list.len; - rf_offset = i % lo->rfatt_list.len; - bbatt = &(lo->bbatt_list.list[bb_offset]); - rfatt = &(lo->rfatt_list.list[rf_offset]); - - cal = b43_calibrate_lo_setting(dev, bbatt, rfatt); - if (!cal) { - b43warn(dev->wl, "LO: Could not " - "calibrate DC table entry\n"); - continue; - } - /*FIXME: Is Q really in the low nibble? */ - val = (u8)(cal->ctl.q); - val |= ((u8)(cal->ctl.i)) << 4; - kfree(cal); - - /* Get the index into the hardware DC LT. */ - idx = i / 2; - /* Change the table in memory. */ - if (i % 2) { - /* Change the high byte. */ - lo->dc_lt[idx] = (lo->dc_lt[idx] & 0x00FF) - | ((val & 0x00FF) << 8); - } else { - /* Change the low byte. */ - lo->dc_lt[idx] = (lo->dc_lt[idx] & 0xFF00) - | (val & 0x00FF); - } - table_changed = true; - } - if (table_changed) { - /* The table changed in memory. Update the hardware table. */ - for (i = 0; i < B43_DC_LT_SIZE; i++) - b43_phy_write(dev, 0x3A0 + i, lo->dc_lt[i]); - } - b43_mac_enable(dev); -} - -/* Fixup the RF attenuation value for the case where we are - * using the PAD mixer. */ -static inline void b43_lo_fixup_rfatt(struct b43_rfatt *rf) -{ - if (!rf->with_padmix) - return; - if ((rf->att != 1) && (rf->att != 2) && (rf->att != 3)) - rf->att = 4; -} - -void b43_lo_g_adjust(struct b43_wldev *dev) -{ - struct b43_phy_g *gphy = dev->phy.g; - struct b43_lo_calib *cal; - struct b43_rfatt rf; - - memcpy(&rf, &gphy->rfatt, sizeof(rf)); - b43_lo_fixup_rfatt(&rf); - - cal = b43_get_calib_lo_settings(dev, &gphy->bbatt, &rf); - if (!cal) - return; - b43_lo_write(dev, &cal->ctl); -} - -void b43_lo_g_adjust_to(struct b43_wldev *dev, - u16 rfatt, u16 bbatt, u16 tx_control) -{ - struct b43_rfatt rf; - struct b43_bbatt bb; - struct b43_lo_calib *cal; - - memset(&rf, 0, sizeof(rf)); - memset(&bb, 0, sizeof(bb)); - rf.att = rfatt; - bb.att = bbatt; - b43_lo_fixup_rfatt(&rf); - cal = b43_get_calib_lo_settings(dev, &bb, &rf); - if (!cal) - return; - b43_lo_write(dev, &cal->ctl); -} - -/* Periodic LO maintenance work */ -void b43_lo_g_maintenance_work(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - unsigned long now; - unsigned long expire; - struct b43_lo_calib *cal, *tmp; - bool current_item_expired = false; - bool hwpctl; - - if (!lo) - return; - now = jiffies; - hwpctl = b43_has_hardware_pctl(dev); - - if (hwpctl) { - /* Read the power vector and update it, if needed. */ - expire = now - B43_LO_PWRVEC_EXPIRE; - if (time_before(lo->pwr_vec_read_time, expire)) { - lo_read_power_vector(dev); - b43_gphy_dc_lt_init(dev, 0); - } - //FIXME Recalc the whole DC table from time to time? - } - - if (hwpctl) - return; - /* Search for expired LO settings. Remove them. - * Recalibrate the current setting, if expired. */ - expire = now - B43_LO_CALIB_EXPIRE; - list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) { - if (!time_before(cal->calib_time, expire)) - continue; - /* This item expired. */ - if (b43_compare_bbatt(&cal->bbatt, &gphy->bbatt) && - b43_compare_rfatt(&cal->rfatt, &gphy->rfatt)) { - B43_WARN_ON(current_item_expired); - current_item_expired = true; - } - if (b43_debug(dev, B43_DBG_LO)) { - b43dbg(dev->wl, "LO: Item BB(%u), RF(%u,%u), " - "I=%d, Q=%d expired\n", - cal->bbatt.att, cal->rfatt.att, - cal->rfatt.with_padmix, - cal->ctl.i, cal->ctl.q); - } - list_del(&cal->list); - kfree(cal); - } - if (current_item_expired || unlikely(list_empty(&lo->calib_list))) { - /* Recalibrate currently used LO setting. */ - if (b43_debug(dev, B43_DBG_LO)) - b43dbg(dev->wl, "LO: Recalibrating current LO setting\n"); - cal = b43_calibrate_lo_setting(dev, &gphy->bbatt, &gphy->rfatt); - if (cal) { - list_add(&cal->list, &lo->calib_list); - b43_lo_write(dev, &cal->ctl); - } else - b43warn(dev->wl, "Failed to recalibrate current LO setting\n"); - } -} - -void b43_lo_g_cleanup(struct b43_wldev *dev) -{ - struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; - struct b43_lo_calib *cal, *tmp; - - if (!lo) - return; - list_for_each_entry_safe(cal, tmp, &lo->calib_list, list) { - list_del(&cal->list); - kfree(cal); - } -} - -/* LO Initialization */ -void b43_lo_g_init(struct b43_wldev *dev) -{ - if (b43_has_hardware_pctl(dev)) { - lo_read_power_vector(dev); - b43_gphy_dc_lt_init(dev, 1); - } -} diff --git a/drivers/net/wireless/b43/lo.h b/drivers/net/wireless/b43/lo.h deleted file mode 100644 index 7b4df3883..000000000 --- a/drivers/net/wireless/b43/lo.h +++ /dev/null @@ -1,87 +0,0 @@ -#ifndef B43_LO_H_ -#define B43_LO_H_ - -/* G-PHY Local Oscillator */ - -#include "phy_g.h" - -struct b43_wldev; - -/* Local Oscillator control value-pair. */ -struct b43_loctl { - /* Control values. */ - s8 i; - s8 q; -}; -/* Debugging: Poison value for i and q values. */ -#define B43_LOCTL_POISON 111 - -/* This struct holds calibrated LO settings for a set of - * Baseband and RF attenuation settings. */ -struct b43_lo_calib { - /* The set of attenuation values this set of LO - * control values is calibrated for. */ - struct b43_bbatt bbatt; - struct b43_rfatt rfatt; - /* The set of control values for the LO. */ - struct b43_loctl ctl; - /* The time when these settings were calibrated (in jiffies) */ - unsigned long calib_time; - /* List. */ - struct list_head list; -}; - -/* Size of the DC Lookup Table in 16bit words. */ -#define B43_DC_LT_SIZE 32 - -/* Local Oscillator calibration information */ -struct b43_txpower_lo_control { - /* Lists of RF and BB attenuation values for this device. - * Used for building hardware power control tables. */ - struct b43_rfatt_list rfatt_list; - struct b43_bbatt_list bbatt_list; - - /* The DC Lookup Table is cached in memory here. - * Note that this is only used for Hardware Power Control. */ - u16 dc_lt[B43_DC_LT_SIZE]; - - /* List of calibrated control values (struct b43_lo_calib). */ - struct list_head calib_list; - /* Last time the power vector was read (jiffies). */ - unsigned long pwr_vec_read_time; - /* Last time the txctl values were measured (jiffies). */ - unsigned long txctl_measured_time; - - /* Current TX Bias value */ - u8 tx_bias; - /* Current TX Magnification Value (if used by the device) */ - u8 tx_magn; - - /* Saved device PowerVector */ - u64 power_vector; -}; - -/* Calibration expire timeouts. - * Timeouts must be multiple of 15 seconds. To make sure - * the item really expired when the 15 second timer hits, we - * subtract two additional seconds from the timeout. */ -#define B43_LO_CALIB_EXPIRE (HZ * (30 - 2)) -#define B43_LO_PWRVEC_EXPIRE (HZ * (30 - 2)) -#define B43_LO_TXCTL_EXPIRE (HZ * (180 - 4)) - - -/* Adjust the Local Oscillator to the saved attenuation - * and txctl values. - */ -void b43_lo_g_adjust(struct b43_wldev *dev); -/* Adjust to specific values. */ -void b43_lo_g_adjust_to(struct b43_wldev *dev, - u16 rfatt, u16 bbatt, u16 tx_control); - -void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all); - -void b43_lo_g_maintenance_work(struct b43_wldev *dev); -void b43_lo_g_cleanup(struct b43_wldev *dev); -void b43_lo_g_init(struct b43_wldev *dev); - -#endif /* B43_LO_H_ */ diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c deleted file mode 100644 index 3af6826cb..000000000 --- a/drivers/net/wireless/b43/main.c +++ /dev/null @@ -1,5891 +0,0 @@ -/* - - Broadcom B43 wireless driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> - Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2009 Michael Buesch <m@bues.ch> - Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> - - SDIO support - Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es> - - Some parts of the code in this file are derived from the ipw2200 - driver Copyright(c) 2003 - 2004 Intel Corporation. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/delay.h> -#include <linux/init.h> -#include <linux/module.h> -#include <linux/if_arp.h> -#include <linux/etherdevice.h> -#include <linux/firmware.h> -#include <linux/workqueue.h> -#include <linux/skbuff.h> -#include <linux/io.h> -#include <linux/dma-mapping.h> -#include <linux/slab.h> -#include <asm/unaligned.h> - -#include "b43.h" -#include "main.h" -#include "debugfs.h" -#include "phy_common.h" -#include "phy_g.h" -#include "phy_n.h" -#include "dma.h" -#include "pio.h" -#include "sysfs.h" -#include "xmit.h" -#include "lo.h" -#include "sdio.h" -#include <linux/mmc/sdio_func.h> - -MODULE_DESCRIPTION("Broadcom B43 wireless driver"); -MODULE_AUTHOR("Martin Langer"); -MODULE_AUTHOR("Stefano Brivio"); -MODULE_AUTHOR("Michael Buesch"); -MODULE_AUTHOR("Gábor Stefanik"); -MODULE_AUTHOR("Rafał Miłecki"); -MODULE_LICENSE("GPL"); - -/*(DEBLOBBED)*/ - -static int modparam_bad_frames_preempt; -module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); -MODULE_PARM_DESC(bad_frames_preempt, - "enable(1) / disable(0) Bad Frames Preemption"); - -static char modparam_fwpostfix[16]; -module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); -MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); - -static int modparam_hwpctl; -module_param_named(hwpctl, modparam_hwpctl, int, 0444); -MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); - -static int modparam_nohwcrypt; -module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); -MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); - -static int modparam_hwtkip; -module_param_named(hwtkip, modparam_hwtkip, int, 0444); -MODULE_PARM_DESC(hwtkip, "Enable hardware tkip."); - -static int modparam_qos = 1; -module_param_named(qos, modparam_qos, int, 0444); -MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); - -static int modparam_btcoex = 1; -module_param_named(btcoex, modparam_btcoex, int, 0444); -MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)"); - -int b43_modparam_verbose = B43_VERBOSITY_DEFAULT; -module_param_named(verbose, b43_modparam_verbose, int, 0644); -MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug"); - -static int b43_modparam_pio = 0; -module_param_named(pio, b43_modparam_pio, int, 0644); -MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); - -static int modparam_allhwsupport = !IS_ENABLED(CONFIG_BRCMSMAC); -module_param_named(allhwsupport, modparam_allhwsupport, int, 0444); -MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the brcmsmac driver)"); - -#ifdef CONFIG_B43_BCMA -static const struct bcma_device_id b43_bcma_tbl[] = { - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x15, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1C, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1E, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x28, BCMA_ANY_CLASS), - BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x2A, BCMA_ANY_CLASS), - {}, -}; -MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl); -#endif - -#ifdef CONFIG_B43_SSB -static const struct ssb_device_id b43_ssb_tbl[] = { - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15), - SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), - {}, -}; -MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); -#endif - -/* Channel and ratetables are shared for all devices. - * They can't be const, because ieee80211 puts some precalculated - * data in there. This data is the same for all devices, so we don't - * get concurrency issues */ -#define RATETAB_ENT(_rateid, _flags) \ - { \ - .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ - .hw_value = (_rateid), \ - .flags = (_flags), \ - } - -/* - * NOTE: When changing this, sync with xmit.c's - * b43_plcp_get_bitrate_idx_* functions! - */ -static struct ieee80211_rate __b43_ratetable[] = { - RATETAB_ENT(B43_CCK_RATE_1MB, 0), - RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), - RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), - RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), - RATETAB_ENT(B43_OFDM_RATE_6MB, 0), - RATETAB_ENT(B43_OFDM_RATE_9MB, 0), - RATETAB_ENT(B43_OFDM_RATE_12MB, 0), - RATETAB_ENT(B43_OFDM_RATE_18MB, 0), - RATETAB_ENT(B43_OFDM_RATE_24MB, 0), - RATETAB_ENT(B43_OFDM_RATE_36MB, 0), - RATETAB_ENT(B43_OFDM_RATE_48MB, 0), - RATETAB_ENT(B43_OFDM_RATE_54MB, 0), -}; - -#define b43_a_ratetable (__b43_ratetable + 4) -#define b43_a_ratetable_size 8 -#define b43_b_ratetable (__b43_ratetable + 0) -#define b43_b_ratetable_size 4 -#define b43_g_ratetable (__b43_ratetable + 0) -#define b43_g_ratetable_size 12 - -#define CHAN2G(_channel, _freq, _flags) { \ - .band = IEEE80211_BAND_2GHZ, \ - .center_freq = (_freq), \ - .hw_value = (_channel), \ - .flags = (_flags), \ - .max_antenna_gain = 0, \ - .max_power = 30, \ -} -static struct ieee80211_channel b43_2ghz_chantable[] = { - CHAN2G(1, 2412, 0), - CHAN2G(2, 2417, 0), - CHAN2G(3, 2422, 0), - CHAN2G(4, 2427, 0), - CHAN2G(5, 2432, 0), - CHAN2G(6, 2437, 0), - CHAN2G(7, 2442, 0), - CHAN2G(8, 2447, 0), - CHAN2G(9, 2452, 0), - CHAN2G(10, 2457, 0), - CHAN2G(11, 2462, 0), - CHAN2G(12, 2467, 0), - CHAN2G(13, 2472, 0), - CHAN2G(14, 2484, 0), -}; - -/* No support for the last 3 channels (12, 13, 14) */ -#define b43_2ghz_chantable_limited_size 11 -#undef CHAN2G - -#define CHAN4G(_channel, _flags) { \ - .band = IEEE80211_BAND_5GHZ, \ - .center_freq = 4000 + (5 * (_channel)), \ - .hw_value = (_channel), \ - .flags = (_flags), \ - .max_antenna_gain = 0, \ - .max_power = 30, \ -} -#define CHAN5G(_channel, _flags) { \ - .band = IEEE80211_BAND_5GHZ, \ - .center_freq = 5000 + (5 * (_channel)), \ - .hw_value = (_channel), \ - .flags = (_flags), \ - .max_antenna_gain = 0, \ - .max_power = 30, \ -} -static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { - CHAN4G(184, 0), CHAN4G(186, 0), - CHAN4G(188, 0), CHAN4G(190, 0), - CHAN4G(192, 0), CHAN4G(194, 0), - CHAN4G(196, 0), CHAN4G(198, 0), - CHAN4G(200, 0), CHAN4G(202, 0), - CHAN4G(204, 0), CHAN4G(206, 0), - CHAN4G(208, 0), CHAN4G(210, 0), - CHAN4G(212, 0), CHAN4G(214, 0), - CHAN4G(216, 0), CHAN4G(218, 0), - CHAN4G(220, 0), CHAN4G(222, 0), - CHAN4G(224, 0), CHAN4G(226, 0), - CHAN4G(228, 0), - CHAN5G(32, 0), CHAN5G(34, 0), - CHAN5G(36, 0), CHAN5G(38, 0), - CHAN5G(40, 0), CHAN5G(42, 0), - CHAN5G(44, 0), CHAN5G(46, 0), - CHAN5G(48, 0), CHAN5G(50, 0), - CHAN5G(52, 0), CHAN5G(54, 0), - CHAN5G(56, 0), CHAN5G(58, 0), - CHAN5G(60, 0), CHAN5G(62, 0), - CHAN5G(64, 0), CHAN5G(66, 0), - CHAN5G(68, 0), CHAN5G(70, 0), - CHAN5G(72, 0), CHAN5G(74, 0), - CHAN5G(76, 0), CHAN5G(78, 0), - CHAN5G(80, 0), CHAN5G(82, 0), - CHAN5G(84, 0), CHAN5G(86, 0), - CHAN5G(88, 0), CHAN5G(90, 0), - CHAN5G(92, 0), CHAN5G(94, 0), - CHAN5G(96, 0), CHAN5G(98, 0), - CHAN5G(100, 0), CHAN5G(102, 0), - CHAN5G(104, 0), CHAN5G(106, 0), - CHAN5G(108, 0), CHAN5G(110, 0), - CHAN5G(112, 0), CHAN5G(114, 0), - CHAN5G(116, 0), CHAN5G(118, 0), - CHAN5G(120, 0), CHAN5G(122, 0), - CHAN5G(124, 0), CHAN5G(126, 0), - CHAN5G(128, 0), CHAN5G(130, 0), - CHAN5G(132, 0), CHAN5G(134, 0), - CHAN5G(136, 0), CHAN5G(138, 0), - CHAN5G(140, 0), CHAN5G(142, 0), - CHAN5G(144, 0), CHAN5G(145, 0), - CHAN5G(146, 0), CHAN5G(147, 0), - CHAN5G(148, 0), CHAN5G(149, 0), - CHAN5G(150, 0), CHAN5G(151, 0), - CHAN5G(152, 0), CHAN5G(153, 0), - CHAN5G(154, 0), CHAN5G(155, 0), - CHAN5G(156, 0), CHAN5G(157, 0), - CHAN5G(158, 0), CHAN5G(159, 0), - CHAN5G(160, 0), CHAN5G(161, 0), - CHAN5G(162, 0), CHAN5G(163, 0), - CHAN5G(164, 0), CHAN5G(165, 0), - CHAN5G(166, 0), CHAN5G(168, 0), - CHAN5G(170, 0), CHAN5G(172, 0), - CHAN5G(174, 0), CHAN5G(176, 0), - CHAN5G(178, 0), CHAN5G(180, 0), - CHAN5G(182, 0), -}; - -static struct ieee80211_channel b43_5ghz_nphy_chantable_limited[] = { - CHAN5G(36, 0), CHAN5G(40, 0), - CHAN5G(44, 0), CHAN5G(48, 0), - CHAN5G(149, 0), CHAN5G(153, 0), - CHAN5G(157, 0), CHAN5G(161, 0), - CHAN5G(165, 0), -}; - -static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { - CHAN5G(34, 0), CHAN5G(36, 0), - CHAN5G(38, 0), CHAN5G(40, 0), - CHAN5G(42, 0), CHAN5G(44, 0), - CHAN5G(46, 0), CHAN5G(48, 0), - CHAN5G(52, 0), CHAN5G(56, 0), - CHAN5G(60, 0), CHAN5G(64, 0), - CHAN5G(100, 0), CHAN5G(104, 0), - CHAN5G(108, 0), CHAN5G(112, 0), - CHAN5G(116, 0), CHAN5G(120, 0), - CHAN5G(124, 0), CHAN5G(128, 0), - CHAN5G(132, 0), CHAN5G(136, 0), - CHAN5G(140, 0), CHAN5G(149, 0), - CHAN5G(153, 0), CHAN5G(157, 0), - CHAN5G(161, 0), CHAN5G(165, 0), - CHAN5G(184, 0), CHAN5G(188, 0), - CHAN5G(192, 0), CHAN5G(196, 0), - CHAN5G(200, 0), CHAN5G(204, 0), - CHAN5G(208, 0), CHAN5G(212, 0), - CHAN5G(216, 0), -}; -#undef CHAN4G -#undef CHAN5G - -static struct ieee80211_supported_band b43_band_5GHz_nphy = { - .band = IEEE80211_BAND_5GHZ, - .channels = b43_5ghz_nphy_chantable, - .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), - .bitrates = b43_a_ratetable, - .n_bitrates = b43_a_ratetable_size, -}; - -static struct ieee80211_supported_band b43_band_5GHz_nphy_limited = { - .band = IEEE80211_BAND_5GHZ, - .channels = b43_5ghz_nphy_chantable_limited, - .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable_limited), - .bitrates = b43_a_ratetable, - .n_bitrates = b43_a_ratetable_size, -}; - -static struct ieee80211_supported_band b43_band_5GHz_aphy = { - .band = IEEE80211_BAND_5GHZ, - .channels = b43_5ghz_aphy_chantable, - .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), - .bitrates = b43_a_ratetable, - .n_bitrates = b43_a_ratetable_size, -}; - -static struct ieee80211_supported_band b43_band_2GHz = { - .band = IEEE80211_BAND_2GHZ, - .channels = b43_2ghz_chantable, - .n_channels = ARRAY_SIZE(b43_2ghz_chantable), - .bitrates = b43_g_ratetable, - .n_bitrates = b43_g_ratetable_size, -}; - -static struct ieee80211_supported_band b43_band_2ghz_limited = { - .band = IEEE80211_BAND_2GHZ, - .channels = b43_2ghz_chantable, - .n_channels = b43_2ghz_chantable_limited_size, - .bitrates = b43_g_ratetable, - .n_bitrates = b43_g_ratetable_size, -}; - -static void b43_wireless_core_exit(struct b43_wldev *dev); -static int b43_wireless_core_init(struct b43_wldev *dev); -static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev); -static int b43_wireless_core_start(struct b43_wldev *dev); -static void b43_op_bss_info_changed(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_bss_conf *conf, - u32 changed); - -static int b43_ratelimit(struct b43_wl *wl) -{ - if (!wl || !wl->current_dev) - return 1; - if (b43_status(wl->current_dev) < B43_STAT_STARTED) - return 1; - /* We are up and running. - * Ratelimit the messages to avoid DoS over the net. */ - return net_ratelimit(); -} - -void b43info(struct b43_wl *wl, const char *fmt, ...) -{ - struct va_format vaf; - va_list args; - - if (b43_modparam_verbose < B43_VERBOSITY_INFO) - return; - if (!b43_ratelimit(wl)) - return; - - va_start(args, fmt); - - vaf.fmt = fmt; - vaf.va = &args; - - printk(KERN_INFO "b43-%s: %pV", - (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); - - va_end(args); -} - -void b43err(struct b43_wl *wl, const char *fmt, ...) -{ - struct va_format vaf; - va_list args; - - if (b43_modparam_verbose < B43_VERBOSITY_ERROR) - return; - if (!b43_ratelimit(wl)) - return; - - va_start(args, fmt); - - vaf.fmt = fmt; - vaf.va = &args; - - printk(KERN_ERR "b43-%s ERROR: %pV", - (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); - - va_end(args); -} - -void b43warn(struct b43_wl *wl, const char *fmt, ...) -{ - struct va_format vaf; - va_list args; - - if (b43_modparam_verbose < B43_VERBOSITY_WARN) - return; - if (!b43_ratelimit(wl)) - return; - - va_start(args, fmt); - - vaf.fmt = fmt; - vaf.va = &args; - - printk(KERN_WARNING "b43-%s warning: %pV", - (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); - - va_end(args); -} - -void b43dbg(struct b43_wl *wl, const char *fmt, ...) -{ - struct va_format vaf; - va_list args; - - if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) - return; - - va_start(args, fmt); - - vaf.fmt = fmt; - vaf.va = &args; - - printk(KERN_DEBUG "b43-%s debug: %pV", - (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf); - - va_end(args); -} - -static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) -{ - u32 macctl; - - B43_WARN_ON(offset % 4 != 0); - - macctl = b43_read32(dev, B43_MMIO_MACCTL); - if (macctl & B43_MACCTL_BE) - val = swab32(val); - - b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); - mmiowb(); - b43_write32(dev, B43_MMIO_RAM_DATA, val); -} - -static inline void b43_shm_control_word(struct b43_wldev *dev, - u16 routing, u16 offset) -{ - u32 control; - - /* "offset" is the WORD offset. */ - control = routing; - control <<= 16; - control |= offset; - b43_write32(dev, B43_MMIO_SHM_CONTROL, control); -} - -u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) -{ - u32 ret; - - if (routing == B43_SHM_SHARED) { - B43_WARN_ON(offset & 0x0001); - if (offset & 0x0003) { - /* Unaligned access */ - b43_shm_control_word(dev, routing, offset >> 2); - ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); - b43_shm_control_word(dev, routing, (offset >> 2) + 1); - ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16; - - goto out; - } - offset >>= 2; - } - b43_shm_control_word(dev, routing, offset); - ret = b43_read32(dev, B43_MMIO_SHM_DATA); -out: - return ret; -} - -u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset) -{ - u16 ret; - - if (routing == B43_SHM_SHARED) { - B43_WARN_ON(offset & 0x0001); - if (offset & 0x0003) { - /* Unaligned access */ - b43_shm_control_word(dev, routing, offset >> 2); - ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); - - goto out; - } - offset >>= 2; - } - b43_shm_control_word(dev, routing, offset); - ret = b43_read16(dev, B43_MMIO_SHM_DATA); -out: - return ret; -} - -void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) -{ - if (routing == B43_SHM_SHARED) { - B43_WARN_ON(offset & 0x0001); - if (offset & 0x0003) { - /* Unaligned access */ - b43_shm_control_word(dev, routing, offset >> 2); - b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, - value & 0xFFFF); - b43_shm_control_word(dev, routing, (offset >> 2) + 1); - b43_write16(dev, B43_MMIO_SHM_DATA, - (value >> 16) & 0xFFFF); - return; - } - offset >>= 2; - } - b43_shm_control_word(dev, routing, offset); - b43_write32(dev, B43_MMIO_SHM_DATA, value); -} - -void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) -{ - if (routing == B43_SHM_SHARED) { - B43_WARN_ON(offset & 0x0001); - if (offset & 0x0003) { - /* Unaligned access */ - b43_shm_control_word(dev, routing, offset >> 2); - b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); - return; - } - offset >>= 2; - } - b43_shm_control_word(dev, routing, offset); - b43_write16(dev, B43_MMIO_SHM_DATA, value); -} - -/* Read HostFlags */ -u64 b43_hf_read(struct b43_wldev *dev) -{ - u64 ret; - - ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3); - ret <<= 16; - ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2); - ret <<= 16; - ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1); - - return ret; -} - -/* Write HostFlags */ -void b43_hf_write(struct b43_wldev *dev, u64 value) -{ - u16 lo, mi, hi; - - lo = (value & 0x00000000FFFFULL); - mi = (value & 0x0000FFFF0000ULL) >> 16; - hi = (value & 0xFFFF00000000ULL) >> 32; - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi); -} - -/* Read the firmware capabilities bitmask (Opensource firmware only) */ -static u16 b43_fwcapa_read(struct b43_wldev *dev) -{ - B43_WARN_ON(!dev->fw.opensource); - return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA); -} - -void b43_tsf_read(struct b43_wldev *dev, u64 *tsf) -{ - u32 low, high; - - B43_WARN_ON(dev->dev->core_rev < 3); - - /* The hardware guarantees us an atomic read, if we - * read the low register first. */ - low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); - high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); - - *tsf = high; - *tsf <<= 32; - *tsf |= low; -} - -static void b43_time_lock(struct b43_wldev *dev) -{ - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD); - /* Commit the write */ - b43_read32(dev, B43_MMIO_MACCTL); -} - -static void b43_time_unlock(struct b43_wldev *dev) -{ - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0); - /* Commit the write */ - b43_read32(dev, B43_MMIO_MACCTL); -} - -static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) -{ - u32 low, high; - - B43_WARN_ON(dev->dev->core_rev < 3); - - low = tsf; - high = (tsf >> 32); - /* The hardware guarantees us an atomic write, if we - * write the low register first. */ - b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low); - mmiowb(); - b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high); - mmiowb(); -} - -void b43_tsf_write(struct b43_wldev *dev, u64 tsf) -{ - b43_time_lock(dev); - b43_tsf_write_locked(dev, tsf); - b43_time_unlock(dev); -} - -static -void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac) -{ - static const u8 zero_addr[ETH_ALEN] = { 0 }; - u16 data; - - if (!mac) - mac = zero_addr; - - offset |= 0x0020; - b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); - - data = mac[0]; - data |= mac[1] << 8; - b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); - data = mac[2]; - data |= mac[3] << 8; - b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); - data = mac[4]; - data |= mac[5] << 8; - b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); -} - -static void b43_write_mac_bssid_templates(struct b43_wldev *dev) -{ - const u8 *mac; - const u8 *bssid; - u8 mac_bssid[ETH_ALEN * 2]; - int i; - u32 tmp; - - bssid = dev->wl->bssid; - mac = dev->wl->mac_addr; - - b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); - - memcpy(mac_bssid, mac, ETH_ALEN); - memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); - - /* Write our MAC address and BSSID to template ram */ - for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { - tmp = (u32) (mac_bssid[i + 0]); - tmp |= (u32) (mac_bssid[i + 1]) << 8; - tmp |= (u32) (mac_bssid[i + 2]) << 16; - tmp |= (u32) (mac_bssid[i + 3]) << 24; - b43_ram_write(dev, 0x20 + i, tmp); - } -} - -static void b43_upload_card_macaddress(struct b43_wldev *dev) -{ - b43_write_mac_bssid_templates(dev); - b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); -} - -static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) -{ - /* slot_time is in usec. */ - /* This test used to exit for all but a G PHY. */ - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - return; - b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); - /* Shared memory location 0x0010 is the slot time and should be - * set to slot_time; however, this register is initially 0 and changing - * the value adversely affects the transmit rate for BCM4311 - * devices. Until this behavior is unterstood, delete this step - * - * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); - */ -} - -static void b43_short_slot_timing_enable(struct b43_wldev *dev) -{ - b43_set_slot_time(dev, 9); -} - -static void b43_short_slot_timing_disable(struct b43_wldev *dev) -{ - b43_set_slot_time(dev, 20); -} - -/* DummyTransmission function, as documented on - * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission - */ -void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) -{ - struct b43_phy *phy = &dev->phy; - unsigned int i, max_loop; - u16 value; - u32 buffer[5] = { - 0x00000000, - 0x00D40000, - 0x00000000, - 0x01000000, - 0x00000000, - }; - - if (ofdm) { - max_loop = 0x1E; - buffer[0] = 0x000201CC; - } else { - max_loop = 0xFA; - buffer[0] = 0x000B846E; - } - - for (i = 0; i < 5; i++) - b43_ram_write(dev, i * 4, buffer[i]); - - b43_write16(dev, B43_MMIO_XMTSEL, 0x0000); - - if (dev->dev->core_rev < 11) - b43_write16(dev, B43_MMIO_WEPCTL, 0x0000); - else - b43_write16(dev, B43_MMIO_WEPCTL, 0x0100); - - value = (ofdm ? 0x41 : 0x40); - b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value); - if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP || - phy->type == B43_PHYTYPE_LCN) - b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02); - - b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000); - b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000); - - b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000); - b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014); - b43_write16(dev, B43_MMIO_XMTSEL, 0x0826); - b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000); - - if (!pa_on && phy->type == B43_PHYTYPE_N) - ; /*b43_nphy_pa_override(dev, false) */ - - switch (phy->type) { - case B43_PHYTYPE_N: - case B43_PHYTYPE_LCN: - b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0); - break; - case B43_PHYTYPE_LP: - b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050); - break; - default: - b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030); - } - b43_read16(dev, B43_MMIO_TXE0_AUX); - - if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) - b43_radio_write16(dev, 0x0051, 0x0017); - for (i = 0x00; i < max_loop; i++) { - value = b43_read16(dev, B43_MMIO_TXE0_STATUS); - if (value & 0x0080) - break; - udelay(10); - } - for (i = 0x00; i < 0x0A; i++) { - value = b43_read16(dev, B43_MMIO_TXE0_STATUS); - if (value & 0x0400) - break; - udelay(10); - } - for (i = 0x00; i < 0x19; i++) { - value = b43_read16(dev, B43_MMIO_IFSSTAT); - if (!(value & 0x0100)) - break; - udelay(10); - } - if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) - b43_radio_write16(dev, 0x0051, 0x0037); -} - -static void key_write(struct b43_wldev *dev, - u8 index, u8 algorithm, const u8 *key) -{ - unsigned int i; - u32 offset; - u16 value; - u16 kidx; - - /* Key index/algo block */ - kidx = b43_kidx_to_fw(dev, index); - value = ((kidx << 4) | algorithm); - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); - - /* Write the key to the Key Table Pointer offset */ - offset = dev->ktp + (index * B43_SEC_KEYSIZE); - for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { - value = key[i]; - value |= (u16) (key[i + 1]) << 8; - b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); - } -} - -static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr) -{ - u32 addrtmp[2] = { 0, 0, }; - u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; - - if (b43_new_kidx_api(dev)) - pairwise_keys_start = B43_NR_GROUP_KEYS; - - B43_WARN_ON(index < pairwise_keys_start); - /* We have four default TX keys and possibly four default RX keys. - * Physical mac 0 is mapped to physical key 4 or 8, depending - * on the firmware version. - * So we must adjust the index here. - */ - index -= pairwise_keys_start; - B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); - - if (addr) { - addrtmp[0] = addr[0]; - addrtmp[0] |= ((u32) (addr[1]) << 8); - addrtmp[0] |= ((u32) (addr[2]) << 16); - addrtmp[0] |= ((u32) (addr[3]) << 24); - addrtmp[1] = addr[4]; - addrtmp[1] |= ((u32) (addr[5]) << 8); - } - - /* Receive match transmitter address (RCMTA) mechanism */ - b43_shm_write32(dev, B43_SHM_RCMTA, - (index * 2) + 0, addrtmp[0]); - b43_shm_write16(dev, B43_SHM_RCMTA, - (index * 2) + 1, addrtmp[1]); -} - -/* The ucode will use phase1 key with TEK key to decrypt rx packets. - * When a packet is received, the iv32 is checked. - * - if it doesn't the packet is returned without modification (and software - * decryption can be done). That's what happen when iv16 wrap. - * - if it does, the rc4 key is computed, and decryption is tried. - * Either it will success and B43_RX_MAC_DEC is returned, - * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned - * and the packet is not usable (it got modified by the ucode). - * So in order to never have B43_RX_MAC_DECERR, we should provide - * a iv32 and phase1key that match. Because we drop packets in case of - * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all - * packets will be lost without higher layer knowing (ie no resync possible - * until next wrap). - * - * NOTE : this should support 50 key like RCMTA because - * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50 - */ -static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32, - u16 *phase1key) -{ - unsigned int i; - u32 offset; - u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; - - if (!modparam_hwtkip) - return; - - if (b43_new_kidx_api(dev)) - pairwise_keys_start = B43_NR_GROUP_KEYS; - - B43_WARN_ON(index < pairwise_keys_start); - /* We have four default TX keys and possibly four default RX keys. - * Physical mac 0 is mapped to physical key 4 or 8, depending - * on the firmware version. - * So we must adjust the index here. - */ - index -= pairwise_keys_start; - B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS); - - if (b43_debug(dev, B43_DBG_KEYS)) { - b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n", - index, iv32); - } - /* Write the key to the RX tkip shared mem */ - offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4); - for (i = 0; i < 10; i += 2) { - b43_shm_write16(dev, B43_SHM_SHARED, offset + i, - phase1key ? phase1key[i / 2] : 0); - } - b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32); - b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16); -} - -static void b43_op_update_tkip_key(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_key_conf *keyconf, - struct ieee80211_sta *sta, - u32 iv32, u16 *phase1key) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - int index = keyconf->hw_key_idx; - - if (B43_WARN_ON(!modparam_hwtkip)) - return; - - /* This is only called from the RX path through mac80211, where - * our mutex is already locked. */ - B43_WARN_ON(!mutex_is_locked(&wl->mutex)); - dev = wl->current_dev; - B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED); - - keymac_write(dev, index, NULL); /* First zero out mac to avoid race */ - - rx_tkip_phase1_write(dev, index, iv32, phase1key); - /* only pairwise TKIP keys are supported right now */ - if (WARN_ON(!sta)) - return; - keymac_write(dev, index, sta->addr); -} - -static void do_key_write(struct b43_wldev *dev, - u8 index, u8 algorithm, - const u8 *key, size_t key_len, const u8 *mac_addr) -{ - u8 buf[B43_SEC_KEYSIZE] = { 0, }; - u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2; - - if (b43_new_kidx_api(dev)) - pairwise_keys_start = B43_NR_GROUP_KEYS; - - B43_WARN_ON(index >= ARRAY_SIZE(dev->key)); - B43_WARN_ON(key_len > B43_SEC_KEYSIZE); - - if (index >= pairwise_keys_start) - keymac_write(dev, index, NULL); /* First zero out mac. */ - if (algorithm == B43_SEC_ALGO_TKIP) { - /* - * We should provide an initial iv32, phase1key pair. - * We could start with iv32=0 and compute the corresponding - * phase1key, but this means calling ieee80211_get_tkip_key - * with a fake skb (or export other tkip function). - * Because we are lazy we hope iv32 won't start with - * 0xffffffff and let's b43_op_update_tkip_key provide a - * correct pair. - */ - rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf); - } else if (index >= pairwise_keys_start) /* clear it */ - rx_tkip_phase1_write(dev, index, 0, NULL); - if (key) - memcpy(buf, key, key_len); - key_write(dev, index, algorithm, buf); - if (index >= pairwise_keys_start) - keymac_write(dev, index, mac_addr); - - dev->key[index].algorithm = algorithm; -} - -static int b43_key_write(struct b43_wldev *dev, - int index, u8 algorithm, - const u8 *key, size_t key_len, - const u8 *mac_addr, - struct ieee80211_key_conf *keyconf) -{ - int i; - int pairwise_keys_start; - - /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block: - * - Temporal Encryption Key (128 bits) - * - Temporal Authenticator Tx MIC Key (64 bits) - * - Temporal Authenticator Rx MIC Key (64 bits) - * - * Hardware only store TEK - */ - if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32) - key_len = 16; - if (key_len > B43_SEC_KEYSIZE) - return -EINVAL; - for (i = 0; i < ARRAY_SIZE(dev->key); i++) { - /* Check that we don't already have this key. */ - B43_WARN_ON(dev->key[i].keyconf == keyconf); - } - if (index < 0) { - /* Pairwise key. Get an empty slot for the key. */ - if (b43_new_kidx_api(dev)) - pairwise_keys_start = B43_NR_GROUP_KEYS; - else - pairwise_keys_start = B43_NR_GROUP_KEYS * 2; - for (i = pairwise_keys_start; - i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS; - i++) { - B43_WARN_ON(i >= ARRAY_SIZE(dev->key)); - if (!dev->key[i].keyconf) { - /* found empty */ - index = i; - break; - } - } - if (index < 0) { - b43warn(dev->wl, "Out of hardware key memory\n"); - return -ENOSPC; - } - } else - B43_WARN_ON(index > 3); - - do_key_write(dev, index, algorithm, key, key_len, mac_addr); - if ((index <= 3) && !b43_new_kidx_api(dev)) { - /* Default RX key */ - B43_WARN_ON(mac_addr); - do_key_write(dev, index + 4, algorithm, key, key_len, NULL); - } - keyconf->hw_key_idx = index; - dev->key[index].keyconf = keyconf; - - return 0; -} - -static int b43_key_clear(struct b43_wldev *dev, int index) -{ - if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key)))) - return -EINVAL; - do_key_write(dev, index, B43_SEC_ALGO_NONE, - NULL, B43_SEC_KEYSIZE, NULL); - if ((index <= 3) && !b43_new_kidx_api(dev)) { - do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, - NULL, B43_SEC_KEYSIZE, NULL); - } - dev->key[index].keyconf = NULL; - - return 0; -} - -static void b43_clear_keys(struct b43_wldev *dev) -{ - int i, count; - - if (b43_new_kidx_api(dev)) - count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; - else - count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; - for (i = 0; i < count; i++) - b43_key_clear(dev, i); -} - -static void b43_dump_keymemory(struct b43_wldev *dev) -{ - unsigned int i, index, count, offset, pairwise_keys_start; - u8 mac[ETH_ALEN]; - u16 algo; - u32 rcmta0; - u16 rcmta1; - u64 hf; - struct b43_key *key; - - if (!b43_debug(dev, B43_DBG_KEYS)) - return; - - hf = b43_hf_read(dev); - b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n", - !!(hf & B43_HF_USEDEFKEYS)); - if (b43_new_kidx_api(dev)) { - pairwise_keys_start = B43_NR_GROUP_KEYS; - count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS; - } else { - pairwise_keys_start = B43_NR_GROUP_KEYS * 2; - count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS; - } - for (index = 0; index < count; index++) { - key = &(dev->key[index]); - printk(KERN_DEBUG "Key slot %02u: %s", - index, (key->keyconf == NULL) ? " " : "*"); - offset = dev->ktp + (index * B43_SEC_KEYSIZE); - for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { - u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); - printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); - } - - algo = b43_shm_read16(dev, B43_SHM_SHARED, - B43_SHM_SH_KEYIDXBLOCK + (index * 2)); - printk(" Algo: %04X/%02X", algo, key->algorithm); - - if (index >= pairwise_keys_start) { - if (key->algorithm == B43_SEC_ALGO_TKIP) { - printk(" TKIP: "); - offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4); - for (i = 0; i < 14; i += 2) { - u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i); - printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF)); - } - } - rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA, - ((index - pairwise_keys_start) * 2) + 0); - rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA, - ((index - pairwise_keys_start) * 2) + 1); - *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0); - *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1); - printk(" MAC: %pM", mac); - } else - printk(" DEFAULT KEY"); - printk("\n"); - } -} - -void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) -{ - u32 macctl; - u16 ucstat; - bool hwps; - bool awake; - int i; - - B43_WARN_ON((ps_flags & B43_PS_ENABLED) && - (ps_flags & B43_PS_DISABLED)); - B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); - - if (ps_flags & B43_PS_ENABLED) { - hwps = true; - } else if (ps_flags & B43_PS_DISABLED) { - hwps = false; - } else { - //TODO: If powersave is not off and FIXME is not set and we are not in adhoc - // and thus is not an AP and we are associated, set bit 25 - } - if (ps_flags & B43_PS_AWAKE) { - awake = true; - } else if (ps_flags & B43_PS_ASLEEP) { - awake = false; - } else { - //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, - // or we are associated, or FIXME, or the latest PS-Poll packet sent was - // successful, set bit26 - } - -/* FIXME: For now we force awake-on and hwps-off */ - hwps = false; - awake = true; - - macctl = b43_read32(dev, B43_MMIO_MACCTL); - if (hwps) - macctl |= B43_MACCTL_HWPS; - else - macctl &= ~B43_MACCTL_HWPS; - if (awake) - macctl |= B43_MACCTL_AWAKE; - else - macctl &= ~B43_MACCTL_AWAKE; - b43_write32(dev, B43_MMIO_MACCTL, macctl); - /* Commit write */ - b43_read32(dev, B43_MMIO_MACCTL); - if (awake && dev->dev->core_rev >= 5) { - /* Wait for the microcode to wake up. */ - for (i = 0; i < 100; i++) { - ucstat = b43_shm_read16(dev, B43_SHM_SHARED, - B43_SHM_SH_UCODESTAT); - if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) - break; - udelay(10); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */ -void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev) -{ - struct bcma_drv_cc *bcma_cc __maybe_unused; - struct ssb_chipcommon *ssb_cc __maybe_unused; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_cc = &dev->dev->bdev->bus->drv_cc; - - bcma_cc_write32(bcma_cc, BCMA_CC_CHIPCTL_ADDR, 0); - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4); - bcma_cc_set32(bcma_cc, BCMA_CC_CHIPCTL_DATA, 0x4); - bcma_cc_mask32(bcma_cc, BCMA_CC_CHIPCTL_DATA, ~0x4); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - ssb_cc = &dev->dev->sdev->bus->chipco; - - chipco_write32(ssb_cc, SSB_CHIPCO_CHIPCTL_ADDR, 0); - chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); - chipco_set32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, 0x4); - chipco_mask32(ssb_cc, SSB_CHIPCO_CHIPCTL_DATA, ~0x4); - break; -#endif - } -} - -#ifdef CONFIG_B43_BCMA -static void b43_bcma_phy_reset(struct b43_wldev *dev) -{ - u32 flags; - - /* Put PHY into reset */ - flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - flags |= B43_BCMA_IOCTL_PHY_RESET; - flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */ - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags); - udelay(2); - - b43_phy_take_out_of_reset(dev); -} - -static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) -{ - u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ | - B43_BCMA_CLKCTLST_PHY_PLL_REQ; - u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST | - B43_BCMA_CLKCTLST_PHY_PLL_ST; - u32 flags; - - flags = B43_BCMA_IOCTL_PHY_CLKEN; - if (gmode) - flags |= B43_BCMA_IOCTL_GMODE; - b43_device_enable(dev, flags); - - if (dev->phy.type == B43_PHYTYPE_AC) { - u16 tmp; - - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~B43_BCMA_IOCTL_DAC; - tmp |= 0x100; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp |= B43_BCMA_IOCTL_PHY_CLKEN; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - } - - bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); - b43_bcma_phy_reset(dev); - bcma_core_pll_ctl(dev->dev->bdev, req, status, true); -} -#endif - -#ifdef CONFIG_B43_SSB -static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode) -{ - u32 flags = 0; - - if (gmode) - flags |= B43_TMSLOW_GMODE; - flags |= B43_TMSLOW_PHYCLKEN; - flags |= B43_TMSLOW_PHYRESET; - if (dev->phy.type == B43_PHYTYPE_N) - flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ - b43_device_enable(dev, flags); - msleep(2); /* Wait for the PLL to turn on. */ - - b43_phy_take_out_of_reset(dev); -} -#endif - -void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode) -{ - u32 macctl; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - b43_bcma_wireless_core_reset(dev, gmode); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - b43_ssb_wireless_core_reset(dev, gmode); - break; -#endif - } - - /* Turn Analog ON, but only if we already know the PHY-type. - * This protects against very early setup where we don't know the - * PHY-type, yet. wireless_core_reset will be called once again later, - * when we know the PHY-type. */ - if (dev->phy.ops) - dev->phy.ops->switch_analog(dev, 1); - - macctl = b43_read32(dev, B43_MMIO_MACCTL); - macctl &= ~B43_MACCTL_GMODE; - if (gmode) - macctl |= B43_MACCTL_GMODE; - macctl |= B43_MACCTL_IHR_ENABLED; - b43_write32(dev, B43_MMIO_MACCTL, macctl); -} - -static void handle_irq_transmit_status(struct b43_wldev *dev) -{ - u32 v0, v1; - u16 tmp; - struct b43_txstatus stat; - - while (1) { - v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); - if (!(v0 & 0x00000001)) - break; - v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); - - stat.cookie = (v0 >> 16); - stat.seq = (v1 & 0x0000FFFF); - stat.phy_stat = ((v1 & 0x00FF0000) >> 16); - tmp = (v0 & 0x0000FFFF); - stat.frame_count = ((tmp & 0xF000) >> 12); - stat.rts_count = ((tmp & 0x0F00) >> 8); - stat.supp_reason = ((tmp & 0x001C) >> 2); - stat.pm_indicated = !!(tmp & 0x0080); - stat.intermediate = !!(tmp & 0x0040); - stat.for_ampdu = !!(tmp & 0x0020); - stat.acked = !!(tmp & 0x0002); - - b43_handle_txstatus(dev, &stat); - } -} - -static void drain_txstatus_queue(struct b43_wldev *dev) -{ - u32 dummy; - - if (dev->dev->core_rev < 5) - return; - /* Read all entries from the microcode TXstatus FIFO - * and throw them away. - */ - while (1) { - dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); - if (!(dummy & 0x00000001)) - break; - dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); - } -} - -static u32 b43_jssi_read(struct b43_wldev *dev) -{ - u32 val = 0; - - val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1); - val <<= 16; - val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0); - - return val; -} - -static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) -{ - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0, - (jssi & 0x0000FFFF)); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1, - (jssi & 0xFFFF0000) >> 16); -} - -static void b43_generate_noise_sample(struct b43_wldev *dev) -{ - b43_jssi_write(dev, 0x7F7F7F7F); - b43_write32(dev, B43_MMIO_MACCMD, - b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); -} - -static void b43_calculate_link_quality(struct b43_wldev *dev) -{ - /* Top half of Link Quality calculation. */ - - if (dev->phy.type != B43_PHYTYPE_G) - return; - if (dev->noisecalc.calculation_running) - return; - dev->noisecalc.calculation_running = true; - dev->noisecalc.nr_samples = 0; - - b43_generate_noise_sample(dev); -} - -static void handle_irq_noise(struct b43_wldev *dev) -{ - struct b43_phy_g *phy = dev->phy.g; - u16 tmp; - u8 noise[4]; - u8 i, j; - s32 average; - - /* Bottom half of Link Quality calculation. */ - - if (dev->phy.type != B43_PHYTYPE_G) - return; - - /* Possible race condition: It might be possible that the user - * changed to a different channel in the meantime since we - * started the calculation. We ignore that fact, since it's - * not really that much of a problem. The background noise is - * an estimation only anyway. Slightly wrong results will get damped - * by the averaging of the 8 sample rounds. Additionally the - * value is shortlived. So it will be replaced by the next noise - * calculation round soon. */ - - B43_WARN_ON(!dev->noisecalc.calculation_running); - *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); - if (noise[0] == 0x7F || noise[1] == 0x7F || - noise[2] == 0x7F || noise[3] == 0x7F) - goto generate_new; - - /* Get the noise samples. */ - B43_WARN_ON(dev->noisecalc.nr_samples >= 8); - i = dev->noisecalc.nr_samples; - noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); - noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); - noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); - noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); - dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; - dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; - dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; - dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; - dev->noisecalc.nr_samples++; - if (dev->noisecalc.nr_samples == 8) { - /* Calculate the Link Quality by the noise samples. */ - average = 0; - for (i = 0; i < 8; i++) { - for (j = 0; j < 4; j++) - average += dev->noisecalc.samples[i][j]; - } - average /= (8 * 4); - average *= 125; - average += 64; - average /= 128; - tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); - tmp = (tmp / 128) & 0x1F; - if (tmp >= 8) - average += 2; - else - average -= 25; - if (tmp == 8) - average -= 72; - else - average -= 48; - - dev->stats.link_noise = average; - dev->noisecalc.calculation_running = false; - return; - } -generate_new: - b43_generate_noise_sample(dev); -} - -static void handle_irq_tbtt_indication(struct b43_wldev *dev) -{ - if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) { - ///TODO: PS TBTT - } else { - if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) - b43_power_saving_ctl_bits(dev, 0); - } - if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) - dev->dfq_valid = true; -} - -static void handle_irq_atim_end(struct b43_wldev *dev) -{ - if (dev->dfq_valid) { - b43_write32(dev, B43_MMIO_MACCMD, - b43_read32(dev, B43_MMIO_MACCMD) - | B43_MACCMD_DFQ_VALID); - dev->dfq_valid = false; - } -} - -static void handle_irq_pmq(struct b43_wldev *dev) -{ - u32 tmp; - - //TODO: AP mode. - - while (1) { - tmp = b43_read32(dev, B43_MMIO_PS_STATUS); - if (!(tmp & 0x00000008)) - break; - } - /* 16bit write is odd, but correct. */ - b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); -} - -static void b43_write_template_common(struct b43_wldev *dev, - const u8 *data, u16 size, - u16 ram_offset, - u16 shm_size_offset, u8 rate) -{ - u32 i, tmp; - struct b43_plcp_hdr4 plcp; - - plcp.data = 0; - b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); - b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); - ram_offset += sizeof(u32); - /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. - * So leave the first two bytes of the next write blank. - */ - tmp = (u32) (data[0]) << 16; - tmp |= (u32) (data[1]) << 24; - b43_ram_write(dev, ram_offset, tmp); - ram_offset += sizeof(u32); - for (i = 2; i < size; i += sizeof(u32)) { - tmp = (u32) (data[i + 0]); - if (i + 1 < size) - tmp |= (u32) (data[i + 1]) << 8; - if (i + 2 < size) - tmp |= (u32) (data[i + 2]) << 16; - if (i + 3 < size) - tmp |= (u32) (data[i + 3]) << 24; - b43_ram_write(dev, ram_offset + i - 2, tmp); - } - b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, - size + sizeof(struct b43_plcp_hdr6)); -} - -/* Check if the use of the antenna that ieee80211 told us to - * use is possible. This will fall back to DEFAULT. - * "antenna_nr" is the antenna identifier we got from ieee80211. */ -u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, - u8 antenna_nr) -{ - u8 antenna_mask; - - if (antenna_nr == 0) { - /* Zero means "use default antenna". That's always OK. */ - return 0; - } - - /* Get the mask of available antennas. */ - if (dev->phy.gmode) - antenna_mask = dev->dev->bus_sprom->ant_available_bg; - else - antenna_mask = dev->dev->bus_sprom->ant_available_a; - - if (!(antenna_mask & (1 << (antenna_nr - 1)))) { - /* This antenna is not available. Fall back to default. */ - return 0; - } - - return antenna_nr; -} - -/* Convert a b43 antenna number value to the PHY TX control value. */ -static u16 b43_antenna_to_phyctl(int antenna) -{ - switch (antenna) { - case B43_ANTENNA0: - return B43_TXH_PHY_ANT0; - case B43_ANTENNA1: - return B43_TXH_PHY_ANT1; - case B43_ANTENNA2: - return B43_TXH_PHY_ANT2; - case B43_ANTENNA3: - return B43_TXH_PHY_ANT3; - case B43_ANTENNA_AUTO0: - case B43_ANTENNA_AUTO1: - return B43_TXH_PHY_ANT01AUTO; - } - B43_WARN_ON(1); - return 0; -} - -static void b43_write_beacon_template(struct b43_wldev *dev, - u16 ram_offset, - u16 shm_size_offset) -{ - unsigned int i, len, variable_len; - const struct ieee80211_mgmt *bcn; - const u8 *ie; - bool tim_found = false; - unsigned int rate; - u16 ctl; - int antenna; - struct ieee80211_tx_info *info; - unsigned long flags; - struct sk_buff *beacon_skb; - - spin_lock_irqsave(&dev->wl->beacon_lock, flags); - info = IEEE80211_SKB_CB(dev->wl->current_beacon); - rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value; - /* Clone the beacon, so it cannot go away, while we write it to hw. */ - beacon_skb = skb_clone(dev->wl->current_beacon, GFP_ATOMIC); - spin_unlock_irqrestore(&dev->wl->beacon_lock, flags); - - if (!beacon_skb) { - b43dbg(dev->wl, "Could not upload beacon. " - "Failed to clone beacon skb."); - return; - } - - bcn = (const struct ieee80211_mgmt *)(beacon_skb->data); - len = min_t(size_t, beacon_skb->len, - 0x200 - sizeof(struct b43_plcp_hdr6)); - - b43_write_template_common(dev, (const u8 *)bcn, - len, ram_offset, shm_size_offset, rate); - - /* Write the PHY TX control parameters. */ - antenna = B43_ANTENNA_DEFAULT; - antenna = b43_antenna_to_phyctl(antenna); - ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); - /* We can't send beacons with short preamble. Would get PHY errors. */ - ctl &= ~B43_TXH_PHY_SHORTPRMBL; - ctl &= ~B43_TXH_PHY_ANT; - ctl &= ~B43_TXH_PHY_ENC; - ctl |= antenna; - if (b43_is_cck_rate(rate)) - ctl |= B43_TXH_PHY_ENC_CCK; - else - ctl |= B43_TXH_PHY_ENC_OFDM; - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); - - /* Find the position of the TIM and the DTIM_period value - * and write them to SHM. */ - ie = bcn->u.beacon.variable; - variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); - for (i = 0; i < variable_len - 2; ) { - uint8_t ie_id, ie_len; - - ie_id = ie[i]; - ie_len = ie[i + 1]; - if (ie_id == 5) { - u16 tim_position; - u16 dtim_period; - /* This is the TIM Information Element */ - - /* Check whether the ie_len is in the beacon data range. */ - if (variable_len < ie_len + 2 + i) - break; - /* A valid TIM is at least 4 bytes long. */ - if (ie_len < 4) - break; - tim_found = true; - - tim_position = sizeof(struct b43_plcp_hdr6); - tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); - tim_position += i; - - dtim_period = ie[i + 3]; - - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_TIMBPOS, tim_position); - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_DTIMPER, dtim_period); - break; - } - i += ie_len + 2; - } - if (!tim_found) { - /* - * If ucode wants to modify TIM do it behind the beacon, this - * will happen, for example, when doing mesh networking. - */ - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_TIMBPOS, - len + sizeof(struct b43_plcp_hdr6)); - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_DTIMPER, 0); - } - b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset); - - dev_kfree_skb_any(beacon_skb); -} - -static void b43_upload_beacon0(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - - if (wl->beacon0_uploaded) - return; - b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0); - wl->beacon0_uploaded = true; -} - -static void b43_upload_beacon1(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - - if (wl->beacon1_uploaded) - return; - b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1); - wl->beacon1_uploaded = true; -} - -static void handle_irq_beacon(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - u32 cmd, beacon0_valid, beacon1_valid; - - if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && - !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) && - !b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) - return; - - /* This is the bottom half of the asynchronous beacon update. */ - - /* Ignore interrupt in the future. */ - dev->irq_mask &= ~B43_IRQ_BEACON; - - cmd = b43_read32(dev, B43_MMIO_MACCMD); - beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); - beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); - - /* Schedule interrupt manually, if busy. */ - if (beacon0_valid && beacon1_valid) { - b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); - dev->irq_mask |= B43_IRQ_BEACON; - return; - } - - if (unlikely(wl->beacon_templates_virgin)) { - /* We never uploaded a beacon before. - * Upload both templates now, but only mark one valid. */ - wl->beacon_templates_virgin = false; - b43_upload_beacon0(dev); - b43_upload_beacon1(dev); - cmd = b43_read32(dev, B43_MMIO_MACCMD); - cmd |= B43_MACCMD_BEACON0_VALID; - b43_write32(dev, B43_MMIO_MACCMD, cmd); - } else { - if (!beacon0_valid) { - b43_upload_beacon0(dev); - cmd = b43_read32(dev, B43_MMIO_MACCMD); - cmd |= B43_MACCMD_BEACON0_VALID; - b43_write32(dev, B43_MMIO_MACCMD, cmd); - } else if (!beacon1_valid) { - b43_upload_beacon1(dev); - cmd = b43_read32(dev, B43_MMIO_MACCMD); - cmd |= B43_MACCMD_BEACON1_VALID; - b43_write32(dev, B43_MMIO_MACCMD, cmd); - } - } -} - -static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev) -{ - u32 old_irq_mask = dev->irq_mask; - - /* update beacon right away or defer to irq */ - handle_irq_beacon(dev); - if (old_irq_mask != dev->irq_mask) { - /* The handler updated the IRQ mask. */ - B43_WARN_ON(!dev->irq_mask); - if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) { - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); - } else { - /* Device interrupts are currently disabled. That means - * we just ran the hardirq handler and scheduled the - * IRQ thread. The thread will write the IRQ mask when - * it finished, so there's nothing to do here. Writing - * the mask _here_ would incorrectly re-enable IRQs. */ - } - } -} - -static void b43_beacon_update_trigger_work(struct work_struct *work) -{ - struct b43_wl *wl = container_of(work, struct b43_wl, - beacon_update_trigger); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { - if (b43_bus_host_is_sdio(dev->dev)) { - /* wl->mutex is enough. */ - b43_do_beacon_update_trigger_work(dev); - mmiowb(); - } else { - spin_lock_irq(&wl->hardirq_lock); - b43_do_beacon_update_trigger_work(dev); - mmiowb(); - spin_unlock_irq(&wl->hardirq_lock); - } - } - mutex_unlock(&wl->mutex); -} - -/* Asynchronously update the packet templates in template RAM. */ -static void b43_update_templates(struct b43_wl *wl) -{ - struct sk_buff *beacon, *old_beacon; - unsigned long flags; - - /* This is the top half of the asynchronous beacon update. - * The bottom half is the beacon IRQ. - * Beacon update must be asynchronous to avoid sending an - * invalid beacon. This can happen for example, if the firmware - * transmits a beacon while we are updating it. */ - - /* We could modify the existing beacon and set the aid bit in - * the TIM field, but that would probably require resizing and - * moving of data within the beacon template. - * Simply request a new beacon and let mac80211 do the hard work. */ - beacon = ieee80211_beacon_get(wl->hw, wl->vif); - if (unlikely(!beacon)) - return; - - spin_lock_irqsave(&wl->beacon_lock, flags); - old_beacon = wl->current_beacon; - wl->current_beacon = beacon; - wl->beacon0_uploaded = false; - wl->beacon1_uploaded = false; - spin_unlock_irqrestore(&wl->beacon_lock, flags); - - ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger); - - if (old_beacon) - dev_kfree_skb_any(old_beacon); -} - -static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) -{ - b43_time_lock(dev); - if (dev->dev->core_rev >= 3) { - b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); - b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); - } else { - b43_write16(dev, 0x606, (beacon_int >> 6)); - b43_write16(dev, 0x610, beacon_int); - } - b43_time_unlock(dev); - b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); -} - -static void b43_handle_firmware_panic(struct b43_wldev *dev) -{ - u16 reason; - - /* Read the register that contains the reason code for the panic. */ - reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG); - b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason); - - switch (reason) { - default: - b43dbg(dev->wl, "The panic reason is unknown.\n"); - /* fallthrough */ - case B43_FWPANIC_DIE: - /* Do not restart the controller or firmware. - * The device is nonfunctional from now on. - * Restarting would result in this panic to trigger again, - * so we avoid that recursion. */ - break; - case B43_FWPANIC_RESTART: - b43_controller_restart(dev, "Microcode panic"); - break; - } -} - -static void handle_irq_ucode_debug(struct b43_wldev *dev) -{ - unsigned int i, cnt; - u16 reason, marker_id, marker_line; - __le16 *buf; - - /* The proprietary firmware doesn't have this IRQ. */ - if (!dev->fw.opensource) - return; - - /* Read the register that contains the reason code for this IRQ. */ - reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG); - - switch (reason) { - case B43_DEBUGIRQ_PANIC: - b43_handle_firmware_panic(dev); - break; - case B43_DEBUGIRQ_DUMP_SHM: - if (!B43_DEBUG) - break; /* Only with driver debugging enabled. */ - buf = kmalloc(4096, GFP_ATOMIC); - if (!buf) { - b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n"); - goto out; - } - for (i = 0; i < 4096; i += 2) { - u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i); - buf[i / 2] = cpu_to_le16(tmp); - } - b43info(dev->wl, "Shared memory dump:\n"); - print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, - 16, 2, buf, 4096, 1); - kfree(buf); - break; - case B43_DEBUGIRQ_DUMP_REGS: - if (!B43_DEBUG) - break; /* Only with driver debugging enabled. */ - b43info(dev->wl, "Microcode register dump:\n"); - for (i = 0, cnt = 0; i < 64; i++) { - u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i); - if (cnt == 0) - printk(KERN_INFO); - printk("r%02u: 0x%04X ", i, tmp); - cnt++; - if (cnt == 6) { - printk("\n"); - cnt = 0; - } - } - printk("\n"); - break; - case B43_DEBUGIRQ_MARKER: - if (!B43_DEBUG) - break; /* Only with driver debugging enabled. */ - marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH, - B43_MARKER_ID_REG); - marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH, - B43_MARKER_LINE_REG); - b43info(dev->wl, "The firmware just executed the MARKER(%u) " - "at line number %u\n", - marker_id, marker_line); - break; - default: - b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n", - reason); - } -out: - /* Acknowledge the debug-IRQ, so the firmware can continue. */ - b43_shm_write16(dev, B43_SHM_SCRATCH, - B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK); -} - -static void b43_do_interrupt_thread(struct b43_wldev *dev) -{ - u32 reason; - u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; - u32 merged_dma_reason = 0; - int i; - - if (unlikely(b43_status(dev) != B43_STAT_STARTED)) - return; - - reason = dev->irq_reason; - for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { - dma_reason[i] = dev->dma_reason[i]; - merged_dma_reason |= dma_reason[i]; - } - - if (unlikely(reason & B43_IRQ_MAC_TXERR)) - b43err(dev->wl, "MAC transmission error\n"); - - if (unlikely(reason & B43_IRQ_PHY_TXERR)) { - b43err(dev->wl, "PHY transmission error\n"); - rmb(); - if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { - atomic_set(&dev->phy.txerr_cnt, - B43_PHY_TX_BADNESS_LIMIT); - b43err(dev->wl, "Too many PHY TX errors, " - "restarting the controller\n"); - b43_controller_restart(dev, "PHY TX errors"); - } - } - - if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) { - b43err(dev->wl, - "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n", - dma_reason[0], dma_reason[1], - dma_reason[2], dma_reason[3], - dma_reason[4], dma_reason[5]); - b43err(dev->wl, "This device does not support DMA " - "on your system. It will now be switched to PIO.\n"); - /* Fall back to PIO transfers if we get fatal DMA errors! */ - dev->use_pio = true; - b43_controller_restart(dev, "DMA error"); - return; - } - - if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) - handle_irq_ucode_debug(dev); - if (reason & B43_IRQ_TBTT_INDI) - handle_irq_tbtt_indication(dev); - if (reason & B43_IRQ_ATIM_END) - handle_irq_atim_end(dev); - if (reason & B43_IRQ_BEACON) - handle_irq_beacon(dev); - if (reason & B43_IRQ_PMQ) - handle_irq_pmq(dev); - if (reason & B43_IRQ_TXFIFO_FLUSH_OK) - ;/* TODO */ - if (reason & B43_IRQ_NOISESAMPLE_OK) - handle_irq_noise(dev); - - /* Check the DMA reason registers for received data. */ - if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) { - if (B43_DEBUG) - b43warn(dev->wl, "RX descriptor underrun\n"); - b43_dma_handle_rx_overflow(dev->dma.rx_ring); - } - if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { - if (b43_using_pio_transfers(dev)) - b43_pio_rx(dev->pio.rx_queue); - else - b43_dma_rx(dev->dma.rx_ring); - } - B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); - B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); - B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); - B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); - B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); - - if (reason & B43_IRQ_TX_OK) - handle_irq_transmit_status(dev); - - /* Re-enable interrupts on the device by restoring the current interrupt mask. */ - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); - -#if B43_DEBUG - if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { - dev->irq_count++; - for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { - if (reason & (1 << i)) - dev->irq_bit_count[i]++; - } - } -#endif -} - -/* Interrupt thread handler. Handles device interrupts in thread context. */ -static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id) -{ - struct b43_wldev *dev = dev_id; - - mutex_lock(&dev->wl->mutex); - b43_do_interrupt_thread(dev); - mmiowb(); - mutex_unlock(&dev->wl->mutex); - - return IRQ_HANDLED; -} - -static irqreturn_t b43_do_interrupt(struct b43_wldev *dev) -{ - u32 reason; - - /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses. - * On SDIO, this runs under wl->mutex. */ - - reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); - if (reason == 0xffffffff) /* shared IRQ */ - return IRQ_NONE; - reason &= dev->irq_mask; - if (!reason) - return IRQ_NONE; - - dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) - & 0x0001FC00; - dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) - & 0x0000DC00; - dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) - & 0x0000DC00; - dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) - & 0x0001DC00; - dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) - & 0x0000DC00; -/* Unused ring - dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) - & 0x0000DC00; -*/ - - /* ACK the interrupt. */ - b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); - b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); - b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); - b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); - b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); - b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); -/* Unused ring - b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); -*/ - - /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */ - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); - /* Save the reason bitmasks for the IRQ thread handler. */ - dev->irq_reason = reason; - - return IRQ_WAKE_THREAD; -} - -/* Interrupt handler top-half. This runs with interrupts disabled. */ -static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) -{ - struct b43_wldev *dev = dev_id; - irqreturn_t ret; - - if (unlikely(b43_status(dev) < B43_STAT_STARTED)) - return IRQ_NONE; - - spin_lock(&dev->wl->hardirq_lock); - ret = b43_do_interrupt(dev); - mmiowb(); - spin_unlock(&dev->wl->hardirq_lock); - - return ret; -} - -/* SDIO interrupt handler. This runs in process context. */ -static void b43_sdio_interrupt_handler(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - irqreturn_t ret; - - mutex_lock(&wl->mutex); - - ret = b43_do_interrupt(dev); - if (ret == IRQ_WAKE_THREAD) - b43_do_interrupt_thread(dev); - - mutex_unlock(&wl->mutex); -} - -void b43_do_release_fw(struct b43_firmware_file *fw) -{ - release_firmware(fw->data); - fw->data = NULL; - fw->filename = NULL; -} - -static void b43_release_firmware(struct b43_wldev *dev) -{ - complete(&dev->fw_load_complete); - b43_do_release_fw(&dev->fw.ucode); - b43_do_release_fw(&dev->fw.pcm); - b43_do_release_fw(&dev->fw.initvals); - b43_do_release_fw(&dev->fw.initvals_band); -} - -static void b43_print_fw_helptext(struct b43_wl *wl, bool error) -{ - const char text[] = - "/*(DEBLOBBED)*/"; - - if (error) - b43err(wl, text); - else - b43warn(wl, text); -} - -static void b43_fw_cb(const struct firmware *firmware, void *context) -{ - struct b43_request_fw_context *ctx = context; - - ctx->blob = firmware; - complete(&ctx->dev->fw_load_complete); -} - -int b43_do_request_fw(struct b43_request_fw_context *ctx, - const char *name, - struct b43_firmware_file *fw, bool async) -{ - struct b43_fw_header *hdr; - u32 size; - int err; - - if (!name) { - /* Don't fetch anything. Free possibly cached firmware. */ - /* FIXME: We should probably keep it anyway, to save some headache - * on suspend/resume with multiband devices. */ - b43_do_release_fw(fw); - return 0; - } - if (fw->filename) { - if ((fw->type == ctx->req_type) && - (strcmp(fw->filename, name) == 0)) - return 0; /* Already have this fw. */ - /* Free the cached firmware first. */ - /* FIXME: We should probably do this later after we successfully - * got the new fw. This could reduce headache with multiband devices. - * We could also redesign this to cache the firmware for all possible - * bands all the time. */ - b43_do_release_fw(fw); - } - - switch (ctx->req_type) { - case B43_FWTYPE_PROPRIETARY: - snprintf(ctx->fwname, sizeof(ctx->fwname), - "/*(DEBLOBBED)*/", - modparam_fwpostfix, name); - break; - case B43_FWTYPE_OPENSOURCE: - snprintf(ctx->fwname, sizeof(ctx->fwname), - "b43-open%s/%s.fw", - modparam_fwpostfix, name); - break; - default: - B43_WARN_ON(1); - return -ENOSYS; - } - if (async) { - /* do this part asynchronously */ - init_completion(&ctx->dev->fw_load_complete); - err = maybe_reject_firmware_nowait(THIS_MODULE, 1, ctx->fwname, - ctx->dev->dev->dev, GFP_KERNEL, - ctx, b43_fw_cb); - if (err < 0) { - pr_err("Unable to load firmware\n"); - return err; - } - wait_for_completion(&ctx->dev->fw_load_complete); - if (ctx->blob) - goto fw_ready; - /* On some ARM systems, the async request will fail, but the next sync - * request works. For this reason, we fall through here - */ - } - err = maybe_reject_firmware(&ctx->blob, ctx->fwname, - ctx->dev->dev->dev); - if (err == -ENOENT) { - snprintf(ctx->errors[ctx->req_type], - sizeof(ctx->errors[ctx->req_type]), - "Firmware file \"%s\" not found\n", - ctx->fwname); - return err; - } else if (err) { - snprintf(ctx->errors[ctx->req_type], - sizeof(ctx->errors[ctx->req_type]), - "Firmware file \"%s\" request failed (err=%d)\n", - ctx->fwname, err); - return err; - } -fw_ready: - if (ctx->blob->size < sizeof(struct b43_fw_header)) - goto err_format; - hdr = (struct b43_fw_header *)(ctx->blob->data); - switch (hdr->type) { - case B43_FW_TYPE_UCODE: - case B43_FW_TYPE_PCM: - size = be32_to_cpu(hdr->size); - if (size != ctx->blob->size - sizeof(struct b43_fw_header)) - goto err_format; - /* fallthrough */ - case B43_FW_TYPE_IV: - if (hdr->ver != 1) - goto err_format; - break; - default: - goto err_format; - } - - fw->data = ctx->blob; - fw->filename = name; - fw->type = ctx->req_type; - - return 0; - -err_format: - snprintf(ctx->errors[ctx->req_type], - sizeof(ctx->errors[ctx->req_type]), - "Firmware file \"%s\" format error.\n", ctx->fwname); - release_firmware(ctx->blob); - - return -EPROTO; -} - -/* http://bcm-v4.sipsolutions.net/802.11/Init/Firmware */ -static int b43_try_request_fw(struct b43_request_fw_context *ctx) -{ - struct b43_wldev *dev = ctx->dev; - struct b43_firmware *fw = &ctx->dev->fw; - struct b43_phy *phy = &dev->phy; - const u8 rev = ctx->dev->dev->core_rev; - const char *filename; - int err; - - /* Get microcode */ - filename = NULL; - switch (rev) { - case 42: - if (phy->type == B43_PHYTYPE_AC) - filename = "ucode42"; - break; - case 40: - if (phy->type == B43_PHYTYPE_AC) - filename = "ucode40"; - break; - case 33: - if (phy->type == B43_PHYTYPE_LCN40) - filename = "ucode33_lcn40"; - break; - case 30: - if (phy->type == B43_PHYTYPE_N) - filename = "ucode30_mimo"; - break; - case 29: - if (phy->type == B43_PHYTYPE_HT) - filename = "ucode29_mimo"; - break; - case 26: - if (phy->type == B43_PHYTYPE_HT) - filename = "ucode26_mimo"; - break; - case 28: - case 25: - if (phy->type == B43_PHYTYPE_N) - filename = "ucode25_mimo"; - else if (phy->type == B43_PHYTYPE_LCN) - filename = "ucode25_lcn"; - break; - case 24: - if (phy->type == B43_PHYTYPE_LCN) - filename = "ucode24_lcn"; - break; - case 23: - if (phy->type == B43_PHYTYPE_N) - filename = "ucode16_mimo"; - break; - case 16 ... 19: - if (phy->type == B43_PHYTYPE_N) - filename = "ucode16_mimo"; - else if (phy->type == B43_PHYTYPE_LP) - filename = "ucode16_lp"; - break; - case 15: - filename = "ucode15"; - break; - case 14: - filename = "ucode14"; - break; - case 13: - filename = "ucode13"; - break; - case 11 ... 12: - filename = "ucode11"; - break; - case 5 ... 10: - filename = "ucode5"; - break; - } - if (!filename) - goto err_no_ucode; - err = b43_do_request_fw(ctx, filename, &fw->ucode, true); - if (err) - goto err_load; - - /* Get PCM code */ - if ((rev >= 5) && (rev <= 10)) - filename = "pcm5"; - else if (rev >= 11) - filename = NULL; - else - goto err_no_pcm; - fw->pcm_request_failed = false; - err = b43_do_request_fw(ctx, filename, &fw->pcm, false); - if (err == -ENOENT) { - /* We did not find a PCM file? Not fatal, but - * core rev <= 10 must do without hwcrypto then. */ - fw->pcm_request_failed = true; - } else if (err) - goto err_load; - - /* Get initvals */ - filename = NULL; - switch (dev->phy.type) { - case B43_PHYTYPE_G: - if (rev == 13) - filename = "b0g0initvals13"; - else if (rev >= 5 && rev <= 10) - filename = "b0g0initvals5"; - break; - case B43_PHYTYPE_N: - if (rev == 30) - filename = "n16initvals30"; - else if (rev == 28 || rev == 25) - filename = "n0initvals25"; - else if (rev == 24) - filename = "n0initvals24"; - else if (rev == 23) - filename = "n0initvals16"; /* What about n0initvals22? */ - else if (rev >= 16 && rev <= 18) - filename = "n0initvals16"; - else if (rev >= 11 && rev <= 12) - filename = "n0initvals11"; - break; - case B43_PHYTYPE_LP: - if (rev >= 16 && rev <= 18) - filename = "lp0initvals16"; - else if (rev == 15) - filename = "lp0initvals15"; - else if (rev == 14) - filename = "lp0initvals14"; - else if (rev == 13) - filename = "lp0initvals13"; - break; - case B43_PHYTYPE_HT: - if (rev == 29) - filename = "ht0initvals29"; - else if (rev == 26) - filename = "ht0initvals26"; - break; - case B43_PHYTYPE_LCN: - if (rev == 24) - filename = "lcn0initvals24"; - break; - case B43_PHYTYPE_LCN40: - if (rev == 33) - filename = "lcn400initvals33"; - break; - case B43_PHYTYPE_AC: - if (rev == 42) - filename = "ac1initvals42"; - else if (rev == 40) - filename = "ac0initvals40"; - break; - } - if (!filename) - goto err_no_initvals; - err = b43_do_request_fw(ctx, filename, &fw->initvals, false); - if (err) - goto err_load; - - /* Get bandswitch initvals */ - filename = NULL; - switch (dev->phy.type) { - case B43_PHYTYPE_G: - if (rev == 13) - filename = "b0g0bsinitvals13"; - else if (rev >= 5 && rev <= 10) - filename = "b0g0bsinitvals5"; - break; - case B43_PHYTYPE_N: - if (rev == 30) - filename = "n16bsinitvals30"; - else if (rev == 28 || rev == 25) - filename = "n0bsinitvals25"; - else if (rev == 24) - filename = "n0bsinitvals24"; - else if (rev == 23) - filename = "n0bsinitvals16"; /* What about n0bsinitvals22? */ - else if (rev >= 16 && rev <= 18) - filename = "n0bsinitvals16"; - else if (rev >= 11 && rev <= 12) - filename = "n0bsinitvals11"; - break; - case B43_PHYTYPE_LP: - if (rev >= 16 && rev <= 18) - filename = "lp0bsinitvals16"; - else if (rev == 15) - filename = "lp0bsinitvals15"; - else if (rev == 14) - filename = "lp0bsinitvals14"; - else if (rev == 13) - filename = "lp0bsinitvals13"; - break; - case B43_PHYTYPE_HT: - if (rev == 29) - filename = "ht0bsinitvals29"; - else if (rev == 26) - filename = "ht0bsinitvals26"; - break; - case B43_PHYTYPE_LCN: - if (rev == 24) - filename = "lcn0bsinitvals24"; - break; - case B43_PHYTYPE_LCN40: - if (rev == 33) - filename = "lcn400bsinitvals33"; - break; - case B43_PHYTYPE_AC: - if (rev == 42) - filename = "ac1bsinitvals42"; - else if (rev == 40) - filename = "ac0bsinitvals40"; - break; - } - if (!filename) - goto err_no_initvals; - err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false); - if (err) - goto err_load; - - fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE); - - return 0; - -err_no_ucode: - err = ctx->fatal_failure = -EOPNOTSUPP; - b43err(dev->wl, "The driver does not know which firmware (ucode) " - "is required for your device (wl-core rev %u)\n", rev); - goto error; - -err_no_pcm: - err = ctx->fatal_failure = -EOPNOTSUPP; - b43err(dev->wl, "The driver does not know which firmware (PCM) " - "is required for your device (wl-core rev %u)\n", rev); - goto error; - -err_no_initvals: - err = ctx->fatal_failure = -EOPNOTSUPP; - b43err(dev->wl, "The driver does not know which firmware (initvals) " - "is required for your device (wl-core rev %u)\n", rev); - goto error; - -err_load: - /* We failed to load this firmware image. The error message - * already is in ctx->errors. Return and let our caller decide - * what to do. */ - goto error; - -error: - b43_release_firmware(dev); - return err; -} - -static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl); -static void b43_one_core_detach(struct b43_bus_dev *dev); -static int b43_rng_init(struct b43_wl *wl); - -static void b43_request_firmware(struct work_struct *work) -{ - struct b43_wl *wl = container_of(work, - struct b43_wl, firmware_load); - struct b43_wldev *dev = wl->current_dev; - struct b43_request_fw_context *ctx; - unsigned int i; - int err; - const char *errmsg; - - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return; - ctx->dev = dev; - - ctx->req_type = B43_FWTYPE_PROPRIETARY; - err = b43_try_request_fw(ctx); - if (!err) - goto start_ieee80211; /* Successfully loaded it. */ - /* Was fw version known? */ - if (ctx->fatal_failure) - goto out; - - /* proprietary fw not found, try open source */ - ctx->req_type = B43_FWTYPE_OPENSOURCE; - err = b43_try_request_fw(ctx); - if (!err) - goto start_ieee80211; /* Successfully loaded it. */ - if(ctx->fatal_failure) - goto out; - - /* Could not find a usable firmware. Print the errors. */ - for (i = 0; i < B43_NR_FWTYPES; i++) { - errmsg = ctx->errors[i]; - if (strlen(errmsg)) - b43err(dev->wl, "%s", errmsg); - } - b43_print_fw_helptext(dev->wl, 1); - goto out; - -start_ieee80211: - wl->hw->queues = B43_QOS_QUEUE_NUM; - if (!modparam_qos || dev->fw.opensource) - wl->hw->queues = 1; - - err = ieee80211_register_hw(wl->hw); - if (err) - goto err_one_core_detach; - wl->hw_registred = true; - b43_leds_register(wl->current_dev); - - /* Register HW RNG driver */ - b43_rng_init(wl); - - goto out; - -err_one_core_detach: - b43_one_core_detach(dev->dev); - -out: - kfree(ctx); -} - -static int b43_upload_microcode(struct b43_wldev *dev) -{ - struct wiphy *wiphy = dev->wl->hw->wiphy; - const size_t hdr_len = sizeof(struct b43_fw_header); - const __be32 *data; - unsigned int i, len; - u16 fwrev, fwpatch, fwdate, fwtime; - u32 tmp, macctl; - int err = 0; - - /* Jump the microcode PSM to offset 0 */ - macctl = b43_read32(dev, B43_MMIO_MACCTL); - B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); - macctl |= B43_MACCTL_PSM_JMP0; - b43_write32(dev, B43_MMIO_MACCTL, macctl); - /* Zero out all microcode PSM registers and shared memory. */ - for (i = 0; i < 64; i++) - b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); - for (i = 0; i < 4096; i += 2) - b43_shm_write16(dev, B43_SHM_SHARED, i, 0); - - /* Upload Microcode. */ - data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); - len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); - b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); - for (i = 0; i < len; i++) { - b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); - udelay(10); - } - - if (dev->fw.pcm.data) { - /* Upload PCM data. */ - data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); - len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); - b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); - b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); - /* No need for autoinc bit in SHM_HW */ - b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); - for (i = 0; i < len; i++) { - b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); - udelay(10); - } - } - - b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); - - /* Start the microcode PSM */ - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0, - B43_MACCTL_PSM_RUN); - - /* Wait for the microcode to load and respond */ - i = 0; - while (1) { - tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); - if (tmp == B43_IRQ_MAC_SUSPENDED) - break; - i++; - if (i >= 20) { - b43err(dev->wl, "Microcode not responding\n"); - b43_print_fw_helptext(dev->wl, 1); - err = -ENODEV; - goto error; - } - msleep(50); - } - b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ - - /* Get and check the revisions. */ - fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); - fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); - fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); - fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); - - if (fwrev <= 0x128) { - b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " - "binary drivers older than version 4.x is unsupported. " - "You must upgrade your firmware files.\n"); - b43_print_fw_helptext(dev->wl, 1); - err = -EOPNOTSUPP; - goto error; - } - dev->fw.rev = fwrev; - dev->fw.patch = fwpatch; - if (dev->fw.rev >= 598) - dev->fw.hdr_format = B43_FW_HDR_598; - else if (dev->fw.rev >= 410) - dev->fw.hdr_format = B43_FW_HDR_410; - else - dev->fw.hdr_format = B43_FW_HDR_351; - WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF)); - - dev->qos_enabled = dev->wl->hw->queues > 1; - /* Default to firmware/hardware crypto acceleration. */ - dev->hwcrypto_enabled = true; - - if (!dev->fw.opensource) { - b43err(dev->wl, "Rejected non-Free firmware\n"); - err = -EOPNOTSUPP; - goto error; - } - if (dev->fw.opensource) { - u16 fwcapa; - - /* Patchlevel info is encoded in the "time" field. */ - dev->fw.patch = fwtime; - b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n", - dev->fw.rev, dev->fw.patch); - - fwcapa = b43_fwcapa_read(dev); - if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) { - b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n"); - /* Disable hardware crypto and fall back to software crypto. */ - dev->hwcrypto_enabled = false; - } - /* adding QoS support should use an offline discovery mechanism */ - WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n"); - } else { - b43info(dev->wl, "Loading firmware version %u.%u " - "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", - fwrev, fwpatch, - (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, - (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); - if (dev->fw.pcm_request_failed) { - b43warn(dev->wl, "No \"/*(DEBLOBBED)*/\" firmware file found. " - "Hardware accelerated cryptography is disabled.\n"); - b43_print_fw_helptext(dev->wl, 0); - } - } - - snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", - dev->fw.rev, dev->fw.patch); - wiphy->hw_version = dev->dev->core_id; - - if (dev->fw.hdr_format == B43_FW_HDR_351) { - /* We're over the deadline, but we keep support for old fw - * until it turns out to be in major conflict with something new. */ - b43warn(dev->wl, "You are using an old firmware image. " - "Support for old firmware will be removed soon " - "(official deadline was July 2008).\n"); - b43_print_fw_helptext(dev->wl, 0); - } - - return 0; - -error: - /* Stop the microcode PSM. */ - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, - B43_MACCTL_PSM_JMP0); - - return err; -} - -static int b43_write_initvals(struct b43_wldev *dev, - const struct b43_iv *ivals, - size_t count, - size_t array_size) -{ - const struct b43_iv *iv; - u16 offset; - size_t i; - bool bit32; - - BUILD_BUG_ON(sizeof(struct b43_iv) != 6); - iv = ivals; - for (i = 0; i < count; i++) { - if (array_size < sizeof(iv->offset_size)) - goto err_format; - array_size -= sizeof(iv->offset_size); - offset = be16_to_cpu(iv->offset_size); - bit32 = !!(offset & B43_IV_32BIT); - offset &= B43_IV_OFFSET_MASK; - if (offset >= 0x1000) - goto err_format; - if (bit32) { - u32 value; - - if (array_size < sizeof(iv->data.d32)) - goto err_format; - array_size -= sizeof(iv->data.d32); - - value = get_unaligned_be32(&iv->data.d32); - b43_write32(dev, offset, value); - - iv = (const struct b43_iv *)((const uint8_t *)iv + - sizeof(__be16) + - sizeof(__be32)); - } else { - u16 value; - - if (array_size < sizeof(iv->data.d16)) - goto err_format; - array_size -= sizeof(iv->data.d16); - - value = be16_to_cpu(iv->data.d16); - b43_write16(dev, offset, value); - - iv = (const struct b43_iv *)((const uint8_t *)iv + - sizeof(__be16) + - sizeof(__be16)); - } - } - if (array_size) - goto err_format; - - return 0; - -err_format: - b43err(dev->wl, "Initial Values Firmware file-format error.\n"); - b43_print_fw_helptext(dev->wl, 1); - - return -EPROTO; -} - -static int b43_upload_initvals(struct b43_wldev *dev) -{ - const size_t hdr_len = sizeof(struct b43_fw_header); - const struct b43_fw_header *hdr; - struct b43_firmware *fw = &dev->fw; - const struct b43_iv *ivals; - size_t count; - - hdr = (const struct b43_fw_header *)(fw->initvals.data->data); - ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); - count = be32_to_cpu(hdr->size); - return b43_write_initvals(dev, ivals, count, - fw->initvals.data->size - hdr_len); -} - -static int b43_upload_initvals_band(struct b43_wldev *dev) -{ - const size_t hdr_len = sizeof(struct b43_fw_header); - const struct b43_fw_header *hdr; - struct b43_firmware *fw = &dev->fw; - const struct b43_iv *ivals; - size_t count; - - if (!fw->initvals_band.data) - return 0; - - hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); - ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); - count = be32_to_cpu(hdr->size); - return b43_write_initvals(dev, ivals, count, - fw->initvals_band.data->size - hdr_len); -} - -/* Initialize the GPIOs - * http://bcm-specs.sipsolutions.net/GPIO - */ - -#ifdef CONFIG_B43_SSB -static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - -#ifdef CONFIG_SSB_DRIVER_PCICORE - return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); -#else - return bus->chipco.dev; -#endif -} -#endif - -static int b43_gpio_init(struct b43_wldev *dev) -{ -#ifdef CONFIG_B43_SSB - struct ssb_device *gpiodev; -#endif - u32 mask, set; - - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); - b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF); - - mask = 0x0000001F; - set = 0x0000000F; - if (dev->dev->chip_id == 0x4301) { - mask |= 0x0060; - set |= 0x0060; - } else if (dev->dev->chip_id == 0x5354) { - /* Don't allow overtaking buttons GPIOs */ - set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */ - } - - if (0 /* FIXME: conditional unknown */ ) { - b43_write16(dev, B43_MMIO_GPIO_MASK, - b43_read16(dev, B43_MMIO_GPIO_MASK) - | 0x0100); - /* BT Coexistance Input */ - mask |= 0x0080; - set |= 0x0080; - /* BT Coexistance Out */ - mask |= 0x0100; - set |= 0x0100; - } - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) { - /* PA is controlled by gpio 9, let ucode handle it */ - b43_write16(dev, B43_MMIO_GPIO_MASK, - b43_read16(dev, B43_MMIO_GPIO_MASK) - | 0x0200); - mask |= 0x0200; - set |= 0x0200; - } - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - gpiodev = b43_ssb_gpio_dev(dev); - if (gpiodev) - ssb_write32(gpiodev, B43_GPIO_CONTROL, - (ssb_read32(gpiodev, B43_GPIO_CONTROL) - & ~mask) | set); - break; -#endif - } - - return 0; -} - -/* Turn off all GPIO stuff. Call this on module unload, for example. */ -static void b43_gpio_cleanup(struct b43_wldev *dev) -{ -#ifdef CONFIG_B43_SSB - struct ssb_device *gpiodev; -#endif - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - gpiodev = b43_ssb_gpio_dev(dev); - if (gpiodev) - ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); - break; -#endif - } -} - -/* http://bcm-specs.sipsolutions.net/EnableMac */ -void b43_mac_enable(struct b43_wldev *dev) -{ - if (b43_debug(dev, B43_DBG_FIRMWARE)) { - u16 fwstate; - - fwstate = b43_shm_read16(dev, B43_SHM_SHARED, - B43_SHM_SH_UCODESTAT); - if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) && - (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) { - b43err(dev->wl, "b43_mac_enable(): The firmware " - "should be suspended, but current state is %u\n", - fwstate); - } - } - - dev->mac_suspended--; - B43_WARN_ON(dev->mac_suspended < 0); - if (dev->mac_suspended == 0) { - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED); - b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, - B43_IRQ_MAC_SUSPENDED); - /* Commit writes */ - b43_read32(dev, B43_MMIO_MACCTL); - b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); - b43_power_saving_ctl_bits(dev, 0); - } -} - -/* http://bcm-specs.sipsolutions.net/SuspendMAC */ -void b43_mac_suspend(struct b43_wldev *dev) -{ - int i; - u32 tmp; - - might_sleep(); - B43_WARN_ON(dev->mac_suspended < 0); - - if (dev->mac_suspended == 0) { - b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0); - /* force pci to flush the write */ - b43_read32(dev, B43_MMIO_MACCTL); - for (i = 35; i; i--) { - tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); - if (tmp & B43_IRQ_MAC_SUSPENDED) - goto out; - udelay(10); - } - /* Hm, it seems this will take some time. Use msleep(). */ - for (i = 40; i; i--) { - tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); - if (tmp & B43_IRQ_MAC_SUSPENDED) - goto out; - msleep(1); - } - b43err(dev->wl, "MAC suspend failed\n"); - } -out: - dev->mac_suspended++; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ -void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) -{ - u32 tmp; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - if (on) - tmp |= B43_BCMA_IOCTL_MACPHYCLKEN; - else - tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - if (on) - tmp |= B43_TMSLOW_MACPHYCLKEN; - else - tmp &= ~B43_TMSLOW_MACPHYCLKEN; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - break; -#endif - } -} - -/* brcms_b_switch_macfreq */ -void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode) -{ - u16 chip_id = dev->dev->chip_id; - - if (chip_id == BCMA_CHIP_ID_BCM4331) { - switch (spurmode) { - case 2: /* 168 Mhz: 2^26/168 = 0x61862 */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x1862); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); - break; - case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x3e70); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); - break; - default: /* 160 Mhz: 2^26/160 = 0x66666 */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x6666); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x6); - break; - } - } else if (chip_id == BCMA_CHIP_ID_BCM43131 || - chip_id == BCMA_CHIP_ID_BCM43217 || - chip_id == BCMA_CHIP_ID_BCM43222 || - chip_id == BCMA_CHIP_ID_BCM43224 || - chip_id == BCMA_CHIP_ID_BCM43225 || - chip_id == BCMA_CHIP_ID_BCM43227 || - chip_id == BCMA_CHIP_ID_BCM43228) { - switch (spurmode) { - case 2: /* 126 Mhz */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x2082); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); - break; - case 1: /* 123 Mhz */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x5341); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); - break; - default: /* 120 Mhz */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x8889); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8); - break; - } - } else if (dev->phy.type == B43_PHYTYPE_LCN) { - switch (spurmode) { - case 1: /* 82 Mhz */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0x7CE0); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); - break; - default: /* 80 Mhz */ - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, 0xCCCD); - b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0xC); - break; - } - } -} - -static void b43_adjust_opmode(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - u32 ctl; - u16 cfp_pretbtt; - - ctl = b43_read32(dev, B43_MMIO_MACCTL); - /* Reset status to STA infrastructure mode. */ - ctl &= ~B43_MACCTL_AP; - ctl &= ~B43_MACCTL_KEEP_CTL; - ctl &= ~B43_MACCTL_KEEP_BADPLCP; - ctl &= ~B43_MACCTL_KEEP_BAD; - ctl &= ~B43_MACCTL_PROMISC; - ctl &= ~B43_MACCTL_BEACPROMISC; - ctl |= B43_MACCTL_INFRA; - - if (b43_is_mode(wl, NL80211_IFTYPE_AP) || - b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) - ctl |= B43_MACCTL_AP; - else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) - ctl &= ~B43_MACCTL_INFRA; - - if (wl->filter_flags & FIF_CONTROL) - ctl |= B43_MACCTL_KEEP_CTL; - if (wl->filter_flags & FIF_FCSFAIL) - ctl |= B43_MACCTL_KEEP_BAD; - if (wl->filter_flags & FIF_PLCPFAIL) - ctl |= B43_MACCTL_KEEP_BADPLCP; - if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) - ctl |= B43_MACCTL_BEACPROMISC; - - /* Workaround: On old hardware the HW-MAC-address-filter - * doesn't work properly, so always run promisc in filter - * it in software. */ - if (dev->dev->core_rev <= 4) - ctl |= B43_MACCTL_PROMISC; - - b43_write32(dev, B43_MMIO_MACCTL, ctl); - - cfp_pretbtt = 2; - if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { - if (dev->dev->chip_id == 0x4306 && - dev->dev->chip_rev == 3) - cfp_pretbtt = 100; - else - cfp_pretbtt = 50; - } - b43_write16(dev, 0x612, cfp_pretbtt); - - /* FIXME: We don't currently implement the PMQ mechanism, - * so always disable it. If we want to implement PMQ, - * we need to enable it here (clear DISCPMQ) in AP mode. - */ - if (0 /* ctl & B43_MACCTL_AP */) - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0); - else - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ); -} - -static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) -{ - u16 offset; - - if (is_ofdm) { - offset = 0x480; - offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; - } else { - offset = 0x4C0; - offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; - } - b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, - b43_shm_read16(dev, B43_SHM_SHARED, offset)); -} - -static void b43_rate_memory_init(struct b43_wldev *dev) -{ - switch (dev->phy.type) { - case B43_PHYTYPE_A: - case B43_PHYTYPE_G: - case B43_PHYTYPE_N: - case B43_PHYTYPE_LP: - case B43_PHYTYPE_HT: - case B43_PHYTYPE_LCN: - b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_9MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); - b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); - if (dev->phy.type == B43_PHYTYPE_A) - break; - /* fallthrough */ - case B43_PHYTYPE_B: - b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); - b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); - b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); - b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); - break; - default: - B43_WARN_ON(1); - } -} - -/* Set the default values for the PHY TX Control Words. */ -static void b43_set_phytxctl_defaults(struct b43_wldev *dev) -{ - u16 ctl = 0; - - ctl |= B43_TXH_PHY_ENC_CCK; - ctl |= B43_TXH_PHY_ANT01AUTO; - ctl |= B43_TXH_PHY_TXPWR; - - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); -} - -/* Set the TX-Antenna for management frames sent by firmware. */ -static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) -{ - u16 ant; - u16 tmp; - - ant = b43_antenna_to_phyctl(antenna); - - /* For ACK/CTS */ - tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); - tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); - /* For Probe Resposes */ - tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); - tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); -} - -/* This is the opposite of b43_chip_init() */ -static void b43_chip_exit(struct b43_wldev *dev) -{ - b43_phy_exit(dev); - b43_gpio_cleanup(dev); - /* firmware is released later */ -} - -/* Initialize the chip - * http://bcm-specs.sipsolutions.net/ChipInit - */ -static int b43_chip_init(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - int err; - u32 macctl; - u16 value16; - - /* Initialize the MAC control */ - macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; - if (dev->phy.gmode) - macctl |= B43_MACCTL_GMODE; - macctl |= B43_MACCTL_INFRA; - b43_write32(dev, B43_MMIO_MACCTL, macctl); - - err = b43_upload_microcode(dev); - if (err) - goto out; /* firmware is released later */ - - err = b43_gpio_init(dev); - if (err) - goto out; /* firmware is released later */ - - err = b43_upload_initvals(dev); - if (err) - goto err_gpio_clean; - - err = b43_upload_initvals_band(dev); - if (err) - goto err_gpio_clean; - - /* Turn the Analog on and initialize the PHY. */ - phy->ops->switch_analog(dev, 1); - err = b43_phy_init(dev); - if (err) - goto err_gpio_clean; - - /* Disable Interference Mitigation. */ - if (phy->ops->interf_mitigation) - phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); - - /* Select the antennae */ - if (phy->ops->set_rx_antenna) - phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT); - b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); - - if (phy->type == B43_PHYTYPE_B) { - value16 = b43_read16(dev, 0x005E); - value16 |= 0x0004; - b43_write16(dev, 0x005E, value16); - } - b43_write32(dev, 0x0100, 0x01000000); - if (dev->dev->core_rev < 5) - b43_write32(dev, 0x010C, 0x01000000); - - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0); - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA); - - /* Probe Response Timeout value */ - /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0); - - /* Initially set the wireless operation mode. */ - b43_adjust_opmode(dev); - - if (dev->dev->core_rev < 3) { - b43_write16(dev, 0x060E, 0x0000); - b43_write16(dev, 0x0610, 0x8000); - b43_write16(dev, 0x0604, 0x0000); - b43_write16(dev, 0x0606, 0x0200); - } else { - b43_write32(dev, 0x0188, 0x80000000); - b43_write32(dev, 0x018C, 0x02000000); - } - b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); - b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00); - b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); - b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); - b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); - b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); - b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); - - b43_mac_phy_clock_set(dev, true); - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - /* FIXME: 0xE74 is quite common, but should be read from CC */ - b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - b43_write16(dev, B43_MMIO_POWERUP_DELAY, - dev->dev->sdev->bus->chipco.fast_pwrup_delay); - break; -#endif - } - - err = 0; - b43dbg(dev->wl, "Chip initialized\n"); -out: - return err; - -err_gpio_clean: - b43_gpio_cleanup(dev); - return err; -} - -static void b43_periodic_every60sec(struct b43_wldev *dev) -{ - const struct b43_phy_operations *ops = dev->phy.ops; - - if (ops->pwork_60sec) - ops->pwork_60sec(dev); - - /* Force check the TX power emission now. */ - b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME); -} - -static void b43_periodic_every30sec(struct b43_wldev *dev) -{ - /* Update device statistics. */ - b43_calculate_link_quality(dev); -} - -static void b43_periodic_every15sec(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 wdr; - - if (dev->fw.opensource) { - /* Check if the firmware is still alive. - * It will reset the watchdog counter to 0 in its idle loop. */ - wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG); - if (unlikely(wdr)) { - b43err(dev->wl, "Firmware watchdog: The firmware died!\n"); - b43_controller_restart(dev, "Firmware watchdog"); - return; - } else { - b43_shm_write16(dev, B43_SHM_SCRATCH, - B43_WATCHDOG_REG, 1); - } - } - - if (phy->ops->pwork_15sec) - phy->ops->pwork_15sec(dev); - - atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); - wmb(); - -#if B43_DEBUG - if (b43_debug(dev, B43_DBG_VERBOSESTATS)) { - unsigned int i; - - b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n", - dev->irq_count / 15, - dev->tx_count / 15, - dev->rx_count / 15); - dev->irq_count = 0; - dev->tx_count = 0; - dev->rx_count = 0; - for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) { - if (dev->irq_bit_count[i]) { - b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n", - dev->irq_bit_count[i] / 15, i, (1 << i)); - dev->irq_bit_count[i] = 0; - } - } - } -#endif -} - -static void do_periodic_work(struct b43_wldev *dev) -{ - unsigned int state; - - state = dev->periodic_state; - if (state % 4 == 0) - b43_periodic_every60sec(dev); - if (state % 2 == 0) - b43_periodic_every30sec(dev); - b43_periodic_every15sec(dev); -} - -/* Periodic work locking policy: - * The whole periodic work handler is protected by - * wl->mutex. If another lock is needed somewhere in the - * pwork callchain, it's acquired in-place, where it's needed. - */ -static void b43_periodic_work_handler(struct work_struct *work) -{ - struct b43_wldev *dev = container_of(work, struct b43_wldev, - periodic_work.work); - struct b43_wl *wl = dev->wl; - unsigned long delay; - - mutex_lock(&wl->mutex); - - if (unlikely(b43_status(dev) != B43_STAT_STARTED)) - goto out; - if (b43_debug(dev, B43_DBG_PWORK_STOP)) - goto out_requeue; - - do_periodic_work(dev); - - dev->periodic_state++; -out_requeue: - if (b43_debug(dev, B43_DBG_PWORK_FAST)) - delay = msecs_to_jiffies(50); - else - delay = round_jiffies_relative(HZ * 15); - ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay); -out: - mutex_unlock(&wl->mutex); -} - -static void b43_periodic_tasks_setup(struct b43_wldev *dev) -{ - struct delayed_work *work = &dev->periodic_work; - - dev->periodic_state = 0; - INIT_DELAYED_WORK(work, b43_periodic_work_handler); - ieee80211_queue_delayed_work(dev->wl->hw, work, 0); -} - -/* Check if communication with the device works correctly. */ -static int b43_validate_chipaccess(struct b43_wldev *dev) -{ - u32 v, backup0, backup4; - - backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0); - backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4); - - /* Check for read/write and endianness problems. */ - b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); - if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) - goto error; - b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); - if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) - goto error; - - /* Check if unaligned 32bit SHM_SHARED access works properly. - * However, don't bail out on failure, because it's noncritical. */ - b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122); - b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344); - b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566); - b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788); - if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344) - b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n"); - b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD); - if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 || - b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD || - b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB || - b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788) - b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n"); - - b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); - b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); - - if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) { - /* The 32bit register shadows the two 16bit registers - * with update sideeffects. Validate this. */ - b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); - b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); - if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) - goto error; - if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) - goto error; - } - b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); - - v = b43_read32(dev, B43_MMIO_MACCTL); - v |= B43_MACCTL_GMODE; - if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) - goto error; - - return 0; -error: - b43err(dev->wl, "Failed to validate the chipaccess\n"); - return -ENODEV; -} - -static void b43_security_init(struct b43_wldev *dev) -{ - dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); - /* KTP is a word address, but we address SHM bytewise. - * So multiply by two. - */ - dev->ktp *= 2; - /* Number of RCMTA address slots */ - b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS); - /* Clear the key memory. */ - b43_clear_keys(dev); -} - -#ifdef CONFIG_B43_HWRNG -static int b43_rng_read(struct hwrng *rng, u32 *data) -{ - struct b43_wl *wl = (struct b43_wl *)rng->priv; - struct b43_wldev *dev; - int count = -ENODEV; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) { - *data = b43_read16(dev, B43_MMIO_RNG); - count = sizeof(u16); - } - mutex_unlock(&wl->mutex); - - return count; -} -#endif /* CONFIG_B43_HWRNG */ - -static void b43_rng_exit(struct b43_wl *wl) -{ -#ifdef CONFIG_B43_HWRNG - if (wl->rng_initialized) - hwrng_unregister(&wl->rng); -#endif /* CONFIG_B43_HWRNG */ -} - -static int b43_rng_init(struct b43_wl *wl) -{ - int err = 0; - -#ifdef CONFIG_B43_HWRNG - snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), - "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); - wl->rng.name = wl->rng_name; - wl->rng.data_read = b43_rng_read; - wl->rng.priv = (unsigned long)wl; - wl->rng_initialized = true; - err = hwrng_register(&wl->rng); - if (err) { - wl->rng_initialized = false; - b43err(wl, "Failed to register the random " - "number generator (%d)\n", err); - } -#endif /* CONFIG_B43_HWRNG */ - - return err; -} - -static void b43_tx_work(struct work_struct *work) -{ - struct b43_wl *wl = container_of(work, struct b43_wl, tx_work); - struct b43_wldev *dev; - struct sk_buff *skb; - int queue_num; - int err = 0; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) { - mutex_unlock(&wl->mutex); - return; - } - - for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { - while (skb_queue_len(&wl->tx_queue[queue_num])) { - skb = skb_dequeue(&wl->tx_queue[queue_num]); - if (b43_using_pio_transfers(dev)) - err = b43_pio_tx(dev, skb); - else - err = b43_dma_tx(dev, skb); - if (err == -ENOSPC) { - wl->tx_queue_stopped[queue_num] = 1; - ieee80211_stop_queue(wl->hw, queue_num); - skb_queue_head(&wl->tx_queue[queue_num], skb); - break; - } - if (unlikely(err)) - ieee80211_free_txskb(wl->hw, skb); - err = 0; - } - - if (!err) - wl->tx_queue_stopped[queue_num] = 0; - } - -#if B43_DEBUG - dev->tx_count++; -#endif - mutex_unlock(&wl->mutex); -} - -static void b43_op_tx(struct ieee80211_hw *hw, - struct ieee80211_tx_control *control, - struct sk_buff *skb) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - - if (unlikely(skb->len < 2 + 2 + 6)) { - /* Too short, this can't be a valid frame. */ - ieee80211_free_txskb(hw, skb); - return; - } - B43_WARN_ON(skb_shinfo(skb)->nr_frags); - - skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb); - if (!wl->tx_queue_stopped[skb->queue_mapping]) { - ieee80211_queue_work(wl->hw, &wl->tx_work); - } else { - ieee80211_stop_queue(wl->hw, skb->queue_mapping); - } -} - -static void b43_qos_params_upload(struct b43_wldev *dev, - const struct ieee80211_tx_queue_params *p, - u16 shm_offset) -{ - u16 params[B43_NR_QOSPARAMS]; - int bslots, tmp; - unsigned int i; - - if (!dev->qos_enabled) - return; - - bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min; - - memset(¶ms, 0, sizeof(params)); - - params[B43_QOSPARAM_TXOP] = p->txop * 32; - params[B43_QOSPARAM_CWMIN] = p->cw_min; - params[B43_QOSPARAM_CWMAX] = p->cw_max; - params[B43_QOSPARAM_CWCUR] = p->cw_min; - params[B43_QOSPARAM_AIFS] = p->aifs; - params[B43_QOSPARAM_BSLOTS] = bslots; - params[B43_QOSPARAM_REGGAP] = bslots + p->aifs; - - for (i = 0; i < ARRAY_SIZE(params); i++) { - if (i == B43_QOSPARAM_STATUS) { - tmp = b43_shm_read16(dev, B43_SHM_SHARED, - shm_offset + (i * 2)); - /* Mark the parameters as updated. */ - tmp |= 0x100; - b43_shm_write16(dev, B43_SHM_SHARED, - shm_offset + (i * 2), - tmp); - } else { - b43_shm_write16(dev, B43_SHM_SHARED, - shm_offset + (i * 2), - params[i]); - } - } -} - -/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */ -static const u16 b43_qos_shm_offsets[] = { - /* [mac80211-queue-nr] = SHM_OFFSET, */ - [0] = B43_QOS_VOICE, - [1] = B43_QOS_VIDEO, - [2] = B43_QOS_BESTEFFORT, - [3] = B43_QOS_BACKGROUND, -}; - -/* Update all QOS parameters in hardware. */ -static void b43_qos_upload_all(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - struct b43_qos_params *params; - unsigned int i; - - if (!dev->qos_enabled) - return; - - BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != - ARRAY_SIZE(wl->qos_params)); - - b43_mac_suspend(dev); - for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { - params = &(wl->qos_params[i]); - b43_qos_params_upload(dev, &(params->p), - b43_qos_shm_offsets[i]); - } - b43_mac_enable(dev); -} - -static void b43_qos_clear(struct b43_wl *wl) -{ - struct b43_qos_params *params; - unsigned int i; - - /* Initialize QoS parameters to sane defaults. */ - - BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != - ARRAY_SIZE(wl->qos_params)); - - for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { - params = &(wl->qos_params[i]); - - switch (b43_qos_shm_offsets[i]) { - case B43_QOS_VOICE: - params->p.txop = 0; - params->p.aifs = 2; - params->p.cw_min = 0x0001; - params->p.cw_max = 0x0001; - break; - case B43_QOS_VIDEO: - params->p.txop = 0; - params->p.aifs = 2; - params->p.cw_min = 0x0001; - params->p.cw_max = 0x0001; - break; - case B43_QOS_BESTEFFORT: - params->p.txop = 0; - params->p.aifs = 3; - params->p.cw_min = 0x0001; - params->p.cw_max = 0x03FF; - break; - case B43_QOS_BACKGROUND: - params->p.txop = 0; - params->p.aifs = 7; - params->p.cw_min = 0x0001; - params->p.cw_max = 0x03FF; - break; - default: - B43_WARN_ON(1); - } - } -} - -/* Initialize the core's QOS capabilities */ -static void b43_qos_init(struct b43_wldev *dev) -{ - if (!dev->qos_enabled) { - /* Disable QOS support. */ - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF); - b43_write16(dev, B43_MMIO_IFSCTL, - b43_read16(dev, B43_MMIO_IFSCTL) - & ~B43_MMIO_IFSCTL_USE_EDCF); - b43dbg(dev->wl, "QoS disabled\n"); - return; - } - - /* Upload the current QOS parameters. */ - b43_qos_upload_all(dev); - - /* Enable QOS support. */ - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); - b43_write16(dev, B43_MMIO_IFSCTL, - b43_read16(dev, B43_MMIO_IFSCTL) - | B43_MMIO_IFSCTL_USE_EDCF); - b43dbg(dev->wl, "QoS enabled\n"); -} - -static int b43_op_conf_tx(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, u16 _queue, - const struct ieee80211_tx_queue_params *params) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - unsigned int queue = (unsigned int)_queue; - int err = -ENODEV; - - if (queue >= ARRAY_SIZE(wl->qos_params)) { - /* Queue not available or don't support setting - * params on this queue. Return success to not - * confuse mac80211. */ - return 0; - } - BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) != - ARRAY_SIZE(wl->qos_params)); - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) - goto out_unlock; - - memcpy(&(wl->qos_params[queue].p), params, sizeof(*params)); - b43_mac_suspend(dev); - b43_qos_params_upload(dev, &(wl->qos_params[queue].p), - b43_qos_shm_offsets[queue]); - b43_mac_enable(dev); - err = 0; - -out_unlock: - mutex_unlock(&wl->mutex); - - return err; -} - -static int b43_op_get_stats(struct ieee80211_hw *hw, - struct ieee80211_low_level_stats *stats) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - - mutex_lock(&wl->mutex); - memcpy(stats, &wl->ieee_stats, sizeof(*stats)); - mutex_unlock(&wl->mutex); - - return 0; -} - -static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - u64 tsf; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - - if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) - b43_tsf_read(dev, &tsf); - else - tsf = 0; - - mutex_unlock(&wl->mutex); - - return tsf; -} - -static void b43_op_set_tsf(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, u64 tsf) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - - if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) - b43_tsf_write(dev, tsf); - - mutex_unlock(&wl->mutex); -} - -static const char *band_to_string(enum ieee80211_band band) -{ - switch (band) { - case IEEE80211_BAND_5GHZ: - return "5"; - case IEEE80211_BAND_2GHZ: - return "2.4"; - default: - break; - } - B43_WARN_ON(1); - return ""; -} - -/* Expects wl->mutex locked */ -static int b43_switch_band(struct b43_wldev *dev, - struct ieee80211_channel *chan) -{ - struct b43_phy *phy = &dev->phy; - bool gmode; - u32 tmp; - - switch (chan->band) { - case IEEE80211_BAND_5GHZ: - gmode = false; - break; - case IEEE80211_BAND_2GHZ: - gmode = true; - break; - default: - B43_WARN_ON(1); - return -EINVAL; - } - - if (!((gmode && phy->supports_2ghz) || - (!gmode && phy->supports_5ghz))) { - b43err(dev->wl, "This device doesn't support %s-GHz band\n", - band_to_string(chan->band)); - return -ENODEV; - } - - if (!!phy->gmode == !!gmode) { - /* This device is already running. */ - return 0; - } - - b43dbg(dev->wl, "Switching to %s GHz band\n", - band_to_string(chan->band)); - - /* Some new devices don't need disabling radio for band switching */ - if (!(phy->type == B43_PHYTYPE_N && phy->rev >= 3)) - b43_software_rfkill(dev, true); - - phy->gmode = gmode; - b43_phy_put_into_reset(dev); - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - if (gmode) - tmp |= B43_BCMA_IOCTL_GMODE; - else - tmp &= ~B43_BCMA_IOCTL_GMODE; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - if (gmode) - tmp |= B43_TMSLOW_GMODE; - else - tmp &= ~B43_TMSLOW_GMODE; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - break; -#endif - } - b43_phy_take_out_of_reset(dev); - - b43_upload_initvals_band(dev); - - b43_phy_init(dev); - - return 0; -} - -static void b43_set_beacon_listen_interval(struct b43_wldev *dev, u16 interval) -{ - interval = min_t(u16, interval, (u16)0xFF); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BCN_LI, interval); -} - -/* Write the short and long frame retry limit values. */ -static void b43_set_retry_limits(struct b43_wldev *dev, - unsigned int short_retry, - unsigned int long_retry) -{ - /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing - * the chip-internal counter. */ - short_retry = min(short_retry, (unsigned int)0xF); - long_retry = min(long_retry, (unsigned int)0xF); - - b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, - short_retry); - b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, - long_retry); -} - -static int b43_op_config(struct ieee80211_hw *hw, u32 changed) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - struct b43_phy *phy = &dev->phy; - struct ieee80211_conf *conf = &hw->conf; - int antenna; - int err = 0; - - mutex_lock(&wl->mutex); - b43_mac_suspend(dev); - - if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) - b43_set_beacon_listen_interval(dev, conf->listen_interval); - - if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { - phy->chandef = &conf->chandef; - phy->channel = conf->chandef.chan->hw_value; - - /* Switch the band (if necessary). */ - err = b43_switch_band(dev, conf->chandef.chan); - if (err) - goto out_mac_enable; - - /* Switch to the requested channel. - * The firmware takes care of races with the TX handler. - */ - b43_switch_channel(dev, phy->channel); - } - - if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) - b43_set_retry_limits(dev, conf->short_frame_max_tx_count, - conf->long_frame_max_tx_count); - changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS; - if (!changed) - goto out_mac_enable; - - dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); - - /* Adjust the desired TX power level. */ - if (conf->power_level != 0) { - if (conf->power_level != phy->desired_txpower) { - phy->desired_txpower = conf->power_level; - b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME | - B43_TXPWR_IGNORE_TSSI); - } - } - - /* Antennas for RX and management frame TX. */ - antenna = B43_ANTENNA_DEFAULT; - b43_mgmtframe_txantenna(dev, antenna); - antenna = B43_ANTENNA_DEFAULT; - if (phy->ops->set_rx_antenna) - phy->ops->set_rx_antenna(dev, antenna); - - if (wl->radio_enabled != phy->radio_on) { - if (wl->radio_enabled) { - b43_software_rfkill(dev, false); - b43info(dev->wl, "Radio turned on by software\n"); - if (!dev->radio_hw_enable) { - b43info(dev->wl, "The hardware RF-kill button " - "still turns the radio physically off. " - "Press the button to turn it on.\n"); - } - } else { - b43_software_rfkill(dev, true); - b43info(dev->wl, "Radio turned off by software\n"); - } - } - -out_mac_enable: - b43_mac_enable(dev); - mutex_unlock(&wl->mutex); - - return err; -} - -static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates) -{ - struct ieee80211_supported_band *sband = - dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)]; - struct ieee80211_rate *rate; - int i; - u16 basic, direct, offset, basic_offset, rateptr; - - for (i = 0; i < sband->n_bitrates; i++) { - rate = &sband->bitrates[i]; - - if (b43_is_cck_rate(rate->hw_value)) { - direct = B43_SHM_SH_CCKDIRECT; - basic = B43_SHM_SH_CCKBASIC; - offset = b43_plcp_get_ratecode_cck(rate->hw_value); - offset &= 0xF; - } else { - direct = B43_SHM_SH_OFDMDIRECT; - basic = B43_SHM_SH_OFDMBASIC; - offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); - offset &= 0xF; - } - - rate = ieee80211_get_response_rate(sband, brates, rate->bitrate); - - if (b43_is_cck_rate(rate->hw_value)) { - basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value); - basic_offset &= 0xF; - } else { - basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value); - basic_offset &= 0xF; - } - - /* - * Get the pointer that we need to point to - * from the direct map - */ - rateptr = b43_shm_read16(dev, B43_SHM_SHARED, - direct + 2 * basic_offset); - /* and write it to the basic map */ - b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset, - rateptr); - } -} - -static void b43_op_bss_info_changed(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_bss_conf *conf, - u32 changed) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - - dev = wl->current_dev; - if (!dev || b43_status(dev) < B43_STAT_STARTED) - goto out_unlock_mutex; - - B43_WARN_ON(wl->vif != vif); - - if (changed & BSS_CHANGED_BSSID) { - if (conf->bssid) - memcpy(wl->bssid, conf->bssid, ETH_ALEN); - else - eth_zero_addr(wl->bssid); - } - - if (b43_status(dev) >= B43_STAT_INITIALIZED) { - if (changed & BSS_CHANGED_BEACON && - (b43_is_mode(wl, NL80211_IFTYPE_AP) || - b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || - b43_is_mode(wl, NL80211_IFTYPE_ADHOC))) - b43_update_templates(wl); - - if (changed & BSS_CHANGED_BSSID) - b43_write_mac_bssid_templates(dev); - } - - b43_mac_suspend(dev); - - /* Update templates for AP/mesh mode. */ - if (changed & BSS_CHANGED_BEACON_INT && - (b43_is_mode(wl, NL80211_IFTYPE_AP) || - b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) || - b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) && - conf->beacon_int) - b43_set_beacon_int(dev, conf->beacon_int); - - if (changed & BSS_CHANGED_BASIC_RATES) - b43_update_basic_rates(dev, conf->basic_rates); - - if (changed & BSS_CHANGED_ERP_SLOT) { - if (conf->use_short_slot) - b43_short_slot_timing_enable(dev); - else - b43_short_slot_timing_disable(dev); - } - - b43_mac_enable(dev); -out_unlock_mutex: - mutex_unlock(&wl->mutex); -} - -static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, - struct ieee80211_vif *vif, struct ieee80211_sta *sta, - struct ieee80211_key_conf *key) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - u8 algorithm; - u8 index; - int err; - static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; - - if (modparam_nohwcrypt) - return -ENOSPC; /* User disabled HW-crypto */ - - if ((vif->type == NL80211_IFTYPE_ADHOC || - vif->type == NL80211_IFTYPE_MESH_POINT) && - (key->cipher == WLAN_CIPHER_SUITE_TKIP || - key->cipher == WLAN_CIPHER_SUITE_CCMP) && - !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { - /* - * For now, disable hw crypto for the RSN IBSS group keys. This - * could be optimized in the future, but until that gets - * implemented, use of software crypto for group addressed - * frames is a acceptable to allow RSN IBSS to be used. - */ - return -EOPNOTSUPP; - } - - mutex_lock(&wl->mutex); - - dev = wl->current_dev; - err = -ENODEV; - if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) - goto out_unlock; - - if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) { - /* We don't have firmware for the crypto engine. - * Must use software-crypto. */ - err = -EOPNOTSUPP; - goto out_unlock; - } - - err = -EINVAL; - switch (key->cipher) { - case WLAN_CIPHER_SUITE_WEP40: - algorithm = B43_SEC_ALGO_WEP40; - break; - case WLAN_CIPHER_SUITE_WEP104: - algorithm = B43_SEC_ALGO_WEP104; - break; - case WLAN_CIPHER_SUITE_TKIP: - algorithm = B43_SEC_ALGO_TKIP; - break; - case WLAN_CIPHER_SUITE_CCMP: - algorithm = B43_SEC_ALGO_AES; - break; - default: - B43_WARN_ON(1); - goto out_unlock; - } - index = (u8) (key->keyidx); - if (index > 3) - goto out_unlock; - - switch (cmd) { - case SET_KEY: - if (algorithm == B43_SEC_ALGO_TKIP && - (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) || - !modparam_hwtkip)) { - /* We support only pairwise key */ - err = -EOPNOTSUPP; - goto out_unlock; - } - - if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { - if (WARN_ON(!sta)) { - err = -EOPNOTSUPP; - goto out_unlock; - } - /* Pairwise key with an assigned MAC address. */ - err = b43_key_write(dev, -1, algorithm, - key->key, key->keylen, - sta->addr, key); - } else { - /* Group key */ - err = b43_key_write(dev, index, algorithm, - key->key, key->keylen, NULL, key); - } - if (err) - goto out_unlock; - - if (algorithm == B43_SEC_ALGO_WEP40 || - algorithm == B43_SEC_ALGO_WEP104) { - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); - } else { - b43_hf_write(dev, - b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); - } - key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; - if (algorithm == B43_SEC_ALGO_TKIP) - key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; - break; - case DISABLE_KEY: { - err = b43_key_clear(dev, key->hw_key_idx); - if (err) - goto out_unlock; - break; - } - default: - B43_WARN_ON(1); - } - -out_unlock: - if (!err) { - b43dbg(wl, "%s hardware based encryption for keyidx: %d, " - "mac: %pM\n", - cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, - sta ? sta->addr : bcast_addr); - b43_dump_keymemory(dev); - } - mutex_unlock(&wl->mutex); - - return err; -} - -static void b43_op_configure_filter(struct ieee80211_hw *hw, - unsigned int changed, unsigned int *fflags, - u64 multicast) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (!dev) { - *fflags = 0; - goto out_unlock; - } - - *fflags &= FIF_ALLMULTI | - FIF_FCSFAIL | - FIF_PLCPFAIL | - FIF_CONTROL | - FIF_OTHER_BSS | - FIF_BCN_PRBRESP_PROMISC; - - changed &= FIF_ALLMULTI | - FIF_FCSFAIL | - FIF_PLCPFAIL | - FIF_CONTROL | - FIF_OTHER_BSS | - FIF_BCN_PRBRESP_PROMISC; - - wl->filter_flags = *fflags; - - if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) - b43_adjust_opmode(dev); - -out_unlock: - mutex_unlock(&wl->mutex); -} - -/* Locking: wl->mutex - * Returns the current dev. This might be different from the passed in dev, - * because the core might be gone away while we unlocked the mutex. */ -static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev) -{ - struct b43_wl *wl; - struct b43_wldev *orig_dev; - u32 mask; - int queue_num; - - if (!dev) - return NULL; - wl = dev->wl; -redo: - if (!dev || b43_status(dev) < B43_STAT_STARTED) - return dev; - - /* Cancel work. Unlock to avoid deadlocks. */ - mutex_unlock(&wl->mutex); - cancel_delayed_work_sync(&dev->periodic_work); - cancel_work_sync(&wl->tx_work); - b43_leds_stop(dev); - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (!dev || b43_status(dev) < B43_STAT_STARTED) { - /* Whoops, aliens ate up the device while we were unlocked. */ - return dev; - } - - /* Disable interrupts on the device. */ - b43_set_status(dev, B43_STAT_INITIALIZED); - if (b43_bus_host_is_sdio(dev->dev)) { - /* wl->mutex is locked. That is enough. */ - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); - b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ - } else { - spin_lock_irq(&wl->hardirq_lock); - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); - b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ - spin_unlock_irq(&wl->hardirq_lock); - } - /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ - orig_dev = dev; - mutex_unlock(&wl->mutex); - if (b43_bus_host_is_sdio(dev->dev)) { - b43_sdio_free_irq(dev); - } else { - synchronize_irq(dev->dev->irq); - free_irq(dev->dev->irq, dev); - } - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (!dev) - return dev; - if (dev != orig_dev) { - if (b43_status(dev) >= B43_STAT_STARTED) - goto redo; - return dev; - } - mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); - B43_WARN_ON(mask != 0xFFFFFFFF && mask); - - /* Drain all TX queues. */ - for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { - while (skb_queue_len(&wl->tx_queue[queue_num])) { - struct sk_buff *skb; - - skb = skb_dequeue(&wl->tx_queue[queue_num]); - ieee80211_free_txskb(wl->hw, skb); - } - } - - b43_mac_suspend(dev); - b43_leds_exit(dev); - b43dbg(wl, "Wireless interface stopped\n"); - - return dev; -} - -/* Locking: wl->mutex */ -static int b43_wireless_core_start(struct b43_wldev *dev) -{ - int err; - - B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); - - drain_txstatus_queue(dev); - if (b43_bus_host_is_sdio(dev->dev)) { - err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); - if (err) { - b43err(dev->wl, "Cannot request SDIO IRQ\n"); - goto out; - } - } else { - err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler, - b43_interrupt_thread_handler, - IRQF_SHARED, KBUILD_MODNAME, dev); - if (err) { - b43err(dev->wl, "Cannot request IRQ-%d\n", - dev->dev->irq); - goto out; - } - } - - /* We are ready to run. */ - ieee80211_wake_queues(dev->wl->hw); - b43_set_status(dev, B43_STAT_STARTED); - - /* Start data flow (TX/RX). */ - b43_mac_enable(dev); - b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask); - - /* Start maintenance work */ - b43_periodic_tasks_setup(dev); - - b43_leds_init(dev); - - b43dbg(dev->wl, "Wireless interface started\n"); -out: - return err; -} - -static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type) -{ - switch (phy_type) { - case B43_PHYTYPE_A: - return "A"; - case B43_PHYTYPE_B: - return "B"; - case B43_PHYTYPE_G: - return "G"; - case B43_PHYTYPE_N: - return "N"; - case B43_PHYTYPE_LP: - return "LP"; - case B43_PHYTYPE_SSLPN: - return "SSLPN"; - case B43_PHYTYPE_HT: - return "HT"; - case B43_PHYTYPE_LCN: - return "LCN"; - case B43_PHYTYPE_LCNXN: - return "LCNXN"; - case B43_PHYTYPE_LCN40: - return "LCN40"; - case B43_PHYTYPE_AC: - return "AC"; - } - return "UNKNOWN"; -} - -/* Get PHY and RADIO versioning numbers */ -static int b43_phy_versioning(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - const u8 core_rev = dev->dev->core_rev; - u32 tmp; - u8 analog_type; - u8 phy_type; - u8 phy_rev; - u16 radio_manuf; - u16 radio_id; - u16 radio_rev; - u8 radio_ver; - int unsupported = 0; - - /* Get PHY versioning */ - tmp = b43_read16(dev, B43_MMIO_PHY_VER); - analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; - phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; - phy_rev = (tmp & B43_PHYVER_VERSION); - - /* LCNXN is continuation of N which run out of revisions */ - if (phy_type == B43_PHYTYPE_LCNXN) { - phy_type = B43_PHYTYPE_N; - phy_rev += 16; - } - - switch (phy_type) { -#ifdef CONFIG_B43_PHY_G - case B43_PHYTYPE_G: - if (phy_rev > 9) - unsupported = 1; - break; -#endif -#ifdef CONFIG_B43_PHY_N - case B43_PHYTYPE_N: - if (phy_rev >= 19) - unsupported = 1; - break; -#endif -#ifdef CONFIG_B43_PHY_LP - case B43_PHYTYPE_LP: - if (phy_rev > 2) - unsupported = 1; - break; -#endif -#ifdef CONFIG_B43_PHY_HT - case B43_PHYTYPE_HT: - if (phy_rev > 1) - unsupported = 1; - break; -#endif -#ifdef CONFIG_B43_PHY_LCN - case B43_PHYTYPE_LCN: - if (phy_rev > 1) - unsupported = 1; - break; -#endif -#ifdef CONFIG_B43_PHY_AC - case B43_PHYTYPE_AC: - if (phy_rev > 1) - unsupported = 1; - break; -#endif - default: - unsupported = 1; - } - if (unsupported) { - b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n", - analog_type, phy_type, b43_phy_name(dev, phy_type), - phy_rev); - return -EOPNOTSUPP; - } - b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n", - analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev); - - /* Get RADIO versioning */ - if (core_rev == 40 || core_rev == 42) { - radio_manuf = 0x17F; - - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0); - radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA); - - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1); - radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA); - - radio_ver = 0; /* Is there version somewhere? */ - } else if (core_rev >= 24) { - u16 radio24[3]; - - for (tmp = 0; tmp < 3; tmp++) { - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp); - radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); - } - - radio_manuf = 0x17F; - radio_id = (radio24[2] << 8) | radio24[1]; - radio_rev = (radio24[0] & 0xF); - radio_ver = (radio24[0] & 0xF0) >> 4; - } else { - if (dev->dev->chip_id == 0x4317) { - if (dev->dev->chip_rev == 0) - tmp = 0x3205017F; - else if (dev->dev->chip_rev == 1) - tmp = 0x4205017F; - else - tmp = 0x5205017F; - } else { - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, - B43_RADIOCTL_ID); - tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, - B43_RADIOCTL_ID); - tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; - } - radio_manuf = (tmp & 0x00000FFF); - radio_id = (tmp & 0x0FFFF000) >> 12; - radio_rev = (tmp & 0xF0000000) >> 28; - radio_ver = 0; /* Probably not available on old hw */ - } - - if (radio_manuf != 0x17F /* Broadcom */) - unsupported = 1; - switch (phy_type) { - case B43_PHYTYPE_A: - if (radio_id != 0x2060) - unsupported = 1; - if (radio_rev != 1) - unsupported = 1; - if (radio_manuf != 0x17F) - unsupported = 1; - break; - case B43_PHYTYPE_B: - if ((radio_id & 0xFFF0) != 0x2050) - unsupported = 1; - break; - case B43_PHYTYPE_G: - if (radio_id != 0x2050) - unsupported = 1; - break; - case B43_PHYTYPE_N: - if (radio_id != 0x2055 && radio_id != 0x2056 && - radio_id != 0x2057) - unsupported = 1; - if (radio_id == 0x2057 && - !(radio_rev == 9 || radio_rev == 14)) - unsupported = 1; - break; - case B43_PHYTYPE_LP: - if (radio_id != 0x2062 && radio_id != 0x2063) - unsupported = 1; - break; - case B43_PHYTYPE_HT: - if (radio_id != 0x2059) - unsupported = 1; - break; - case B43_PHYTYPE_LCN: - if (radio_id != 0x2064) - unsupported = 1; - break; - case B43_PHYTYPE_AC: - if (radio_id != 0x2069) - unsupported = 1; - break; - default: - B43_WARN_ON(1); - } - if (unsupported) { - b43err(dev->wl, - "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n", - radio_manuf, radio_id, radio_rev, radio_ver); - return -EOPNOTSUPP; - } - b43info(dev->wl, - "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n", - radio_manuf, radio_id, radio_rev, radio_ver); - - /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */ - phy->radio_manuf = radio_manuf; - phy->radio_ver = radio_id; - phy->radio_rev = radio_rev; - - phy->analog = analog_type; - phy->type = phy_type; - phy->rev = phy_rev; - - return 0; -} - -static void setup_struct_phy_for_init(struct b43_wldev *dev, - struct b43_phy *phy) -{ - phy->hardware_power_control = !!modparam_hwpctl; - phy->next_txpwr_check_time = jiffies; - /* PHY TX errors counter. */ - atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); - -#if B43_DEBUG - phy->phy_locked = false; - phy->radio_locked = false; -#endif -} - -static void setup_struct_wldev_for_init(struct b43_wldev *dev) -{ - dev->dfq_valid = false; - - /* Assume the radio is enabled. If it's not enabled, the state will - * immediately get fixed on the first periodic work run. */ - dev->radio_hw_enable = true; - - /* Stats */ - memset(&dev->stats, 0, sizeof(dev->stats)); - - setup_struct_phy_for_init(dev, &dev->phy); - - /* IRQ related flags */ - dev->irq_reason = 0; - memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); - dev->irq_mask = B43_IRQ_MASKTEMPLATE; - if (b43_modparam_verbose < B43_VERBOSITY_DEBUG) - dev->irq_mask &= ~B43_IRQ_PHY_TXERR; - - dev->mac_suspended = 1; - - /* Noise calculation context */ - memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); -} - -static void b43_bluetooth_coext_enable(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - u64 hf; - - if (!modparam_btcoex) - return; - if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) - return; - if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) - return; - - hf = b43_hf_read(dev); - if (sprom->boardflags_lo & B43_BFL_BTCMOD) - hf |= B43_HF_BTCOEXALT; - else - hf |= B43_HF_BTCOEX; - b43_hf_write(dev, hf); -} - -static void b43_bluetooth_coext_disable(struct b43_wldev *dev) -{ - if (!modparam_btcoex) - return; - //TODO -} - -static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) -{ - struct ssb_bus *bus; - u32 tmp; - -#ifdef CONFIG_B43_SSB - if (dev->dev->bus_type != B43_BUS_SSB) - return; -#else - return; -#endif - - bus = dev->dev->sdev->bus; - - if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || - (bus->chip_id == 0x4312)) { - tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO); - tmp &= ~SSB_IMCFGLO_REQTO; - tmp &= ~SSB_IMCFGLO_SERTO; - tmp |= 0x3; - ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp); - ssb_commit_settings(bus); - } -} - -static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) -{ - u16 pu_delay; - - /* The time value is in microseconds. */ - if (dev->phy.type == B43_PHYTYPE_A) - pu_delay = 3700; - else - pu_delay = 1050; - if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle) - pu_delay = 500; - if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) - pu_delay = max(pu_delay, (u16)2400); - - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); -} - -/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ -static void b43_set_pretbtt(struct b43_wldev *dev) -{ - u16 pretbtt; - - /* The time value is in microseconds. */ - if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) { - pretbtt = 2; - } else { - if (dev->phy.type == B43_PHYTYPE_A) - pretbtt = 120; - else - pretbtt = 250; - } - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); - b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); -} - -/* Shutdown a wireless core */ -/* Locking: wl->mutex */ -static void b43_wireless_core_exit(struct b43_wldev *dev) -{ - B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED); - if (!dev || b43_status(dev) != B43_STAT_INITIALIZED) - return; - - b43_set_status(dev, B43_STAT_UNINIT); - - /* Stop the microcode PSM. */ - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN, - B43_MACCTL_PSM_JMP0); - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_host_pci_down(dev->dev->bdev->bus); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - /* TODO */ - break; -#endif - } - - b43_dma_free(dev); - b43_pio_free(dev); - b43_chip_exit(dev); - dev->phy.ops->switch_analog(dev, 0); - if (dev->wl->current_beacon) { - dev_kfree_skb_any(dev->wl->current_beacon); - dev->wl->current_beacon = NULL; - } - - b43_device_disable(dev, 0); - b43_bus_may_powerdown(dev); -} - -/* Initialize a wireless core */ -static int b43_wireless_core_init(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - int err; - u64 hf; - - B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); - - err = b43_bus_powerup(dev, 0); - if (err) - goto out; - if (!b43_device_is_enabled(dev)) - b43_wireless_core_reset(dev, phy->gmode); - - /* Reset all data structures. */ - setup_struct_wldev_for_init(dev); - phy->ops->prepare_structs(dev); - - /* Enable IRQ routing to this device. */ - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_host_pci_irq_ctl(dev->dev->bdev->bus, - dev->dev->bdev, true); - bcma_host_pci_up(dev->dev->bdev->bus); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore, - dev->dev->sdev); - break; -#endif - } - - b43_imcfglo_timeouts_workaround(dev); - b43_bluetooth_coext_disable(dev); - if (phy->ops->prepare_hardware) { - err = phy->ops->prepare_hardware(dev); - if (err) - goto err_busdown; - } - err = b43_chip_init(dev); - if (err) - goto err_busdown; - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_WLCOREREV, dev->dev->core_rev); - hf = b43_hf_read(dev); - if (phy->type == B43_PHYTYPE_G) { - hf |= B43_HF_SYMW; - if (phy->rev == 1) - hf |= B43_HF_GDCW; - if (sprom->boardflags_lo & B43_BFL_PACTRL) - hf |= B43_HF_OFDMPABOOST; - } - if (phy->radio_ver == 0x2050) { - if (phy->radio_rev == 6) - hf |= B43_HF_4318TSSI; - if (phy->radio_rev < 6) - hf |= B43_HF_VCORECALC; - } - if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) - hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ -#if defined(CONFIG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE) - if (dev->dev->bus_type == B43_BUS_SSB && - dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI && - dev->dev->sdev->bus->pcicore.dev->id.revision <= 10) - hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ -#endif - hf &= ~B43_HF_SKCFPUP; - b43_hf_write(dev, hf); - - /* tell the ucode MAC capabilities */ - if (dev->dev->core_rev >= 13) { - u32 mac_hw_cap = b43_read32(dev, B43_MMIO_MAC_HW_CAP); - - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_L, - mac_hw_cap & 0xffff); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_MACHW_H, - (mac_hw_cap >> 16) & 0xffff); - } - - b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, - B43_DEFAULT_LONG_RETRY_LIMIT); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); - - /* Disable sending probe responses from firmware. - * Setting the MaxTime to one usec will always trigger - * a timeout, so we never send any probe resp. - * A timeout of zero is infinite. */ - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); - - b43_rate_memory_init(dev); - b43_set_phytxctl_defaults(dev); - - /* Minimum Contention Window */ - if (phy->type == B43_PHYTYPE_B) - b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); - else - b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); - /* Maximum Contention Window */ - b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); - - /* write phytype and phyvers */ - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYTYPE, phy->type); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PHYVER, phy->rev); - - if (b43_bus_host_is_pcmcia(dev->dev) || - b43_bus_host_is_sdio(dev->dev)) { - dev->__using_pio_transfers = true; - err = b43_pio_init(dev); - } else if (dev->use_pio) { - b43warn(dev->wl, "Forced PIO by use_pio module parameter. " - "This should not be needed and will result in lower " - "performance.\n"); - dev->__using_pio_transfers = true; - err = b43_pio_init(dev); - } else { - dev->__using_pio_transfers = false; - err = b43_dma_init(dev); - } - if (err) - goto err_chip_exit; - b43_qos_init(dev); - b43_set_synth_pu_delay(dev, 1); - b43_bluetooth_coext_enable(dev); - - b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); - b43_upload_card_macaddress(dev); - b43_security_init(dev); - - ieee80211_wake_queues(dev->wl->hw); - - b43_set_status(dev, B43_STAT_INITIALIZED); - -out: - return err; - -err_chip_exit: - b43_chip_exit(dev); -err_busdown: - b43_bus_may_powerdown(dev); - B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); - return err; -} - -static int b43_op_add_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - int err = -EOPNOTSUPP; - - /* TODO: allow WDS/AP devices to coexist */ - - if (vif->type != NL80211_IFTYPE_AP && - vif->type != NL80211_IFTYPE_MESH_POINT && - vif->type != NL80211_IFTYPE_STATION && - vif->type != NL80211_IFTYPE_WDS && - vif->type != NL80211_IFTYPE_ADHOC) - return -EOPNOTSUPP; - - mutex_lock(&wl->mutex); - if (wl->operating) - goto out_mutex_unlock; - - b43dbg(wl, "Adding Interface type %d\n", vif->type); - - dev = wl->current_dev; - wl->operating = true; - wl->vif = vif; - wl->if_type = vif->type; - memcpy(wl->mac_addr, vif->addr, ETH_ALEN); - - b43_adjust_opmode(dev); - b43_set_pretbtt(dev); - b43_set_synth_pu_delay(dev, 0); - b43_upload_card_macaddress(dev); - - err = 0; - out_mutex_unlock: - mutex_unlock(&wl->mutex); - - if (err == 0) - b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0); - - return err; -} - -static void b43_op_remove_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - - b43dbg(wl, "Removing Interface type %d\n", vif->type); - - mutex_lock(&wl->mutex); - - B43_WARN_ON(!wl->operating); - B43_WARN_ON(wl->vif != vif); - wl->vif = NULL; - - wl->operating = false; - - b43_adjust_opmode(dev); - eth_zero_addr(wl->mac_addr); - b43_upload_card_macaddress(dev); - - mutex_unlock(&wl->mutex); -} - -static int b43_op_start(struct ieee80211_hw *hw) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - int did_init = 0; - int err = 0; - - /* Kill all old instance specific information to make sure - * the card won't use it in the short timeframe between start - * and mac80211 reconfiguring it. */ - eth_zero_addr(wl->bssid); - eth_zero_addr(wl->mac_addr); - wl->filter_flags = 0; - wl->radiotap_enabled = false; - b43_qos_clear(wl); - wl->beacon0_uploaded = false; - wl->beacon1_uploaded = false; - wl->beacon_templates_virgin = true; - wl->radio_enabled = true; - - mutex_lock(&wl->mutex); - - if (b43_status(dev) < B43_STAT_INITIALIZED) { - err = b43_wireless_core_init(dev); - if (err) - goto out_mutex_unlock; - did_init = 1; - } - - if (b43_status(dev) < B43_STAT_STARTED) { - err = b43_wireless_core_start(dev); - if (err) { - if (did_init) - b43_wireless_core_exit(dev); - goto out_mutex_unlock; - } - } - - /* XXX: only do if device doesn't support rfkill irq */ - wiphy_rfkill_start_polling(hw->wiphy); - - out_mutex_unlock: - mutex_unlock(&wl->mutex); - - /* - * Configuration may have been overwritten during initialization. - * Reload the configuration, but only if initialization was - * successful. Reloading the configuration after a failed init - * may hang the system. - */ - if (!err) - b43_op_config(hw, ~0); - - return err; -} - -static void b43_op_stop(struct ieee80211_hw *hw) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - - cancel_work_sync(&(wl->beacon_update_trigger)); - - if (!dev) - goto out; - - mutex_lock(&wl->mutex); - if (b43_status(dev) >= B43_STAT_STARTED) { - dev = b43_wireless_core_stop(dev); - if (!dev) - goto out_unlock; - } - b43_wireless_core_exit(dev); - wl->radio_enabled = false; - -out_unlock: - mutex_unlock(&wl->mutex); -out: - cancel_work_sync(&(wl->txpower_adjust_work)); -} - -static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, bool set) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - - b43_update_templates(wl); - - return 0; -} - -static void b43_op_sta_notify(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - enum sta_notify_cmd notify_cmd, - struct ieee80211_sta *sta) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - - B43_WARN_ON(!vif || wl->vif != vif); -} - -static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - const u8 *mac_addr) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { - /* Disable CFP update during scan on other channels. */ - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP); - } - mutex_unlock(&wl->mutex); -} - -static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) { - /* Re-enable CFP update. */ - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP); - } - mutex_unlock(&wl->mutex); -} - -static int b43_op_get_survey(struct ieee80211_hw *hw, int idx, - struct survey_info *survey) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - struct ieee80211_conf *conf = &hw->conf; - - if (idx != 0) - return -ENOENT; - - survey->channel = conf->chandef.chan; - survey->filled = SURVEY_INFO_NOISE_DBM; - survey->noise = dev->stats.link_noise; - - return 0; -} - -static const struct ieee80211_ops b43_hw_ops = { - .tx = b43_op_tx, - .conf_tx = b43_op_conf_tx, - .add_interface = b43_op_add_interface, - .remove_interface = b43_op_remove_interface, - .config = b43_op_config, - .bss_info_changed = b43_op_bss_info_changed, - .configure_filter = b43_op_configure_filter, - .set_key = b43_op_set_key, - .update_tkip_key = b43_op_update_tkip_key, - .get_stats = b43_op_get_stats, - .get_tsf = b43_op_get_tsf, - .set_tsf = b43_op_set_tsf, - .start = b43_op_start, - .stop = b43_op_stop, - .set_tim = b43_op_beacon_set_tim, - .sta_notify = b43_op_sta_notify, - .sw_scan_start = b43_op_sw_scan_start_notifier, - .sw_scan_complete = b43_op_sw_scan_complete_notifier, - .get_survey = b43_op_get_survey, - .rfkill_poll = b43_rfkill_poll, -}; - -/* Hard-reset the chip. Do not call this directly. - * Use b43_controller_restart() - */ -static void b43_chip_reset(struct work_struct *work) -{ - struct b43_wldev *dev = - container_of(work, struct b43_wldev, restart_work); - struct b43_wl *wl = dev->wl; - int err = 0; - int prev_status; - - mutex_lock(&wl->mutex); - - prev_status = b43_status(dev); - /* Bring the device down... */ - if (prev_status >= B43_STAT_STARTED) { - dev = b43_wireless_core_stop(dev); - if (!dev) { - err = -ENODEV; - goto out; - } - } - if (prev_status >= B43_STAT_INITIALIZED) - b43_wireless_core_exit(dev); - - /* ...and up again. */ - if (prev_status >= B43_STAT_INITIALIZED) { - err = b43_wireless_core_init(dev); - if (err) - goto out; - } - if (prev_status >= B43_STAT_STARTED) { - err = b43_wireless_core_start(dev); - if (err) { - b43_wireless_core_exit(dev); - goto out; - } - } -out: - if (err) - wl->current_dev = NULL; /* Failed to init the dev. */ - mutex_unlock(&wl->mutex); - - if (err) { - b43err(wl, "Controller restart FAILED\n"); - return; - } - - /* reload configuration */ - b43_op_config(wl->hw, ~0); - if (wl->vif) - b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0); - - b43info(wl, "Controller restarted\n"); -} - -static int b43_setup_bands(struct b43_wldev *dev, - bool have_2ghz_phy, bool have_5ghz_phy) -{ - struct ieee80211_hw *hw = dev->wl->hw; - struct b43_phy *phy = &dev->phy; - bool limited_2g; - bool limited_5g; - - /* We don't support all 2 GHz channels on some devices */ - limited_2g = phy->radio_ver == 0x2057 && - (phy->radio_rev == 9 || phy->radio_rev == 14); - limited_5g = phy->radio_ver == 0x2057 && - phy->radio_rev == 9; - - if (have_2ghz_phy) - hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ? - &b43_band_2ghz_limited : &b43_band_2GHz; - if (dev->phy.type == B43_PHYTYPE_N) { - if (have_5ghz_phy) - hw->wiphy->bands[IEEE80211_BAND_5GHZ] = limited_5g ? - &b43_band_5GHz_nphy_limited : - &b43_band_5GHz_nphy; - } else { - if (have_5ghz_phy) - hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; - } - - dev->phy.supports_2ghz = have_2ghz_phy; - dev->phy.supports_5ghz = have_5ghz_phy; - - return 0; -} - -static void b43_wireless_core_detach(struct b43_wldev *dev) -{ - /* We release firmware that late to not be required to re-request - * is all the time when we reinit the core. */ - b43_release_firmware(dev); - b43_phy_free(dev); -} - -static void b43_supported_bands(struct b43_wldev *dev, bool *have_2ghz_phy, - bool *have_5ghz_phy) -{ - u16 dev_id = 0; - -#ifdef CONFIG_B43_BCMA - if (dev->dev->bus_type == B43_BUS_BCMA && - dev->dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI) - dev_id = dev->dev->bdev->bus->host_pci->device; -#endif -#ifdef CONFIG_B43_SSB - if (dev->dev->bus_type == B43_BUS_SSB && - dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) - dev_id = dev->dev->sdev->bus->host_pci->device; -#endif - /* Override with SPROM value if available */ - if (dev->dev->bus_sprom->dev_id) - dev_id = dev->dev->bus_sprom->dev_id; - - /* Note: below IDs can be "virtual" (not maching e.g. real PCI ID) */ - switch (dev_id) { - case 0x4324: /* BCM4306 */ - case 0x4312: /* BCM4311 */ - case 0x4319: /* BCM4318 */ - case 0x4328: /* BCM4321 */ - case 0x432b: /* BCM4322 */ - case 0x4350: /* BCM43222 */ - case 0x4353: /* BCM43224 */ - case 0x0576: /* BCM43224 */ - case 0x435f: /* BCM6362 */ - case 0x4331: /* BCM4331 */ - case 0x4359: /* BCM43228 */ - case 0x43a0: /* BCM4360 */ - case 0x43b1: /* BCM4352 */ - /* Dual band devices */ - *have_2ghz_phy = true; - *have_5ghz_phy = true; - return; - case 0x4321: /* BCM4306 */ - /* There are 14e4:4321 PCI devs with 2.4 GHz BCM4321 (N-PHY) */ - if (dev->phy.type != B43_PHYTYPE_G) - break; - /* fall through */ - case 0x4313: /* BCM4311 */ - case 0x431a: /* BCM4318 */ - case 0x432a: /* BCM4321 */ - case 0x432d: /* BCM4322 */ - case 0x4352: /* BCM43222 */ - case 0x435a: /* BCM43228 */ - case 0x4333: /* BCM4331 */ - case 0x43a2: /* BCM4360 */ - case 0x43b3: /* BCM4352 */ - /* 5 GHz only devices */ - *have_2ghz_phy = false; - *have_5ghz_phy = true; - return; - } - - /* As a fallback, try to guess using PHY type */ - switch (dev->phy.type) { - case B43_PHYTYPE_A: - *have_2ghz_phy = false; - *have_5ghz_phy = true; - return; - case B43_PHYTYPE_G: - case B43_PHYTYPE_N: - case B43_PHYTYPE_LP: - case B43_PHYTYPE_HT: - case B43_PHYTYPE_LCN: - *have_2ghz_phy = true; - *have_5ghz_phy = false; - return; - } - - B43_WARN_ON(1); -} - -static int b43_wireless_core_attach(struct b43_wldev *dev) -{ - struct b43_wl *wl = dev->wl; - struct b43_phy *phy = &dev->phy; - int err; - u32 tmp; - bool have_2ghz_phy = false, have_5ghz_phy = false; - - /* Do NOT do any device initialization here. - * Do it in wireless_core_init() instead. - * This function is for gathering basic information about the HW, only. - * Also some structs may be set up here. But most likely you want to have - * that in core_init(), too. - */ - - err = b43_bus_powerup(dev, 0); - if (err) { - b43err(wl, "Bus powerup failed\n"); - goto out; - } - - phy->do_full_init = true; - - /* Try to guess supported bands for the first init needs */ - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST); - have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY); - have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - if (dev->dev->core_rev >= 5) { - tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH); - have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY); - have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY); - } else - B43_WARN_ON(1); - break; -#endif - } - - dev->phy.gmode = have_2ghz_phy; - b43_wireless_core_reset(dev, dev->phy.gmode); - - /* Get the PHY type. */ - err = b43_phy_versioning(dev); - if (err) - goto err_powerdown; - - /* Get real info about supported bands */ - b43_supported_bands(dev, &have_2ghz_phy, &have_5ghz_phy); - - /* We don't support 5 GHz on some PHYs yet */ - if (have_5ghz_phy) { - switch (dev->phy.type) { - case B43_PHYTYPE_A: - case B43_PHYTYPE_G: - case B43_PHYTYPE_LP: - case B43_PHYTYPE_HT: - b43warn(wl, "5 GHz band is unsupported on this PHY\n"); - have_5ghz_phy = false; - } - } - - if (!have_2ghz_phy && !have_5ghz_phy) { - b43err(wl, "b43 can't support any band on this device\n"); - err = -EOPNOTSUPP; - goto err_powerdown; - } - - err = b43_phy_allocate(dev); - if (err) - goto err_powerdown; - - dev->phy.gmode = have_2ghz_phy; - b43_wireless_core_reset(dev, dev->phy.gmode); - - err = b43_validate_chipaccess(dev); - if (err) - goto err_phy_free; - err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); - if (err) - goto err_phy_free; - - /* Now set some default "current_dev" */ - if (!wl->current_dev) - wl->current_dev = dev; - INIT_WORK(&dev->restart_work, b43_chip_reset); - - dev->phy.ops->switch_analog(dev, 0); - b43_device_disable(dev, 0); - b43_bus_may_powerdown(dev); - -out: - return err; - -err_phy_free: - b43_phy_free(dev); -err_powerdown: - b43_bus_may_powerdown(dev); - return err; -} - -static void b43_one_core_detach(struct b43_bus_dev *dev) -{ - struct b43_wldev *wldev; - struct b43_wl *wl; - - /* Do not cancel ieee80211-workqueue based work here. - * See comment in b43_remove(). */ - - wldev = b43_bus_get_wldev(dev); - wl = wldev->wl; - b43_debugfs_remove_device(wldev); - b43_wireless_core_detach(wldev); - list_del(&wldev->list); - b43_bus_set_wldev(dev, NULL); - kfree(wldev); -} - -static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl) -{ - struct b43_wldev *wldev; - int err = -ENOMEM; - - wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); - if (!wldev) - goto out; - - wldev->use_pio = b43_modparam_pio; - wldev->dev = dev; - wldev->wl = wl; - b43_set_status(wldev, B43_STAT_UNINIT); - wldev->bad_frames_preempt = modparam_bad_frames_preempt; - INIT_LIST_HEAD(&wldev->list); - - err = b43_wireless_core_attach(wldev); - if (err) - goto err_kfree_wldev; - - b43_bus_set_wldev(dev, wldev); - b43_debugfs_add_device(wldev); - - out: - return err; - - err_kfree_wldev: - kfree(wldev); - return err; -} - -#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ - (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ - (pdev->device == _device) && \ - (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ - (pdev->subsystem_device == _subdevice) ) - -#ifdef CONFIG_B43_SSB -static void b43_sprom_fixup(struct ssb_bus *bus) -{ - struct pci_dev *pdev; - - /* boardflags workarounds */ - if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && - bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74) - bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; - if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && - bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40) - bus->sprom.boardflags_lo |= B43_BFL_PACTRL; - if (bus->bustype == SSB_BUSTYPE_PCI) { - pdev = bus->host_pci; - if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || - IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) || - IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) || - IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || - IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) || - IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) || - IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010)) - bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; - } -} - -static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl) -{ - struct ieee80211_hw *hw = wl->hw; - - ssb_set_devtypedata(dev->sdev, NULL); - ieee80211_free_hw(hw); -} -#endif - -static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev) -{ - struct ssb_sprom *sprom = dev->bus_sprom; - struct ieee80211_hw *hw; - struct b43_wl *wl; - char chip_name[6]; - int queue_num; - - hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); - if (!hw) { - b43err(NULL, "Could not allocate ieee80211 device\n"); - return ERR_PTR(-ENOMEM); - } - wl = hw_to_b43_wl(hw); - - /* fill hw info */ - ieee80211_hw_set(hw, RX_INCLUDES_FCS); - ieee80211_hw_set(hw, SIGNAL_DBM); - - hw->wiphy->interface_modes = - BIT(NL80211_IFTYPE_AP) | - BIT(NL80211_IFTYPE_MESH_POINT) | - BIT(NL80211_IFTYPE_STATION) | - BIT(NL80211_IFTYPE_WDS) | - BIT(NL80211_IFTYPE_ADHOC); - - hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; - - wl->hw_registred = false; - hw->max_rates = 2; - SET_IEEE80211_DEV(hw, dev->dev); - if (is_valid_ether_addr(sprom->et1mac)) - SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); - else - SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); - - /* Initialize struct b43_wl */ - wl->hw = hw; - mutex_init(&wl->mutex); - spin_lock_init(&wl->hardirq_lock); - spin_lock_init(&wl->beacon_lock); - INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); - INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work); - INIT_WORK(&wl->tx_work, b43_tx_work); - - /* Initialize queues and flags. */ - for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) { - skb_queue_head_init(&wl->tx_queue[queue_num]); - wl->tx_queue_stopped[queue_num] = 0; - } - - snprintf(chip_name, ARRAY_SIZE(chip_name), - (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id); - b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name, - dev->core_rev); - return wl; -} - -#ifdef CONFIG_B43_BCMA -static int b43_bcma_probe(struct bcma_device *core) -{ - struct b43_bus_dev *dev; - struct b43_wl *wl; - int err; - - if (!modparam_allhwsupport && - (core->id.rev == 0x17 || core->id.rev == 0x18)) { - pr_err("Support for cores revisions 0x17 and 0x18 disabled by module param allhwsupport=0. Try b43.allhwsupport=1\n"); - return -ENOTSUPP; - } - - dev = b43_bus_dev_bcma_init(core); - if (!dev) - return -ENODEV; - - wl = b43_wireless_init(dev); - if (IS_ERR(wl)) { - err = PTR_ERR(wl); - goto bcma_out; - } - - err = b43_one_core_attach(dev, wl); - if (err) - goto bcma_err_wireless_exit; - - /* setup and start work to load firmware */ - INIT_WORK(&wl->firmware_load, b43_request_firmware); - schedule_work(&wl->firmware_load); - -bcma_out: - return err; - -bcma_err_wireless_exit: - ieee80211_free_hw(wl->hw); - return err; -} - -static void b43_bcma_remove(struct bcma_device *core) -{ - struct b43_wldev *wldev = bcma_get_drvdata(core); - struct b43_wl *wl = wldev->wl; - - /* We must cancel any work here before unregistering from ieee80211, - * as the ieee80211 unreg will destroy the workqueue. */ - cancel_work_sync(&wldev->restart_work); - cancel_work_sync(&wl->firmware_load); - - B43_WARN_ON(!wl); - if (!wldev->fw.ucode.data) - return; /* NULL if firmware never loaded */ - if (wl->current_dev == wldev && wl->hw_registred) { - b43_leds_stop(wldev); - ieee80211_unregister_hw(wl->hw); - } - - b43_one_core_detach(wldev->dev); - - /* Unregister HW RNG driver */ - b43_rng_exit(wl); - - b43_leds_unregister(wl); - - ieee80211_free_hw(wl->hw); -} - -static struct bcma_driver b43_bcma_driver = { - .name = KBUILD_MODNAME, - .id_table = b43_bcma_tbl, - .probe = b43_bcma_probe, - .remove = b43_bcma_remove, -}; -#endif - -#ifdef CONFIG_B43_SSB -static -int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id) -{ - struct b43_bus_dev *dev; - struct b43_wl *wl; - int err; - - dev = b43_bus_dev_ssb_init(sdev); - if (!dev) - return -ENOMEM; - - wl = ssb_get_devtypedata(sdev); - if (wl) { - b43err(NULL, "Dual-core devices are not supported\n"); - err = -ENOTSUPP; - goto err_ssb_kfree_dev; - } - - b43_sprom_fixup(sdev->bus); - - wl = b43_wireless_init(dev); - if (IS_ERR(wl)) { - err = PTR_ERR(wl); - goto err_ssb_kfree_dev; - } - ssb_set_devtypedata(sdev, wl); - B43_WARN_ON(ssb_get_devtypedata(sdev) != wl); - - err = b43_one_core_attach(dev, wl); - if (err) - goto err_ssb_wireless_exit; - - /* setup and start work to load firmware */ - INIT_WORK(&wl->firmware_load, b43_request_firmware); - schedule_work(&wl->firmware_load); - - return err; - -err_ssb_wireless_exit: - b43_wireless_exit(dev, wl); -err_ssb_kfree_dev: - kfree(dev); - return err; -} - -static void b43_ssb_remove(struct ssb_device *sdev) -{ - struct b43_wl *wl = ssb_get_devtypedata(sdev); - struct b43_wldev *wldev = ssb_get_drvdata(sdev); - struct b43_bus_dev *dev = wldev->dev; - - /* We must cancel any work here before unregistering from ieee80211, - * as the ieee80211 unreg will destroy the workqueue. */ - cancel_work_sync(&wldev->restart_work); - cancel_work_sync(&wl->firmware_load); - - B43_WARN_ON(!wl); - if (!wldev->fw.ucode.data) - return; /* NULL if firmware never loaded */ - if (wl->current_dev == wldev && wl->hw_registred) { - b43_leds_stop(wldev); - ieee80211_unregister_hw(wl->hw); - } - - b43_one_core_detach(dev); - - /* Unregister HW RNG driver */ - b43_rng_exit(wl); - - b43_leds_unregister(wl); - b43_wireless_exit(dev, wl); -} - -static struct ssb_driver b43_ssb_driver = { - .name = KBUILD_MODNAME, - .id_table = b43_ssb_tbl, - .probe = b43_ssb_probe, - .remove = b43_ssb_remove, -}; -#endif /* CONFIG_B43_SSB */ - -/* Perform a hardware reset. This can be called from any context. */ -void b43_controller_restart(struct b43_wldev *dev, const char *reason) -{ - /* Must avoid requeueing, if we are in shutdown. */ - if (b43_status(dev) < B43_STAT_INITIALIZED) - return; - b43info(dev->wl, "Controller RESET (%s) ...\n", reason); - ieee80211_queue_work(dev->wl->hw, &dev->restart_work); -} - -static void b43_print_driverinfo(void) -{ - const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", - *feat_leds = "", *feat_sdio = ""; - -#ifdef CONFIG_B43_PCI_AUTOSELECT - feat_pci = "P"; -#endif -#ifdef CONFIG_B43_PCMCIA - feat_pcmcia = "M"; -#endif -#ifdef CONFIG_B43_PHY_N - feat_nphy = "N"; -#endif -#ifdef CONFIG_B43_LEDS - feat_leds = "L"; -#endif -#ifdef CONFIG_B43_SDIO - feat_sdio = "S"; -#endif - printk(KERN_INFO "Broadcom 43xx driver loaded " - "[ Features: %s%s%s%s%s ]\n", - feat_pci, feat_pcmcia, feat_nphy, - feat_leds, feat_sdio); -} - -static int __init b43_init(void) -{ - int err; - - b43_debugfs_init(); - err = b43_sdio_init(); - if (err) - goto err_dfs_exit; -#ifdef CONFIG_B43_BCMA - err = bcma_driver_register(&b43_bcma_driver); - if (err) - goto err_sdio_exit; -#endif -#ifdef CONFIG_B43_SSB - err = ssb_driver_register(&b43_ssb_driver); - if (err) - goto err_bcma_driver_exit; -#endif - b43_print_driverinfo(); - - return err; - -#ifdef CONFIG_B43_SSB -err_bcma_driver_exit: -#endif -#ifdef CONFIG_B43_BCMA - bcma_driver_unregister(&b43_bcma_driver); -err_sdio_exit: -#endif - b43_sdio_exit(); -err_dfs_exit: - b43_debugfs_exit(); - return err; -} - -static void __exit b43_exit(void) -{ -#ifdef CONFIG_B43_SSB - ssb_driver_unregister(&b43_ssb_driver); -#endif -#ifdef CONFIG_B43_BCMA - bcma_driver_unregister(&b43_bcma_driver); -#endif - b43_sdio_exit(); - b43_debugfs_exit(); -} - -module_init(b43_init) -module_exit(b43_exit) diff --git a/drivers/net/wireless/b43/main.h b/drivers/net/wireless/b43/main.h deleted file mode 100644 index c46430cc7..000000000 --- a/drivers/net/wireless/b43/main.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - - Broadcom B43 wireless driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Stefano Brivio <stefano.brivio@polimi.it> - Michael Buesch <m@bues.ch> - Danny van Dyk <kugelfang@gentoo.org> - Andreas Jaggi <andreas.jaggi@waterwave.ch> - - Some parts of the code in this file are derived from the ipw2200 - driver Copyright(c) 2003 - 2004 Intel Corporation. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#ifndef B43_MAIN_H_ -#define B43_MAIN_H_ - -#include "b43.h" - -#define P4D_BYT3S(magic, nr_bytes) u8 __p4dding##magic[nr_bytes] -#define P4D_BYTES(line, nr_bytes) P4D_BYT3S(line, nr_bytes) -/* Magic helper macro to pad structures. Ignore those above. It's magic. */ -#define PAD_BYTES(nr_bytes) P4D_BYTES( __LINE__ , (nr_bytes)) - - -extern int b43_modparam_verbose; - -/* Logmessage verbosity levels. Update the b43_modparam_verbose helptext, if - * you add or remove levels. */ -enum b43_verbosity { - B43_VERBOSITY_ERROR, - B43_VERBOSITY_WARN, - B43_VERBOSITY_INFO, - B43_VERBOSITY_DEBUG, - __B43_VERBOSITY_AFTERLAST, /* keep last */ - - B43_VERBOSITY_MAX = __B43_VERBOSITY_AFTERLAST - 1, -#if B43_DEBUG - B43_VERBOSITY_DEFAULT = B43_VERBOSITY_DEBUG, -#else - B43_VERBOSITY_DEFAULT = B43_VERBOSITY_INFO, -#endif -}; - -static inline int b43_is_cck_rate(int rate) -{ - return (rate == B43_CCK_RATE_1MB || - rate == B43_CCK_RATE_2MB || - rate == B43_CCK_RATE_5MB || rate == B43_CCK_RATE_11MB); -} - -static inline int b43_is_ofdm_rate(int rate) -{ - return !b43_is_cck_rate(rate); -} - -u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, - u8 antenna_nr); - -void b43_tsf_read(struct b43_wldev *dev, u64 * tsf); -void b43_tsf_write(struct b43_wldev *dev, u64 tsf); - -u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset); -u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset); -void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value); -void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value); - -u64 b43_hf_read(struct b43_wldev *dev); -void b43_hf_write(struct b43_wldev *dev, u64 value); - -void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on); - -void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode); - -void b43_controller_restart(struct b43_wldev *dev, const char *reason); - -#define B43_PS_ENABLED (1 << 0) /* Force enable hardware power saving */ -#define B43_PS_DISABLED (1 << 1) /* Force disable hardware power saving */ -#define B43_PS_AWAKE (1 << 2) /* Force device awake */ -#define B43_PS_ASLEEP (1 << 3) /* Force device asleep */ -void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags); - -void b43_wireless_core_phy_pll_reset(struct b43_wldev *dev); - -void b43_mac_suspend(struct b43_wldev *dev); -void b43_mac_enable(struct b43_wldev *dev); -void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on); -void b43_mac_switch_freq(struct b43_wldev *dev, u8 spurmode); - - -struct b43_request_fw_context; -int b43_do_request_fw(struct b43_request_fw_context *ctx, const char *name, - struct b43_firmware_file *fw, bool async); -void b43_do_release_fw(struct b43_firmware_file *fw); - -#endif /* B43_MAIN_H_ */ diff --git a/drivers/net/wireless/b43/phy_a.c b/drivers/net/wireless/b43/phy_a.c deleted file mode 100644 index 99c036f5e..000000000 --- a/drivers/net/wireless/b43/phy_a.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11a PHY driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> - Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/slab.h> - -#include "b43.h" -#include "phy_a.h" -#include "phy_common.h" -#include "wa.h" -#include "tables.h" -#include "main.h" - - -/* Get the freq, as it has to be written to the device. */ -static inline u16 channel2freq_a(u8 channel) -{ - B43_WARN_ON(channel > 200); - - return (5000 + 5 * channel); -} - -static inline u16 freq_r3A_value(u16 frequency) -{ - u16 value; - - if (frequency < 5091) - value = 0x0040; - else if (frequency < 5321) - value = 0x0000; - else if (frequency < 5806) - value = 0x0080; - else - value = 0x0040; - - return value; -} - -#if 0 -/* This function converts a TSSI value to dBm in Q5.2 */ -static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - s8 dbm = 0; - s32 tmp; - - tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi); - tmp += 0x80; - tmp = clamp_val(tmp, 0x00, 0xFF); - dbm = aphy->tssi2dbm[tmp]; - //TODO: There's a FIXME on the specs - - return dbm; -} -#endif - -static void b43_radio_set_tx_iq(struct b43_wldev *dev) -{ - static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 }; - static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A }; - u16 tmp = b43_radio_read16(dev, 0x001E); - int i, j; - - for (i = 0; i < 5; i++) { - for (j = 0; j < 5; j++) { - if (tmp == (data_high[i] << 4 | data_low[j])) { - b43_phy_write(dev, 0x0069, - (i - j) << 8 | 0x00C0); - return; - } - } - } -} - -static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel) -{ - u16 freq, r8, tmp; - - freq = channel2freq_a(channel); - - r8 = b43_radio_read16(dev, 0x0008); - b43_write16(dev, 0x03F0, freq); - b43_radio_write16(dev, 0x0008, r8); - - //TODO: write max channel TX power? to Radio 0x2D - tmp = b43_radio_read16(dev, 0x002E); - tmp &= 0x0080; - //TODO: OR tmp with the Power out estimation for this channel? - b43_radio_write16(dev, 0x002E, tmp); - - if (freq >= 4920 && freq <= 5500) { - /* - * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F; - * = (freq * 0.025862069 - */ - r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */ - } - b43_radio_write16(dev, 0x0007, (r8 << 4) | r8); - b43_radio_write16(dev, 0x0020, (r8 << 4) | r8); - b43_radio_write16(dev, 0x0021, (r8 << 4) | r8); - b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4)); - b43_radio_write16(dev, 0x002A, (r8 << 4)); - b43_radio_write16(dev, 0x002B, (r8 << 4)); - b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4)); - b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0); - b43_radio_write16(dev, 0x0035, 0x00AA); - b43_radio_write16(dev, 0x0036, 0x0085); - b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq)); - b43_radio_mask(dev, 0x003D, 0x00FF); - b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080); - b43_radio_mask(dev, 0x0035, 0xFFEF); - b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010); - b43_radio_set_tx_iq(dev); - //TODO: TSSI2dbm workaround -//FIXME b43_phy_xmitpower(dev); -} - -static void b43_radio_init2060(struct b43_wldev *dev) -{ - b43_radio_write16(dev, 0x0004, 0x00C0); - b43_radio_write16(dev, 0x0005, 0x0008); - b43_radio_write16(dev, 0x0009, 0x0040); - b43_radio_write16(dev, 0x0005, 0x00AA); - b43_radio_write16(dev, 0x0032, 0x008F); - b43_radio_write16(dev, 0x0006, 0x008F); - b43_radio_write16(dev, 0x0034, 0x008F); - b43_radio_write16(dev, 0x002C, 0x0007); - b43_radio_write16(dev, 0x0082, 0x0080); - b43_radio_write16(dev, 0x0080, 0x0000); - b43_radio_write16(dev, 0x003F, 0x00DA); - b43_radio_mask(dev, 0x0005, ~0x0008); - b43_radio_mask(dev, 0x0081, ~0x0010); - b43_radio_mask(dev, 0x0081, ~0x0020); - b43_radio_mask(dev, 0x0081, ~0x0020); - msleep(1); /* delay 400usec */ - - b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010); - msleep(1); /* delay 400usec */ - - b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008); - b43_radio_mask(dev, 0x0085, ~0x0010); - b43_radio_mask(dev, 0x0005, ~0x0008); - b43_radio_mask(dev, 0x0081, ~0x0040); - b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040); - b43_radio_write16(dev, 0x0005, - (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008); - b43_phy_write(dev, 0x0063, 0xDDC6); - b43_phy_write(dev, 0x0069, 0x07BE); - b43_phy_write(dev, 0x006A, 0x0000); - - aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev)); - - msleep(1); -} - -static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable) -{ - int i; - - if (dev->phy.rev < 3) { - if (enable) - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) { - b43_ofdmtab_write16(dev, - B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8); - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, 0xFFF8); - } - else - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) { - b43_ofdmtab_write16(dev, - B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]); - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]); - } - } else { - if (enable) - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, 0x0820); - else - for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++) - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]); - } -} - -static void b43_phy_ww(struct b43_wldev *dev) -{ - u16 b, curr_s, best_s = 0xFFFF; - int i; - - b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN); - b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); - b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300); - b43_radio_set(dev, 0x0009, 0x0080); - b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002); - b43_wa_initgains(dev); - b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5); - b = b43_phy_read(dev, B43_PHY_PWRDOWN); - b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005); - b43_radio_set(dev, 0x0004, 0x0004); - for (i = 0x10; i <= 0x20; i++) { - b43_radio_write16(dev, 0x0013, i); - curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF; - if (!curr_s) { - best_s = 0x0000; - break; - } else if (curr_s >= 0x0080) - curr_s = 0x0100 - curr_s; - if (curr_s < best_s) - best_s = curr_s; - } - b43_phy_write(dev, B43_PHY_PWRDOWN, b); - b43_radio_mask(dev, 0x0004, 0xFFFB); - b43_radio_write16(dev, 0x0013, best_s); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC); - b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80); - b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00); - b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); - b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); - b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); - b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053); - b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120); - b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000); - b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017); - for (i = 0; i < 6; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013); - b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030); - b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); -} - -static void hardware_pctl_init_aphy(struct b43_wldev *dev) -{ - //TODO -} - -void b43_phy_inita(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - /* This lowlevel A-PHY init is also called from G-PHY init. - * So we must not access phy->a, if called from G-PHY code. - */ - B43_WARN_ON((phy->type != B43_PHYTYPE_A) && - (phy->type != B43_PHYTYPE_G)); - - might_sleep(); - - if (phy->rev >= 6) { - if (phy->type == B43_PHYTYPE_A) - b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000); - if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) - b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); - else - b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); - } - - b43_wa_all(dev); - - if (phy->type == B43_PHYTYPE_A) { - if (phy->gmode && (phy->rev < 3)) - b43_phy_set(dev, 0x0034, 0x0001); - b43_phy_rssiagc(dev, 0); - - b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); - - b43_radio_init2060(dev); - - if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && - ((dev->dev->board_type == SSB_BOARD_BU4306) || - (dev->dev->board_type == SSB_BOARD_BU4309))) { - ; //TODO: A PHY LO - } - - if (phy->rev >= 3) - b43_phy_ww(dev); - - hardware_pctl_init_aphy(dev); - - //TODO: radar detection - } - - if ((phy->type == B43_PHYTYPE_G) && - (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)) { - b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); - } -} - -/* Initialise the TSSI->dBm lookup table */ -static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - s16 pab0, pab1, pab2; - - pab0 = (s16) (dev->dev->bus_sprom->pa1b0); - pab1 = (s16) (dev->dev->bus_sprom->pa1b1); - pab2 = (s16) (dev->dev->bus_sprom->pa1b2); - - if (pab0 != 0 && pab1 != 0 && pab2 != 0 && - pab0 != -1 && pab1 != -1 && pab2 != -1) { - /* The pabX values are set in SPROM. Use them. */ - if ((s8) dev->dev->bus_sprom->itssi_a != 0 && - (s8) dev->dev->bus_sprom->itssi_a != -1) - aphy->tgt_idle_tssi = - (s8) (dev->dev->bus_sprom->itssi_a); - else - aphy->tgt_idle_tssi = 62; - aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, - pab1, pab2); - if (!aphy->tssi2dbm) - return -ENOMEM; - } else { - /* pabX values not set in SPROM, - * but APHY needs a generated table. */ - aphy->tssi2dbm = NULL; - b43err(dev->wl, "Could not generate tssi2dBm " - "table (wrong SPROM info)!\n"); - return -ENODEV; - } - - return 0; -} - -static int b43_aphy_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_a *aphy; - int err; - - aphy = kzalloc(sizeof(*aphy), GFP_KERNEL); - if (!aphy) - return -ENOMEM; - dev->phy.a = aphy; - - err = b43_aphy_init_tssi2dbm_table(dev); - if (err) - goto err_free_aphy; - - return 0; - -err_free_aphy: - kfree(aphy); - dev->phy.a = NULL; - - return err; -} - -static void b43_aphy_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - const void *tssi2dbm; - int tgt_idle_tssi; - - /* tssi2dbm table is constant, so it is initialized at alloc time. - * Save a copy of the pointer. */ - tssi2dbm = aphy->tssi2dbm; - tgt_idle_tssi = aphy->tgt_idle_tssi; - - /* Zero out the whole PHY structure. */ - memset(aphy, 0, sizeof(*aphy)); - - aphy->tssi2dbm = tssi2dbm; - aphy->tgt_idle_tssi = tgt_idle_tssi; - - //TODO init struct b43_phy_a - -} - -static void b43_aphy_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - - kfree(aphy->tssi2dbm); - aphy->tssi2dbm = NULL; - - kfree(aphy); - dev->phy.a = NULL; -} - -static int b43_aphy_op_init(struct b43_wldev *dev) -{ - b43_phy_inita(dev); - - return 0; -} - -static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset) -{ - /* OFDM registers are base-registers for the A-PHY. */ - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { - offset &= ~B43_PHYROUTE; - offset |= B43_PHYROUTE_BASE; - } - -#if B43_DEBUG - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { - /* Ext-G registers are only available on G-PHYs */ - b43err(dev->wl, "Invalid EXT-G PHY access at " - "0x%04X on A-PHY\n", offset); - dump_stack(); - } - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) { - /* N-BMODE registers are only available on N-PHYs */ - b43err(dev->wl, "Invalid N-BMODE PHY access at " - "0x%04X on A-PHY\n", offset); - dump_stack(); - } -#endif /* B43_DEBUG */ - - return offset; -} - -static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg) -{ - reg = adjust_phyreg(dev, reg); - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - return b43_read16(dev, B43_MMIO_PHY_DATA); -} - -static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - reg = adjust_phyreg(dev, reg); - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, value); -} - -static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - /* A-PHY needs 0x40 for read access */ - reg |= 0x40; - - b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); -} - -static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - - b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); -} - -static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev) -{ - return (dev->phy.rev >= 5); -} - -static void b43_aphy_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - struct b43_phy *phy = &dev->phy; - - if (!blocked) { - if (phy->radio_on) - return; - b43_radio_write16(dev, 0x0004, 0x00C0); - b43_radio_write16(dev, 0x0005, 0x0008); - b43_phy_mask(dev, 0x0010, 0xFFF7); - b43_phy_mask(dev, 0x0011, 0xFFF7); - b43_radio_init2060(dev); - } else { - b43_radio_write16(dev, 0x0004, 0x00FF); - b43_radio_write16(dev, 0x0005, 0x00FB); - b43_phy_set(dev, 0x0010, 0x0008); - b43_phy_set(dev, 0x0011, 0x0008); - } -} - -static int b43_aphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - if (new_channel > 200) - return -EINVAL; - aphy_channel_switch(dev, new_channel); - - return 0; -} - -static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev) -{ - return 36; /* Default to channel 36 */ -} - -static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) -{//TODO - struct b43_phy *phy = &dev->phy; - u16 tmp; - int autodiv = 0; - - if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1) - autodiv = 1; - - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); - - b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, - (autodiv ? B43_ANTENNA_AUTO1 : antenna) << - B43_PHY_BBANDCFG_RXANT_SHIFT); - - if (autodiv) { - tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); - if (antenna == B43_ANTENNA_AUTO1) - tmp &= ~B43_PHY_ANTDWELL_AUTODIV1; - else - tmp |= B43_PHY_ANTDWELL_AUTODIV1; - b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); - } - if (phy->rev < 3) - b43_phy_maskset(dev, B43_PHY_ANTDWELL, 0xFF00, 0x24); - else { - b43_phy_set(dev, B43_PHY_OFDM61, 0x10); - if (phy->rev == 3) { - b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x1D); - b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); - } else { - b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x3A); - b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); - } - } - - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); -} - -static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev) -{//TODO -} - -static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev, - bool ignore_tssi) -{//TODO - return B43_TXPWR_RES_DONE; -} - -static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev) -{//TODO -} - -static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev) -{//TODO -} - -static const struct b43_phy_operations b43_phyops_a = { - .allocate = b43_aphy_op_allocate, - .free = b43_aphy_op_free, - .prepare_structs = b43_aphy_op_prepare_structs, - .init = b43_aphy_op_init, - .phy_read = b43_aphy_op_read, - .phy_write = b43_aphy_op_write, - .radio_read = b43_aphy_op_radio_read, - .radio_write = b43_aphy_op_radio_write, - .supports_hwpctl = b43_aphy_op_supports_hwpctl, - .software_rfkill = b43_aphy_op_software_rfkill, - .switch_analog = b43_phyop_switch_analog_generic, - .switch_channel = b43_aphy_op_switch_channel, - .get_default_chan = b43_aphy_op_get_default_chan, - .set_rx_antenna = b43_aphy_op_set_rx_antenna, - .recalc_txpower = b43_aphy_op_recalc_txpower, - .adjust_txpower = b43_aphy_op_adjust_txpower, - .pwork_15sec = b43_aphy_op_pwork_15sec, - .pwork_60sec = b43_aphy_op_pwork_60sec, -}; diff --git a/drivers/net/wireless/b43/phy_a.h b/drivers/net/wireless/b43/phy_a.h deleted file mode 100644 index f7d0d929a..000000000 --- a/drivers/net/wireless/b43/phy_a.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef LINUX_B43_PHY_A_H_ -#define LINUX_B43_PHY_A_H_ - -#include "phy_common.h" - - -/* OFDM (A) PHY Registers */ -#define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */ -#define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */ -#define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */ -#define B43_PHY_BBANDCFG_RXANT_SHIFT 7 -#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */ -#define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */ -#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */ -#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */ -#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */ -#define B43_PHY_CRS0 B43_PHY_OFDM(0x29) -#define B43_PHY_CRS0_EN 0x4000 -#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30) -#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */ -#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */ -#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */ -#define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */ -#define B43_PHY_LMS B43_PHY_OFDM(0x55) -#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */ -#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */ -#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */ -#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */ -#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */ -#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */ -#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */ -#define B43_PHY_OTABLENR_SHIFT 10 -#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */ -#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */ -#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */ -#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */ -#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B) -#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */ -#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */ -#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */ -#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */ -#define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */ -#define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */ -#define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0) -#define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1) -#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2) -#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3) -#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4) -#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */ -#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */ -#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */ -#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9) -#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA) -#define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB) -#define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */ -#define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */ -#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */ -#define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */ -#define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */ -#define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */ -#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */ - -/*** OFDM table numbers ***/ -#define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset)) -#define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0) -#define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0) -#define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename -#define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4) -#define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0) -#define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3) -#define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0) -#define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0) -#define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0) -#define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0) -#define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0) -#define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0) -#define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0) -#define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0) -#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7) -#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12) -#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13) -#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename -#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename -#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12) -#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0) -#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename -#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0) -#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove! -#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0) -#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0) -#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4) -#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0) -#define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0) -#define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0) -#define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0) - -u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset); -void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table, - u16 offset, u16 value); -u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset); -void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table, - u16 offset, u32 value); - - -struct b43_phy_a { - /* Pointer to the table used to convert a - * TSSI value to dBm-Q5.2 */ - const s8 *tssi2dbm; - /* Target idle TSSI */ - int tgt_idle_tssi; - /* Current idle TSSI */ - int cur_idle_tssi;//FIXME value currently not set - - /* A-PHY TX Power control value. */ - u16 txpwr_offset; - - //TODO lots of missing stuff -}; - -/** - * b43_phy_inita - Lowlevel A-PHY init routine. - * This is _only_ used by the G-PHY code. - */ -void b43_phy_inita(struct b43_wldev *dev); - -#endif /* LINUX_B43_PHY_A_H_ */ diff --git a/drivers/net/wireless/b43/phy_ac.c b/drivers/net/wireless/b43/phy_ac.c deleted file mode 100644 index e75633d67..000000000 --- a/drivers/net/wireless/b43/phy_ac.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Broadcom B43 wireless driver - * IEEE 802.11ac AC-PHY support - * - * Copyright (c) 2015 Rafał Miłecki <zajec5@gmail.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include "b43.h" -#include "phy_ac.h" - -/************************************************** - * Basic PHY ops - **************************************************/ - -static int b43_phy_ac_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_ac *phy_ac; - - phy_ac = kzalloc(sizeof(*phy_ac), GFP_KERNEL); - if (!phy_ac) - return -ENOMEM; - dev->phy.ac = phy_ac; - - return 0; -} - -static void b43_phy_ac_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_ac *phy_ac = phy->ac; - - kfree(phy_ac); - phy->ac = NULL; -} - -static void b43_phy_ac_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, - u16 set) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, - (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); -} - -static u16 b43_phy_ac_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO24_DATA); -} - -static void b43_phy_ac_op_radio_write(struct b43_wldev *dev, u16 reg, - u16 value) -{ - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO24_DATA, value); -} - -static unsigned int b43_phy_ac_op_get_default_chan(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - return 11; - return 36; -} - -static enum b43_txpwr_result -b43_phy_ac_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi) -{ - return B43_TXPWR_RES_DONE; -} - -static void b43_phy_ac_op_adjust_txpower(struct b43_wldev *dev) -{ -} - -/************************************************** - * PHY ops struct - **************************************************/ - -const struct b43_phy_operations b43_phyops_ac = { - .allocate = b43_phy_ac_op_allocate, - .free = b43_phy_ac_op_free, - .phy_maskset = b43_phy_ac_op_maskset, - .radio_read = b43_phy_ac_op_radio_read, - .radio_write = b43_phy_ac_op_radio_write, - .get_default_chan = b43_phy_ac_op_get_default_chan, - .recalc_txpower = b43_phy_ac_op_recalc_txpower, - .adjust_txpower = b43_phy_ac_op_adjust_txpower, -}; diff --git a/drivers/net/wireless/b43/phy_ac.h b/drivers/net/wireless/b43/phy_ac.h deleted file mode 100644 index d1ca79e0e..000000000 --- a/drivers/net/wireless/b43/phy_ac.h +++ /dev/null @@ -1,38 +0,0 @@ -#ifndef B43_PHY_AC_H_ -#define B43_PHY_AC_H_ - -#include "phy_common.h" - -#define B43_PHY_AC_BBCFG 0x001 -#define B43_PHY_AC_BBCFG_RSTCCA 0x4000 /* Reset CCA */ -#define B43_PHY_AC_BANDCTL 0x003 /* Band control */ -#define B43_PHY_AC_BANDCTL_5GHZ 0x0001 -#define B43_PHY_AC_TABLE_ID 0x00d -#define B43_PHY_AC_TABLE_OFFSET 0x00e -#define B43_PHY_AC_TABLE_DATA1 0x00f -#define B43_PHY_AC_TABLE_DATA2 0x010 -#define B43_PHY_AC_TABLE_DATA3 0x011 -#define B43_PHY_AC_CLASSCTL 0x140 /* Classifier control */ -#define B43_PHY_AC_CLASSCTL_CCKEN 0x0001 /* CCK enable */ -#define B43_PHY_AC_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ -#define B43_PHY_AC_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ -#define B43_PHY_AC_BW1A 0x371 -#define B43_PHY_AC_BW2 0x372 -#define B43_PHY_AC_BW3 0x373 -#define B43_PHY_AC_BW4 0x374 -#define B43_PHY_AC_BW5 0x375 -#define B43_PHY_AC_BW6 0x376 -#define B43_PHY_AC_RFCTL_CMD 0x408 -#define B43_PHY_AC_C1_CLIP 0x6d4 -#define B43_PHY_AC_C1_CLIP_DIS 0x4000 -#define B43_PHY_AC_C2_CLIP 0x8d4 -#define B43_PHY_AC_C2_CLIP_DIS 0x4000 -#define B43_PHY_AC_C3_CLIP 0xad4 -#define B43_PHY_AC_C3_CLIP_DIS 0x4000 - -struct b43_phy_ac { -}; - -extern const struct b43_phy_operations b43_phyops_ac; - -#endif /* B43_PHY_AC_H_ */ diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c deleted file mode 100644 index ec2b9c577..000000000 --- a/drivers/net/wireless/b43/phy_common.c +++ /dev/null @@ -1,653 +0,0 @@ -/* - - Broadcom B43 wireless driver - Common PHY routines - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> - Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "phy_common.h" -#include "phy_g.h" -#include "phy_a.h" -#include "phy_n.h" -#include "phy_lp.h" -#include "phy_ht.h" -#include "phy_lcn.h" -#include "phy_ac.h" -#include "b43.h" -#include "main.h" - - -int b43_phy_allocate(struct b43_wldev *dev) -{ - struct b43_phy *phy = &(dev->phy); - int err; - - phy->ops = NULL; - - switch (phy->type) { - case B43_PHYTYPE_G: -#ifdef CONFIG_B43_PHY_G - phy->ops = &b43_phyops_g; -#endif - break; - case B43_PHYTYPE_N: -#ifdef CONFIG_B43_PHY_N - phy->ops = &b43_phyops_n; -#endif - break; - case B43_PHYTYPE_LP: -#ifdef CONFIG_B43_PHY_LP - phy->ops = &b43_phyops_lp; -#endif - break; - case B43_PHYTYPE_HT: -#ifdef CONFIG_B43_PHY_HT - phy->ops = &b43_phyops_ht; -#endif - break; - case B43_PHYTYPE_LCN: -#ifdef CONFIG_B43_PHY_LCN - phy->ops = &b43_phyops_lcn; -#endif - break; - case B43_PHYTYPE_AC: -#ifdef CONFIG_B43_PHY_AC - phy->ops = &b43_phyops_ac; -#endif - break; - } - if (B43_WARN_ON(!phy->ops)) - return -ENODEV; - - err = phy->ops->allocate(dev); - if (err) - phy->ops = NULL; - - return err; -} - -void b43_phy_free(struct b43_wldev *dev) -{ - dev->phy.ops->free(dev); - dev->phy.ops = NULL; -} - -int b43_phy_init(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - const struct b43_phy_operations *ops = phy->ops; - int err; - - /* During PHY init we need to use some channel. On the first init this - * function is called *before* b43_op_config, so our pointer is NULL. - */ - if (!phy->chandef) { - phy->chandef = &dev->wl->hw->conf.chandef; - phy->channel = phy->chandef->chan->hw_value; - } - - phy->ops->switch_analog(dev, true); - b43_software_rfkill(dev, false); - - err = ops->init(dev); - if (err) { - b43err(dev->wl, "PHY init failed\n"); - goto err_block_rf; - } - phy->do_full_init = false; - - err = b43_switch_channel(dev, phy->channel); - if (err) { - b43err(dev->wl, "PHY init: Channel switch to default failed\n"); - goto err_phy_exit; - } - - return 0; - -err_phy_exit: - phy->do_full_init = true; - if (ops->exit) - ops->exit(dev); -err_block_rf: - b43_software_rfkill(dev, true); - - return err; -} - -void b43_phy_exit(struct b43_wldev *dev) -{ - const struct b43_phy_operations *ops = dev->phy.ops; - - b43_software_rfkill(dev, true); - dev->phy.do_full_init = true; - if (ops->exit) - ops->exit(dev); -} - -bool b43_has_hardware_pctl(struct b43_wldev *dev) -{ - if (!dev->phy.hardware_power_control) - return false; - if (!dev->phy.ops->supports_hwpctl) - return false; - return dev->phy.ops->supports_hwpctl(dev); -} - -void b43_radio_lock(struct b43_wldev *dev) -{ - u32 macctl; - -#if B43_DEBUG - B43_WARN_ON(dev->phy.radio_locked); - dev->phy.radio_locked = true; -#endif - - macctl = b43_read32(dev, B43_MMIO_MACCTL); - macctl |= B43_MACCTL_RADIOLOCK; - b43_write32(dev, B43_MMIO_MACCTL, macctl); - /* Commit the write and wait for the firmware - * to finish any radio register access. */ - b43_read32(dev, B43_MMIO_MACCTL); - udelay(10); -} - -void b43_radio_unlock(struct b43_wldev *dev) -{ - u32 macctl; - -#if B43_DEBUG - B43_WARN_ON(!dev->phy.radio_locked); - dev->phy.radio_locked = false; -#endif - - /* Commit any write */ - b43_read16(dev, B43_MMIO_PHY_VER); - /* unlock */ - macctl = b43_read32(dev, B43_MMIO_MACCTL); - macctl &= ~B43_MACCTL_RADIOLOCK; - b43_write32(dev, B43_MMIO_MACCTL, macctl); -} - -void b43_phy_lock(struct b43_wldev *dev) -{ -#if B43_DEBUG - B43_WARN_ON(dev->phy.phy_locked); - dev->phy.phy_locked = true; -#endif - B43_WARN_ON(dev->dev->core_rev < 3); - - if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) - b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); -} - -void b43_phy_unlock(struct b43_wldev *dev) -{ -#if B43_DEBUG - B43_WARN_ON(!dev->phy.phy_locked); - dev->phy.phy_locked = false; -#endif - B43_WARN_ON(dev->dev->core_rev < 3); - - if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) - b43_power_saving_ctl_bits(dev, 0); -} - -static inline void assert_mac_suspended(struct b43_wldev *dev) -{ - if (!B43_DEBUG) - return; - if ((b43_status(dev) >= B43_STAT_INITIALIZED) && - (dev->mac_suspended <= 0)) { - b43dbg(dev->wl, "PHY/RADIO register access with " - "enabled MAC.\n"); - dump_stack(); - } -} - -u16 b43_radio_read(struct b43_wldev *dev, u16 reg) -{ - assert_mac_suspended(dev); - dev->phy.writes_counter = 0; - return dev->phy.ops->radio_read(dev, reg); -} - -void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - assert_mac_suspended(dev); - if (b43_bus_host_is_pci(dev->dev) && - ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { - b43_read32(dev, B43_MMIO_MACCTL); - dev->phy.writes_counter = 1; - } - dev->phy.ops->radio_write(dev, reg, value); -} - -void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask) -{ - b43_radio_write16(dev, offset, - b43_radio_read16(dev, offset) & mask); -} - -void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set) -{ - b43_radio_write16(dev, offset, - b43_radio_read16(dev, offset) | set); -} - -void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) -{ - b43_radio_write16(dev, offset, - (b43_radio_read16(dev, offset) & mask) | set); -} - -bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, - u16 value, int delay, int timeout) -{ - u16 val; - int i; - - for (i = 0; i < timeout; i += delay) { - val = b43_radio_read(dev, offset); - if ((val & mask) == value) - return true; - udelay(delay); - } - return false; -} - -u16 b43_phy_read(struct b43_wldev *dev, u16 reg) -{ - assert_mac_suspended(dev); - dev->phy.writes_counter = 0; - - if (dev->phy.ops->phy_read) - return dev->phy.ops->phy_read(dev, reg); - - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - return b43_read16(dev, B43_MMIO_PHY_DATA); -} - -void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - assert_mac_suspended(dev); - if (b43_bus_host_is_pci(dev->dev) && - ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { - b43_read16(dev, B43_MMIO_PHY_VER); - dev->phy.writes_counter = 1; - } - - if (dev->phy.ops->phy_write) - return dev->phy.ops->phy_write(dev, reg, value); - - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, value); -} - -void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg) -{ - b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg)); -} - -void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask) -{ - if (dev->phy.ops->phy_maskset) { - assert_mac_suspended(dev); - dev->phy.ops->phy_maskset(dev, offset, mask, 0); - } else { - b43_phy_write(dev, offset, - b43_phy_read(dev, offset) & mask); - } -} - -void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set) -{ - if (dev->phy.ops->phy_maskset) { - assert_mac_suspended(dev); - dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set); - } else { - b43_phy_write(dev, offset, - b43_phy_read(dev, offset) | set); - } -} - -void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) -{ - if (dev->phy.ops->phy_maskset) { - assert_mac_suspended(dev); - dev->phy.ops->phy_maskset(dev, offset, mask, set); - } else { - b43_phy_write(dev, offset, - (b43_phy_read(dev, offset) & mask) | set); - } -} - -void b43_phy_put_into_reset(struct b43_wldev *dev) -{ - u32 tmp; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~B43_BCMA_IOCTL_GMODE; - tmp |= B43_BCMA_IOCTL_PHY_RESET; - tmp |= BCMA_IOCTL_FGC; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - udelay(1); - - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~BCMA_IOCTL_FGC; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - udelay(1); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - tmp &= ~B43_TMSLOW_GMODE; - tmp |= B43_TMSLOW_PHYRESET; - tmp |= SSB_TMSLOW_FGC; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - usleep_range(1000, 2000); - - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - tmp &= ~SSB_TMSLOW_FGC; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - usleep_range(1000, 2000); - - break; -#endif - } -} - -void b43_phy_take_out_of_reset(struct b43_wldev *dev) -{ - u32 tmp; - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - /* Unset reset bit (with forcing clock) */ - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~B43_BCMA_IOCTL_PHY_RESET; - tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; - tmp |= BCMA_IOCTL_FGC; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - udelay(1); - - /* Do not force clock anymore */ - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - tmp &= ~BCMA_IOCTL_FGC; - tmp |= B43_BCMA_IOCTL_PHY_CLKEN; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - udelay(1); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - /* Unset reset bit (with forcing clock) */ - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - tmp &= ~B43_TMSLOW_PHYRESET; - tmp &= ~B43_TMSLOW_PHYCLKEN; - tmp |= SSB_TMSLOW_FGC; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ - usleep_range(1000, 2000); - - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - tmp &= ~SSB_TMSLOW_FGC; - tmp |= B43_TMSLOW_PHYCLKEN; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ - usleep_range(1000, 2000); - break; -#endif - } -} - -int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel) -{ - struct b43_phy *phy = &(dev->phy); - u16 channelcookie, savedcookie; - int err; - - /* First we set the channel radio code to prevent the - * firmware from sending ghost packets. - */ - channelcookie = new_channel; - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - channelcookie |= B43_SHM_SH_CHAN_5GHZ; - /* FIXME: set 40Mhz flag if required */ - if (0) - channelcookie |= B43_SHM_SH_CHAN_40MHZ; - savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie); - - /* Now try to switch the PHY hardware channel. */ - err = phy->ops->switch_channel(dev, new_channel); - if (err) - goto err_restore_cookie; - - /* Wait for the radio to tune to the channel and stabilize. */ - msleep(8); - - return 0; - -err_restore_cookie: - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_CHAN, savedcookie); - - return err; -} - -void b43_software_rfkill(struct b43_wldev *dev, bool blocked) -{ - struct b43_phy *phy = &dev->phy; - - b43_mac_suspend(dev); - phy->ops->software_rfkill(dev, blocked); - phy->radio_on = !blocked; - b43_mac_enable(dev); -} - -/** - * b43_phy_txpower_adjust_work - TX power workqueue. - * - * Workqueue for updating the TX power parameters in hardware. - */ -void b43_phy_txpower_adjust_work(struct work_struct *work) -{ - struct b43_wl *wl = container_of(work, struct b43_wl, - txpower_adjust_work); - struct b43_wldev *dev; - - mutex_lock(&wl->mutex); - dev = wl->current_dev; - - if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED))) - dev->phy.ops->adjust_txpower(dev); - - mutex_unlock(&wl->mutex); -} - -void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags) -{ - struct b43_phy *phy = &dev->phy; - unsigned long now = jiffies; - enum b43_txpwr_result result; - - if (!(flags & B43_TXPWR_IGNORE_TIME)) { - /* Check if it's time for a TXpower check. */ - if (time_before(now, phy->next_txpwr_check_time)) - return; /* Not yet */ - } - /* The next check will be needed in two seconds, or later. */ - phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2)); - - if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && - (dev->dev->board_type == SSB_BOARD_BU4306)) - return; /* No software txpower adjustment needed */ - - result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI)); - if (result == B43_TXPWR_RES_DONE) - return; /* We are done. */ - B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST); - B43_WARN_ON(phy->ops->adjust_txpower == NULL); - - /* We must adjust the transmission power in hardware. - * Schedule b43_phy_txpower_adjust_work(). */ - ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work); -} - -int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset) -{ - const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK); - unsigned int a, b, c, d; - unsigned int average; - u32 tmp; - - tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset); - a = tmp & 0xFF; - b = (tmp >> 8) & 0xFF; - c = (tmp >> 16) & 0xFF; - d = (tmp >> 24) & 0xFF; - if (a == 0 || a == B43_TSSI_MAX || - b == 0 || b == B43_TSSI_MAX || - c == 0 || c == B43_TSSI_MAX || - d == 0 || d == B43_TSSI_MAX) - return -ENOENT; - /* The values are OK. Clear them. */ - tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) | - (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24); - b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp); - - if (is_ofdm) { - a = (a + 32) & 0x3F; - b = (b + 32) & 0x3F; - c = (c + 32) & 0x3F; - d = (d + 32) & 0x3F; - } - - /* Get the average of the values with 0.5 added to each value. */ - average = (a + b + c + d + 2) / 4; - if (is_ofdm) { - /* Adjust for CCK-boost */ - if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1) - & B43_HF_CCKBOOST) - average = (average >= 13) ? (average - 13) : 0; - } - - return average; -} - -void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on) -{ - b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); -} - - -bool b43_is_40mhz(struct b43_wldev *dev) -{ - return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ -void b43_phy_force_clock(struct b43_wldev *dev, bool force) -{ - u32 tmp; - - WARN_ON(dev->phy.type != B43_PHYTYPE_N && - dev->phy.type != B43_PHYTYPE_HT && - dev->phy.type != B43_PHYTYPE_AC); - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); - if (force) - tmp |= BCMA_IOCTL_FGC; - else - tmp &= ~BCMA_IOCTL_FGC; - bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); - if (force) - tmp |= SSB_TMSLOW_FGC; - else - tmp &= ~SSB_TMSLOW_FGC; - ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); - break; -#endif - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */ -struct b43_c32 b43_cordic(int theta) -{ - static const u32 arctg[] = { - 2949120, 1740967, 919879, 466945, 234379, 117304, - 58666, 29335, 14668, 7334, 3667, 1833, - 917, 458, 229, 115, 57, 29, - }; - u8 i; - s32 tmp; - s8 signx = 1; - u32 angle = 0; - struct b43_c32 ret = { .i = 39797, .q = 0, }; - - while (theta > (180 << 16)) - theta -= (360 << 16); - while (theta < -(180 << 16)) - theta += (360 << 16); - - if (theta > (90 << 16)) { - theta -= (180 << 16); - signx = -1; - } else if (theta < -(90 << 16)) { - theta += (180 << 16); - signx = -1; - } - - for (i = 0; i <= 17; i++) { - if (theta > angle) { - tmp = ret.i - (ret.q >> i); - ret.q += ret.i >> i; - ret.i = tmp; - angle += arctg[i]; - } else { - tmp = ret.i + (ret.q >> i); - ret.q -= ret.i >> i; - ret.i = tmp; - angle -= arctg[i]; - } - } - - ret.i *= signx; - ret.q *= signx; - - return ret; -} diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h deleted file mode 100644 index 78d865267..000000000 --- a/drivers/net/wireless/b43/phy_common.h +++ /dev/null @@ -1,457 +0,0 @@ -#ifndef LINUX_B43_PHY_COMMON_H_ -#define LINUX_B43_PHY_COMMON_H_ - -#include <linux/types.h> -#include <linux/nl80211.h> - -struct b43_wldev; - -/* Complex number using 2 32-bit signed integers */ -struct b43_c32 { s32 i, q; }; - -#define CORDIC_CONVERT(value) (((value) >= 0) ? \ - ((((value) >> 15) + 1) >> 1) : \ - -((((-(value)) >> 15) + 1) >> 1)) - -/* PHY register routing bits */ -#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */ -#define B43_PHYROUTE_BASE 0x0000 /* Base registers */ -#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ -#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ -#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */ - -/* CCK (B-PHY) registers. */ -#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) -/* N-PHY registers. */ -#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE) -/* N-PHY BMODE registers. */ -#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE) -/* OFDM (A-PHY) registers. */ -#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) -/* Extended G-PHY registers. */ -#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) - - -/* Masks for the PHY versioning registers. */ -#define B43_PHYVER_ANALOG 0xF000 -#define B43_PHYVER_ANALOG_SHIFT 12 -#define B43_PHYVER_TYPE 0x0F00 -#define B43_PHYVER_TYPE_SHIFT 8 -#define B43_PHYVER_VERSION 0x00FF - -/* PHY writes need to be flushed if we reach limit */ -#define B43_MAX_WRITES_IN_ROW 24 - -/** - * enum b43_interference_mitigation - Interference Mitigation mode - * - * @B43_INTERFMODE_NONE: Disabled - * @B43_INTERFMODE_NONWLAN: Non-WLAN Interference Mitigation - * @B43_INTERFMODE_MANUALWLAN: WLAN Interference Mitigation - * @B43_INTERFMODE_AUTOWLAN: Automatic WLAN Interference Mitigation - */ -enum b43_interference_mitigation { - B43_INTERFMODE_NONE, - B43_INTERFMODE_NONWLAN, - B43_INTERFMODE_MANUALWLAN, - B43_INTERFMODE_AUTOWLAN, -}; - -/* Antenna identifiers */ -enum { - B43_ANTENNA0 = 0, /* Antenna 0 */ - B43_ANTENNA1 = 1, /* Antenna 1 */ - B43_ANTENNA_AUTO0 = 2, /* Automatic, starting with antenna 0 */ - B43_ANTENNA_AUTO1 = 3, /* Automatic, starting with antenna 1 */ - B43_ANTENNA2 = 4, - B43_ANTENNA3 = 8, - - B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0, - B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO, -}; - -/** - * enum b43_txpwr_result - Return value for the recalc_txpower PHY op. - * - * @B43_TXPWR_RES_NEED_ADJUST: Values changed. Hardware adjustment is needed. - * @B43_TXPWR_RES_DONE: No more work to do. Everything is done. - */ -enum b43_txpwr_result { - B43_TXPWR_RES_NEED_ADJUST, - B43_TXPWR_RES_DONE, -}; - -/** - * struct b43_phy_operations - Function pointers for PHY ops. - * - * @allocate: Allocate and initialise the PHY data structures. - * Must not be NULL. - * @free: Destroy and free the PHY data structures. - * Must not be NULL. - * - * @prepare_structs: Prepare the PHY data structures. - * The data structures allocated in @allocate are - * initialized here. - * Must not be NULL. - * @prepare_hardware: Prepare the PHY. This is called before b43_chip_init to - * do some early early PHY hardware init. - * Can be NULL, if not required. - * @init: Initialize the PHY. - * Must not be NULL. - * @exit: Shutdown the PHY. - * Can be NULL, if not required. - * - * @phy_read: Read from a PHY register. - * Must not be NULL. - * @phy_write: Write to a PHY register. - * Must not be NULL. - * @phy_maskset: Maskset a PHY register, taking shortcuts. - * If it is NULL, a generic algorithm is used. - * @radio_read: Read from a Radio register. - * Must not be NULL. - * @radio_write: Write to a Radio register. - * Must not be NULL. - * - * @supports_hwpctl: Returns a boolean whether Hardware Power Control - * is supported or not. - * If NULL, hwpctl is assumed to be never supported. - * @software_rfkill: Turn the radio ON or OFF. - * Possible state values are - * RFKILL_STATE_SOFT_BLOCKED or - * RFKILL_STATE_UNBLOCKED - * Must not be NULL. - * @switch_analog: Turn the Analog on/off. - * Must not be NULL. - * @switch_channel: Switch the radio to another channel. - * Must not be NULL. - * @get_default_chan: Just returns the default channel number. - * Must not be NULL. - * @set_rx_antenna: Set the antenna used for RX. - * Can be NULL, if not supported. - * @interf_mitigation: Switch the Interference Mitigation mode. - * Can be NULL, if not supported. - * - * @recalc_txpower: Recalculate the transmission power parameters. - * This callback has to recalculate the TX power settings, - * but does not need to write them to the hardware, yet. - * Returns enum b43_txpwr_result to indicate whether the hardware - * needs to be adjusted. - * If B43_TXPWR_NEED_ADJUST is returned, @adjust_txpower - * will be called later. - * If the parameter "ignore_tssi" is true, the TSSI values should - * be ignored and a recalculation of the power settings should be - * done even if the TSSI values did not change. - * This function may sleep, but should not. - * Must not be NULL. - * @adjust_txpower: Write the previously calculated TX power settings - * (from @recalc_txpower) to the hardware. - * This function may sleep. - * Can be NULL, if (and ONLY if) @recalc_txpower _always_ - * returns B43_TXPWR_RES_DONE. - * - * @pwork_15sec: Periodic work. Called every 15 seconds. - * Can be NULL, if not required. - * @pwork_60sec: Periodic work. Called every 60 seconds. - * Can be NULL, if not required. - */ -struct b43_phy_operations { - /* Initialisation */ - int (*allocate)(struct b43_wldev *dev); - void (*free)(struct b43_wldev *dev); - void (*prepare_structs)(struct b43_wldev *dev); - int (*prepare_hardware)(struct b43_wldev *dev); - int (*init)(struct b43_wldev *dev); - void (*exit)(struct b43_wldev *dev); - - /* Register access */ - u16 (*phy_read)(struct b43_wldev *dev, u16 reg); - void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); - void (*phy_maskset)(struct b43_wldev *dev, u16 reg, u16 mask, u16 set); - u16 (*radio_read)(struct b43_wldev *dev, u16 reg); - void (*radio_write)(struct b43_wldev *dev, u16 reg, u16 value); - - /* Radio */ - bool (*supports_hwpctl)(struct b43_wldev *dev); - void (*software_rfkill)(struct b43_wldev *dev, bool blocked); - void (*switch_analog)(struct b43_wldev *dev, bool on); - int (*switch_channel)(struct b43_wldev *dev, unsigned int new_channel); - unsigned int (*get_default_chan)(struct b43_wldev *dev); - void (*set_rx_antenna)(struct b43_wldev *dev, int antenna); - int (*interf_mitigation)(struct b43_wldev *dev, - enum b43_interference_mitigation new_mode); - - /* Transmission power adjustment */ - enum b43_txpwr_result (*recalc_txpower)(struct b43_wldev *dev, - bool ignore_tssi); - void (*adjust_txpower)(struct b43_wldev *dev); - - /* Misc */ - void (*pwork_15sec)(struct b43_wldev *dev); - void (*pwork_60sec)(struct b43_wldev *dev); -}; - -struct b43_phy_a; -struct b43_phy_g; -struct b43_phy_n; -struct b43_phy_lp; -struct b43_phy_ht; -struct b43_phy_lcn; - -struct b43_phy { - /* Hardware operation callbacks. */ - const struct b43_phy_operations *ops; - - /* Most hardware context information is stored in the standard- - * specific data structures pointed to by the pointers below. - * Only one of them is valid (the currently enabled PHY). */ -#ifdef CONFIG_B43_DEBUG - /* No union for debug build to force NULL derefs in buggy code. */ - struct { -#else - union { -#endif - /* A-PHY specific information */ - struct b43_phy_a *a; - /* G-PHY specific information */ - struct b43_phy_g *g; - /* N-PHY specific information */ - struct b43_phy_n *n; - /* LP-PHY specific information */ - struct b43_phy_lp *lp; - /* HT-PHY specific information */ - struct b43_phy_ht *ht; - /* LCN-PHY specific information */ - struct b43_phy_lcn *lcn; - /* AC-PHY specific information */ - struct b43_phy_ac *ac; - }; - - /* Band support flags. */ - bool supports_2ghz; - bool supports_5ghz; - - /* Is GMODE (2 GHz mode) bit enabled? */ - bool gmode; - - /* After power reset full init has to be performed */ - bool do_full_init; - - /* Analog Type */ - u8 analog; - /* B43_PHYTYPE_ */ - u8 type; - /* PHY revision number. */ - u8 rev; - - /* Count writes since last read */ - u8 writes_counter; - - /* Radio versioning */ - u16 radio_manuf; /* Radio manufacturer */ - u16 radio_ver; /* Radio version */ - u8 radio_rev; /* Radio revision */ - - /* Software state of the radio */ - bool radio_on; - - /* Desired TX power level (in dBm). - * This is set by the user and adjusted in b43_phy_xmitpower(). */ - int desired_txpower; - - /* Hardware Power Control enabled? */ - bool hardware_power_control; - - /* The time (in absolute jiffies) when the next TX power output - * check is needed. */ - unsigned long next_txpwr_check_time; - - /* Current channel */ - struct cfg80211_chan_def *chandef; - unsigned int channel; - - /* PHY TX errors counter. */ - atomic_t txerr_cnt; - -#ifdef CONFIG_B43_DEBUG - /* PHY registers locked (w.r.t. firmware) */ - bool phy_locked; - /* Radio registers locked (w.r.t. firmware) */ - bool radio_locked; -#endif /* B43_DEBUG */ -}; - - -/** - * b43_phy_allocate - Allocate PHY structs - * Allocate the PHY data structures, based on the current dev->phy.type - */ -int b43_phy_allocate(struct b43_wldev *dev); - -/** - * b43_phy_free - Free PHY structs - */ -void b43_phy_free(struct b43_wldev *dev); - -/** - * b43_phy_init - Initialise the PHY - */ -int b43_phy_init(struct b43_wldev *dev); - -/** - * b43_phy_exit - Cleanup PHY - */ -void b43_phy_exit(struct b43_wldev *dev); - -/** - * b43_has_hardware_pctl - Hardware Power Control supported? - * Returns a boolean, whether hardware power control is supported. - */ -bool b43_has_hardware_pctl(struct b43_wldev *dev); - -/** - * b43_phy_read - 16bit PHY register read access - */ -u16 b43_phy_read(struct b43_wldev *dev, u16 reg); - -/** - * b43_phy_write - 16bit PHY register write access - */ -void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value); - -/** - * b43_phy_copy - copy contents of 16bit PHY register to another - */ -void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg); - -/** - * b43_phy_mask - Mask a PHY register with a mask - */ -void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask); - -/** - * b43_phy_set - OR a PHY register with a bitmap - */ -void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set); - -/** - * b43_phy_maskset - Mask and OR a PHY register with a mask and bitmap - */ -void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); - -/** - * b43_radio_read - 16bit Radio register read access - */ -u16 b43_radio_read(struct b43_wldev *dev, u16 reg); -#define b43_radio_read16 b43_radio_read /* DEPRECATED */ - -/** - * b43_radio_write - 16bit Radio register write access - */ -void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value); -#define b43_radio_write16 b43_radio_write /* DEPRECATED */ - -/** - * b43_radio_mask - Mask a 16bit radio register with a mask - */ -void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask); - -/** - * b43_radio_set - OR a 16bit radio register with a bitmap - */ -void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set); - -/** - * b43_radio_maskset - Mask and OR a radio register with a mask and bitmap - */ -void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set); - -/** - * b43_radio_wait_value - Waits for a given value in masked register read - */ -bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, - u16 value, int delay, int timeout); - -/** - * b43_radio_lock - Lock firmware radio register access - */ -void b43_radio_lock(struct b43_wldev *dev); - -/** - * b43_radio_unlock - Unlock firmware radio register access - */ -void b43_radio_unlock(struct b43_wldev *dev); - -/** - * b43_phy_lock - Lock firmware PHY register access - */ -void b43_phy_lock(struct b43_wldev *dev); - -/** - * b43_phy_unlock - Unlock firmware PHY register access - */ -void b43_phy_unlock(struct b43_wldev *dev); - -void b43_phy_put_into_reset(struct b43_wldev *dev); -void b43_phy_take_out_of_reset(struct b43_wldev *dev); - -/** - * b43_switch_channel - Switch to another channel - */ -int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel); - -/** - * b43_software_rfkill - Turn the radio ON or OFF in software. - */ -void b43_software_rfkill(struct b43_wldev *dev, bool blocked); - -/** - * b43_phy_txpower_check - Check TX power output. - * - * Compare the current TX power output to the desired power emission - * and schedule an adjustment in case it mismatches. - * - * @flags: OR'ed enum b43_phy_txpower_check_flags flags. - * See the docs below. - */ -void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags); -/** - * enum b43_phy_txpower_check_flags - Flags for b43_phy_txpower_check() - * - * @B43_TXPWR_IGNORE_TIME: Ignore the schedule time and force-redo - * the check now. - * @B43_TXPWR_IGNORE_TSSI: Redo the recalculation, even if the average - * TSSI did not change. - */ -enum b43_phy_txpower_check_flags { - B43_TXPWR_IGNORE_TIME = (1 << 0), - B43_TXPWR_IGNORE_TSSI = (1 << 1), -}; - -struct work_struct; -void b43_phy_txpower_adjust_work(struct work_struct *work); - -/** - * b43_phy_shm_tssi_read - Read the average of the last 4 TSSI from SHM. - * - * @shm_offset: The SHM address to read the values from. - * - * Returns the average of the 4 TSSI values, or a negative error code. - */ -int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset); - -/** - * b43_phy_switch_analog_generic - Generic PHY operation for switching the Analog. - * - * It does the switching based on the PHY0 core register. - * Do _not_ call this directly. Only use it as a switch_analog callback - * for struct b43_phy_operations. - */ -void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on); - -bool b43_is_40mhz(struct b43_wldev *dev); - -void b43_phy_force_clock(struct b43_wldev *dev, bool force); - -struct b43_c32 b43_cordic(int theta); - -#endif /* LINUX_B43_PHY_COMMON_H_ */ diff --git a/drivers/net/wireless/b43/phy_g.c b/drivers/net/wireless/b43/phy_g.c deleted file mode 100644 index 462310e6e..000000000 --- a/drivers/net/wireless/b43/phy_g.c +++ /dev/null @@ -1,3055 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11g PHY driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> - Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "phy_g.h" -#include "phy_common.h" -#include "lo.h" -#include "main.h" - -#include <linux/bitrev.h> -#include <linux/slab.h> - - -static const s8 b43_tssi2dbm_g_table[] = { - 77, 77, 77, 76, - 76, 76, 75, 75, - 74, 74, 73, 73, - 73, 72, 72, 71, - 71, 70, 70, 69, - 68, 68, 67, 67, - 66, 65, 65, 64, - 63, 63, 62, 61, - 60, 59, 58, 57, - 56, 55, 54, 53, - 52, 50, 49, 47, - 45, 43, 40, 37, - 33, 28, 22, 14, - 5, -7, -20, -20, - -20, -20, -20, -20, - -20, -20, -20, -20, -}; - -static const u8 b43_radio_channel_codes_bg[] = { - 12, 17, 22, 27, - 32, 37, 42, 47, - 52, 57, 62, 67, - 72, 84, -}; - - -static void b43_calc_nrssi_threshold(struct b43_wldev *dev); - - -#define bitrev4(tmp) (bitrev8(tmp) >> 4) - - -/* Get the freq, as it has to be written to the device. */ -static inline u16 channel2freq_bg(u8 channel) -{ - B43_WARN_ON(!(channel >= 1 && channel <= 14)); - - return b43_radio_channel_codes_bg[channel - 1]; -} - -static void generate_rfatt_list(struct b43_wldev *dev, - struct b43_rfatt_list *list) -{ - struct b43_phy *phy = &dev->phy; - - /* APHY.rev < 5 || GPHY.rev < 6 */ - static const struct b43_rfatt rfatt_0[] = { - {.att = 3,.with_padmix = 0,}, - {.att = 1,.with_padmix = 0,}, - {.att = 5,.with_padmix = 0,}, - {.att = 7,.with_padmix = 0,}, - {.att = 9,.with_padmix = 0,}, - {.att = 2,.with_padmix = 0,}, - {.att = 0,.with_padmix = 0,}, - {.att = 4,.with_padmix = 0,}, - {.att = 6,.with_padmix = 0,}, - {.att = 8,.with_padmix = 0,}, - {.att = 1,.with_padmix = 1,}, - {.att = 2,.with_padmix = 1,}, - {.att = 3,.with_padmix = 1,}, - {.att = 4,.with_padmix = 1,}, - }; - /* Radio.rev == 8 && Radio.version == 0x2050 */ - static const struct b43_rfatt rfatt_1[] = { - {.att = 2,.with_padmix = 1,}, - {.att = 4,.with_padmix = 1,}, - {.att = 6,.with_padmix = 1,}, - {.att = 8,.with_padmix = 1,}, - {.att = 10,.with_padmix = 1,}, - {.att = 12,.with_padmix = 1,}, - {.att = 14,.with_padmix = 1,}, - }; - /* Otherwise */ - static const struct b43_rfatt rfatt_2[] = { - {.att = 0,.with_padmix = 1,}, - {.att = 2,.with_padmix = 1,}, - {.att = 4,.with_padmix = 1,}, - {.att = 6,.with_padmix = 1,}, - {.att = 8,.with_padmix = 1,}, - {.att = 9,.with_padmix = 1,}, - {.att = 9,.with_padmix = 1,}, - }; - - if (!b43_has_hardware_pctl(dev)) { - /* Software pctl */ - list->list = rfatt_0; - list->len = ARRAY_SIZE(rfatt_0); - list->min_val = 0; - list->max_val = 9; - return; - } - if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { - /* Hardware pctl */ - list->list = rfatt_1; - list->len = ARRAY_SIZE(rfatt_1); - list->min_val = 0; - list->max_val = 14; - return; - } - /* Hardware pctl */ - list->list = rfatt_2; - list->len = ARRAY_SIZE(rfatt_2); - list->min_val = 0; - list->max_val = 9; -} - -static void generate_bbatt_list(struct b43_wldev *dev, - struct b43_bbatt_list *list) -{ - static const struct b43_bbatt bbatt_0[] = { - {.att = 0,}, - {.att = 1,}, - {.att = 2,}, - {.att = 3,}, - {.att = 4,}, - {.att = 5,}, - {.att = 6,}, - {.att = 7,}, - {.att = 8,}, - }; - - list->list = bbatt_0; - list->len = ARRAY_SIZE(bbatt_0); - list->min_val = 0; - list->max_val = 8; -} - -static void b43_shm_clear_tssi(struct b43_wldev *dev) -{ - b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F); - b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F); - b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F); - b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F); -} - -/* Synthetic PU workaround */ -static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel) -{ - struct b43_phy *phy = &dev->phy; - - might_sleep(); - - if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) { - /* We do not need the workaround. */ - return; - } - - if (channel <= 10) { - b43_write16(dev, B43_MMIO_CHANNEL, - channel2freq_bg(channel + 4)); - } else { - b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1)); - } - msleep(1); - b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); -} - -/* Set the baseband attenuation value on chip. */ -void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, - u16 baseband_attenuation) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->analog == 0) { - b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0) - & 0xFFF0) | - baseband_attenuation); - } else if (phy->analog > 1) { - b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2)); - } else { - b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3)); - } -} - -/* Adjust the transmission power output (G-PHY) */ -static void b43_set_txpower_g(struct b43_wldev *dev, - const struct b43_bbatt *bbatt, - const struct b43_rfatt *rfatt, u8 tx_control) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - u16 bb, rf; - u16 tx_bias, tx_magn; - - bb = bbatt->att; - rf = rfatt->att; - tx_bias = lo->tx_bias; - tx_magn = lo->tx_magn; - if (unlikely(tx_bias == 0xFF)) - tx_bias = 0; - - /* Save the values for later. Use memmove, because it's valid - * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */ - gphy->tx_control = tx_control; - memmove(&gphy->rfatt, rfatt, sizeof(*rfatt)); - gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX); - memmove(&gphy->bbatt, bbatt, sizeof(*bbatt)); - - if (b43_debug(dev, B43_DBG_XMITPOWER)) { - b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), " - "rfatt(%u), tx_control(0x%02X), " - "tx_bias(0x%02X), tx_magn(0x%02X)\n", - bb, rf, tx_control, tx_bias, tx_magn); - } - - b43_gphy_set_baseband_attenuation(dev, bb); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf); - if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { - b43_radio_write16(dev, 0x43, - (rf & 0x000F) | (tx_control & 0x0070)); - } else { - b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F)); - b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070)); - } - if (has_tx_magnification(phy)) { - b43_radio_write16(dev, 0x52, tx_magn | tx_bias); - } else { - b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F)); - } - b43_lo_g_adjust(dev); -} - -/* GPHY_TSSI_Power_Lookup_Table_Init */ -static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev) -{ - struct b43_phy_g *gphy = dev->phy.g; - int i; - u16 value; - - for (i = 0; i < 32; i++) - b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]); - for (i = 32; i < 64; i++) - b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]); - for (i = 0; i < 64; i += 2) { - value = (u16) gphy->tssi2dbm[i]; - value |= ((u16) gphy->tssi2dbm[i + 1]) << 8; - b43_phy_write(dev, 0x380 + (i / 2), value); - } -} - -/* GPHY_Gain_Lookup_Table_Init */ -static void b43_gphy_gain_lt_init(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - u16 nr_written = 0; - u16 tmp; - u8 rf, bb; - - for (rf = 0; rf < lo->rfatt_list.len; rf++) { - for (bb = 0; bb < lo->bbatt_list.len; bb++) { - if (nr_written >= 0x40) - return; - tmp = lo->bbatt_list.list[bb].att; - tmp <<= 8; - if (phy->radio_rev == 8) - tmp |= 0x50; - else - tmp |= 0x40; - tmp |= lo->rfatt_list.list[rf].att; - b43_phy_write(dev, 0x3C0 + nr_written, tmp); - nr_written++; - } - } -} - -static void b43_set_all_gains(struct b43_wldev *dev, - s16 first, s16 second, s16 third) -{ - struct b43_phy *phy = &dev->phy; - u16 i; - u16 start = 0x08, end = 0x18; - u16 tmp; - u16 table; - - if (phy->rev <= 1) { - start = 0x10; - end = 0x20; - } - - table = B43_OFDMTAB_GAINX; - if (phy->rev <= 1) - table = B43_OFDMTAB_GAINX_R1; - for (i = 0; i < 4; i++) - b43_ofdmtab_write16(dev, table, i, first); - - for (i = start; i < end; i++) - b43_ofdmtab_write16(dev, table, i, second); - - if (third != -1) { - tmp = ((u16) third << 14) | ((u16) third << 6); - b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp); - b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp); - b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp); - } - b43_dummy_transmission(dev, false, true); -} - -static void b43_set_original_gains(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 i, tmp; - u16 table; - u16 start = 0x0008, end = 0x0018; - - if (phy->rev <= 1) { - start = 0x0010; - end = 0x0020; - } - - table = B43_OFDMTAB_GAINX; - if (phy->rev <= 1) - table = B43_OFDMTAB_GAINX_R1; - for (i = 0; i < 4; i++) { - tmp = (i & 0xFFFC); - tmp |= (i & 0x0001) << 1; - tmp |= (i & 0x0002) >> 1; - - b43_ofdmtab_write16(dev, table, i, tmp); - } - - for (i = start; i < end; i++) - b43_ofdmtab_write16(dev, table, i, i - start); - - b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040); - b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040); - b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000); - b43_dummy_transmission(dev, false, true); -} - -/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ -static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) -{ - b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); - b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); -} - -/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ -static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset) -{ - u16 val; - - b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); - val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); - - return (s16) val; -} - -/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ -static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) -{ - u16 i; - s16 tmp; - - for (i = 0; i < 64; i++) { - tmp = b43_nrssi_hw_read(dev, i); - tmp -= val; - tmp = clamp_val(tmp, -32, 31); - b43_nrssi_hw_write(dev, i, tmp); - } -} - -/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ -static void b43_nrssi_mem_update(struct b43_wldev *dev) -{ - struct b43_phy_g *gphy = dev->phy.g; - s16 i, delta; - s32 tmp; - - delta = 0x1F - gphy->nrssi[0]; - for (i = 0; i < 64; i++) { - tmp = (i - delta) * gphy->nrssislope; - tmp /= 0x10000; - tmp += 0x3A; - tmp = clamp_val(tmp, 0, 0x3F); - gphy->nrssi_lt[i] = tmp; - } -} - -static void b43_calc_nrssi_offset(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 backup[20] = { 0 }; - s16 v47F; - u16 i; - u16 saved = 0xFFFF; - - backup[0] = b43_phy_read(dev, 0x0001); - backup[1] = b43_phy_read(dev, 0x0811); - backup[2] = b43_phy_read(dev, 0x0812); - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - backup[3] = b43_phy_read(dev, 0x0814); - backup[4] = b43_phy_read(dev, 0x0815); - } - backup[5] = b43_phy_read(dev, 0x005A); - backup[6] = b43_phy_read(dev, 0x0059); - backup[7] = b43_phy_read(dev, 0x0058); - backup[8] = b43_phy_read(dev, 0x000A); - backup[9] = b43_phy_read(dev, 0x0003); - backup[10] = b43_radio_read16(dev, 0x007A); - backup[11] = b43_radio_read16(dev, 0x0043); - - b43_phy_mask(dev, 0x0429, 0x7FFF); - b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000); - b43_phy_set(dev, 0x0811, 0x000C); - b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004); - b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); - if (phy->rev >= 6) { - backup[12] = b43_phy_read(dev, 0x002E); - backup[13] = b43_phy_read(dev, 0x002F); - backup[14] = b43_phy_read(dev, 0x080F); - backup[15] = b43_phy_read(dev, 0x0810); - backup[16] = b43_phy_read(dev, 0x0801); - backup[17] = b43_phy_read(dev, 0x0060); - backup[18] = b43_phy_read(dev, 0x0014); - backup[19] = b43_phy_read(dev, 0x0478); - - b43_phy_write(dev, 0x002E, 0); - b43_phy_write(dev, 0x002F, 0); - b43_phy_write(dev, 0x080F, 0); - b43_phy_write(dev, 0x0810, 0); - b43_phy_set(dev, 0x0478, 0x0100); - b43_phy_set(dev, 0x0801, 0x0040); - b43_phy_set(dev, 0x0060, 0x0040); - b43_phy_set(dev, 0x0014, 0x0200); - } - b43_radio_set(dev, 0x007A, 0x0070); - b43_radio_set(dev, 0x007A, 0x0080); - udelay(30); - - v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); - if (v47F >= 0x20) - v47F -= 0x40; - if (v47F == 31) { - for (i = 7; i >= 4; i--) { - b43_radio_write16(dev, 0x007B, i); - udelay(20); - v47F = - (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); - if (v47F >= 0x20) - v47F -= 0x40; - if (v47F < 31 && saved == 0xFFFF) - saved = i; - } - if (saved == 0xFFFF) - saved = 4; - } else { - b43_radio_mask(dev, 0x007A, 0x007F); - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_set(dev, 0x0814, 0x0001); - b43_phy_mask(dev, 0x0815, 0xFFFE); - } - b43_phy_set(dev, 0x0811, 0x000C); - b43_phy_set(dev, 0x0812, 0x000C); - b43_phy_set(dev, 0x0811, 0x0030); - b43_phy_set(dev, 0x0812, 0x0030); - b43_phy_write(dev, 0x005A, 0x0480); - b43_phy_write(dev, 0x0059, 0x0810); - b43_phy_write(dev, 0x0058, 0x000D); - if (phy->rev == 0) { - b43_phy_write(dev, 0x0003, 0x0122); - } else { - b43_phy_set(dev, 0x000A, 0x2000); - } - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_set(dev, 0x0814, 0x0004); - b43_phy_mask(dev, 0x0815, 0xFFFB); - } - b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); - b43_radio_set(dev, 0x007A, 0x000F); - b43_set_all_gains(dev, 3, 0, 1); - b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F); - udelay(30); - v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); - if (v47F >= 0x20) - v47F -= 0x40; - if (v47F == -32) { - for (i = 0; i < 4; i++) { - b43_radio_write16(dev, 0x007B, i); - udelay(20); - v47F = - (s16) ((b43_phy_read(dev, 0x047F) >> 8) & - 0x003F); - if (v47F >= 0x20) - v47F -= 0x40; - if (v47F > -31 && saved == 0xFFFF) - saved = i; - } - if (saved == 0xFFFF) - saved = 3; - } else - saved = 0; - } - b43_radio_write16(dev, 0x007B, saved); - - if (phy->rev >= 6) { - b43_phy_write(dev, 0x002E, backup[12]); - b43_phy_write(dev, 0x002F, backup[13]); - b43_phy_write(dev, 0x080F, backup[14]); - b43_phy_write(dev, 0x0810, backup[15]); - } - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_write(dev, 0x0814, backup[3]); - b43_phy_write(dev, 0x0815, backup[4]); - } - b43_phy_write(dev, 0x005A, backup[5]); - b43_phy_write(dev, 0x0059, backup[6]); - b43_phy_write(dev, 0x0058, backup[7]); - b43_phy_write(dev, 0x000A, backup[8]); - b43_phy_write(dev, 0x0003, backup[9]); - b43_radio_write16(dev, 0x0043, backup[11]); - b43_radio_write16(dev, 0x007A, backup[10]); - b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2); - b43_phy_set(dev, 0x0429, 0x8000); - b43_set_original_gains(dev); - if (phy->rev >= 6) { - b43_phy_write(dev, 0x0801, backup[16]); - b43_phy_write(dev, 0x0060, backup[17]); - b43_phy_write(dev, 0x0014, backup[18]); - b43_phy_write(dev, 0x0478, backup[19]); - } - b43_phy_write(dev, 0x0001, backup[0]); - b43_phy_write(dev, 0x0812, backup[2]); - b43_phy_write(dev, 0x0811, backup[1]); -} - -static void b43_calc_nrssi_slope(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 backup[18] = { 0 }; - u16 tmp; - s16 nrssi0, nrssi1; - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - - if (phy->radio_rev >= 9) - return; - if (phy->radio_rev == 8) - b43_calc_nrssi_offset(dev); - - b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); - b43_phy_mask(dev, 0x0802, 0xFFFC); - backup[7] = b43_read16(dev, 0x03E2); - b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); - backup[0] = b43_radio_read16(dev, 0x007A); - backup[1] = b43_radio_read16(dev, 0x0052); - backup[2] = b43_radio_read16(dev, 0x0043); - backup[3] = b43_phy_read(dev, 0x0015); - backup[4] = b43_phy_read(dev, 0x005A); - backup[5] = b43_phy_read(dev, 0x0059); - backup[6] = b43_phy_read(dev, 0x0058); - backup[8] = b43_read16(dev, 0x03E6); - backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT); - if (phy->rev >= 3) { - backup[10] = b43_phy_read(dev, 0x002E); - backup[11] = b43_phy_read(dev, 0x002F); - backup[12] = b43_phy_read(dev, 0x080F); - backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL); - backup[14] = b43_phy_read(dev, 0x0801); - backup[15] = b43_phy_read(dev, 0x0060); - backup[16] = b43_phy_read(dev, 0x0014); - backup[17] = b43_phy_read(dev, 0x0478); - b43_phy_write(dev, 0x002E, 0); - b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0); - switch (phy->rev) { - case 4: - case 6: - case 7: - b43_phy_set(dev, 0x0478, 0x0100); - b43_phy_set(dev, 0x0801, 0x0040); - break; - case 3: - case 5: - b43_phy_mask(dev, 0x0801, 0xFFBF); - break; - } - b43_phy_set(dev, 0x0060, 0x0040); - b43_phy_set(dev, 0x0014, 0x0200); - } - b43_radio_set(dev, 0x007A, 0x0070); - b43_set_all_gains(dev, 0, 8, 0); - b43_radio_mask(dev, 0x007A, 0x00F7); - if (phy->rev >= 2) { - b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030); - b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010); - } - b43_radio_set(dev, 0x007A, 0x0080); - udelay(20); - - nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); - if (nrssi0 >= 0x0020) - nrssi0 -= 0x0040; - - b43_radio_mask(dev, 0x007A, 0x007F); - if (phy->rev >= 2) { - b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); - } - - b43_write16(dev, B43_MMIO_CHANNEL_EXT, - b43_read16(dev, B43_MMIO_CHANNEL_EXT) - | 0x2000); - b43_radio_set(dev, 0x007A, 0x000F); - b43_phy_write(dev, 0x0015, 0xF330); - if (phy->rev >= 2) { - b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020); - b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020); - } - - b43_set_all_gains(dev, 3, 0, 1); - if (phy->radio_rev == 8) { - b43_radio_write16(dev, 0x0043, 0x001F); - } else { - tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F; - b43_radio_write16(dev, 0x0052, tmp | 0x0060); - tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0; - b43_radio_write16(dev, 0x0043, tmp | 0x0009); - } - b43_phy_write(dev, 0x005A, 0x0480); - b43_phy_write(dev, 0x0059, 0x0810); - b43_phy_write(dev, 0x0058, 0x000D); - udelay(20); - nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); - if (nrssi1 >= 0x0020) - nrssi1 -= 0x0040; - if (nrssi0 == nrssi1) - gphy->nrssislope = 0x00010000; - else - gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1); - if (nrssi0 >= -4) { - gphy->nrssi[0] = nrssi1; - gphy->nrssi[1] = nrssi0; - } - if (phy->rev >= 3) { - b43_phy_write(dev, 0x002E, backup[10]); - b43_phy_write(dev, 0x002F, backup[11]); - b43_phy_write(dev, 0x080F, backup[12]); - b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); - } - if (phy->rev >= 2) { - b43_phy_mask(dev, 0x0812, 0xFFCF); - b43_phy_mask(dev, 0x0811, 0xFFCF); - } - - b43_radio_write16(dev, 0x007A, backup[0]); - b43_radio_write16(dev, 0x0052, backup[1]); - b43_radio_write16(dev, 0x0043, backup[2]); - b43_write16(dev, 0x03E2, backup[7]); - b43_write16(dev, 0x03E6, backup[8]); - b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]); - b43_phy_write(dev, 0x0015, backup[3]); - b43_phy_write(dev, 0x005A, backup[4]); - b43_phy_write(dev, 0x0059, backup[5]); - b43_phy_write(dev, 0x0058, backup[6]); - b43_synth_pu_workaround(dev, phy->channel); - b43_phy_set(dev, 0x0802, (0x0001 | 0x0002)); - b43_set_original_gains(dev); - b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); - if (phy->rev >= 3) { - b43_phy_write(dev, 0x0801, backup[14]); - b43_phy_write(dev, 0x0060, backup[15]); - b43_phy_write(dev, 0x0014, backup[16]); - b43_phy_write(dev, 0x0478, backup[17]); - } - b43_nrssi_mem_update(dev); - b43_calc_nrssi_threshold(dev); -} - -static void b43_calc_nrssi_threshold(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - s32 a, b; - s16 tmp16; - u16 tmp_u16; - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - - if (!phy->gmode || - !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { - tmp16 = b43_nrssi_hw_read(dev, 0x20); - if (tmp16 >= 0x20) - tmp16 -= 0x40; - if (tmp16 < 3) { - b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB); - } else { - b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED); - } - } else { - if (gphy->interfmode == B43_INTERFMODE_NONWLAN) { - a = 0xE; - b = 0xA; - } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) { - a = 0x13; - b = 0x12; - } else { - a = 0xE; - b = 0x11; - } - - a = a * (gphy->nrssi[1] - gphy->nrssi[0]); - a += (gphy->nrssi[0] << 6); - if (a < 32) - a += 31; - else - a += 32; - a = a >> 6; - a = clamp_val(a, -31, 31); - - b = b * (gphy->nrssi[1] - gphy->nrssi[0]); - b += (gphy->nrssi[0] << 6); - if (b < 32) - b += 31; - else - b += 32; - b = b >> 6; - b = clamp_val(b, -31, 31); - - tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; - tmp_u16 |= ((u32) b & 0x0000003F); - tmp_u16 |= (((u32) a & 0x0000003F) << 6); - b43_phy_write(dev, 0x048A, tmp_u16); - } -} - -/* Stack implementation to save/restore values from the - * interference mitigation code. - * It is save to restore values in random order. - */ -static void _stack_save(u32 *_stackptr, size_t *stackidx, - u8 id, u16 offset, u16 value) -{ - u32 *stackptr = &(_stackptr[*stackidx]); - - B43_WARN_ON(offset & 0xF000); - B43_WARN_ON(id & 0xF0); - *stackptr = offset; - *stackptr |= ((u32) id) << 12; - *stackptr |= ((u32) value) << 16; - (*stackidx)++; - B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE); -} - -static u16 _stack_restore(u32 *stackptr, u8 id, u16 offset) -{ - size_t i; - - B43_WARN_ON(offset & 0xF000); - B43_WARN_ON(id & 0xF0); - for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) { - if ((*stackptr & 0x00000FFF) != offset) - continue; - if (((*stackptr & 0x0000F000) >> 12) != id) - continue; - return ((*stackptr & 0xFFFF0000) >> 16); - } - B43_WARN_ON(1); - - return 0; -} - -#define phy_stacksave(offset) \ - do { \ - _stack_save(stack, &stackidx, 0x1, (offset), \ - b43_phy_read(dev, (offset))); \ - } while (0) -#define phy_stackrestore(offset) \ - do { \ - b43_phy_write(dev, (offset), \ - _stack_restore(stack, 0x1, \ - (offset))); \ - } while (0) -#define radio_stacksave(offset) \ - do { \ - _stack_save(stack, &stackidx, 0x2, (offset), \ - b43_radio_read16(dev, (offset))); \ - } while (0) -#define radio_stackrestore(offset) \ - do { \ - b43_radio_write16(dev, (offset), \ - _stack_restore(stack, 0x2, \ - (offset))); \ - } while (0) -#define ofdmtab_stacksave(table, offset) \ - do { \ - _stack_save(stack, &stackidx, 0x3, (offset)|(table), \ - b43_ofdmtab_read16(dev, (table), (offset))); \ - } while (0) -#define ofdmtab_stackrestore(table, offset) \ - do { \ - b43_ofdmtab_write16(dev, (table), (offset), \ - _stack_restore(stack, 0x3, \ - (offset)|(table))); \ - } while (0) - -static void -b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 tmp, flipped; - size_t stackidx = 0; - u32 *stack = gphy->interfstack; - - switch (mode) { - case B43_INTERFMODE_NONWLAN: - if (phy->rev != 1) { - b43_phy_set(dev, 0x042B, 0x0800); - b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000); - break; - } - radio_stacksave(0x0078); - tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); - B43_WARN_ON(tmp > 15); - flipped = bitrev4(tmp); - if (flipped < 10 && flipped >= 8) - flipped = 7; - else if (flipped >= 10) - flipped -= 3; - flipped = (bitrev4(flipped) << 1) | 0x0020; - b43_radio_write16(dev, 0x0078, flipped); - - b43_calc_nrssi_threshold(dev); - - phy_stacksave(0x0406); - b43_phy_write(dev, 0x0406, 0x7E28); - - b43_phy_set(dev, 0x042B, 0x0800); - b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); - - phy_stacksave(0x04A0); - b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008); - phy_stacksave(0x04A1); - b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605); - phy_stacksave(0x04A2); - b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204); - phy_stacksave(0x04A8); - b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803); - phy_stacksave(0x04AB); - b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605); - - phy_stacksave(0x04A7); - b43_phy_write(dev, 0x04A7, 0x0002); - phy_stacksave(0x04A3); - b43_phy_write(dev, 0x04A3, 0x287A); - phy_stacksave(0x04A9); - b43_phy_write(dev, 0x04A9, 0x2027); - phy_stacksave(0x0493); - b43_phy_write(dev, 0x0493, 0x32F5); - phy_stacksave(0x04AA); - b43_phy_write(dev, 0x04AA, 0x2027); - phy_stacksave(0x04AC); - b43_phy_write(dev, 0x04AC, 0x32F5); - break; - case B43_INTERFMODE_MANUALWLAN: - if (b43_phy_read(dev, 0x0033) & 0x0800) - break; - - gphy->aci_enable = true; - - phy_stacksave(B43_PHY_RADIO_BITFIELD); - phy_stacksave(B43_PHY_G_CRS); - if (phy->rev < 2) { - phy_stacksave(0x0406); - } else { - phy_stacksave(0x04C0); - phy_stacksave(0x04C1); - } - phy_stacksave(0x0033); - phy_stacksave(0x04A7); - phy_stacksave(0x04A3); - phy_stacksave(0x04A9); - phy_stacksave(0x04AA); - phy_stacksave(0x04AC); - phy_stacksave(0x0493); - phy_stacksave(0x04A1); - phy_stacksave(0x04A0); - phy_stacksave(0x04A2); - phy_stacksave(0x048A); - phy_stacksave(0x04A8); - phy_stacksave(0x04AB); - if (phy->rev == 2) { - phy_stacksave(0x04AD); - phy_stacksave(0x04AE); - } else if (phy->rev >= 3) { - phy_stacksave(0x04AD); - phy_stacksave(0x0415); - phy_stacksave(0x0416); - phy_stacksave(0x0417); - ofdmtab_stacksave(0x1A00, 0x2); - ofdmtab_stacksave(0x1A00, 0x3); - } - phy_stacksave(0x042B); - phy_stacksave(0x048C); - - b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); - b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002); - - b43_phy_write(dev, 0x0033, 0x0800); - b43_phy_write(dev, 0x04A3, 0x2027); - b43_phy_write(dev, 0x04A9, 0x1CA8); - b43_phy_write(dev, 0x0493, 0x287A); - b43_phy_write(dev, 0x04AA, 0x1CA8); - b43_phy_write(dev, 0x04AC, 0x287A); - - b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A); - b43_phy_write(dev, 0x04A7, 0x000D); - - if (phy->rev < 2) { - b43_phy_write(dev, 0x0406, 0xFF0D); - } else if (phy->rev == 2) { - b43_phy_write(dev, 0x04C0, 0xFFFF); - b43_phy_write(dev, 0x04C1, 0x00A9); - } else { - b43_phy_write(dev, 0x04C0, 0x00C1); - b43_phy_write(dev, 0x04C1, 0x0059); - } - - b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800); - b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015); - b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000); - b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00); - b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000); - b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800); - b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010); - b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005); - b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010); - b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006); - b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800); - b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500); - b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B); - - if (phy->rev >= 3) { - b43_phy_mask(dev, 0x048A, 0x7FFF); - b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8); - b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8); - b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D); - } else { - b43_phy_set(dev, 0x048A, 0x1000); - b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000); - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); - } - if (phy->rev >= 2) { - b43_phy_set(dev, 0x042B, 0x0800); - } - b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200); - if (phy->rev == 2) { - b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F); - b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300); - } else if (phy->rev >= 6) { - b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); - b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); - b43_phy_mask(dev, 0x04AD, 0x00FF); - } - b43_calc_nrssi_slope(dev); - break; - default: - B43_WARN_ON(1); - } -} - -static void -b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u32 *stack = gphy->interfstack; - - switch (mode) { - case B43_INTERFMODE_NONWLAN: - if (phy->rev != 1) { - b43_phy_mask(dev, 0x042B, ~0x0800); - b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); - break; - } - radio_stackrestore(0x0078); - b43_calc_nrssi_threshold(dev); - phy_stackrestore(0x0406); - b43_phy_mask(dev, 0x042B, ~0x0800); - if (!dev->bad_frames_preempt) { - b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11)); - } - b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); - phy_stackrestore(0x04A0); - phy_stackrestore(0x04A1); - phy_stackrestore(0x04A2); - phy_stackrestore(0x04A8); - phy_stackrestore(0x04AB); - phy_stackrestore(0x04A7); - phy_stackrestore(0x04A3); - phy_stackrestore(0x04A9); - phy_stackrestore(0x0493); - phy_stackrestore(0x04AA); - phy_stackrestore(0x04AC); - break; - case B43_INTERFMODE_MANUALWLAN: - if (!(b43_phy_read(dev, 0x0033) & 0x0800)) - break; - - gphy->aci_enable = false; - - phy_stackrestore(B43_PHY_RADIO_BITFIELD); - phy_stackrestore(B43_PHY_G_CRS); - phy_stackrestore(0x0033); - phy_stackrestore(0x04A3); - phy_stackrestore(0x04A9); - phy_stackrestore(0x0493); - phy_stackrestore(0x04AA); - phy_stackrestore(0x04AC); - phy_stackrestore(0x04A0); - phy_stackrestore(0x04A7); - if (phy->rev >= 2) { - phy_stackrestore(0x04C0); - phy_stackrestore(0x04C1); - } else - phy_stackrestore(0x0406); - phy_stackrestore(0x04A1); - phy_stackrestore(0x04AB); - phy_stackrestore(0x04A8); - if (phy->rev == 2) { - phy_stackrestore(0x04AD); - phy_stackrestore(0x04AE); - } else if (phy->rev >= 3) { - phy_stackrestore(0x04AD); - phy_stackrestore(0x0415); - phy_stackrestore(0x0416); - phy_stackrestore(0x0417); - ofdmtab_stackrestore(0x1A00, 0x2); - ofdmtab_stackrestore(0x1A00, 0x3); - } - phy_stackrestore(0x04A2); - phy_stackrestore(0x048A); - phy_stackrestore(0x042B); - phy_stackrestore(0x048C); - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW); - b43_calc_nrssi_slope(dev); - break; - default: - B43_WARN_ON(1); - } -} - -#undef phy_stacksave -#undef phy_stackrestore -#undef radio_stacksave -#undef radio_stackrestore -#undef ofdmtab_stacksave -#undef ofdmtab_stackrestore - -static u16 b43_radio_core_calibration_value(struct b43_wldev *dev) -{ - u16 reg, index, ret; - - static const u8 rcc_table[] = { - 0x02, 0x03, 0x01, 0x0F, - 0x06, 0x07, 0x05, 0x0F, - 0x0A, 0x0B, 0x09, 0x0F, - 0x0E, 0x0F, 0x0D, 0x0F, - }; - - reg = b43_radio_read16(dev, 0x60); - index = (reg & 0x001E) >> 1; - ret = rcc_table[index] << 1; - ret |= (reg & 0x0001); - ret |= 0x0020; - - return ret; -} - -#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0)) -static u16 radio2050_rfover_val(struct b43_wldev *dev, - u16 phy_register, unsigned int lpd) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - if (!phy->gmode) - return 0; - - if (has_loopback_gain(phy)) { - int max_lb_gain = gphy->max_lb_gain; - u16 extlna; - u16 i; - - if (phy->radio_rev == 8) - max_lb_gain += 0x3E; - else - max_lb_gain += 0x26; - if (max_lb_gain >= 0x46) { - extlna = 0x3000; - max_lb_gain -= 0x46; - } else if (max_lb_gain >= 0x3A) { - extlna = 0x1000; - max_lb_gain -= 0x3A; - } else if (max_lb_gain >= 0x2E) { - extlna = 0x2000; - max_lb_gain -= 0x2E; - } else { - extlna = 0; - max_lb_gain -= 0x10; - } - - for (i = 0; i < 16; i++) { - max_lb_gain -= (i * 6); - if (max_lb_gain < 6) - break; - } - - if ((phy->rev < 7) || - !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { - if (phy_register == B43_PHY_RFOVER) { - return 0x1B3; - } else if (phy_register == B43_PHY_RFOVERVAL) { - extlna |= (i << 8); - switch (lpd) { - case LPD(0, 1, 1): - return 0x0F92; - case LPD(0, 0, 1): - case LPD(1, 0, 1): - return (0x0092 | extlna); - case LPD(1, 0, 0): - return (0x0093 | extlna); - } - B43_WARN_ON(1); - } - B43_WARN_ON(1); - } else { - if (phy_register == B43_PHY_RFOVER) { - return 0x9B3; - } else if (phy_register == B43_PHY_RFOVERVAL) { - if (extlna) - extlna |= 0x8000; - extlna |= (i << 8); - switch (lpd) { - case LPD(0, 1, 1): - return 0x8F92; - case LPD(0, 0, 1): - return (0x8092 | extlna); - case LPD(1, 0, 1): - return (0x2092 | extlna); - case LPD(1, 0, 0): - return (0x2093 | extlna); - } - B43_WARN_ON(1); - } - B43_WARN_ON(1); - } - } else { - if ((phy->rev < 7) || - !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { - if (phy_register == B43_PHY_RFOVER) { - return 0x1B3; - } else if (phy_register == B43_PHY_RFOVERVAL) { - switch (lpd) { - case LPD(0, 1, 1): - return 0x0FB2; - case LPD(0, 0, 1): - return 0x00B2; - case LPD(1, 0, 1): - return 0x30B2; - case LPD(1, 0, 0): - return 0x30B3; - } - B43_WARN_ON(1); - } - B43_WARN_ON(1); - } else { - if (phy_register == B43_PHY_RFOVER) { - return 0x9B3; - } else if (phy_register == B43_PHY_RFOVERVAL) { - switch (lpd) { - case LPD(0, 1, 1): - return 0x8FB2; - case LPD(0, 0, 1): - return 0x80B2; - case LPD(1, 0, 1): - return 0x20B2; - case LPD(1, 0, 0): - return 0x20B3; - } - B43_WARN_ON(1); - } - B43_WARN_ON(1); - } - } - return 0; -} - -struct init2050_saved_values { - /* Core registers */ - u16 reg_3EC; - u16 reg_3E6; - u16 reg_3F4; - /* Radio registers */ - u16 radio_43; - u16 radio_51; - u16 radio_52; - /* PHY registers */ - u16 phy_pgactl; - u16 phy_cck_5A; - u16 phy_cck_59; - u16 phy_cck_58; - u16 phy_cck_30; - u16 phy_rfover; - u16 phy_rfoverval; - u16 phy_analogover; - u16 phy_analogoverval; - u16 phy_crs0; - u16 phy_classctl; - u16 phy_lo_mask; - u16 phy_lo_ctl; - u16 phy_syncctl; -}; - -static u16 b43_radio_init2050(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct init2050_saved_values sav; - u16 rcc; - u16 radio78; - u16 ret; - u16 i, j; - u32 tmp1 = 0, tmp2 = 0; - - memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */ - - sav.radio_43 = b43_radio_read16(dev, 0x43); - sav.radio_51 = b43_radio_read16(dev, 0x51); - sav.radio_52 = b43_radio_read16(dev, 0x52); - sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); - sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); - sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); - sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); - - if (phy->type == B43_PHYTYPE_B) { - sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); - sav.reg_3EC = b43_read16(dev, 0x3EC); - - b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); - b43_write16(dev, 0x3EC, 0x3F3F); - } else if (phy->gmode || phy->rev >= 2) { - sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); - sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); - sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); - sav.phy_analogoverval = - b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); - sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); - sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); - - b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); - b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); - b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); - b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); - if (has_loopback_gain(phy)) { - sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); - sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); - - if (phy->rev >= 3) - b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); - else - b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); - b43_phy_write(dev, B43_PHY_LO_CTL, 0); - } - - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, - LPD(0, 1, 1))); - b43_phy_write(dev, B43_PHY_RFOVER, - radio2050_rfover_val(dev, B43_PHY_RFOVER, 0)); - } - b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); - - sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); - b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F); - sav.reg_3E6 = b43_read16(dev, 0x3E6); - sav.reg_3F4 = b43_read16(dev, 0x3F4); - - if (phy->analog == 0) { - b43_write16(dev, 0x03E6, 0x0122); - } else { - if (phy->analog >= 2) { - b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); - } - b43_write16(dev, B43_MMIO_CHANNEL_EXT, - (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); - } - - rcc = b43_radio_core_calibration_value(dev); - - if (phy->type == B43_PHYTYPE_B) - b43_radio_write16(dev, 0x78, 0x26); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, - LPD(0, 1, 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); - b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, - LPD(0, 0, 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0); - b43_radio_set(dev, 0x51, 0x0004); - if (phy->radio_rev == 8) { - b43_radio_write16(dev, 0x43, 0x1F); - } else { - b43_radio_write16(dev, 0x52, 0); - b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009); - } - b43_phy_write(dev, B43_PHY_CCK(0x58), 0); - - for (i = 0; i < 16; i++) { - b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); - b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); - b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); - udelay(10); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); - udelay(10); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, 0))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); - udelay(20); - tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); - b43_phy_write(dev, B43_PHY_CCK(0x58), 0); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); - } - udelay(10); - - b43_phy_write(dev, B43_PHY_CCK(0x58), 0); - tmp1++; - tmp1 >>= 9; - - for (i = 0; i < 16; i++) { - radio78 = (bitrev4(i) << 1) | 0x0020; - b43_radio_write16(dev, 0x78, radio78); - udelay(10); - for (j = 0; j < 16; j++) { - b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); - b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); - b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, - 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); - udelay(10); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, - 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); - udelay(10); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, - 0))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); - udelay(10); - tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); - b43_phy_write(dev, B43_PHY_CCK(0x58), 0); - if (phy->gmode || phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_RFOVERVAL, - radio2050_rfover_val(dev, - B43_PHY_RFOVERVAL, - LPD(1, 0, - 1))); - } - b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); - } - tmp2++; - tmp2 >>= 8; - if (tmp1 < tmp2) - break; - } - - /* Restore the registers */ - b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl); - b43_radio_write16(dev, 0x51, sav.radio_51); - b43_radio_write16(dev, 0x52, sav.radio_52); - b43_radio_write16(dev, 0x43, sav.radio_43); - b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); - b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); - b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); - b43_write16(dev, 0x3E6, sav.reg_3E6); - if (phy->analog != 0) - b43_write16(dev, 0x3F4, sav.reg_3F4); - b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); - b43_synth_pu_workaround(dev, phy->channel); - if (phy->type == B43_PHYTYPE_B) { - b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); - b43_write16(dev, 0x3EC, sav.reg_3EC); - } else if (phy->gmode) { - b43_write16(dev, B43_MMIO_PHY_RADIO, - b43_read16(dev, B43_MMIO_PHY_RADIO) - & 0x7FFF); - b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover); - b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval); - b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover); - b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, - sav.phy_analogoverval); - b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0); - b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl); - if (has_loopback_gain(phy)) { - b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask); - b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl); - } - } - if (i > 15) - ret = radio78; - else - ret = rcc; - - return ret; -} - -static void b43_phy_initb5(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 offset, value; - u8 old_channel; - - if (phy->analog == 1) { - b43_radio_set(dev, 0x007A, 0x0050); - } - if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) && - (dev->dev->board_type != SSB_BOARD_BU4306)) { - value = 0x2120; - for (offset = 0x00A8; offset < 0x00C7; offset++) { - b43_phy_write(dev, offset, value); - value += 0x202; - } - } - b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700); - if (phy->radio_ver == 0x2050) - b43_phy_write(dev, 0x0038, 0x0667); - - if (phy->gmode || phy->rev >= 2) { - if (phy->radio_ver == 0x2050) { - b43_radio_set(dev, 0x007A, 0x0020); - b43_radio_set(dev, 0x0051, 0x0004); - } - b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000); - - b43_phy_set(dev, 0x0802, 0x0100); - b43_phy_set(dev, 0x042B, 0x2000); - - b43_phy_write(dev, 0x001C, 0x186A); - - b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900); - b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064); - b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A); - } - - if (dev->bad_frames_preempt) { - b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11)); - } - - if (phy->analog == 1) { - b43_phy_write(dev, 0x0026, 0xCE00); - b43_phy_write(dev, 0x0021, 0x3763); - b43_phy_write(dev, 0x0022, 0x1BC3); - b43_phy_write(dev, 0x0023, 0x06F9); - b43_phy_write(dev, 0x0024, 0x037E); - } else - b43_phy_write(dev, 0x0026, 0xCC00); - b43_phy_write(dev, 0x0030, 0x00C6); - b43_write16(dev, 0x03EC, 0x3F22); - - if (phy->analog == 1) - b43_phy_write(dev, 0x0020, 0x3E1C); - else - b43_phy_write(dev, 0x0020, 0x301C); - - if (phy->analog == 0) - b43_write16(dev, 0x03E4, 0x3000); - - old_channel = phy->channel; - /* Force to channel 7, even if not supported. */ - b43_gphy_channel_switch(dev, 7, 0); - - if (phy->radio_ver != 0x2050) { - b43_radio_write16(dev, 0x0075, 0x0080); - b43_radio_write16(dev, 0x0079, 0x0081); - } - - b43_radio_write16(dev, 0x0050, 0x0020); - b43_radio_write16(dev, 0x0050, 0x0023); - - if (phy->radio_ver == 0x2050) { - b43_radio_write16(dev, 0x0050, 0x0020); - b43_radio_write16(dev, 0x005A, 0x0070); - } - - b43_radio_write16(dev, 0x005B, 0x007B); - b43_radio_write16(dev, 0x005C, 0x00B0); - - b43_radio_set(dev, 0x007A, 0x0007); - - b43_gphy_channel_switch(dev, old_channel, 0); - - b43_phy_write(dev, 0x0014, 0x0080); - b43_phy_write(dev, 0x0032, 0x00CA); - b43_phy_write(dev, 0x002A, 0x88A3); - - b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); - - if (phy->radio_ver == 0x2050) - b43_radio_write16(dev, 0x005D, 0x000D); - - b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/B6 */ -static void b43_phy_initb6(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 offset, val; - u8 old_channel; - - b43_phy_write(dev, 0x003E, 0x817A); - b43_radio_write16(dev, 0x007A, - (b43_radio_read16(dev, 0x007A) | 0x0058)); - if (phy->radio_rev == 4 || phy->radio_rev == 5) { - b43_radio_write16(dev, 0x51, 0x37); - b43_radio_write16(dev, 0x52, 0x70); - b43_radio_write16(dev, 0x53, 0xB3); - b43_radio_write16(dev, 0x54, 0x9B); - b43_radio_write16(dev, 0x5A, 0x88); - b43_radio_write16(dev, 0x5B, 0x88); - b43_radio_write16(dev, 0x5D, 0x88); - b43_radio_write16(dev, 0x5E, 0x88); - b43_radio_write16(dev, 0x7D, 0x88); - b43_hf_write(dev, b43_hf_read(dev) - | B43_HF_TSSIRPSMW); - } - B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */ - if (phy->radio_rev == 8) { - b43_radio_write16(dev, 0x51, 0); - b43_radio_write16(dev, 0x52, 0x40); - b43_radio_write16(dev, 0x53, 0xB7); - b43_radio_write16(dev, 0x54, 0x98); - b43_radio_write16(dev, 0x5A, 0x88); - b43_radio_write16(dev, 0x5B, 0x6B); - b43_radio_write16(dev, 0x5C, 0x0F); - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) { - b43_radio_write16(dev, 0x5D, 0xFA); - b43_radio_write16(dev, 0x5E, 0xD8); - } else { - b43_radio_write16(dev, 0x5D, 0xF5); - b43_radio_write16(dev, 0x5E, 0xB8); - } - b43_radio_write16(dev, 0x0073, 0x0003); - b43_radio_write16(dev, 0x007D, 0x00A8); - b43_radio_write16(dev, 0x007C, 0x0001); - b43_radio_write16(dev, 0x007E, 0x0008); - } - val = 0x1E1F; - for (offset = 0x0088; offset < 0x0098; offset++) { - b43_phy_write(dev, offset, val); - val -= 0x0202; - } - val = 0x3E3F; - for (offset = 0x0098; offset < 0x00A8; offset++) { - b43_phy_write(dev, offset, val); - val -= 0x0202; - } - val = 0x2120; - for (offset = 0x00A8; offset < 0x00C8; offset++) { - b43_phy_write(dev, offset, (val & 0x3F3F)); - val += 0x0202; - } - if (phy->type == B43_PHYTYPE_G) { - b43_radio_set(dev, 0x007A, 0x0020); - b43_radio_set(dev, 0x0051, 0x0004); - b43_phy_set(dev, 0x0802, 0x0100); - b43_phy_set(dev, 0x042B, 0x2000); - b43_phy_write(dev, 0x5B, 0); - b43_phy_write(dev, 0x5C, 0); - } - - old_channel = phy->channel; - if (old_channel >= 8) - b43_gphy_channel_switch(dev, 1, 0); - else - b43_gphy_channel_switch(dev, 13, 0); - - b43_radio_write16(dev, 0x0050, 0x0020); - b43_radio_write16(dev, 0x0050, 0x0023); - udelay(40); - if (phy->radio_rev < 6 || phy->radio_rev == 8) { - b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C) - | 0x0002)); - b43_radio_write16(dev, 0x50, 0x20); - } - if (phy->radio_rev <= 2) { - b43_radio_write16(dev, 0x50, 0x20); - b43_radio_write16(dev, 0x5A, 0x70); - b43_radio_write16(dev, 0x5B, 0x7B); - b43_radio_write16(dev, 0x5C, 0xB0); - } - b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007); - - b43_gphy_channel_switch(dev, old_channel, 0); - - b43_phy_write(dev, 0x0014, 0x0200); - if (phy->radio_rev >= 6) - b43_phy_write(dev, 0x2A, 0x88C2); - else - b43_phy_write(dev, 0x2A, 0x8AC0); - b43_phy_write(dev, 0x0038, 0x0668); - b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); - if (phy->radio_rev == 4 || phy->radio_rev == 5) - b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003); - if (phy->radio_rev <= 2) - b43_radio_write16(dev, 0x005D, 0x000D); - - if (phy->analog == 4) { - b43_write16(dev, 0x3E4, 9); - b43_phy_mask(dev, 0x61, 0x0FFF); - } else { - b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004); - } - if (phy->type == B43_PHYTYPE_B) - B43_WARN_ON(1); - else if (phy->type == B43_PHYTYPE_G) - b43_write16(dev, 0x03E6, 0x0); -} - -static void b43_calc_loopback_gain(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 backup_phy[16] = { 0 }; - u16 backup_radio[3]; - u16 backup_bband; - u16 i, j, loop_i_max; - u16 trsw_rx; - u16 loop1_outer_done, loop1_inner_done; - - backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0); - backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG); - backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER); - backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL); - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); - backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); - } - backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); - backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); - backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); - backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); - backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); - backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); - backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); - backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); - backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); - backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); - backup_bband = gphy->bbatt.att; - backup_radio[0] = b43_radio_read16(dev, 0x52); - backup_radio[1] = b43_radio_read16(dev, 0x43); - backup_radio[2] = b43_radio_read16(dev, 0x7A); - - b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF); - b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); - b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); - b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD); - b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); - b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE); - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); - b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE); - b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); - b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD); - } - b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); - b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); - b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); - b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10); - - b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); - b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); - b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); - - b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); - b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); - } - b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); - - if (phy->radio_rev == 8) { - b43_radio_write16(dev, 0x43, 0x000F); - } else { - b43_radio_write16(dev, 0x52, 0); - b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9); - } - b43_gphy_set_baseband_attenuation(dev, 11); - - if (phy->rev >= 3) - b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); - else - b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); - b43_phy_write(dev, B43_PHY_LO_CTL, 0); - - b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); - b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); - - b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); - b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); - - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) { - if (phy->rev >= 7) { - b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); - b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); - } - } - b43_radio_mask(dev, 0x7A, 0x00F7); - - j = 0; - loop_i_max = (phy->radio_rev == 8) ? 15 : 9; - for (i = 0; i < loop_i_max; i++) { - for (j = 0; j < 16; j++) { - b43_radio_write16(dev, 0x43, i); - b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); - b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); - b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); - udelay(20); - if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) - goto exit_loop1; - } - } - exit_loop1: - loop1_outer_done = i; - loop1_inner_done = j; - if (j >= 8) { - b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); - trsw_rx = 0x1B; - for (j = j - 8; j < 16; j++) { - b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); - b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); - b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); - udelay(20); - trsw_rx -= 3; - if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) - goto exit_loop2; - } - } else - trsw_rx = 0x18; - exit_loop2: - - if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ - b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); - b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); - } - b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); - b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); - b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); - b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); - b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); - b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); - b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); - b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); - b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); - - b43_gphy_set_baseband_attenuation(dev, backup_bband); - - b43_radio_write16(dev, 0x52, backup_radio[0]); - b43_radio_write16(dev, 0x43, backup_radio[1]); - b43_radio_write16(dev, 0x7A, backup_radio[2]); - - b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003); - udelay(10); - b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]); - b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]); - b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]); - b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]); - - gphy->max_lb_gain = - ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11; - gphy->trsw_rx_gain = trsw_rx * 2; -} - -static void b43_hardware_pctl_early_init(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (!b43_has_hardware_pctl(dev)) { - b43_phy_write(dev, 0x047A, 0xC111); - return; - } - - b43_phy_mask(dev, 0x0036, 0xFEFF); - b43_phy_write(dev, 0x002F, 0x0202); - b43_phy_set(dev, 0x047C, 0x0002); - b43_phy_set(dev, 0x047A, 0xF000); - if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { - b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); - b43_phy_set(dev, 0x005D, 0x8000); - b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); - b43_phy_write(dev, 0x002E, 0xC07F); - b43_phy_set(dev, 0x0036, 0x0400); - } else { - b43_phy_set(dev, 0x0036, 0x0200); - b43_phy_set(dev, 0x0036, 0x0400); - b43_phy_mask(dev, 0x005D, 0x7FFF); - b43_phy_mask(dev, 0x004F, 0xFFFE); - b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); - b43_phy_write(dev, 0x002E, 0xC07F); - b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); - } -} - -/* Hardware power control for G-PHY */ -static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - - if (!b43_has_hardware_pctl(dev)) { - /* No hardware power control */ - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL); - return; - } - - b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); - b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); - b43_gphy_tssi_power_lt_init(dev); - b43_gphy_gain_lt_init(dev); - b43_phy_mask(dev, 0x0060, 0xFFBF); - b43_phy_write(dev, 0x0014, 0x0000); - - B43_WARN_ON(phy->rev < 6); - b43_phy_set(dev, 0x0478, 0x0800); - b43_phy_mask(dev, 0x0478, 0xFEFF); - b43_phy_mask(dev, 0x0801, 0xFFBF); - - b43_gphy_dc_lt_init(dev, 1); - - /* Enable hardware pctl in firmware. */ - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL); -} - -/* Initialize B/G PHY power control */ -static void b43_phy_init_pctl(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_rfatt old_rfatt; - struct b43_bbatt old_bbatt; - u8 old_tx_control = 0; - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - - if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && - (dev->dev->board_type == SSB_BOARD_BU4306)) - return; - - b43_phy_write(dev, 0x0028, 0x8018); - - /* This does something with the Analog... */ - b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0) - & 0xFFDF); - - if (!phy->gmode) - return; - b43_hardware_pctl_early_init(dev); - if (gphy->cur_idle_tssi == 0) { - if (phy->radio_ver == 0x2050 && phy->analog == 0) { - b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084); - } else { - struct b43_rfatt rfatt; - struct b43_bbatt bbatt; - - memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt)); - memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt)); - old_tx_control = gphy->tx_control; - - bbatt.att = 11; - if (phy->radio_rev == 8) { - rfatt.att = 15; - rfatt.with_padmix = true; - } else { - rfatt.att = 9; - rfatt.with_padmix = false; - } - b43_set_txpower_g(dev, &bbatt, &rfatt, 0); - } - b43_dummy_transmission(dev, false, true); - gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI); - if (B43_DEBUG) { - /* Current-Idle-TSSI sanity check. */ - if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) { - b43dbg(dev->wl, - "!WARNING! Idle-TSSI phy->cur_idle_tssi " - "measuring failed. (cur=%d, tgt=%d). Disabling TX power " - "adjustment.\n", gphy->cur_idle_tssi, - gphy->tgt_idle_tssi); - gphy->cur_idle_tssi = 0; - } - } - if (phy->radio_ver == 0x2050 && phy->analog == 0) { - b43_radio_mask(dev, 0x0076, 0xFF7B); - } else { - b43_set_txpower_g(dev, &old_bbatt, - &old_rfatt, old_tx_control); - } - } - b43_hardware_pctl_init_gphy(dev); - b43_shm_clear_tssi(dev); -} - -static void b43_phy_initg(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u16 tmp; - - if (phy->rev == 1) - b43_phy_initb5(dev); - else - b43_phy_initb6(dev); - - if (phy->rev >= 2 || phy->gmode) - b43_phy_inita(dev); - - if (phy->rev >= 2) { - b43_phy_write(dev, B43_PHY_ANALOGOVER, 0); - b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0); - } - if (phy->rev == 2) { - b43_phy_write(dev, B43_PHY_RFOVER, 0); - b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); - } - if (phy->rev > 5) { - b43_phy_write(dev, B43_PHY_RFOVER, 0x400); - b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); - } - if (phy->gmode || phy->rev >= 2) { - tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM); - tmp &= B43_PHYVER_VERSION; - if (tmp == 3 || tmp == 5) { - b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); - b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); - } - if (tmp == 5) { - b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); - } - } - if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2) - b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); - if (phy->radio_rev == 8) { - b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80); - b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); - } - if (has_loopback_gain(phy)) - b43_calc_loopback_gain(dev); - - if (phy->radio_rev != 8) { - if (gphy->initval == 0xFFFF) - gphy->initval = b43_radio_init2050(dev); - else - b43_radio_write16(dev, 0x0078, gphy->initval); - } - b43_lo_g_init(dev); - if (has_tx_magnification(phy)) { - b43_radio_write16(dev, 0x52, - (b43_radio_read16(dev, 0x52) & 0xFF00) - | gphy->lo_control->tx_bias | gphy-> - lo_control->tx_magn); - } else { - b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias); - } - if (phy->rev >= 6) { - b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); - } - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) - b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); - else - b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); - if (phy->rev < 2) - b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); - else - b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); - if (phy->gmode || phy->rev >= 2) { - b43_lo_g_adjust(dev); - b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); - } - - if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { - /* The specs state to update the NRSSI LT with - * the value 0x7FFFFFFF here. I think that is some weird - * compiler optimization in the original driver. - * Essentially, what we do here is resetting all NRSSI LT - * entries to -32 (see the clamp_val() in nrssi_hw_update()) - */ - b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? - b43_calc_nrssi_threshold(dev); - } else if (phy->gmode || phy->rev >= 2) { - if (gphy->nrssi[0] == -1000) { - B43_WARN_ON(gphy->nrssi[1] != -1000); - b43_calc_nrssi_slope(dev); - } else - b43_calc_nrssi_threshold(dev); - } - if (phy->radio_rev == 8) - b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230); - b43_phy_init_pctl(dev); - /* FIXME: The spec says in the following if, the 0 should be replaced - 'if OFDM may not be used in the current locale' - but OFDM is legal everywhere */ - if ((dev->dev->chip_id == 0x4306 - && dev->dev->chip_pkg == 2) || 0) { - b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); - b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); - } -} - -void b43_gphy_channel_switch(struct b43_wldev *dev, - unsigned int channel, - bool synthetic_pu_workaround) -{ - if (synthetic_pu_workaround) - b43_synth_pu_workaround(dev, channel); - - b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); - - if (channel == 14) { - if (dev->dev->bus_sprom->country_code == - SSB_SPROM1CCODE_JAPAN) - b43_hf_write(dev, - b43_hf_read(dev) & ~B43_HF_ACPR); - else - b43_hf_write(dev, - b43_hf_read(dev) | B43_HF_ACPR); - b43_write16(dev, B43_MMIO_CHANNEL_EXT, - b43_read16(dev, B43_MMIO_CHANNEL_EXT) - | (1 << 11)); - } else { - b43_write16(dev, B43_MMIO_CHANNEL_EXT, - b43_read16(dev, B43_MMIO_CHANNEL_EXT) - & 0xF7BF); - } -} - -static void default_baseband_attenuation(struct b43_wldev *dev, - struct b43_bbatt *bb) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->radio_ver == 0x2050 && phy->radio_rev < 6) - bb->att = 0; - else - bb->att = 2; -} - -static void default_radio_attenuation(struct b43_wldev *dev, - struct b43_rfatt *rf) -{ - struct b43_bus_dev *bdev = dev->dev; - struct b43_phy *phy = &dev->phy; - - rf->with_padmix = false; - - if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && - dev->dev->board_type == SSB_BOARD_BCM4309G) { - if (dev->dev->board_rev < 0x43) { - rf->att = 2; - return; - } else if (dev->dev->board_rev < 0x51) { - rf->att = 3; - return; - } - } - - if (phy->type == B43_PHYTYPE_A) { - rf->att = 0x60; - return; - } - - switch (phy->radio_ver) { - case 0x2053: - switch (phy->radio_rev) { - case 1: - rf->att = 6; - return; - } - break; - case 0x2050: - switch (phy->radio_rev) { - case 0: - rf->att = 5; - return; - case 1: - if (phy->type == B43_PHYTYPE_G) { - if (bdev->board_vendor == SSB_BOARDVENDOR_BCM - && bdev->board_type == SSB_BOARD_BCM4309G - && bdev->board_rev >= 30) - rf->att = 3; - else if (bdev->board_vendor == - SSB_BOARDVENDOR_BCM - && bdev->board_type == - SSB_BOARD_BU4306) - rf->att = 3; - else - rf->att = 1; - } else { - if (bdev->board_vendor == SSB_BOARDVENDOR_BCM - && bdev->board_type == SSB_BOARD_BCM4309G - && bdev->board_rev >= 30) - rf->att = 7; - else - rf->att = 6; - } - return; - case 2: - if (phy->type == B43_PHYTYPE_G) { - if (bdev->board_vendor == SSB_BOARDVENDOR_BCM - && bdev->board_type == SSB_BOARD_BCM4309G - && bdev->board_rev >= 30) - rf->att = 3; - else if (bdev->board_vendor == - SSB_BOARDVENDOR_BCM - && bdev->board_type == - SSB_BOARD_BU4306) - rf->att = 5; - else if (bdev->chip_id == 0x4320) - rf->att = 4; - else - rf->att = 3; - } else - rf->att = 6; - return; - case 3: - rf->att = 5; - return; - case 4: - case 5: - rf->att = 1; - return; - case 6: - case 7: - rf->att = 5; - return; - case 8: - rf->att = 0xA; - rf->with_padmix = true; - return; - case 9: - default: - rf->att = 5; - return; - } - } - rf->att = 5; -} - -static u16 default_tx_control(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->radio_ver != 0x2050) - return 0; - if (phy->radio_rev == 1) - return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX; - if (phy->radio_rev < 6) - return B43_TXCTL_PA2DB; - if (phy->radio_rev == 8) - return B43_TXCTL_TXMIX; - return 0; -} - -static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - u8 ret = 0; - u16 saved, rssi, temp; - int i, j = 0; - - saved = b43_phy_read(dev, 0x0403); - b43_switch_channel(dev, channel); - b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5); - if (gphy->aci_hw_rssi) - rssi = b43_phy_read(dev, 0x048A) & 0x3F; - else - rssi = saved & 0x3F; - /* clamp temp to signed 5bit */ - if (rssi > 32) - rssi -= 64; - for (i = 0; i < 100; i++) { - temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F; - if (temp > 32) - temp -= 64; - if (temp < rssi) - j++; - if (j >= 20) - ret = 1; - } - b43_phy_write(dev, 0x0403, saved); - - return ret; -} - -static u8 b43_gphy_aci_scan(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u8 ret[13]; - unsigned int channel = phy->channel; - unsigned int i, j, start, end; - - if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0))) - return 0; - - b43_phy_lock(dev); - b43_radio_lock(dev); - b43_phy_mask(dev, 0x0802, 0xFFFC); - b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); - b43_set_all_gains(dev, 3, 8, 1); - - start = (channel - 5 > 0) ? channel - 5 : 1; - end = (channel + 5 < 14) ? channel + 5 : 13; - - for (i = start; i <= end; i++) { - if (abs(channel - i) > 2) - ret[i - 1] = b43_gphy_aci_detect(dev, i); - } - b43_switch_channel(dev, channel); - b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003); - b43_phy_mask(dev, 0x0403, 0xFFF8); - b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); - b43_set_original_gains(dev); - for (i = 0; i < 13; i++) { - if (!ret[i]) - continue; - end = (i + 5 < 13) ? i + 5 : 13; - for (j = i; j < end; j++) - ret[j] = 1; - } - b43_radio_unlock(dev); - b43_phy_unlock(dev); - - return ret[channel - 1]; -} - -static s32 b43_tssi2dbm_ad(s32 num, s32 den) -{ - if (num < 0) - return num / den; - else - return (num + den / 2) / den; -} - -static s8 b43_tssi2dbm_entry(s8 entry[], u8 index, - s16 pab0, s16 pab1, s16 pab2) -{ - s32 m1, m2, f = 256, q, delta; - s8 i = 0; - - m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32); - m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1); - do { - if (i > 15) - return -EINVAL; - q = b43_tssi2dbm_ad(f * 4096 - - b43_tssi2dbm_ad(m2 * f, 16) * f, 2048); - delta = abs(q - f); - f = q; - i++; - } while (delta >= 2); - entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128); - return 0; -} - -u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, - s16 pab0, s16 pab1, s16 pab2) -{ - unsigned int i; - u8 *tab; - int err; - - tab = kmalloc(64, GFP_KERNEL); - if (!tab) { - b43err(dev->wl, "Could not allocate memory " - "for tssi2dbm table\n"); - return NULL; - } - for (i = 0; i < 64; i++) { - err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2); - if (err) { - b43err(dev->wl, "Could not generate " - "tssi2dBm table\n"); - kfree(tab); - return NULL; - } - } - - return tab; -} - -/* Initialise the TSSI->dBm lookup table */ -static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - s16 pab0, pab1, pab2; - - pab0 = (s16) (dev->dev->bus_sprom->pa0b0); - pab1 = (s16) (dev->dev->bus_sprom->pa0b1); - pab2 = (s16) (dev->dev->bus_sprom->pa0b2); - - B43_WARN_ON((dev->dev->chip_id == 0x4301) && - (phy->radio_ver != 0x2050)); /* Not supported anymore */ - - gphy->dyn_tssi_tbl = false; - - if (pab0 != 0 && pab1 != 0 && pab2 != 0 && - pab0 != -1 && pab1 != -1 && pab2 != -1) { - /* The pabX values are set in SPROM. Use them. */ - if ((s8) dev->dev->bus_sprom->itssi_bg != 0 && - (s8) dev->dev->bus_sprom->itssi_bg != -1) { - gphy->tgt_idle_tssi = - (s8) (dev->dev->bus_sprom->itssi_bg); - } else - gphy->tgt_idle_tssi = 62; - gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, - pab1, pab2); - if (!gphy->tssi2dbm) - return -ENOMEM; - gphy->dyn_tssi_tbl = true; - } else { - /* pabX values not set in SPROM. */ - gphy->tgt_idle_tssi = 52; - gphy->tssi2dbm = b43_tssi2dbm_g_table; - } - - return 0; -} - -static int b43_gphy_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_g *gphy; - struct b43_txpower_lo_control *lo; - int err; - - gphy = kzalloc(sizeof(*gphy), GFP_KERNEL); - if (!gphy) { - err = -ENOMEM; - goto error; - } - dev->phy.g = gphy; - - lo = kzalloc(sizeof(*lo), GFP_KERNEL); - if (!lo) { - err = -ENOMEM; - goto err_free_gphy; - } - gphy->lo_control = lo; - - err = b43_gphy_init_tssi2dbm_table(dev); - if (err) - goto err_free_lo; - - return 0; - -err_free_lo: - kfree(lo); -err_free_gphy: - kfree(gphy); -error: - return err; -} - -static void b43_gphy_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - const void *tssi2dbm; - int tgt_idle_tssi; - struct b43_txpower_lo_control *lo; - unsigned int i; - - /* tssi2dbm table is constant, so it is initialized at alloc time. - * Save a copy of the pointer. */ - tssi2dbm = gphy->tssi2dbm; - tgt_idle_tssi = gphy->tgt_idle_tssi; - /* Save the LO pointer. */ - lo = gphy->lo_control; - - /* Zero out the whole PHY structure. */ - memset(gphy, 0, sizeof(*gphy)); - - /* Restore pointers. */ - gphy->tssi2dbm = tssi2dbm; - gphy->tgt_idle_tssi = tgt_idle_tssi; - gphy->lo_control = lo; - - memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig)); - - /* NRSSI */ - for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++) - gphy->nrssi[i] = -1000; - for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++) - gphy->nrssi_lt[i] = i; - - gphy->lofcal = 0xFFFF; - gphy->initval = 0xFFFF; - - gphy->interfmode = B43_INTERFMODE_NONE; - - /* OFDM-table address caching. */ - gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; - - gphy->average_tssi = 0xFF; - - /* Local Osciallator structure */ - lo->tx_bias = 0xFF; - INIT_LIST_HEAD(&lo->calib_list); -} - -static void b43_gphy_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - - kfree(gphy->lo_control); - - if (gphy->dyn_tssi_tbl) - kfree(gphy->tssi2dbm); - gphy->dyn_tssi_tbl = false; - gphy->tssi2dbm = NULL; - - kfree(gphy); - dev->phy.g = NULL; -} - -static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - struct b43_txpower_lo_control *lo = gphy->lo_control; - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - - default_baseband_attenuation(dev, &gphy->bbatt); - default_radio_attenuation(dev, &gphy->rfatt); - gphy->tx_control = (default_tx_control(dev) << 4); - generate_rfatt_list(dev, &lo->rfatt_list); - generate_bbatt_list(dev, &lo->bbatt_list); - - /* Commit previous writes */ - b43_read32(dev, B43_MMIO_MACCTL); - - if (phy->rev == 1) { - /* Workaround: Temporarly disable gmode through the early init - * phase, as the gmode stuff is not needed for phy rev 1 */ - phy->gmode = false; - b43_wireless_core_reset(dev, 0); - b43_phy_initg(dev); - phy->gmode = true; - b43_wireless_core_reset(dev, 1); - } - - return 0; -} - -static int b43_gphy_op_init(struct b43_wldev *dev) -{ - b43_phy_initg(dev); - - return 0; -} - -static void b43_gphy_op_exit(struct b43_wldev *dev) -{ - b43_lo_g_cleanup(dev); -} - -static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - return b43_read16(dev, B43_MMIO_PHY_DATA); -} - -static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, value); -} - -static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - /* G-PHY needs 0x80 for read access. */ - reg |= 0x80; - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); -} - -static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); -} - -static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev) -{ - return (dev->phy.rev >= 6); -} - -static void b43_gphy_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - unsigned int channel; - - might_sleep(); - - if (!blocked) { - /* Turn radio ON */ - if (phy->radio_on) - return; - - b43_phy_write(dev, 0x0015, 0x8000); - b43_phy_write(dev, 0x0015, 0xCC00); - b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000)); - if (gphy->radio_off_context.valid) { - /* Restore the RFover values. */ - b43_phy_write(dev, B43_PHY_RFOVER, - gphy->radio_off_context.rfover); - b43_phy_write(dev, B43_PHY_RFOVERVAL, - gphy->radio_off_context.rfoverval); - gphy->radio_off_context.valid = false; - } - channel = phy->channel; - b43_gphy_channel_switch(dev, 6, 1); - b43_gphy_channel_switch(dev, channel, 0); - } else { - /* Turn radio OFF */ - u16 rfover, rfoverval; - - rfover = b43_phy_read(dev, B43_PHY_RFOVER); - rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); - gphy->radio_off_context.rfover = rfover; - gphy->radio_off_context.rfoverval = rfoverval; - gphy->radio_off_context.valid = true; - b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); - b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); - } -} - -static int b43_gphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - if ((new_channel < 1) || (new_channel > 14)) - return -EINVAL; - b43_gphy_channel_switch(dev, new_channel, 0); - - return 0; -} - -static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev) -{ - return 1; /* Default to channel 1 */ -} - -static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) -{ - struct b43_phy *phy = &dev->phy; - u16 tmp; - int autodiv = 0; - - if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1) - autodiv = 1; - - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); - - b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, - (autodiv ? B43_ANTENNA_AUTO1 : antenna) << - B43_PHY_BBANDCFG_RXANT_SHIFT); - - if (autodiv) { - tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); - if (antenna == B43_ANTENNA_AUTO1) - tmp &= ~B43_PHY_ANTDWELL_AUTODIV1; - else - tmp |= B43_PHY_ANTDWELL_AUTODIV1; - b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); - } - - tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT); - if (autodiv) - tmp |= B43_PHY_ANTWRSETT_ARXDIV; - else - tmp &= ~B43_PHY_ANTWRSETT_ARXDIV; - b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp); - - if (autodiv) - b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV); - else { - b43_phy_mask(dev, B43_PHY_ANTWRSETT, - B43_PHY_ANTWRSETT_ARXDIV); - } - - if (phy->rev >= 2) { - b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10); - b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15); - - if (phy->rev == 2) - b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); - else - b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); - } - if (phy->rev >= 6) - b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC); - - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); -} - -static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev, - enum b43_interference_mitigation mode) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - int currentmode; - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - if ((phy->rev == 0) || (!phy->gmode)) - return -ENODEV; - - gphy->aci_wlan_automatic = false; - switch (mode) { - case B43_INTERFMODE_AUTOWLAN: - gphy->aci_wlan_automatic = true; - if (gphy->aci_enable) - mode = B43_INTERFMODE_MANUALWLAN; - else - mode = B43_INTERFMODE_NONE; - break; - case B43_INTERFMODE_NONE: - case B43_INTERFMODE_NONWLAN: - case B43_INTERFMODE_MANUALWLAN: - break; - default: - return -EINVAL; - } - - currentmode = gphy->interfmode; - if (currentmode == mode) - return 0; - if (currentmode != B43_INTERFMODE_NONE) - b43_radio_interference_mitigation_disable(dev, currentmode); - - if (mode == B43_INTERFMODE_NONE) { - gphy->aci_enable = false; - gphy->aci_hw_rssi = false; - } else - b43_radio_interference_mitigation_enable(dev, mode); - gphy->interfmode = mode; - - return 0; -} - -/* http://bcm-specs.sipsolutions.net/EstimatePowerOut - * This function converts a TSSI value to dBm in Q5.2 - */ -static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) -{ - struct b43_phy_g *gphy = dev->phy.g; - s8 dbm; - s32 tmp; - - tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi); - tmp = clamp_val(tmp, 0x00, 0x3F); - dbm = gphy->tssi2dbm[tmp]; - - return dbm; -} - -static void b43_put_attenuation_into_ranges(struct b43_wldev *dev, - int *_bbatt, int *_rfatt) -{ - int rfatt = *_rfatt; - int bbatt = *_bbatt; - struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; - - /* Get baseband and radio attenuation values into their permitted ranges. - * Radio attenuation affects power level 4 times as much as baseband. */ - - /* Range constants */ - const int rf_min = lo->rfatt_list.min_val; - const int rf_max = lo->rfatt_list.max_val; - const int bb_min = lo->bbatt_list.min_val; - const int bb_max = lo->bbatt_list.max_val; - - while (1) { - if (rfatt > rf_max && bbatt > bb_max - 4) - break; /* Can not get it into ranges */ - if (rfatt < rf_min && bbatt < bb_min + 4) - break; /* Can not get it into ranges */ - if (bbatt > bb_max && rfatt > rf_max - 1) - break; /* Can not get it into ranges */ - if (bbatt < bb_min && rfatt < rf_min + 1) - break; /* Can not get it into ranges */ - - if (bbatt > bb_max) { - bbatt -= 4; - rfatt += 1; - continue; - } - if (bbatt < bb_min) { - bbatt += 4; - rfatt -= 1; - continue; - } - if (rfatt > rf_max) { - rfatt -= 1; - bbatt += 4; - continue; - } - if (rfatt < rf_min) { - rfatt += 1; - bbatt -= 4; - continue; - } - break; - } - - *_rfatt = clamp_val(rfatt, rf_min, rf_max); - *_bbatt = clamp_val(bbatt, bb_min, bb_max); -} - -static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - int rfatt, bbatt; - u8 tx_control; - - b43_mac_suspend(dev); - - /* Calculate the new attenuation values. */ - bbatt = gphy->bbatt.att; - bbatt += gphy->bbatt_delta; - rfatt = gphy->rfatt.att; - rfatt += gphy->rfatt_delta; - - b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); - tx_control = gphy->tx_control; - if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) { - if (rfatt <= 1) { - if (tx_control == 0) { - tx_control = - B43_TXCTL_PA2DB | - B43_TXCTL_TXMIX; - rfatt += 2; - bbatt += 2; - } else if (dev->dev->bus_sprom-> - boardflags_lo & - B43_BFL_PACTRL) { - bbatt += 4 * (rfatt - 2); - rfatt = 2; - } - } else if (rfatt > 4 && tx_control) { - tx_control = 0; - if (bbatt < 3) { - rfatt -= 3; - bbatt += 2; - } else { - rfatt -= 2; - bbatt -= 2; - } - } - } - /* Save the control values */ - gphy->tx_control = tx_control; - b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); - gphy->rfatt.att = rfatt; - gphy->bbatt.att = bbatt; - - if (b43_debug(dev, B43_DBG_XMITPOWER)) - b43dbg(dev->wl, "Adjusting TX power\n"); - - /* Adjust the hardware */ - b43_phy_lock(dev); - b43_radio_lock(dev); - b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, - gphy->tx_control); - b43_radio_unlock(dev); - b43_phy_unlock(dev); - - b43_mac_enable(dev); -} - -static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev, - bool ignore_tssi) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - unsigned int average_tssi; - int cck_result, ofdm_result; - int estimated_pwr, desired_pwr, pwr_adjust; - int rfatt_delta, bbatt_delta; - unsigned int max_pwr; - - /* First get the average TSSI */ - cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK); - ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G); - if ((cck_result < 0) && (ofdm_result < 0)) { - /* No TSSI information available */ - if (!ignore_tssi) - goto no_adjustment_needed; - cck_result = 0; - ofdm_result = 0; - } - if (cck_result < 0) - average_tssi = ofdm_result; - else if (ofdm_result < 0) - average_tssi = cck_result; - else - average_tssi = (cck_result + ofdm_result) / 2; - /* Merge the average with the stored value. */ - if (likely(gphy->average_tssi != 0xFF)) - average_tssi = (average_tssi + gphy->average_tssi) / 2; - gphy->average_tssi = average_tssi; - B43_WARN_ON(average_tssi >= B43_TSSI_MAX); - - /* Estimate the TX power emission based on the TSSI */ - estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); - - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - max_pwr = dev->dev->bus_sprom->maxpwr_bg; - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) - max_pwr -= 3; /* minus 0.75 */ - if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) { - b43warn(dev->wl, - "Invalid max-TX-power value in SPROM.\n"); - max_pwr = INT_TO_Q52(20); /* fake it */ - dev->dev->bus_sprom->maxpwr_bg = max_pwr; - } - - /* Get desired power (in Q5.2) */ - if (phy->desired_txpower < 0) - desired_pwr = INT_TO_Q52(0); - else - desired_pwr = INT_TO_Q52(phy->desired_txpower); - /* And limit it. max_pwr already is Q5.2 */ - desired_pwr = clamp_val(desired_pwr, 0, max_pwr); - if (b43_debug(dev, B43_DBG_XMITPOWER)) { - b43dbg(dev->wl, - "[TX power] current = " Q52_FMT - " dBm, desired = " Q52_FMT - " dBm, max = " Q52_FMT "\n", - Q52_ARG(estimated_pwr), - Q52_ARG(desired_pwr), - Q52_ARG(max_pwr)); - } - - /* Calculate the adjustment delta. */ - pwr_adjust = desired_pwr - estimated_pwr; - if (pwr_adjust == 0) - goto no_adjustment_needed; - - /* RF attenuation delta. */ - rfatt_delta = ((pwr_adjust + 7) / 8); - /* Lower attenuation => Bigger power output. Negate it. */ - rfatt_delta = -rfatt_delta; - - /* Baseband attenuation delta. */ - bbatt_delta = pwr_adjust / 2; - /* Lower attenuation => Bigger power output. Negate it. */ - bbatt_delta = -bbatt_delta; - /* RF att affects power level 4 times as much as - * Baseband attennuation. Subtract it. */ - bbatt_delta -= 4 * rfatt_delta; - -#if B43_DEBUG - if (b43_debug(dev, B43_DBG_XMITPOWER)) { - int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust; - b43dbg(dev->wl, - "[TX power deltas] %s" Q52_FMT " dBm => " - "bbatt-delta = %d, rfatt-delta = %d\n", - (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm), - bbatt_delta, rfatt_delta); - } -#endif /* DEBUG */ - - /* So do we finally need to adjust something in hardware? */ - if ((rfatt_delta == 0) && (bbatt_delta == 0)) - goto no_adjustment_needed; - - /* Save the deltas for later when we adjust the power. */ - gphy->bbatt_delta = bbatt_delta; - gphy->rfatt_delta = rfatt_delta; - - /* We need to adjust the TX power on the device. */ - return B43_TXPWR_RES_NEED_ADJUST; - -no_adjustment_needed: - return B43_TXPWR_RES_DONE; -} - -static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - - b43_mac_suspend(dev); - //TODO: update_aci_moving_average - if (gphy->aci_enable && gphy->aci_wlan_automatic) { - if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) { - if (0 /*TODO: bunch of conditions */ ) { - phy->ops->interf_mitigation(dev, - B43_INTERFMODE_MANUALWLAN); - } - } else if (0 /*TODO*/) { - if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev)) - phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); - } - } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN && - phy->rev == 1) { - //TODO: implement rev1 workaround - } - b43_lo_g_maintenance_work(dev); - b43_mac_enable(dev); -} - -static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) - return; - - b43_mac_suspend(dev); - b43_calc_nrssi_slope(dev); - if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { - u8 old_chan = phy->channel; - - /* VCO Calibration */ - if (old_chan >= 8) - b43_switch_channel(dev, 1); - else - b43_switch_channel(dev, 13); - b43_switch_channel(dev, old_chan); - } - b43_mac_enable(dev); -} - -const struct b43_phy_operations b43_phyops_g = { - .allocate = b43_gphy_op_allocate, - .free = b43_gphy_op_free, - .prepare_structs = b43_gphy_op_prepare_structs, - .prepare_hardware = b43_gphy_op_prepare_hardware, - .init = b43_gphy_op_init, - .exit = b43_gphy_op_exit, - .phy_read = b43_gphy_op_read, - .phy_write = b43_gphy_op_write, - .radio_read = b43_gphy_op_radio_read, - .radio_write = b43_gphy_op_radio_write, - .supports_hwpctl = b43_gphy_op_supports_hwpctl, - .software_rfkill = b43_gphy_op_software_rfkill, - .switch_analog = b43_phyop_switch_analog_generic, - .switch_channel = b43_gphy_op_switch_channel, - .get_default_chan = b43_gphy_op_get_default_chan, - .set_rx_antenna = b43_gphy_op_set_rx_antenna, - .interf_mitigation = b43_gphy_op_interf_mitigation, - .recalc_txpower = b43_gphy_op_recalc_txpower, - .adjust_txpower = b43_gphy_op_adjust_txpower, - .pwork_15sec = b43_gphy_op_pwork_15sec, - .pwork_60sec = b43_gphy_op_pwork_60sec, -}; diff --git a/drivers/net/wireless/b43/phy_g.h b/drivers/net/wireless/b43/phy_g.h deleted file mode 100644 index 5413c906a..000000000 --- a/drivers/net/wireless/b43/phy_g.h +++ /dev/null @@ -1,208 +0,0 @@ -#ifndef LINUX_B43_PHY_G_H_ -#define LINUX_B43_PHY_G_H_ - -/* OFDM PHY registers are defined in the A-PHY header. */ -#include "phy_a.h" - -/* CCK (B) PHY Registers */ -#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */ -#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */ -#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */ -#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */ -#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */ -#define B43_PHY_PGACTL_UNKNOWN 0xEFA0 -#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */ -#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */ -#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */ -#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */ -#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35) -#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */ -#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */ -#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */ - -/* Extended G-PHY Registers */ -#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */ -#define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */ -#define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */ -#define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */ -#define B43_PHY_GTABNR_SHIFT 10 -#define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */ -#define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */ -#define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */ -#define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */ -#define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */ -#define B43_PHY_RFOVERVAL_EXTLNA 0x8000 -#define B43_PHY_RFOVERVAL_LNA 0x7000 -#define B43_PHY_RFOVERVAL_LNA_SHIFT 12 -#define B43_PHY_RFOVERVAL_PGA 0x0F00 -#define B43_PHY_RFOVERVAL_PGA_SHIFT 8 -#define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */ -#define B43_PHY_RFOVERVAL_TRSWRX 0x00E0 -#define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */ -#define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */ -#define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */ -#define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */ -#define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */ - - -/*** G-PHY table numbers */ -#define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset)) -#define B43_GTAB_NRSSI B43_GTAB(0x00, 0) -#define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120) -#define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298) - -u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset); -void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value); - - -/* Returns the boolean whether "TX Magnification" is enabled. */ -#define has_tx_magnification(phy) \ - (((phy)->rev >= 2) && \ - ((phy)->radio_ver == 0x2050) && \ - ((phy)->radio_rev == 8)) -/* Card uses the loopback gain stuff */ -#define has_loopback_gain(phy) \ - (((phy)->rev > 1) || ((phy)->gmode)) - -/* Radio Attenuation (RF Attenuation) */ -struct b43_rfatt { - u8 att; /* Attenuation value */ - bool with_padmix; /* Flag, PAD Mixer enabled. */ -}; -struct b43_rfatt_list { - /* Attenuation values list */ - const struct b43_rfatt *list; - u8 len; - /* Minimum/Maximum attenuation values */ - u8 min_val; - u8 max_val; -}; - -/* Returns true, if the values are the same. */ -static inline bool b43_compare_rfatt(const struct b43_rfatt *a, - const struct b43_rfatt *b) -{ - return ((a->att == b->att) && - (a->with_padmix == b->with_padmix)); -} - -/* Baseband Attenuation */ -struct b43_bbatt { - u8 att; /* Attenuation value */ -}; -struct b43_bbatt_list { - /* Attenuation values list */ - const struct b43_bbatt *list; - u8 len; - /* Minimum/Maximum attenuation values */ - u8 min_val; - u8 max_val; -}; - -/* Returns true, if the values are the same. */ -static inline bool b43_compare_bbatt(const struct b43_bbatt *a, - const struct b43_bbatt *b) -{ - return (a->att == b->att); -} - -/* tx_control bits. */ -#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */ -#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */ -#define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */ - -struct b43_txpower_lo_control; - -struct b43_phy_g { - /* ACI (adjacent channel interference) flags. */ - bool aci_enable; - bool aci_wlan_automatic; - bool aci_hw_rssi; - - /* Radio switched on/off */ - bool radio_on; - struct { - /* Values saved when turning the radio off. - * They are needed when turning it on again. */ - bool valid; - u16 rfover; - u16 rfoverval; - } radio_off_context; - - u16 minlowsig[2]; - u16 minlowsigpos[2]; - - /* Pointer to the table used to convert a - * TSSI value to dBm-Q5.2 */ - const s8 *tssi2dbm; - /* tssi2dbm is kmalloc()ed. Only used for free()ing. */ - bool dyn_tssi_tbl; - /* Target idle TSSI */ - int tgt_idle_tssi; - /* Current idle TSSI */ - int cur_idle_tssi; - /* The current average TSSI. */ - u8 average_tssi; - /* Current TX power level attenuation control values */ - struct b43_bbatt bbatt; - struct b43_rfatt rfatt; - u8 tx_control; /* B43_TXCTL_XXX */ - /* The calculated attenuation deltas that are used later - * when adjusting the actual power output. */ - int bbatt_delta; - int rfatt_delta; - - /* LocalOscillator control values. */ - struct b43_txpower_lo_control *lo_control; - /* Values from b43_calc_loopback_gain() */ - s16 max_lb_gain; /* Maximum Loopback gain in hdB */ - s16 trsw_rx_gain; /* TRSW RX gain in hdB */ - s16 lna_lod_gain; /* LNA lod */ - s16 lna_gain; /* LNA */ - s16 pga_gain; /* PGA */ - - /* Current Interference Mitigation mode */ - int interfmode; - /* Stack of saved values from the Interference Mitigation code. - * Each value in the stack is laid out as follows: - * bit 0-11: offset - * bit 12-15: register ID - * bit 16-32: value - * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT - */ -#define B43_INTERFSTACK_SIZE 26 - u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure - - /* Saved values from the NRSSI Slope calculation */ - s16 nrssi[2]; - s32 nrssislope; - /* In memory nrssi lookup table. */ - s8 nrssi_lt[64]; - - u16 lofcal; - - u16 initval; //FIXME rename? - - /* The device does address auto increment for the OFDM tables. - * We cache the previously used address here and omit the address - * write on the next table access, if possible. */ - u16 ofdmtab_addr; /* The address currently set in hardware. */ - enum { /* The last data flow direction. */ - B43_OFDMTAB_DIRECTION_UNKNOWN = 0, - B43_OFDMTAB_DIRECTION_READ, - B43_OFDMTAB_DIRECTION_WRITE, - } ofdmtab_addr_direction; -}; - -void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, - u16 baseband_attenuation); -void b43_gphy_channel_switch(struct b43_wldev *dev, - unsigned int channel, - bool synthetic_pu_workaround); -u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, - s16 pab0, s16 pab1, s16 pab2); - -struct b43_phy_operations; -extern const struct b43_phy_operations b43_phyops_g; - -#endif /* LINUX_B43_PHY_G_H_ */ diff --git a/drivers/net/wireless/b43/phy_ht.c b/drivers/net/wireless/b43/phy_ht.c deleted file mode 100644 index bd6894596..000000000 --- a/drivers/net/wireless/b43/phy_ht.c +++ /dev/null @@ -1,1153 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n HT-PHY support - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/slab.h> - -#include "b43.h" -#include "phy_ht.h" -#include "tables_phy_ht.h" -#include "radio_2059.h" -#include "main.h" - -/* Force values to keep compatibility with wl */ -enum ht_rssi_type { - HT_RSSI_W1 = 0, - HT_RSSI_W2 = 1, - HT_RSSI_NB = 2, - HT_RSSI_IQ = 3, - HT_RSSI_TSSI_2G = 4, - HT_RSSI_TSSI_5G = 5, - HT_RSSI_TBD = 6, -}; - -/************************************************** - * Radio 2059. - **************************************************/ - -static void b43_radio_2059_channel_setup(struct b43_wldev *dev, - const struct b43_phy_ht_channeltab_e_radio2059 *e) -{ - static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, }; - u16 r; - int core; - - b43_radio_write(dev, 0x16, e->radio_syn16); - b43_radio_write(dev, 0x17, e->radio_syn17); - b43_radio_write(dev, 0x22, e->radio_syn22); - b43_radio_write(dev, 0x25, e->radio_syn25); - b43_radio_write(dev, 0x27, e->radio_syn27); - b43_radio_write(dev, 0x28, e->radio_syn28); - b43_radio_write(dev, 0x29, e->radio_syn29); - b43_radio_write(dev, 0x2c, e->radio_syn2c); - b43_radio_write(dev, 0x2d, e->radio_syn2d); - b43_radio_write(dev, 0x37, e->radio_syn37); - b43_radio_write(dev, 0x41, e->radio_syn41); - b43_radio_write(dev, 0x43, e->radio_syn43); - b43_radio_write(dev, 0x47, e->radio_syn47); - - for (core = 0; core < 3; core++) { - r = routing[core]; - b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a); - b43_radio_write(dev, r | 0x58, e->radio_rxtx58); - b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a); - b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a); - b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d); - b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e); - b43_radio_write(dev, r | 0x92, e->radio_rxtx92); - b43_radio_write(dev, r | 0x98, e->radio_rxtx98); - } - - udelay(50); - - /* Calibration */ - b43_radio_mask(dev, R2059_RFPLL_MISC_EN, ~0x1); - b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x4); - b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x4); - b43_radio_set(dev, R2059_RFPLL_MISC_EN, 0x1); - - udelay(300); -} - -/* Calibrate resistors in LPF of PLL? */ -static void b43_radio_2059_rcal(struct b43_wldev *dev) -{ - /* Enable */ - b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x1); - usleep_range(10, 20); - - b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1); - b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2); - - /* Start */ - b43_radio_set(dev, R2059_C3 | R2059_RCAL_CONFIG, 0x2); - usleep_range(100, 200); - - /* Stop */ - b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x2); - - if (!b43_radio_wait_value(dev, R2059_C3 | R2059_RCAL_STATUS, 1, 1, 100, - 1000000)) - b43err(dev->wl, "Radio 0x2059 rcal timeout\n"); - - /* Disable */ - b43_radio_mask(dev, R2059_C3 | R2059_RCAL_CONFIG, ~0x1); - - b43_radio_set(dev, 0xa, 0x60); -} - -/* Calibrate the internal RC oscillator? */ -static void b43_radio_2057_rccal(struct b43_wldev *dev) -{ - const u16 radio_values[3][2] = { - { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, - }; - int i; - - for (i = 0; i < 3; i++) { - b43_radio_write(dev, R2059_RCCAL_MASTER, radio_values[i][0]); - b43_radio_write(dev, R2059_RCCAL_X1, 0x6E); - b43_radio_write(dev, R2059_RCCAL_TRC0, radio_values[i][1]); - - /* Start */ - b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x55); - - /* Wait */ - if (!b43_radio_wait_value(dev, R2059_RCCAL_DONE_OSCCAP, 2, 2, - 500, 5000000)) - b43err(dev->wl, "Radio 0x2059 rccal timeout\n"); - - /* Stop */ - b43_radio_write(dev, R2059_RCCAL_START_R1_Q1_P1, 0x15); - } - - b43_radio_mask(dev, R2059_RCCAL_MASTER, ~0x1); -} - -static void b43_radio_2059_init_pre(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); - b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_FORCE); - b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, ~B43_PHY_HT_RF_CTL_CMD_FORCE); - b43_phy_set(dev, B43_PHY_HT_RF_CTL_CMD, B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); -} - -static void b43_radio_2059_init(struct b43_wldev *dev) -{ - const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 }; - int i; - - /* Prepare (reset?) radio */ - b43_radio_2059_init_pre(dev); - - r2059_upload_inittabs(dev); - - for (i = 0; i < ARRAY_SIZE(routing); i++) - b43_radio_set(dev, routing[i] | 0x146, 0x3); - - /* Post init starts below */ - - b43_radio_set(dev, R2059_RFPLL_MISC_CAL_RESETN, 0x0078); - b43_radio_set(dev, R2059_XTAL_CONFIG2, 0x0080); - msleep(2); - b43_radio_mask(dev, R2059_RFPLL_MISC_CAL_RESETN, ~0x0078); - b43_radio_mask(dev, R2059_XTAL_CONFIG2, ~0x0080); - - if (1) { /* FIXME */ - b43_radio_2059_rcal(dev); - b43_radio_2057_rccal(dev); - } - - b43_radio_mask(dev, R2059_RFPLL_MASTER, ~0x0008); -} - -/************************************************** - * RF - **************************************************/ - -static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq) -{ - u8 i; - - u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE); - b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3); - - b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq); - for (i = 0; i < 200; i++) { - if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) { - i = 0; - break; - } - msleep(1); - } - if (i) - b43err(dev->wl, "Forcing RF sequence timeout\n"); - - b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode); -} - -static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable) -{ - struct b43_phy_ht *htphy = dev->phy.ht; - static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1, - B43_PHY_HT_RF_CTL_INT_C2, - B43_PHY_HT_RF_CTL_INT_C3 }; - int i; - - if (enable) { - for (i = 0; i < 3; i++) - b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]); - } else { - for (i = 0; i < 3; i++) - htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]); - /* TODO: Does 5GHz band use different value (not 0x0400)? */ - for (i = 0; i < 3; i++) - b43_phy_write(dev, regs[i], 0x0400); - } -} - -/************************************************** - * Various PHY ops - **************************************************/ - -static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val) -{ - u16 tmp; - u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN | - B43_PHY_HT_CLASS_CTL_OFDM_EN | - B43_PHY_HT_CLASS_CTL_WAITED_EN; - - tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL); - tmp &= allowed; - tmp &= ~mask; - tmp |= (val & mask); - b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp); - - return tmp; -} - -static void b43_phy_ht_reset_cca(struct b43_wldev *dev) -{ - u16 bbcfg; - - b43_phy_force_clock(dev, true); - bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG); - b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA); - udelay(1); - b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA); - b43_phy_force_clock(dev, false); - - b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); -} - -static void b43_phy_ht_zero_extg(struct b43_wldev *dev) -{ - u8 i, j; - u16 base[] = { 0x40, 0x60, 0x80 }; - - for (i = 0; i < ARRAY_SIZE(base); i++) { - for (j = 0; j < 4; j++) - b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0); - } - - for (i = 0; i < ARRAY_SIZE(base); i++) - b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0); -} - -/* Some unknown AFE (Analog Frondned) op */ -static void b43_phy_ht_afe_unk1(struct b43_wldev *dev) -{ - u8 i; - - static const u16 ctl_regs[3][2] = { - { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 }, - { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 }, - { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3}, - }; - - for (i = 0; i < 3; i++) { - /* TODO: verify masks&sets */ - b43_phy_set(dev, ctl_regs[i][1], 0x4); - b43_phy_set(dev, ctl_regs[i][0], 0x4); - b43_phy_mask(dev, ctl_regs[i][1], ~0x1); - b43_phy_set(dev, ctl_regs[i][0], 0x1); - b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0); - b43_phy_mask(dev, ctl_regs[i][0], ~0x4); - } -} - -static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) -{ - clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES); - clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES); - clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES); -} - -static void b43_phy_ht_bphy_init(struct b43_wldev *dev) -{ - unsigned int i; - u16 val; - - val = 0x1E1F; - for (i = 0; i < 16; i++) { - b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); - val -= 0x202; - } - val = 0x3E3F; - for (i = 0; i < 16; i++) { - b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); - val -= 0x202; - } - b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); -} - -static void b43_phy_ht_bphy_reset(struct b43_wldev *dev, bool reset) -{ - u16 tmp; - - tmp = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, - tmp | B43_PSM_HDR_MAC_PHY_FORCE_CLK); - - /* Put BPHY in or take it out of the reset */ - if (reset) - b43_phy_set(dev, B43_PHY_B_BBCFG, - B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX); - else - b43_phy_mask(dev, B43_PHY_B_BBCFG, - (u16)~(B43_PHY_B_BBCFG_RSTCCA | - B43_PHY_B_BBCFG_RSTRX)); - - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp); -} - -/************************************************** - * Samples - **************************************************/ - -static void b43_phy_ht_stop_playback(struct b43_wldev *dev) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - u16 tmp; - int i; - - tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT); - if (tmp & 0x1) - b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP); - else if (tmp & 0x2) - b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF); - - b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004); - - for (i = 0; i < 3; i++) { - if (phy_ht->bb_mult_save[i] >= 0) { - b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4), - phy_ht->bb_mult_save[i]); - b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4), - phy_ht->bb_mult_save[i]); - } - } -} - -static u16 b43_phy_ht_load_samples(struct b43_wldev *dev) -{ - int i; - u16 len = 20 << 3; - - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400); - - for (i = 0; i < len; i++) { - b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0); - } - - return len; -} - -static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, - u16 wait) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - u16 save_seq_mode; - int i; - - for (i = 0; i < 3; i++) { - if (phy_ht->bb_mult_save[i] < 0) - phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4)); - } - - b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1); - if (loops != 0xFFFF) - loops--; - b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops); - b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait); - - save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE); - b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, - B43_PHY_HT_RF_SEQ_MODE_CA_OVER); - - /* TODO: find out mask bits! Do we need more function arguments? */ - b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); - b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0); - b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0); - b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1); - - for (i = 0; i < 100; i++) { - if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) { - i = 0; - break; - } - udelay(10); - } - if (i) - b43err(dev->wl, "run samples timeout\n"); - - b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode); -} - -static void b43_phy_ht_tx_tone(struct b43_wldev *dev) -{ - u16 samp; - - samp = b43_phy_ht_load_samples(dev); - b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0); -} - -/************************************************** - * RSSI - **************************************************/ - -static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel, - enum ht_rssi_type rssi_type) -{ - static const u16 ctl_regs[3][2] = { - { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, }, - { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, }, - { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, }, - }; - static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, }; - int core; - - if (core_sel == 0) { - b43err(dev->wl, "RSSI selection for core off not implemented yet\n"); - } else { - for (core = 0; core < 3; core++) { - /* Check if caller requested a one specific core */ - if ((core_sel == 1 && core != 0) || - (core_sel == 2 && core != 1) || - (core_sel == 3 && core != 2)) - continue; - - switch (rssi_type) { - case HT_RSSI_TSSI_2G: - b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8); - b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10); - b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9); - b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10); - - b43_radio_set(dev, R2059_C3 | 0xbf, 0x1); - b43_radio_write(dev, radio_r[core] | 0x159, - 0x11); - break; - default: - b43err(dev->wl, "RSSI selection for type %d not implemented yet\n", - rssi_type); - } - } - } -} - -static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type, - s32 *buf, u8 nsamp) -{ - u16 phy_regs_values[12]; - static const u16 phy_regs_to_save[] = { - B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, - 0x848, 0x841, - B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, - 0x868, 0x861, - B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, - 0x888, 0x881, - }; - u16 tmp[3]; - int i; - - for (i = 0; i < 12; i++) - phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]); - - b43_phy_ht_rssi_select(dev, 5, type); - - for (i = 0; i < 6; i++) - buf[i] = 0; - - for (i = 0; i < nsamp; i++) { - tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1); - tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2); - tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3); - - buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2; - buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2; - buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2; - buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2; - buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2; - buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2; - } - - for (i = 0; i < 12; i++) - b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]); -} - -/************************************************** - * Tx/Rx - **************************************************/ - -static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev) -{ - int i; - - for (i = 0; i < 3; i++) { - u16 mask; - u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); - - if (0) /* FIXME */ - mask = 0x2 << (i * 4); - else - mask = 0; - b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask); - - b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); - b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)), - tmp & 0xFF); - b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)), - tmp & 0xFF); - } -} - -static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF | - B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN | - B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN; - static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1, - B43_PHY_HT_TXPCTL_CMD_C2, - B43_PHY_HT_TXPCTL_CMD_C3 }; - static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1, - B43_PHY_HT_TX_PCTL_STATUS_C2, - B43_PHY_HT_TX_PCTL_STATUS_C3 }; - int i; - - if (!enable) { - if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) { - /* We disable enabled TX pwr ctl, save it's state */ - for (i = 0; i < 3; i++) - phy_ht->tx_pwr_idx[i] = - b43_phy_read(dev, status_regs[i]); - } - b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits); - } else { - b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - for (i = 0; i < 3; i++) - b43_phy_write(dev, cmd_regs[i], 0x32); - } - - for (i = 0; i < 3; i++) - if (phy_ht->tx_pwr_idx[i] <= - B43_PHY_HT_TXPCTL_CMD_C1_INIT) - b43_phy_write(dev, cmd_regs[i], - phy_ht->tx_pwr_idx[i]); - } - - phy_ht->tx_pwr_ctl = enable; -} - -static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - static const u16 base[] = { 0x840, 0x860, 0x880 }; - u16 save_regs[3][3]; - s32 rssi_buf[6]; - int core; - - for (core = 0; core < 3; core++) { - save_regs[core][1] = b43_phy_read(dev, base[core] + 6); - save_regs[core][2] = b43_phy_read(dev, base[core] + 7); - save_regs[core][0] = b43_phy_read(dev, base[core] + 0); - - b43_phy_write(dev, base[core] + 6, 0); - b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */ - b43_phy_set(dev, base[core] + 0, 0x0400); - b43_phy_set(dev, base[core] + 0, 0x1000); - } - - b43_phy_ht_tx_tone(dev); - udelay(20); - b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1); - b43_phy_ht_stop_playback(dev); - b43_phy_ht_reset_cca(dev); - - phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff; - phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff; - phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff; - - for (core = 0; core < 3; core++) { - b43_phy_write(dev, base[core] + 0, save_regs[core][0]); - b43_phy_write(dev, base[core] + 6, save_regs[core][1]); - b43_phy_write(dev, base[core] + 7, save_regs[core][2]); - } -} - -static void b43_phy_ht_tssi_setup(struct b43_wldev *dev) -{ - static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, }; - int core; - - /* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */ - for (core = 0; core < 3; core++) { - b43_radio_set(dev, 0x8bf, 0x1); - b43_radio_write(dev, routing[core] | 0x0159, 0x0011); - } -} - -static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - u8 *idle = phy_ht->idle_tssi; - u8 target[3]; - s16 a1[3], b0[3], b1[3]; - - u16 freq = dev->phy.chandef->chan->center_freq; - int i, c; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - for (c = 0; c < 3; c++) { - target[c] = sprom->core_pwr_info[c].maxpwr_2g; - a1[c] = sprom->core_pwr_info[c].pa_2g[0]; - b0[c] = sprom->core_pwr_info[c].pa_2g[1]; - b1[c] = sprom->core_pwr_info[c].pa_2g[2]; - } - } else if (freq >= 4900 && freq < 5100) { - for (c = 0; c < 3; c++) { - target[c] = sprom->core_pwr_info[c].maxpwr_5gl; - a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; - b0[c] = sprom->core_pwr_info[c].pa_5gl[1]; - b1[c] = sprom->core_pwr_info[c].pa_5gl[2]; - } - } else if (freq >= 5100 && freq < 5500) { - for (c = 0; c < 3; c++) { - target[c] = sprom->core_pwr_info[c].maxpwr_5g; - a1[c] = sprom->core_pwr_info[c].pa_5g[0]; - b0[c] = sprom->core_pwr_info[c].pa_5g[1]; - b1[c] = sprom->core_pwr_info[c].pa_5g[2]; - } - } else if (freq >= 5500) { - for (c = 0; c < 3; c++) { - target[c] = sprom->core_pwr_info[c].maxpwr_5gh; - a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; - b0[c] = sprom->core_pwr_info[c].pa_5gh[1]; - b1[c] = sprom->core_pwr_info[c].pa_5gh[2]; - } - } else { - target[0] = target[1] = target[2] = 52; - a1[0] = a1[1] = a1[2] = -424; - b0[0] = b0[1] = b0[2] = 5612; - b1[0] = b1[1] = b1[2] = -1393; - } - - b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN); - b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, - ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF); - - /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */ - b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000); - - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, - ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2, - ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3, - ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19); - - b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, - B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF); - - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, - ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1, - idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, - ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2, - idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2, - ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3, - idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT); - - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID, - 0xf0); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2, - 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT); -#if 0 - /* TODO: what to mask/set? */ - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0) - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0) -#endif - - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR, - ~B43_PHY_HT_TXPCTL_TARG_PWR_C1, - target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR, - ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF, - target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT); - b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2, - ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3, - target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT); - - for (c = 0; c < 3; c++) { - s32 num, den, pwr; - u32 regval[64]; - - for (i = 0; i < 64; i++) { - num = 8 * (16 * b0[c] + b1[c] * i); - den = 32768 + a1[c] * i; - pwr = max((4 * num + den / 2) / den, -8); - regval[i] = pwr; - } - b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval); - } -} - -/************************************************** - * Channel switching ops. - **************************************************/ - -static void b43_phy_ht_spur_avoid(struct b43_wldev *dev, - struct ieee80211_channel *new_channel) -{ - struct bcma_device *core = dev->dev->bdev; - int spuravoid = 0; - - /* Check for 13 and 14 is just a guess, we don't have enough logs. */ - if (new_channel->hw_value == 13 || new_channel->hw_value == 14) - spuravoid = 1; - bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false); - bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid); - bcma_core_pll_ctl(core, - B43_BCMA_CLKCTLST_80211_PLL_REQ | - B43_BCMA_CLKCTLST_PHY_PLL_REQ, - B43_BCMA_CLKCTLST_80211_PLL_ST | - B43_BCMA_CLKCTLST_PHY_PLL_ST, false); - - b43_mac_switch_freq(dev, spuravoid); - - b43_wireless_core_phy_pll_reset(dev); - - if (spuravoid) - b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX); - else - b43_phy_mask(dev, B43_PHY_HT_BBCFG, - ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF); - - b43_phy_ht_reset_cca(dev); -} - -static void b43_phy_ht_channel_setup(struct b43_wldev *dev, - const struct b43_phy_ht_channeltab_e_phy *e, - struct ieee80211_channel *new_channel) -{ - if (new_channel->band == IEEE80211_BAND_5GHZ) { - /* Switch to 2 GHz for a moment to access B-PHY regs */ - b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ); - - b43_phy_ht_bphy_reset(dev, true); - - /* Switch to 5 GHz */ - b43_phy_set(dev, B43_PHY_HT_BANDCTL, B43_PHY_HT_BANDCTL_5GHZ); - } else { - /* Switch to 2 GHz */ - b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ); - - b43_phy_ht_bphy_reset(dev, false); - } - - b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1); - b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2); - b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3); - b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4); - b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); - b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); - - if (new_channel->hw_value == 14) { - b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0); - b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800); - } else { - b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, - B43_PHY_HT_CLASS_CTL_OFDM_EN); - if (new_channel->band == IEEE80211_BAND_2GHZ) - b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840); - } - - if (1) /* TODO: On N it's for early devices only, what about HT? */ - b43_phy_ht_tx_power_fix(dev); - - b43_phy_ht_spur_avoid(dev, new_channel); - - b43_phy_write(dev, 0x017e, 0x3830); -} - -static int b43_phy_ht_set_channel(struct b43_wldev *dev, - struct ieee80211_channel *channel, - enum nl80211_channel_type channel_type) -{ - struct b43_phy *phy = &dev->phy; - - const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL; - - if (phy->radio_ver == 0x2059) { - chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev, - channel->center_freq); - if (!chent_r2059) - return -ESRCH; - } else { - return -ESRCH; - } - - /* TODO: In case of N-PHY some bandwidth switching goes here */ - - if (phy->radio_ver == 0x2059) { - b43_radio_2059_channel_setup(dev, chent_r2059); - b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs), - channel); - } else { - return -ESRCH; - } - - return 0; -} - -/************************************************** - * Basic PHY ops. - **************************************************/ - -static int b43_phy_ht_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_ht *phy_ht; - - phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL); - if (!phy_ht) - return -ENOMEM; - dev->phy.ht = phy_ht; - - return 0; -} - -static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_ht *phy_ht = phy->ht; - int i; - - memset(phy_ht, 0, sizeof(*phy_ht)); - - phy_ht->tx_pwr_ctl = true; - for (i = 0; i < 3; i++) - phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1; - - for (i = 0; i < 3; i++) - phy_ht->bb_mult_save[i] = -1; -} - -static int b43_phy_ht_op_init(struct b43_wldev *dev) -{ - struct b43_phy_ht *phy_ht = dev->phy.ht; - u16 tmp; - u16 clip_state[3]; - bool saved_tx_pwr_ctl; - - if (dev->dev->bus_type != B43_BUS_BCMA) { - b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n"); - return -EOPNOTSUPP; - } - - b43_phy_ht_tables_init(dev); - - b43_phy_mask(dev, 0x0be, ~0x2); - b43_phy_set(dev, 0x23f, 0x7ff); - b43_phy_set(dev, 0x240, 0x7ff); - b43_phy_set(dev, 0x241, 0x7ff); - - b43_phy_ht_zero_extg(dev); - - b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); - - b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0); - b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0); - b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0); - - b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); - b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); - b43_phy_write(dev, 0x20d, 0xb8); - b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8); - b43_phy_write(dev, 0x70, 0x50); - b43_phy_write(dev, 0x1ff, 0x30); - - if (0) /* TODO: condition */ - ; /* TODO: PHY op on reg 0x217 */ - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0); - else - b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, - B43_PHY_HT_CLASS_CTL_CCK_EN); - - b43_phy_set(dev, 0xb1, 0x91); - b43_phy_write(dev, 0x32f, 0x0003); - b43_phy_write(dev, 0x077, 0x0010); - b43_phy_write(dev, 0x0b4, 0x0258); - b43_phy_mask(dev, 0x17e, ~0x4000); - - b43_phy_write(dev, 0x0b9, 0x0072); - - b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f); - b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f); - b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f); - - b43_phy_ht_afe_unk1(dev); - - b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111, - 0x777, 0x111, 0x111, 0x777, 0x111, 0x111); - - b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777); - b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777); - - b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02); - b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02); - b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02); - - b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4, - 0x8e, 0x96, 0x96, 0x96); - b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4, - 0x8f, 0x9f, 0x9f, 0x9f); - b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4, - 0x8f, 0x9f, 0x9f, 0x9f); - - b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2); - b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2); - b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2); - - b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e); - b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e); - b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46); - b43_phy_maskset(dev, 0x0283, 0xff00, 0x40); - - b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4, - 0x09, 0x0e, 0x13, 0x18); - b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4, - 0x09, 0x0e, 0x13, 0x18); - /* TODO: Did wl mean 2 instead of 40? */ - b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4, - 0x09, 0x0e, 0x13, 0x18); - - b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd); - b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd); - b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd); - - b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1); - b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1); - b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1); - b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1); - - /* Copy some tables entries */ - tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144)); - b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp); - tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154)); - b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp); - tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164)); - b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp); - - /* Reset CCA */ - b43_phy_force_clock(dev, true); - tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG); - b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA); - b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA); - b43_phy_force_clock(dev, false); - - b43_mac_phy_clock_set(dev, true); - - b43_phy_ht_pa_override(dev, false); - b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX); - b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); - b43_phy_ht_pa_override(dev, true); - - /* TODO: Should we restore it? Or store it in global PHY info? */ - b43_phy_ht_classifier(dev, 0, 0); - b43_phy_ht_read_clip_detection(dev, clip_state); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_phy_ht_bphy_init(dev); - - b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), - B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late); - - saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl; - b43_phy_ht_tx_power_fix(dev); - b43_phy_ht_tx_power_ctl(dev, false); - b43_phy_ht_tx_power_ctl_idle_tssi(dev); - b43_phy_ht_tx_power_ctl_setup(dev); - b43_phy_ht_tssi_setup(dev); - b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl); - - return 0; -} - -static void b43_phy_ht_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_ht *phy_ht = phy->ht; - - kfree(phy_ht); - phy->ht = NULL; -} - -/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ -static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) - b43err(dev->wl, "MAC not suspended\n"); - - if (blocked) { - b43_phy_mask(dev, B43_PHY_HT_RF_CTL_CMD, - ~B43_PHY_HT_RF_CTL_CMD_CHIP0_PU); - } else { - if (dev->phy.radio_ver == 0x2059) - b43_radio_2059_init(dev); - else - B43_WARN_ON(1); - - b43_switch_channel(dev, dev->phy.channel); - } -} - -static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on) -{ - if (on) { - b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd); - b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000); - b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd); - b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000); - b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd); - b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000); - } else { - b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff); - b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd); - b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff); - b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd); - b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff); - b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd); - } -} - -static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; - enum nl80211_channel_type channel_type = - cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if ((new_channel < 1) || (new_channel > 14)) - return -EINVAL; - } else { - return -EINVAL; - } - - return b43_phy_ht_set_channel(dev, channel, channel_type); -} - -static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - return 11; - return 36; -} - -/************************************************** - * R/W ops. - **************************************************/ - -static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, - u16 set) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, - (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); -} - -static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* HT-PHY needs 0x200 for read access */ - reg |= 0x200; - - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO24_DATA); -} - -static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg, - u16 value) -{ - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO24_DATA, value); -} - -static enum b43_txpwr_result -b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi) -{ - return B43_TXPWR_RES_DONE; -} - -static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev) -{ -} - -/************************************************** - * PHY ops struct. - **************************************************/ - -const struct b43_phy_operations b43_phyops_ht = { - .allocate = b43_phy_ht_op_allocate, - .free = b43_phy_ht_op_free, - .prepare_structs = b43_phy_ht_op_prepare_structs, - .init = b43_phy_ht_op_init, - .phy_maskset = b43_phy_ht_op_maskset, - .radio_read = b43_phy_ht_op_radio_read, - .radio_write = b43_phy_ht_op_radio_write, - .software_rfkill = b43_phy_ht_op_software_rfkill, - .switch_analog = b43_phy_ht_op_switch_analog, - .switch_channel = b43_phy_ht_op_switch_channel, - .get_default_chan = b43_phy_ht_op_get_default_chan, - .recalc_txpower = b43_phy_ht_op_recalc_txpower, - .adjust_txpower = b43_phy_ht_op_adjust_txpower, -}; diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h deleted file mode 100644 index c086f56ce..000000000 --- a/drivers/net/wireless/b43/phy_ht.h +++ /dev/null @@ -1,141 +0,0 @@ -#ifndef B43_PHY_HT_H_ -#define B43_PHY_HT_H_ - -#include "phy_common.h" - - -#define B43_PHY_HT_BBCFG 0x001 /* BB config */ -#define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ -#define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ -#define B43_PHY_HT_BANDCTL 0x009 /* Band control */ -#define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ -#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ -#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ -#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ -#define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */ -#define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */ -#define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */ -#define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */ -#define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */ -#define B43_PHY_HT_SAMP_CMD 0x0C3 /* Sample command */ -#define B43_PHY_HT_SAMP_CMD_STOP 0x0002 /* Stop */ -#define B43_PHY_HT_SAMP_LOOP_CNT 0x0C4 /* Sample loop count */ -#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ -#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ -#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ -#define B43_PHY_HT_EST_PWR_C1 0x118 -#define B43_PHY_HT_EST_PWR_C2 0x119 -#define B43_PHY_HT_EST_PWR_C3 0x11A -#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ -#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ -#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ -#define B43_PHY_HT_BW1 0x1CE -#define B43_PHY_HT_BW2 0x1CF -#define B43_PHY_HT_BW3 0x1D0 -#define B43_PHY_HT_BW4 0x1D1 -#define B43_PHY_HT_BW5 0x1D2 -#define B43_PHY_HT_BW6 0x1D3 -#define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ -#define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ -#define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ -#define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ -#define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ -#define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */ -#define B43_PHY_HT_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ -#define B43_PHY_HT_TXPCTL_N_TSSID_SHIFT 0 -#define B43_PHY_HT_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ -#define B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT 8 -#define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */ -#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1 0x003F -#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT 0 -#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2 0x3F00 -#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT 8 -#define B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF 0x8000 /* Raw TSSI offset bin format */ -#define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */ -#define B43_PHY_HT_TXPCTL_TARG_PWR_C1 0x00FF /* Power 0 */ -#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 -#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ -#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 -#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED -#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE -#define B43_PHY_HT_TXPCTL_CMD_C2 0x222 -#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F -#define B43_PHY_HT_RSSI_C1 0x219 -#define B43_PHY_HT_RSSI_C2 0x21A -#define B43_PHY_HT_RSSI_C3 0x21B - -#define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) -#define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) -#define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) - -#define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) -#define B43_PHY_HT_RF_SEQ_MODE_CA_OVER 0x0001 /* Core active override */ -#define B43_PHY_HT_RF_SEQ_MODE_TR_OVER 0x0002 /* Trigger override */ -#define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) -#define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ -#define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ -#define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ -#define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ -#define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ -#define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ -#define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) -/* Values for the status are the same as for the trigger */ - -#define B43_PHY_HT_RF_CTL_CMD 0x810 -#define B43_PHY_HT_RF_CTL_CMD_FORCE 0x0001 -#define B43_PHY_HT_RF_CTL_CMD_CHIP0_PU 0x0002 - -#define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c) -#define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c) -#define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c) - -#define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) -#define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) -#define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) -#define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) -#define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) -#define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) - -#define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) -#define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F -#define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */ -#define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3 0x003F -#define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT 0 -#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ -#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF -#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 -#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169) - -#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) -#define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ -#define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ -#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) - - -/* Values for PHY registers used on channel switching */ -struct b43_phy_ht_channeltab_e_phy { - u16 bw1; - u16 bw2; - u16 bw3; - u16 bw4; - u16 bw5; - u16 bw6; -}; - - -struct b43_phy_ht { - u16 rf_ctl_int_save[3]; - - bool tx_pwr_ctl; - u8 tx_pwr_idx[3]; - - s32 bb_mult_save[3]; - - u8 idle_tssi[3]; -}; - - -struct b43_phy_operations; -extern const struct b43_phy_operations b43_phyops_ht; - -#endif /* B43_PHY_HT_H_ */ diff --git a/drivers/net/wireless/b43/phy_lcn.c b/drivers/net/wireless/b43/phy_lcn.c deleted file mode 100644 index 97461ccf3..000000000 --- a/drivers/net/wireless/b43/phy_lcn.c +++ /dev/null @@ -1,855 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n LCN-PHY support - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - - This file incorporates work covered by the following copyright and - permission notice: - - Copyright (c) 2010 Broadcom Corporation - - Permission to use, copy, modify, and/or distribute this software for any - purpose with or without fee is hereby granted, provided that the above - copyright notice and this permission notice appear in all copies. -*/ - -#include <linux/slab.h> - -#include "b43.h" -#include "phy_lcn.h" -#include "tables_phy_lcn.h" -#include "main.h" - -struct lcn_tx_gains { - u16 gm_gain; - u16 pga_gain; - u16 pad_gain; - u16 dac_gain; -}; - -struct lcn_tx_iir_filter { - u8 type; - u16 values[16]; -}; - -enum lcn_sense_type { - B43_SENSE_TEMP, - B43_SENSE_VBAT, -}; - -/************************************************** - * Radio 2064. - **************************************************/ - -/* wlc_lcnphy_radio_2064_channel_tune_4313 */ -static void b43_radio_2064_channel_setup(struct b43_wldev *dev) -{ - u16 save[2]; - - b43_radio_set(dev, 0x09d, 0x4); - b43_radio_write(dev, 0x09e, 0xf); - - /* Channel specific values in theory, in practice always the same */ - b43_radio_write(dev, 0x02a, 0xb); - b43_radio_maskset(dev, 0x030, ~0x3, 0xa); - b43_radio_maskset(dev, 0x091, ~0x3, 0); - b43_radio_maskset(dev, 0x038, ~0xf, 0x7); - b43_radio_maskset(dev, 0x030, ~0xc, 0x8); - b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); - b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); - b43_radio_write(dev, 0x06c, 0x80); - - save[0] = b43_radio_read(dev, 0x044); - save[1] = b43_radio_read(dev, 0x12b); - - b43_radio_set(dev, 0x044, 0x7); - b43_radio_set(dev, 0x12b, 0xe); - - /* TODO */ - - b43_radio_write(dev, 0x040, 0xfb); - - b43_radio_write(dev, 0x041, 0x9a); - b43_radio_write(dev, 0x042, 0xa3); - b43_radio_write(dev, 0x043, 0x0c); - - /* TODO */ - - b43_radio_set(dev, 0x044, 0x0c); - udelay(1); - - b43_radio_write(dev, 0x044, save[0]); - b43_radio_write(dev, 0x12b, save[1]); - - if (dev->phy.rev == 1) { - /* brcmsmac uses outdated 0x3 for 0x038 */ - b43_radio_write(dev, 0x038, 0x0); - b43_radio_write(dev, 0x091, 0x7); - } -} - -/* wlc_radio_2064_init */ -static void b43_radio_2064_init(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, 0x09c, 0x0020); - b43_radio_write(dev, 0x105, 0x0008); - } else { - /* TODO */ - } - b43_radio_write(dev, 0x032, 0x0062); - b43_radio_write(dev, 0x033, 0x0019); - b43_radio_write(dev, 0x090, 0x0010); - b43_radio_write(dev, 0x010, 0x0000); - if (dev->phy.rev == 1) { - b43_radio_write(dev, 0x060, 0x007f); - b43_radio_write(dev, 0x061, 0x0072); - b43_radio_write(dev, 0x062, 0x007f); - } - b43_radio_write(dev, 0x01d, 0x0002); - b43_radio_write(dev, 0x01e, 0x0006); - - b43_phy_write(dev, 0x4ea, 0x4688); - b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); - b43_phy_mask(dev, 0x4eb, ~0x01c0); - b43_phy_maskset(dev, 0x46a, 0xff00, 0x19); - - b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); - - b43_radio_mask(dev, 0x05b, (u16) ~0xff02); - b43_radio_set(dev, 0x004, 0x40); - b43_radio_set(dev, 0x120, 0x10); - b43_radio_set(dev, 0x078, 0x80); - b43_radio_set(dev, 0x129, 0x2); - b43_radio_set(dev, 0x057, 0x1); - b43_radio_set(dev, 0x05b, 0x2); - - /* TODO: wait for some bit to be set */ - b43_radio_read(dev, 0x05c); - - b43_radio_mask(dev, 0x05b, (u16) ~0xff02); - b43_radio_mask(dev, 0x057, (u16) ~0xff01); - - b43_phy_write(dev, 0x933, 0x2d6b); - b43_phy_write(dev, 0x934, 0x2d6b); - b43_phy_write(dev, 0x935, 0x2d6b); - b43_phy_write(dev, 0x936, 0x2d6b); - b43_phy_write(dev, 0x937, 0x016b); - - b43_radio_mask(dev, 0x057, (u16) ~0xff02); - b43_radio_write(dev, 0x0c2, 0x006f); -} - -/************************************************** - * Various PHY ops - **************************************************/ - -/* wlc_lcnphy_toggle_afe_pwdn */ -static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev) -{ - u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2); - u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1); - - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1); - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1); - - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1); - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1); - - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2); - b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1); -} - -/* wlc_lcnphy_get_pa_gain */ -static u16 b43_phy_lcn_get_pa_gain(struct b43_wldev *dev) -{ - return (b43_phy_read(dev, 0x4fb) & 0x7f00) >> 8; -} - -/* wlc_lcnphy_set_dac_gain */ -static void b43_phy_lcn_set_dac_gain(struct b43_wldev *dev, u16 dac_gain) -{ - u16 dac_ctrl; - - dac_ctrl = b43_phy_read(dev, 0x439); - dac_ctrl = dac_ctrl & 0xc7f; - dac_ctrl = dac_ctrl | (dac_gain << 7); - b43_phy_maskset(dev, 0x439, ~0xfff, dac_ctrl); -} - -/* wlc_lcnphy_set_bbmult */ -static void b43_phy_lcn_set_bbmult(struct b43_wldev *dev, u8 m0) -{ - b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x57), m0 << 8); -} - -/* wlc_lcnphy_clear_tx_power_offsets */ -static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev) -{ - u8 i; - - if (1) { /* FIXME */ - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340); - for (i = 0; i < 30; i++) { - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); - } - } - - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80); - for (i = 0; i < 64; i++) { - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); - } -} - -/* wlc_lcnphy_rev0_baseband_init */ -static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev) -{ - b43_radio_write(dev, 0x11c, 0); - - b43_phy_write(dev, 0x43b, 0); - b43_phy_write(dev, 0x43c, 0); - b43_phy_write(dev, 0x44c, 0); - b43_phy_write(dev, 0x4e6, 0); - b43_phy_write(dev, 0x4f9, 0); - b43_phy_write(dev, 0x4b0, 0); - b43_phy_write(dev, 0x938, 0); - b43_phy_write(dev, 0x4b0, 0); - b43_phy_write(dev, 0x44e, 0); - - b43_phy_set(dev, 0x567, 0x03); - - b43_phy_set(dev, 0x44a, 0x44); - b43_phy_write(dev, 0x44a, 0x80); - - if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM)) - ; /* TODO */ - b43_phy_maskset(dev, 0x634, ~0xff, 0xc); - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) { - b43_phy_maskset(dev, 0x634, ~0xff, 0xa); - b43_phy_write(dev, 0x910, 0x1); - } - - b43_phy_write(dev, 0x910, 0x1); - - b43_phy_maskset(dev, 0x448, ~0x300, 0x100); - b43_phy_maskset(dev, 0x608, ~0xff, 0x17); - b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea); -} - -/* wlc_lcnphy_bu_tweaks */ -static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev) -{ - b43_phy_set(dev, 0x805, 0x1); - - b43_phy_maskset(dev, 0x42f, ~0x7, 0x3); - b43_phy_maskset(dev, 0x030, ~0x7, 0x3); - - b43_phy_write(dev, 0x414, 0x1e10); - b43_phy_write(dev, 0x415, 0x0640); - - b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700); - - b43_phy_set(dev, 0x44a, 0x44); - b43_phy_write(dev, 0x44a, 0x80); - - b43_phy_maskset(dev, 0x434, ~0xff, 0xfd); - b43_phy_maskset(dev, 0x420, ~0xff, 0x10); - - if (dev->dev->bus_sprom->board_rev >= 0x1204) - b43_radio_set(dev, 0x09b, 0xf0); - - b43_phy_write(dev, 0x7d6, 0x0902); - - b43_phy_maskset(dev, 0x429, ~0xf, 0x9); - b43_phy_maskset(dev, 0x429, ~(0x3f << 4), 0xe << 4); - - if (dev->phy.rev == 1) { - b43_phy_maskset(dev, 0x423, ~0xff, 0x46); - b43_phy_maskset(dev, 0x411, ~0xff, 1); - b43_phy_set(dev, 0x434, 0xff); /* FIXME: update to wl */ - - /* TODO: wl operates on PHY 0x416, brcmsmac is outdated here */ - - b43_phy_maskset(dev, 0x656, ~0xf, 2); - b43_phy_set(dev, 0x44d, 4); - - b43_radio_set(dev, 0x0f7, 0x4); - b43_radio_mask(dev, 0x0f1, ~0x3); - b43_radio_maskset(dev, 0x0f2, ~0xf8, 0x90); - b43_radio_maskset(dev, 0x0f3, ~0x3, 0x2); - b43_radio_maskset(dev, 0x0f3, ~0xf0, 0xa0); - - b43_radio_set(dev, 0x11f, 0x2); - - b43_phy_lcn_clear_tx_power_offsets(dev); - - /* TODO: something more? */ - } -} - -/* wlc_lcnphy_vbat_temp_sense_setup */ -static void b43_phy_lcn_sense_setup(struct b43_wldev *dev, - enum lcn_sense_type sense_type) -{ - u8 auxpga_vmidcourse, auxpga_vmidfine, auxpga_gain; - u16 auxpga_vmid; - u8 tx_pwr_idx; - u8 i; - - u16 save_radio_regs[6][2] = { - { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 }, - { 0x025, 0 }, { 0x112, 0 }, - }; - u16 save_phy_regs[14][2] = { - { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 }, - { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 }, - { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 }, - { 0x40d, 0 }, { 0x4a2, 0 }, - }; - u16 save_radio_4a4; - - msleep(1); - - /* Save */ - for (i = 0; i < 6; i++) - save_radio_regs[i][1] = b43_radio_read(dev, - save_radio_regs[i][0]); - for (i = 0; i < 14; i++) - save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]); - b43_mac_suspend(dev); - save_radio_4a4 = b43_radio_read(dev, 0x4a4); - /* wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF); */ - tx_pwr_idx = dev->phy.lcn->tx_pwr_curr_idx; - - /* Setup */ - /* TODO: wlc_lcnphy_set_tx_pwr_by_index(pi, 127); */ - b43_radio_set(dev, 0x007, 0x1); - b43_radio_set(dev, 0x0ff, 0x10); - b43_radio_set(dev, 0x11f, 0x4); - - b43_phy_mask(dev, 0x503, ~0x1); - b43_phy_mask(dev, 0x503, ~0x4); - b43_phy_mask(dev, 0x4a4, ~0x4000); - b43_phy_mask(dev, 0x4a4, (u16) ~0x8000); - b43_phy_mask(dev, 0x4d0, ~0x20); - b43_phy_set(dev, 0x4a5, 0xff); - b43_phy_maskset(dev, 0x4a5, ~0x7000, 0x5000); - b43_phy_mask(dev, 0x4a5, ~0x700); - b43_phy_maskset(dev, 0x40d, ~0xff, 64); - b43_phy_maskset(dev, 0x40d, ~0x700, 0x600); - b43_phy_maskset(dev, 0x4a2, ~0xff, 64); - b43_phy_maskset(dev, 0x4a2, ~0x700, 0x600); - b43_phy_maskset(dev, 0x4d9, ~0x70, 0x20); - b43_phy_maskset(dev, 0x4d9, ~0x700, 0x300); - b43_phy_maskset(dev, 0x4d9, ~0x7000, 0x1000); - b43_phy_mask(dev, 0x4da, ~0x1000); - b43_phy_set(dev, 0x4da, 0x2000); - b43_phy_set(dev, 0x4a6, 0x8000); - - b43_radio_write(dev, 0x025, 0xc); - b43_radio_set(dev, 0x005, 0x8); - b43_phy_set(dev, 0x938, 0x4); - b43_phy_set(dev, 0x939, 0x4); - b43_phy_set(dev, 0x4a4, 0x1000); - - /* FIXME: don't hardcode */ - b43_lcntab_write(dev, B43_LCNTAB16(0x8, 0x6), 0x640); - - switch (sense_type) { - case B43_SENSE_TEMP: - b43_phy_set(dev, 0x4d7, 0x8); - b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x1000); - auxpga_vmidcourse = 8; - auxpga_vmidfine = 0x4; - auxpga_gain = 2; - b43_radio_set(dev, 0x082, 0x20); - break; - case B43_SENSE_VBAT: - b43_phy_set(dev, 0x4d7, 0x8); - b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x3000); - auxpga_vmidcourse = 7; - auxpga_vmidfine = 0xa; - auxpga_gain = 2; - break; - } - auxpga_vmid = (0x200 | (auxpga_vmidcourse << 4) | auxpga_vmidfine); - - b43_phy_set(dev, 0x4d8, 0x1); - b43_phy_maskset(dev, 0x4d8, ~(0x3ff << 2), auxpga_vmid << 2); - b43_phy_set(dev, 0x4d8, 0x2); - b43_phy_maskset(dev, 0x4d8, ~(0x7 << 12), auxpga_gain << 12); - b43_phy_set(dev, 0x4d0, 0x20); - b43_radio_write(dev, 0x112, 0x6); - - b43_dummy_transmission(dev, true, false); - /* Wait if not done */ - if (!(b43_phy_read(dev, 0x476) & 0x8000)) - udelay(10); - - /* Restore */ - for (i = 0; i < 6; i++) - b43_radio_write(dev, save_radio_regs[i][0], - save_radio_regs[i][1]); - for (i = 0; i < 14; i++) - b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]); - /* TODO: wlc_lcnphy_set_tx_pwr_by_index(tx_pwr_idx) */ - b43_radio_write(dev, 0x4a4, save_radio_4a4); - - b43_mac_enable(dev); - - msleep(1); -} - -static bool b43_phy_lcn_load_tx_iir_cck_filter(struct b43_wldev *dev, - u8 filter_type) -{ - int i, j; - u16 phy_regs[] = { 0x910, 0x91e, 0x91f, 0x924, 0x925, 0x926, 0x920, - 0x921, 0x927, 0x928, 0x929, 0x922, 0x923, 0x930, - 0x931, 0x932 }; - /* Table is from brcmsmac, values for type 25 were outdated, probably - * others need updating too */ - struct lcn_tx_iir_filter tx_iir_filters_cck[] = { - { 0, { 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, - 1582, 64, 128, 64 } }, - { 1, { 1, 402, 1847, 259, 59, 259, 671, 1794, 68, 54, 68, 608, - 1863, 93, 167, 93 } }, - { 2, { 1, 415, 1874, 64, 128, 64, 792, 1656, 192, 384, 192, - 778, 1582, 64, 128, 64 } }, - { 3, { 1, 302, 1841, 129, 258, 129, 658, 1720, 205, 410, 205, - 754, 1760, 170, 340, 170 } }, - { 20, { 1, 360, 1884, 242, 1734, 242, 752, 1720, 205, 1845, 205, - 767, 1760, 256, 185, 256 } }, - { 21, { 1, 360, 1884, 149, 1874, 149, 752, 1720, 205, 1883, 205, - 767, 1760, 256, 273, 256 } }, - { 22, { 1, 360, 1884, 98, 1948, 98, 752, 1720, 205, 1924, 205, - 767, 1760, 256, 352, 256 } }, - { 23, { 1, 350, 1884, 116, 1966, 116, 752, 1720, 205, 2008, 205, - 767, 1760, 128, 233, 128 } }, - { 24, { 1, 325, 1884, 32, 40, 32, 756, 1720, 256, 471, 256, 766, - 1760, 256, 1881, 256 } }, - { 25, { 1, 299, 1884, 51, 64, 51, 736, 1720, 256, 471, 256, 765, - 1760, 262, 1878, 262 } }, - /* brcmsmac version { 25, { 1, 299, 1884, 51, 64, 51, 736, 1720, - * 256, 471, 256, 765, 1760, 256, 1881, 256 } }, */ - { 26, { 1, 277, 1943, 39, 117, 88, 637, 1838, 64, 192, 144, 614, - 1864, 128, 384, 288 } }, - { 27, { 1, 245, 1943, 49, 147, 110, 626, 1838, 256, 768, 576, - 613, 1864, 128, 384, 288 } }, - { 30, { 1, 302, 1841, 61, 122, 61, 658, 1720, 205, 410, 205, - 754, 1760, 170, 340, 170 } }, - }; - - for (i = 0; i < ARRAY_SIZE(tx_iir_filters_cck); i++) { - if (tx_iir_filters_cck[i].type == filter_type) { - for (j = 0; j < 16; j++) - b43_phy_write(dev, phy_regs[j], - tx_iir_filters_cck[i].values[j]); - return true; - } - } - - return false; -} - -static bool b43_phy_lcn_load_tx_iir_ofdm_filter(struct b43_wldev *dev, - u8 filter_type) -{ - int i, j; - u16 phy_regs[] = { 0x90f, 0x900, 0x901, 0x906, 0x907, 0x908, 0x902, - 0x903, 0x909, 0x90a, 0x90b, 0x904, 0x905, 0x90c, - 0x90d, 0x90e }; - struct lcn_tx_iir_filter tx_iir_filters_ofdm[] = { - { 0, { 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, - 0x0, 0x278, 0xfea0, 0x80, 0x100, 0x80 } }, - { 1, { 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50, 750, - 0xFE2B, 212, 0xFFCE, 212 } }, - { 2, { 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748, - 0xFEF2, 128, 0xFFE2, 128 } }, - }; - - for (i = 0; i < ARRAY_SIZE(tx_iir_filters_ofdm); i++) { - if (tx_iir_filters_ofdm[i].type == filter_type) { - for (j = 0; j < 16; j++) - b43_phy_write(dev, phy_regs[j], - tx_iir_filters_ofdm[i].values[j]); - return true; - } - } - - return false; -} - -/* wlc_lcnphy_set_tx_gain_override */ -static void b43_phy_lcn_set_tx_gain_override(struct b43_wldev *dev, bool enable) -{ - b43_phy_maskset(dev, 0x4b0, ~(0x1 << 7), enable << 7); - b43_phy_maskset(dev, 0x4b0, ~(0x1 << 14), enable << 14); - b43_phy_maskset(dev, 0x43b, ~(0x1 << 6), enable << 6); -} - -/* wlc_lcnphy_set_tx_gain */ -static void b43_phy_lcn_set_tx_gain(struct b43_wldev *dev, - struct lcn_tx_gains *target_gains) -{ - u16 pa_gain = b43_phy_lcn_get_pa_gain(dev); - - b43_phy_write(dev, 0x4b5, - (target_gains->gm_gain | (target_gains->pga_gain << 8))); - b43_phy_maskset(dev, 0x4fb, ~0x7fff, - (target_gains->pad_gain | (pa_gain << 8))); - b43_phy_write(dev, 0x4fc, - (target_gains->gm_gain | (target_gains->pga_gain << 8))); - b43_phy_maskset(dev, 0x4fd, ~0x7fff, - (target_gains->pad_gain | (pa_gain << 8))); - - b43_phy_lcn_set_dac_gain(dev, target_gains->dac_gain); - b43_phy_lcn_set_tx_gain_override(dev, true); -} - -/* wlc_lcnphy_tx_pwr_ctrl_init */ -static void b43_phy_lcn_tx_pwr_ctl_init(struct b43_wldev *dev) -{ - struct lcn_tx_gains tx_gains; - u8 bbmult; - - b43_mac_suspend(dev); - - if (!dev->phy.lcn->hw_pwr_ctl_capable) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - tx_gains.gm_gain = 4; - tx_gains.pga_gain = 12; - tx_gains.pad_gain = 12; - tx_gains.dac_gain = 0; - bbmult = 150; - } else { - tx_gains.gm_gain = 7; - tx_gains.pga_gain = 15; - tx_gains.pad_gain = 14; - tx_gains.dac_gain = 0; - bbmult = 150; - } - b43_phy_lcn_set_tx_gain(dev, &tx_gains); - b43_phy_lcn_set_bbmult(dev, bbmult); - b43_phy_lcn_sense_setup(dev, B43_SENSE_TEMP); - } else { - b43err(dev->wl, "TX power control not supported for this HW\n"); - } - - b43_mac_enable(dev); -} - -/* wlc_lcnphy_txrx_spur_avoidance_mode */ -static void b43_phy_lcn_txrx_spur_avoidance_mode(struct b43_wldev *dev, - bool enable) -{ - if (enable) { - b43_phy_write(dev, 0x942, 0x7); - b43_phy_write(dev, 0x93b, ((1 << 13) + 23)); - b43_phy_write(dev, 0x93c, ((1 << 13) + 1989)); - - b43_phy_write(dev, 0x44a, 0x084); - b43_phy_write(dev, 0x44a, 0x080); - b43_phy_write(dev, 0x6d3, 0x2222); - b43_phy_write(dev, 0x6d3, 0x2220); - } else { - b43_phy_write(dev, 0x942, 0x0); - b43_phy_write(dev, 0x93b, ((0 << 13) + 23)); - b43_phy_write(dev, 0x93c, ((0 << 13) + 1989)); - } - b43_mac_switch_freq(dev, enable); -} - -/************************************************** - * Channel switching ops. - **************************************************/ - -/* wlc_lcnphy_set_chanspec_tweaks */ -static void b43_phy_lcn_set_channel_tweaks(struct b43_wldev *dev, int channel) -{ - struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc; - - b43_phy_maskset(dev, 0x448, ~0x300, (channel == 14) ? 0x200 : 0x100); - - if (channel == 1 || channel == 2 || channel == 3 || channel == 4 || - channel == 9 || channel == 10 || channel == 11 || channel == 12) { - bcma_chipco_pll_write(cc, 0x2, 0x03000c04); - bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x0); - bcma_chipco_pll_write(cc, 0x4, 0x200005c0); - - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400); - - b43_phy_write(dev, 0x942, 0); - - b43_phy_lcn_txrx_spur_avoidance_mode(dev, false); - b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1b00); - b43_phy_write(dev, 0x425, 0x5907); - } else { - bcma_chipco_pll_write(cc, 0x2, 0x03140c04); - bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x333333); - bcma_chipco_pll_write(cc, 0x4, 0x202c2820); - - bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400); - - b43_phy_write(dev, 0x942, 0); - - b43_phy_lcn_txrx_spur_avoidance_mode(dev, true); - b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1f00); - b43_phy_write(dev, 0x425, 0x590a); - } - - b43_phy_set(dev, 0x44a, 0x44); - b43_phy_write(dev, 0x44a, 0x80); -} - -/* wlc_phy_chanspec_set_lcnphy */ -static int b43_phy_lcn_set_channel(struct b43_wldev *dev, - struct ieee80211_channel *channel, - enum nl80211_channel_type channel_type) -{ - static const u16 sfo_cfg[14][2] = { - {965, 1087}, {967, 1085}, {969, 1082}, {971, 1080}, {973, 1078}, - {975, 1076}, {977, 1073}, {979, 1071}, {981, 1069}, {983, 1067}, - {985, 1065}, {987, 1063}, {989, 1060}, {994, 1055}, - }; - - b43_phy_lcn_set_channel_tweaks(dev, channel->hw_value); - - b43_phy_set(dev, 0x44a, 0x44); - b43_phy_write(dev, 0x44a, 0x80); - - b43_radio_2064_channel_setup(dev); - mdelay(1); - - b43_phy_lcn_afe_set_unset(dev); - - b43_phy_write(dev, 0x657, sfo_cfg[channel->hw_value - 1][0]); - b43_phy_write(dev, 0x658, sfo_cfg[channel->hw_value - 1][1]); - - if (channel->hw_value == 14) { - b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (2) << 8); - b43_phy_lcn_load_tx_iir_cck_filter(dev, 3); - } else { - b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (1) << 8); - /* brcmsmac uses filter_type 2, we follow wl with 25 */ - b43_phy_lcn_load_tx_iir_cck_filter(dev, 25); - } - /* brcmsmac uses filter_type 2, we follow wl with 0 */ - b43_phy_lcn_load_tx_iir_ofdm_filter(dev, 0); - - b43_phy_maskset(dev, 0x4eb, ~(0x7 << 3), 0x1 << 3); - - return 0; -} - -/************************************************** - * Basic PHY ops. - **************************************************/ - -static int b43_phy_lcn_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_lcn *phy_lcn; - - phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL); - if (!phy_lcn) - return -ENOMEM; - dev->phy.lcn = phy_lcn; - - return 0; -} - -static void b43_phy_lcn_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_lcn *phy_lcn = phy->lcn; - - kfree(phy_lcn); - phy->lcn = NULL; -} - -static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_lcn *phy_lcn = phy->lcn; - - memset(phy_lcn, 0, sizeof(*phy_lcn)); -} - -/* wlc_phy_init_lcnphy */ -static int b43_phy_lcn_op_init(struct b43_wldev *dev) -{ - struct bcma_drv_cc *cc = &dev->dev->bdev->bus->drv_cc; - - b43_phy_set(dev, 0x44a, 0x80); - b43_phy_mask(dev, 0x44a, 0x7f); - b43_phy_set(dev, 0x6d1, 0x80); - b43_phy_write(dev, 0x6d0, 0x7); - - b43_phy_lcn_afe_set_unset(dev); - - b43_phy_write(dev, 0x60a, 0xa0); - b43_phy_write(dev, 0x46a, 0x19); - b43_phy_maskset(dev, 0x663, 0xFF00, 0x64); - - b43_phy_lcn_tables_init(dev); - - b43_phy_lcn_rev0_baseband_init(dev); - b43_phy_lcn_bu_tweaks(dev); - - if (dev->phy.radio_ver == 0x2064) - b43_radio_2064_init(dev); - else - B43_WARN_ON(1); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_phy_lcn_tx_pwr_ctl_init(dev); - - b43_switch_channel(dev, dev->phy.channel); - - bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9); - bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd); - - /* TODO */ - - b43_phy_set(dev, 0x448, 0x4000); - udelay(100); - b43_phy_mask(dev, 0x448, ~0x4000); - - /* TODO */ - - return 0; -} - -static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) - b43err(dev->wl, "MAC not suspended\n"); - - if (blocked) { - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00); - b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00); - - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00); - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2); - b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808); - - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8); - b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8); - } else { - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00); - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808); - b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8); - } -} - -static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on) -{ - if (on) { - b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7); - } else { - b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7); - b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7); - } -} - -static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; - enum nl80211_channel_type channel_type = - cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if ((new_channel < 1) || (new_channel > 14)) - return -EINVAL; - } else { - return -EINVAL; - } - - return b43_phy_lcn_set_channel(dev, channel, channel_type); -} - -static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - return 1; - return 36; -} - -static enum b43_txpwr_result -b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi) -{ - return B43_TXPWR_RES_DONE; -} - -static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev) -{ -} - -/************************************************** - * R/W ops. - **************************************************/ - -static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, - u16 set) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, - (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); -} - -static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* LCN-PHY needs 0x200 for read access */ - reg |= 0x200; - - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO24_DATA); -} - -static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg, - u16 value) -{ - b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO24_DATA, value); -} - -/************************************************** - * PHY ops struct. - **************************************************/ - -const struct b43_phy_operations b43_phyops_lcn = { - .allocate = b43_phy_lcn_op_allocate, - .free = b43_phy_lcn_op_free, - .prepare_structs = b43_phy_lcn_op_prepare_structs, - .init = b43_phy_lcn_op_init, - .phy_maskset = b43_phy_lcn_op_maskset, - .radio_read = b43_phy_lcn_op_radio_read, - .radio_write = b43_phy_lcn_op_radio_write, - .software_rfkill = b43_phy_lcn_op_software_rfkill, - .switch_analog = b43_phy_lcn_op_switch_analog, - .switch_channel = b43_phy_lcn_op_switch_channel, - .get_default_chan = b43_phy_lcn_op_get_default_chan, - .recalc_txpower = b43_phy_lcn_op_recalc_txpower, - .adjust_txpower = b43_phy_lcn_op_adjust_txpower, -}; diff --git a/drivers/net/wireless/b43/phy_lcn.h b/drivers/net/wireless/b43/phy_lcn.h deleted file mode 100644 index 6a7092e13..000000000 --- a/drivers/net/wireless/b43/phy_lcn.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef B43_PHY_LCN_H_ -#define B43_PHY_LCN_H_ - -#include "phy_common.h" - - -#define B43_PHY_LCN_AFE_CTL1 B43_PHY_OFDM(0x03B) -#define B43_PHY_LCN_AFE_CTL2 B43_PHY_OFDM(0x03C) -#define B43_PHY_LCN_RF_CTL1 B43_PHY_OFDM(0x04C) -#define B43_PHY_LCN_RF_CTL2 B43_PHY_OFDM(0x04D) -#define B43_PHY_LCN_TABLE_ADDR B43_PHY_OFDM(0x055) /* Table address */ -#define B43_PHY_LCN_TABLE_DATALO B43_PHY_OFDM(0x056) /* Table data low */ -#define B43_PHY_LCN_TABLE_DATAHI B43_PHY_OFDM(0x057) /* Table data high */ -#define B43_PHY_LCN_RF_CTL3 B43_PHY_OFDM(0x0B0) -#define B43_PHY_LCN_RF_CTL4 B43_PHY_OFDM(0x0B1) -#define B43_PHY_LCN_RF_CTL5 B43_PHY_OFDM(0x0B7) -#define B43_PHY_LCN_RF_CTL6 B43_PHY_OFDM(0x0F9) -#define B43_PHY_LCN_RF_CTL7 B43_PHY_OFDM(0x0FA) - - -struct b43_phy_lcn { - bool hw_pwr_ctl; - bool hw_pwr_ctl_capable; - u8 tx_pwr_curr_idx; -}; - - -struct b43_phy_operations; -extern const struct b43_phy_operations b43_phyops_lcn; - -#endif /* B43_PHY_LCN_H_ */ diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c deleted file mode 100644 index 058a9f232..000000000 --- a/drivers/net/wireless/b43/phy_lp.c +++ /dev/null @@ -1,2716 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11a/g LP-PHY driver - - Copyright (c) 2008-2009 Michael Buesch <m@bues.ch> - Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/slab.h> - -#include "b43.h" -#include "main.h" -#include "phy_lp.h" -#include "phy_common.h" -#include "tables_lpphy.h" - - -static inline u16 channel2freq_lp(u8 channel) -{ - if (channel < 14) - return (2407 + 5 * channel); - else if (channel == 14) - return 2484; - else if (channel < 184) - return (5000 + 5 * channel); - else - return (4000 + 5 * channel); -} - -static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - return 1; - return 36; -} - -static int b43_lpphy_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy; - - lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL); - if (!lpphy) - return -ENOMEM; - dev->phy.lp = lpphy; - - return 0; -} - -static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_lp *lpphy = phy->lp; - - memset(lpphy, 0, sizeof(*lpphy)); - lpphy->antenna = B43_ANTENNA_DEFAULT; - - //TODO -} - -static void b43_lpphy_op_free(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - kfree(lpphy); - dev->phy.lp = NULL; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */ -static void lpphy_read_band_sprom(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 cckpo, maxpwr; - u32 ofdmpo; - int i; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - lpphy->tx_isolation_med_band = sprom->tri2g; - lpphy->bx_arch = sprom->bxa2g; - lpphy->rx_pwr_offset = sprom->rxpo2g; - lpphy->rssi_vf = sprom->rssismf2g; - lpphy->rssi_vc = sprom->rssismc2g; - lpphy->rssi_gs = sprom->rssisav2g; - lpphy->txpa[0] = sprom->pa0b0; - lpphy->txpa[1] = sprom->pa0b1; - lpphy->txpa[2] = sprom->pa0b2; - maxpwr = sprom->maxpwr_bg; - lpphy->max_tx_pwr_med_band = maxpwr; - cckpo = sprom->cck2gpo; - if (cckpo) { - ofdmpo = sprom->ofdm2gpo; - for (i = 0; i < 4; i++) { - lpphy->tx_max_rate[i] = - maxpwr - (ofdmpo & 0xF) * 2; - ofdmpo >>= 4; - } - ofdmpo = sprom->ofdm2gpo; - for (i = 4; i < 15; i++) { - lpphy->tx_max_rate[i] = - maxpwr - (ofdmpo & 0xF) * 2; - ofdmpo >>= 4; - } - } else { - u8 opo = sprom->opo; - for (i = 0; i < 4; i++) - lpphy->tx_max_rate[i] = maxpwr; - for (i = 4; i < 15; i++) - lpphy->tx_max_rate[i] = maxpwr - opo; - } - } else { /* 5GHz */ - lpphy->tx_isolation_low_band = sprom->tri5gl; - lpphy->tx_isolation_med_band = sprom->tri5g; - lpphy->tx_isolation_hi_band = sprom->tri5gh; - lpphy->bx_arch = sprom->bxa5g; - lpphy->rx_pwr_offset = sprom->rxpo5g; - lpphy->rssi_vf = sprom->rssismf5g; - lpphy->rssi_vc = sprom->rssismc5g; - lpphy->rssi_gs = sprom->rssisav5g; - lpphy->txpa[0] = sprom->pa1b0; - lpphy->txpa[1] = sprom->pa1b1; - lpphy->txpa[2] = sprom->pa1b2; - lpphy->txpal[0] = sprom->pa1lob0; - lpphy->txpal[1] = sprom->pa1lob1; - lpphy->txpal[2] = sprom->pa1lob2; - lpphy->txpah[0] = sprom->pa1hib0; - lpphy->txpah[1] = sprom->pa1hib1; - lpphy->txpah[2] = sprom->pa1hib2; - maxpwr = sprom->maxpwr_al; - ofdmpo = sprom->ofdm5glpo; - lpphy->max_tx_pwr_low_band = maxpwr; - for (i = 4; i < 12; i++) { - lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2; - ofdmpo >>= 4; - } - maxpwr = sprom->maxpwr_a; - ofdmpo = sprom->ofdm5gpo; - lpphy->max_tx_pwr_med_band = maxpwr; - for (i = 4; i < 12; i++) { - lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2; - ofdmpo >>= 4; - } - maxpwr = sprom->maxpwr_ah; - ofdmpo = sprom->ofdm5ghpo; - lpphy->max_tx_pwr_hi_band = maxpwr; - for (i = 4; i < 12; i++) { - lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2; - ofdmpo >>= 4; - } - } -} - -static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 temp[3]; - u16 isolation; - - B43_WARN_ON(dev->phy.rev >= 2); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - isolation = lpphy->tx_isolation_med_band; - else if (freq <= 5320) - isolation = lpphy->tx_isolation_low_band; - else if (freq <= 5700) - isolation = lpphy->tx_isolation_med_band; - else - isolation = lpphy->tx_isolation_hi_band; - - temp[0] = ((isolation - 26) / 12) << 12; - temp[1] = temp[0] + 0x1000; - temp[2] = temp[0] + 0x2000; - - b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp); - b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp); -} - -static void lpphy_table_init(struct b43_wldev *dev) -{ - u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev)); - - if (dev->phy.rev < 2) - lpphy_rev0_1_table_init(dev); - else - lpphy_rev2plus_table_init(dev); - - lpphy_init_tx_gain_table(dev); - - if (dev->phy.rev < 2) - lpphy_adjust_gain_table(dev, freq); -} - -static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 tmp, tmp2; - - b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF); - b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0); - b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); - b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004); - b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800); - b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016); - b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004); - b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400); - b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400); - b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100); - b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006); - b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00); - b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005); - b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A); - b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3); - b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00); - b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, - 0xFF00, lpphy->rx_pwr_offset); - if ((sprom->boardflags_lo & B43_BFL_FEM) && - ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || - (sprom->boardflags_hi & B43_BFH_PAREF))) { - ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28); - ssb_pmu_set_ldo_paref(&bus->chipco, true); - if (dev->phy.rev == 0) { - b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT, - 0xFFCF, 0x0010); - } - b43_lptab_write(dev, B43_LPTAB16(11, 7), 60); - } else { - ssb_pmu_set_ldo_paref(&bus->chipco, false); - b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT, - 0xFFCF, 0x0020); - b43_lptab_write(dev, B43_LPTAB16(11, 7), 100); - } - tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000; - b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp); - if (sprom->boardflags_hi & B43_BFH_RSSIINV) - b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA); - else - b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA); - b43_lptab_write(dev, B43_LPTAB16(11, 1), 24); - b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL, - 0xFFF9, (lpphy->bx_arch << 1)); - if (dev->phy.rev == 1 && - (sprom->boardflags_hi & B43_BFH_FEM_BT)) { - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); - } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || - (dev->dev->board_type == SSB_BOARD_BU4312) || - (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) { - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00); - } else if (dev->phy.rev == 1 || - (sprom->boardflags_lo & B43_BFL_FEM)) { - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300); - } else { - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006); - b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700); - } - if (dev->phy.rev == 1 && (sprom->boardflags_hi & B43_BFH_PAREF)) { - b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1); - b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2); - b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3); - b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4); - } - if ((sprom->boardflags_hi & B43_BFH_FEM_BT) && - (dev->dev->chip_id == 0x5354) && - (dev->dev->chip_pkg == SSB_CHIPPACK_BCM4712S)) { - b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006); - b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005); - b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF); - //FIXME the Broadcom driver caches & delays this HF write! - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W); - } - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000); - b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040); - b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400); - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00); - b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007); - b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003); - b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020); - b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); - } else { /* 5GHz */ - b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF); - b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF); - } - if (dev->phy.rev == 1) { - tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH); - tmp2 = (tmp & 0x03E0) >> 5; - tmp2 |= tmp2 << 5; - b43_phy_write(dev, B43_LPPHY_4C3, tmp2); - tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH); - tmp2 = (tmp & 0x1F00) >> 8; - tmp2 |= tmp2 << 5; - b43_phy_write(dev, B43_LPPHY_4C4, tmp2); - tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB); - tmp2 = tmp & 0x00FF; - tmp2 |= tmp << 8; - b43_phy_write(dev, B43_LPPHY_4C5, tmp2); - } -} - -static void lpphy_save_dig_flt_state(struct b43_wldev *dev) -{ - static const u16 addr[] = { - B43_PHY_OFDM(0xC1), - B43_PHY_OFDM(0xC2), - B43_PHY_OFDM(0xC3), - B43_PHY_OFDM(0xC4), - B43_PHY_OFDM(0xC5), - B43_PHY_OFDM(0xC6), - B43_PHY_OFDM(0xC7), - B43_PHY_OFDM(0xC8), - B43_PHY_OFDM(0xCF), - }; - - static const u16 coefs[] = { - 0xDE5E, 0xE832, 0xE331, 0x4D26, - 0x0026, 0x1420, 0x0020, 0xFE08, - 0x0008, - }; - - struct b43_phy_lp *lpphy = dev->phy.lp; - int i; - - for (i = 0; i < ARRAY_SIZE(addr); i++) { - lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]); - b43_phy_write(dev, addr[i], coefs[i]); - } -} - -static void lpphy_restore_dig_flt_state(struct b43_wldev *dev) -{ - static const u16 addr[] = { - B43_PHY_OFDM(0xC1), - B43_PHY_OFDM(0xC2), - B43_PHY_OFDM(0xC3), - B43_PHY_OFDM(0xC4), - B43_PHY_OFDM(0xC5), - B43_PHY_OFDM(0xC6), - B43_PHY_OFDM(0xC7), - B43_PHY_OFDM(0xC8), - B43_PHY_OFDM(0xCF), - }; - - struct b43_phy_lp *lpphy = dev->phy.lp; - int i; - - for (i = 0; i < ARRAY_SIZE(addr); i++) - b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]); -} - -static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50); - b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800); - b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0); - b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0); - b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0); - b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0); - b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10); - b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4); - b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200); - b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F); - b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40); - b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2); - b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); - b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); - b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1); - if (dev->dev->board_rev >= 0x18) { - b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC); - b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14); - } else { - b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10); - } - b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4); - b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100); - b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48); - b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46); - b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10); - b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9); - b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF); - b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0); - b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300); - b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00); - if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { - b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100); - b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA); - } else { - b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00); - b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD); - } - b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC); - b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC); - b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800); - b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12); - b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000); - - if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { - b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0); - b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40); - } - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40); - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00); - b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6); - b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00); - b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1); - b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF); - } else /* 5GHz */ - b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40); - - b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3); - b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00); - b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset); - b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44); - b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80); - b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954); - b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1, - 0x2000 | ((u16)lpphy->rssi_gs << 10) | - ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf); - - if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { - b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C); - b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800); - b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400); - } - - lpphy_save_dig_flt_state(dev); -} - -static void lpphy_baseband_init(struct b43_wldev *dev) -{ - lpphy_table_init(dev); - if (dev->phy.rev >= 2) - lpphy_baseband_rev2plus_init(dev); - else - lpphy_baseband_rev0_1_init(dev); -} - -struct b2062_freqdata { - u16 freq; - u8 data[6]; -}; - -/* Initialize the 2062 radio. */ -static void lpphy_2062_init(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - struct ssb_bus *bus = dev->dev->sdev->bus; - u32 crystalfreq, tmp, ref; - unsigned int i; - const struct b2062_freqdata *fd = NULL; - - static const struct b2062_freqdata freqdata_tab[] = { - { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6, - .data[3] = 6, .data[4] = 10, .data[5] = 6, }, - { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4, - .data[3] = 4, .data[4] = 11, .data[5] = 7, }, - { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3, - .data[3] = 3, .data[4] = 12, .data[5] = 7, }, - { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3, - .data[3] = 3, .data[4] = 13, .data[5] = 8, }, - { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2, - .data[3] = 2, .data[4] = 14, .data[5] = 8, }, - { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1, - .data[3] = 1, .data[4] = 14, .data[5] = 9, }, - }; - - b2062_upload_init_table(dev); - - b43_radio_write(dev, B2062_N_TX_CTL3, 0); - b43_radio_write(dev, B2062_N_TX_CTL4, 0); - b43_radio_write(dev, B2062_N_TX_CTL5, 0); - b43_radio_write(dev, B2062_N_TX_CTL6, 0); - b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40); - b43_radio_write(dev, B2062_N_PDN_CTL0, 0); - b43_radio_write(dev, B2062_N_CALIB_TS, 0x10); - b43_radio_write(dev, B2062_N_CALIB_TS, 0); - if (dev->phy.rev > 0) { - b43_radio_write(dev, B2062_S_BG_CTL1, - (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80); - } - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1); - else - b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1); - - /* Get the crystal freq, in Hz. */ - crystalfreq = bus->chipco.pmu.crystalfreq * 1000; - - B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)); - B43_WARN_ON(crystalfreq == 0); - - if (crystalfreq <= 30000000) { - lpphy->pdiv = 1; - b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB); - } else { - lpphy->pdiv = 2; - b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4); - } - - tmp = (((800000000 * lpphy->pdiv + crystalfreq) / - (2 * crystalfreq)) - 8) & 0xFF; - b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp); - - tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) / - (32000000 * lpphy->pdiv)) - 1) & 0xFF; - b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp); - - tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) / - (2000000 * lpphy->pdiv)) - 1) & 0xFF; - b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp); - - ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv); - ref &= 0xFFFF; - for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) { - if (ref < freqdata_tab[i].freq) { - fd = &freqdata_tab[i]; - break; - } - } - if (!fd) - fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1]; - b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n", - fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */ - - b43_radio_write(dev, B2062_S_RFPLL_CTL8, - ((u16)(fd->data[1]) << 4) | fd->data[0]); - b43_radio_write(dev, B2062_S_RFPLL_CTL9, - ((u16)(fd->data[3]) << 4) | fd->data[2]); - b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]); - b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]); -} - -/* Initialize the 2063 radio. */ -static void lpphy_2063_init(struct b43_wldev *dev) -{ - b2063_upload_init_table(dev); - b43_radio_write(dev, B2063_LOGEN_SP5, 0); - b43_radio_set(dev, B2063_COMM8, 0x38); - b43_radio_write(dev, B2063_REG_SP1, 0x56); - b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2); - b43_radio_write(dev, B2063_PA_SP7, 0); - b43_radio_write(dev, B2063_TX_RF_SP6, 0x20); - b43_radio_write(dev, B2063_TX_RF_SP9, 0x40); - if (dev->phy.rev == 2) { - b43_radio_write(dev, B2063_PA_SP3, 0xa0); - b43_radio_write(dev, B2063_PA_SP4, 0xa0); - b43_radio_write(dev, B2063_PA_SP2, 0x18); - } else { - b43_radio_write(dev, B2063_PA_SP3, 0x20); - b43_radio_write(dev, B2063_PA_SP2, 0x20); - } -} - -struct lpphy_stx_table_entry { - u16 phy_offset; - u16 phy_shift; - u16 rf_addr; - u16 rf_shift; - u16 mask; -}; - -static const struct lpphy_stx_table_entry lpphy_stx_table[] = { - { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, }, - { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, }, - { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, }, - { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, }, - { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, }, - { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, }, - { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, }, - { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, }, - { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, }, - { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, }, - { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, }, - { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, }, - { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, }, - { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, }, - { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, }, - { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, }, - { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, }, - { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, }, - { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, }, - { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, }, - { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, }, - { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, }, - { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, }, - { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, }, - { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, }, - { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, }, - { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, }, - { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, }, - { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, }, -}; - -static void lpphy_sync_stx(struct b43_wldev *dev) -{ - const struct lpphy_stx_table_entry *e; - unsigned int i; - u16 tmp; - - for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) { - e = &lpphy_stx_table[i]; - tmp = b43_radio_read(dev, e->rf_addr); - tmp >>= e->rf_shift; - tmp <<= e->phy_shift; - b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset), - ~(e->mask << e->phy_shift), tmp); - } -} - -static void lpphy_radio_init(struct b43_wldev *dev) -{ - /* The radio is attached through the 4wire bus. */ - b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2); - udelay(1); - b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD); - udelay(1); - - if (dev->phy.radio_ver == 0x2062) { - lpphy_2062_init(dev); - } else { - lpphy_2063_init(dev); - lpphy_sync_stx(dev); - b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80); - b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0); - if (dev->dev->chip_id == 0x4325) { - // TODO SSB PMU recalibration - } - } -} - -struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; }; - -static void lpphy_set_rc_cap(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1; - - if (dev->phy.rev == 1) //FIXME check channel 14! - rc_cap = min_t(u8, rc_cap + 5, 15); - - b43_radio_write(dev, B2062_N_RXBB_CALIB2, - max_t(u8, lpphy->rc_cap - 4, 0x80)); - b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80); - b43_radio_write(dev, B2062_S_RXG_CNT16, - ((lpphy->rc_cap & 0x1F) >> 2) | 0x80); -} - -static u8 lpphy_get_bb_mult(struct b43_wldev *dev) -{ - return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8; -} - -static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult) -{ - b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8); -} - -static void lpphy_set_deaf(struct b43_wldev *dev, bool user) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - if (user) - lpphy->crs_usr_disable = true; - else - lpphy->crs_sys_disable = true; - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80); -} - -static void lpphy_clear_deaf(struct b43_wldev *dev, bool user) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - if (user) - lpphy->crs_usr_disable = false; - else - lpphy->crs_sys_disable = false; - - if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, - 0xFF1F, 0x60); - else - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, - 0xFF1F, 0x20); - } -} - -static void lpphy_set_trsw_over(struct b43_wldev *dev, bool tx, bool rx) -{ - u16 trsw = (tx << 1) | rx; - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, trsw); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3); -} - -static void lpphy_disable_crs(struct b43_wldev *dev, bool user) -{ - lpphy_set_deaf(dev, user); - lpphy_set_trsw_over(dev, false, true); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF); - b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0); - b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1); - b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF); - b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0); - b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF); -} - -static void lpphy_restore_crs(struct b43_wldev *dev, bool user) -{ - lpphy_clear_deaf(dev, user); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00); -} - -struct lpphy_tx_gains { u16 gm, pga, pad, dac; }; - -static void lpphy_disable_rx_gain_override(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF); - if (dev->phy.rev >= 2) { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF); - b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7); - } - } else { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF); - } -} - -static void lpphy_enable_rx_gain_override(struct b43_wldev *dev) -{ - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40); - if (dev->phy.rev >= 2) { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400); - b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8); - } - } else { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200); - } -} - -static void lpphy_disable_tx_gain_override(struct b43_wldev *dev) -{ - if (dev->phy.rev < 2) - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF); - else { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF); - } - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF); -} - -static void lpphy_enable_tx_gain_override(struct b43_wldev *dev) -{ - if (dev->phy.rev < 2) - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100); - else { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x80); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x4000); - } - b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x40); -} - -static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev) -{ - struct lpphy_tx_gains gains; - u16 tmp; - - gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7; - if (dev->phy.rev < 2) { - tmp = b43_phy_read(dev, - B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF; - gains.gm = tmp & 0x0007; - gains.pga = (tmp & 0x0078) >> 3; - gains.pad = (tmp & 0x780) >> 7; - } else { - tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL); - gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF; - gains.gm = tmp & 0xFF; - gains.pga = (tmp >> 8) & 0xFF; - } - - return gains; -} - -static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac) -{ - u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F; - ctl |= dac << 7; - b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl); -} - -static u16 lpphy_get_pa_gain(struct b43_wldev *dev) -{ - return b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x7F; -} - -static void lpphy_set_pa_gain(struct b43_wldev *dev, u16 gain) -{ - b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), 0xE03F, gain << 6); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), 0x80FF, gain << 8); -} - -static void lpphy_set_tx_gains(struct b43_wldev *dev, - struct lpphy_tx_gains gains) -{ - u16 rf_gain, pa_gain; - - if (dev->phy.rev < 2) { - rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm; - b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, - 0xF800, rf_gain); - } else { - pa_gain = lpphy_get_pa_gain(dev); - b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, - (gains.pga << 8) | gains.gm); - /* - * SPEC FIXME The spec calls for (pa_gain << 8) here, but that - * conflicts with the spec for set_pa_gain! Vendor driver bug? - */ - b43_phy_maskset(dev, B43_PHY_OFDM(0xFB), - 0x8000, gains.pad | (pa_gain << 6)); - b43_phy_write(dev, B43_PHY_OFDM(0xFC), - (gains.pga << 8) | gains.gm); - b43_phy_maskset(dev, B43_PHY_OFDM(0xFD), - 0x8000, gains.pad | (pa_gain << 8)); - } - lpphy_set_dac_gain(dev, gains.dac); - lpphy_enable_tx_gain_override(dev); -} - -static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain) -{ - u16 trsw = gain & 0x1; - u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2); - u16 ext_lna = (gain & 2) >> 1; - - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, - 0xFBFF, ext_lna << 10); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, - 0xF7FF, ext_lna << 11); - b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna); -} - -static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain) -{ - u16 low_gain = gain & 0xFFFF; - u16 high_gain = (gain >> 16) & 0xF; - u16 ext_lna = (gain >> 21) & 0x1; - u16 trsw = ~(gain >> 20) & 0x1; - u16 tmp; - - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, - 0xFDFF, ext_lna << 9); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, - 0xFBFF, ext_lna << 10); - b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - tmp = (gain >> 2) & 0x3; - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, - 0xE7FF, tmp<<11); - b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3); - } -} - -static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain) -{ - if (dev->phy.rev < 2) - lpphy_rev0_1_set_rx_gain(dev, gain); - else - lpphy_rev2plus_set_rx_gain(dev, gain); - lpphy_enable_rx_gain_override(dev); -} - -static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx) -{ - u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx)); - lpphy_set_rx_gain(dev, gain); -} - -static void lpphy_stop_ddfs(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD); - b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF); -} - -static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on, - int incr1, int incr2, int scale_idx) -{ - lpphy_stop_ddfs(dev); - b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80); - b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4); - b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5); - b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB); - b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2); - b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20); -} - -static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time, - struct lpphy_iq_est *iq_est) -{ - int i; - - b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7); - b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples); - b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time); - b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF); - b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200); - - for (i = 0; i < 500; i++) { - if (!(b43_phy_read(dev, - B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) - break; - msleep(1); - } - - if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) { - b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8); - return false; - } - - iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR); - iq_est->iq_prod <<= 16; - iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR); - - iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR); - iq_est->i_pwr <<= 16; - iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR); - - iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR); - iq_est->q_pwr <<= 16; - iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR); - - b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8); - return true; -} - -static int lpphy_loopback(struct b43_wldev *dev) -{ - struct lpphy_iq_est iq_est; - int i, index = -1; - u32 tmp; - - memset(&iq_est, 0, sizeof(iq_est)); - - lpphy_set_trsw_over(dev, true, true); - b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1); - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8); - b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80); - for (i = 0; i < 32; i++) { - lpphy_set_rx_gain_by_index(dev, i); - lpphy_run_ddfs(dev, 1, 1, 5, 5, 0); - if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est))) - continue; - tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000; - if ((tmp > 4000) && (tmp < 10000)) { - index = i; - break; - } - } - lpphy_stop_ddfs(dev); - return index; -} - -/* Fixed-point division algorithm using only integer math. */ -static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision) -{ - u32 quotient, remainder; - - if (divisor == 0) - return 0; - - quotient = dividend / divisor; - remainder = dividend % divisor; - - while (precision > 0) { - quotient <<= 1; - if (remainder << 1 >= divisor) { - quotient++; - remainder = (remainder << 1) - divisor; - } - precision--; - } - - if (remainder << 1 >= divisor) - quotient++; - - return quotient; -} - -/* Read the TX power control mode from hardware. */ -static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 ctl; - - ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD); - switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) { - case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF: - lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF; - break; - case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW: - lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW; - break; - case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW: - lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW; - break; - default: - lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN; - B43_WARN_ON(1); - break; - } -} - -/* Set the TX power control mode in hardware. */ -static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 ctl; - - switch (lpphy->txpctl_mode) { - case B43_LPPHY_TXPCTL_OFF: - ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF; - break; - case B43_LPPHY_TXPCTL_HW: - ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW; - break; - case B43_LPPHY_TXPCTL_SW: - ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW; - break; - default: - ctl = 0; - B43_WARN_ON(1); - } - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, - ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF, ctl); -} - -static void lpphy_set_tx_power_control(struct b43_wldev *dev, - enum b43_lpphy_txpctl_mode mode) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - enum b43_lpphy_txpctl_mode oldmode; - - lpphy_read_tx_pctl_mode_from_hardware(dev); - oldmode = lpphy->txpctl_mode; - if (oldmode == mode) - return; - lpphy->txpctl_mode = mode; - - if (oldmode == B43_LPPHY_TXPCTL_HW) { - //TODO Update TX Power NPT - //TODO Clear all TX Power offsets - } else { - if (mode == B43_LPPHY_TXPCTL_HW) { - //TODO Recalculate target TX power - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, - 0xFF80, lpphy->tssi_idx); - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, - 0x8FFF, ((u16)lpphy->tssi_npt << 16)); - //TODO Set "TSSI Transmit Count" variable to total transmitted frame count - lpphy_disable_tx_gain_override(dev); - lpphy->tx_pwr_idx_over = -1; - } - } - if (dev->phy.rev >= 2) { - if (mode == B43_LPPHY_TXPCTL_HW) - b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2); - else - b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD); - } - lpphy_write_tx_pctl_mode_to_hardware(dev); -} - -static int b43_lpphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel); - -static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - struct lpphy_iq_est iq_est; - struct lpphy_tx_gains tx_gains; - static const u32 ideal_pwr_table[21] = { - 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64, - 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35, - 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088, - 0x0004c, 0x0002c, 0x0001a, - }; - bool old_txg_ovr; - u8 old_bbmult; - u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval, - old_rf2_ovr, old_rf2_ovrval, old_phy_ctl; - enum b43_lpphy_txpctl_mode old_txpctl; - u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0; - int loopback, i, j, inner_sum, err; - - memset(&iq_est, 0, sizeof(iq_est)); - - err = b43_lpphy_op_switch_channel(dev, 7); - if (err) { - b43dbg(dev->wl, - "RC calib: Failed to switch to channel 7, error = %d\n", - err); - } - old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40); - old_bbmult = lpphy_get_bb_mult(dev); - if (old_txg_ovr) - tx_gains = lpphy_get_tx_gains(dev); - old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0); - old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0); - old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR); - old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL); - old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2); - old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL); - old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL); - lpphy_read_tx_pctl_mode_from_hardware(dev); - old_txpctl = lpphy->txpctl_mode; - - lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); - lpphy_disable_crs(dev, true); - loopback = lpphy_loopback(dev); - if (loopback == -1) - goto finish; - lpphy_set_rx_gain_by_index(dev, loopback); - b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0); - for (i = 128; i <= 159; i++) { - b43_radio_write(dev, B2062_N_RXBB_CALIB2, i); - inner_sum = 0; - for (j = 5; j <= 25; j++) { - lpphy_run_ddfs(dev, 1, 1, j, j, 0); - if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est))) - goto finish; - mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr; - if (j == 5) - tmp = mean_sq_pwr; - ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1; - normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12); - mean_sq_pwr = ideal_pwr - normal_pwr; - mean_sq_pwr *= mean_sq_pwr; - inner_sum += mean_sq_pwr; - if ((i == 128) || (inner_sum < mean_sq_pwr_min)) { - lpphy->rc_cap = i; - mean_sq_pwr_min = inner_sum; - } - } - } - lpphy_stop_ddfs(dev); - -finish: - lpphy_restore_crs(dev, true); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr); - b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval); - b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval); - b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr); - b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl); - - lpphy_set_bb_mult(dev, old_bbmult); - if (old_txg_ovr) { - /* - * SPEC FIXME: The specs say "get_tx_gains" here, which is - * illogical. According to lwfinger, vendor driver v4.150.10.5 - * has a Set here, while v4.174.64.19 has a Get - regression in - * the vendor driver? This should be tested this once the code - * is testable. - */ - lpphy_set_tx_gains(dev, tx_gains); - } - lpphy_set_tx_power_control(dev, old_txpctl); - if (lpphy->rc_cap) - lpphy_set_rc_cap(dev); -} - -static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; - u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF; - int i; - - b43_radio_write(dev, B2063_RX_BB_SP8, 0x0); - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); - b43_radio_mask(dev, B2063_PLL_SP1, 0xF7); - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C); - b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15); - b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70); - b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52); - b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1); - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D); - - for (i = 0; i < 10000; i++) { - if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2) - break; - msleep(1); - } - - if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)) - b43_radio_write(dev, B2063_RX_BB_SP8, tmp); - - tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF; - - b43_radio_write(dev, B2063_TX_BB_SP3, 0x0); - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C); - b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55); - b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76); - - if (crystal_freq == 24000000) { - b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC); - b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0); - } else { - b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13); - b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1); - } - - b43_radio_write(dev, B2063_PA_SP7, 0x7D); - - for (i = 0; i < 10000; i++) { - if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2) - break; - msleep(1); - } - - if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)) - b43_radio_write(dev, B2063_TX_BB_SP3, tmp); - - b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E); -} - -static void lpphy_calibrate_rc(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - - if (dev->phy.rev >= 2) { - lpphy_rev2plus_rc_calib(dev); - } else if (!lpphy->rc_cap) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - lpphy_rev0_1_rc_calib(dev); - } else { - lpphy_set_rc_cap(dev); - } -} - -static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) -{ - if (dev->phy.rev >= 2) - return; // rev2+ doesn't support antenna diversity - - if (B43_WARN_ON(antenna > B43_ANTENNA_AUTO1)) - return; - - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); - - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFD, antenna & 0x2); - b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFFE, antenna & 0x1); - - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); - - dev->phy.lp->antenna = antenna; -} - -static void lpphy_set_tx_iqcc(struct b43_wldev *dev, u16 a, u16 b) -{ - u16 tmp[2]; - - tmp[0] = a; - tmp[1] = b; - b43_lptab_write_bulk(dev, B43_LPTAB16(0, 80), 2, tmp); -} - -static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - struct lpphy_tx_gains gains; - u32 iq_comp, tx_gain, coeff, rf_power; - - lpphy->tx_pwr_idx_over = index; - lpphy_read_tx_pctl_mode_from_hardware(dev); - if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF) - lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW); - if (dev->phy.rev >= 2) { - iq_comp = b43_lptab_read(dev, B43_LPTAB32(7, index + 320)); - tx_gain = b43_lptab_read(dev, B43_LPTAB32(7, index + 192)); - gains.pad = (tx_gain >> 16) & 0xFF; - gains.gm = tx_gain & 0xFF; - gains.pga = (tx_gain >> 8) & 0xFF; - gains.dac = (iq_comp >> 28) & 0xFF; - lpphy_set_tx_gains(dev, gains); - } else { - iq_comp = b43_lptab_read(dev, B43_LPTAB32(10, index + 320)); - tx_gain = b43_lptab_read(dev, B43_LPTAB32(10, index + 192)); - b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, - 0xF800, (tx_gain >> 4) & 0x7FFF); - lpphy_set_dac_gain(dev, tx_gain & 0x7); - lpphy_set_pa_gain(dev, (tx_gain >> 24) & 0x7F); - } - lpphy_set_bb_mult(dev, (iq_comp >> 20) & 0xFF); - lpphy_set_tx_iqcc(dev, (iq_comp >> 10) & 0x3FF, iq_comp & 0x3FF); - if (dev->phy.rev >= 2) { - coeff = b43_lptab_read(dev, B43_LPTAB32(7, index + 448)); - } else { - coeff = b43_lptab_read(dev, B43_LPTAB32(10, index + 448)); - } - b43_lptab_write(dev, B43_LPTAB16(0, 85), coeff & 0xFFFF); - if (dev->phy.rev >= 2) { - rf_power = b43_lptab_read(dev, B43_LPTAB32(7, index + 576)); - b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, - rf_power & 0xFFFF);//SPEC FIXME mask & set != 0 - } - lpphy_enable_tx_gain_override(dev); -} - -static void lpphy_btcoex_override(struct b43_wldev *dev) -{ - b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3); - b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF); -} - -static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - //TODO check MAC control register - if (blocked) { - if (dev->phy.rev >= 2) { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x83FF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00); - b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0x80FF); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xDFFF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0808); - } else { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xE0FF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1F00); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFCFF); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x0018); - } - } else { - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xE0FF); - if (dev->phy.rev >= 2) - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xF7F7); - else - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFFE7); - } -} - -/* This was previously called lpphy_japan_filter */ -static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter! - - if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific? - b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9); - if ((dev->phy.rev == 1) && (lpphy->rc_cap)) - lpphy_set_rc_cap(dev); - } else { - b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F); - } -} - -static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode) -{ - if (mode != TSSI_MUX_EXT) { - b43_radio_set(dev, B2063_PA_SP1, 0x2); - b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000); - b43_radio_write(dev, B2063_PA_CTL10, 0x51); - if (mode == TSSI_MUX_POSTPA) { - b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE); - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7); - } else { - b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1); - b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL, - 0xFFC7, 0x20); - } - } else { - B43_WARN_ON(1); - } -} - -static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev) -{ - u16 tmp; - int i; - - //SPEC TODO Call LP PHY Clear TX Power offsets - for (i = 0; i < 64; i++) { - if (dev->phy.rev >= 2) - b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i); - else - b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i); - } - - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF); - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000); - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F); - if (dev->phy.rev < 2) { - b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF); - b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000); - } else { - b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE); - b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4); - b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10); - b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1); - lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA); - } - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000); - b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF); - b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA); - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, - ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF, - B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF); - b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF); - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD, - ~B43_LPPHY_TX_PWR_CTL_CMD_MODE & 0xFFFF, - B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW); - - if (dev->phy.rev < 2) { - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF); - } else { - lpphy_set_tx_power_by_index(dev, 0x7F); - } - - b43_dummy_transmission(dev, true, true); - - tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT); - if (tmp & 0x8000) { - b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, - 0xFFC0, (tmp & 0xFF) - 32); - } - - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF); - - // (SPEC?) TODO Set "Target TX frequency" variable to 0 - // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8! -} - -static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev) -{ - struct lpphy_tx_gains gains; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - gains.gm = 4; - gains.pad = 12; - gains.pga = 12; - gains.dac = 0; - } else { - gains.gm = 7; - gains.pad = 14; - gains.pga = 15; - gains.dac = 0; - } - lpphy_set_tx_gains(dev, gains); - lpphy_set_bb_mult(dev, 150); -} - -/* Initialize TX power control */ -static void lpphy_tx_pctl_init(struct b43_wldev *dev) -{ - if (0/*FIXME HWPCTL capable */) { - lpphy_tx_pctl_init_hw(dev); - } else { /* This device is only software TX power control capable. */ - lpphy_tx_pctl_init_sw(dev); - } -} - -static void lpphy_pr41573_workaround(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u32 *saved_tab; - const unsigned int saved_tab_size = 256; - enum b43_lpphy_txpctl_mode txpctl_mode; - s8 tx_pwr_idx_over; - u16 tssi_npt, tssi_idx; - - saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL); - if (!saved_tab) { - b43err(dev->wl, "PR41573 failed. Out of memory!\n"); - return; - } - - lpphy_read_tx_pctl_mode_from_hardware(dev); - txpctl_mode = lpphy->txpctl_mode; - tx_pwr_idx_over = lpphy->tx_pwr_idx_over; - tssi_npt = lpphy->tssi_npt; - tssi_idx = lpphy->tssi_idx; - - if (dev->phy.rev < 2) { - b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140), - saved_tab_size, saved_tab); - } else { - b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140), - saved_tab_size, saved_tab); - } - //FIXME PHY reset - lpphy_table_init(dev); //FIXME is table init needed? - lpphy_baseband_init(dev); - lpphy_tx_pctl_init(dev); - b43_lpphy_op_software_rfkill(dev, false); - lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); - if (dev->phy.rev < 2) { - b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0x140), - saved_tab_size, saved_tab); - } else { - b43_lptab_write_bulk(dev, B43_LPTAB32(7, 0x140), - saved_tab_size, saved_tab); - } - b43_write16(dev, B43_MMIO_CHANNEL, lpphy->channel); - lpphy->tssi_npt = tssi_npt; - lpphy->tssi_idx = tssi_idx; - lpphy_set_analog_filter(dev, lpphy->channel); - if (tx_pwr_idx_over != -1) - lpphy_set_tx_power_by_index(dev, tx_pwr_idx_over); - if (lpphy->rc_cap) - lpphy_set_rc_cap(dev); - b43_lpphy_op_set_rx_antenna(dev, lpphy->antenna); - lpphy_set_tx_power_control(dev, txpctl_mode); - kfree(saved_tab); -} - -struct lpphy_rx_iq_comp { u8 chan; s8 c1, c0; }; - -static const struct lpphy_rx_iq_comp lpphy_5354_iq_table[] = { - { .chan = 1, .c1 = -66, .c0 = 15, }, - { .chan = 2, .c1 = -66, .c0 = 15, }, - { .chan = 3, .c1 = -66, .c0 = 15, }, - { .chan = 4, .c1 = -66, .c0 = 15, }, - { .chan = 5, .c1 = -66, .c0 = 15, }, - { .chan = 6, .c1 = -66, .c0 = 15, }, - { .chan = 7, .c1 = -66, .c0 = 14, }, - { .chan = 8, .c1 = -66, .c0 = 14, }, - { .chan = 9, .c1 = -66, .c0 = 14, }, - { .chan = 10, .c1 = -66, .c0 = 14, }, - { .chan = 11, .c1 = -66, .c0 = 14, }, - { .chan = 12, .c1 = -66, .c0 = 13, }, - { .chan = 13, .c1 = -66, .c0 = 13, }, - { .chan = 14, .c1 = -66, .c0 = 13, }, -}; - -static const struct lpphy_rx_iq_comp lpphy_rev0_1_iq_table[] = { - { .chan = 1, .c1 = -64, .c0 = 13, }, - { .chan = 2, .c1 = -64, .c0 = 13, }, - { .chan = 3, .c1 = -64, .c0 = 13, }, - { .chan = 4, .c1 = -64, .c0 = 13, }, - { .chan = 5, .c1 = -64, .c0 = 12, }, - { .chan = 6, .c1 = -64, .c0 = 12, }, - { .chan = 7, .c1 = -64, .c0 = 12, }, - { .chan = 8, .c1 = -64, .c0 = 12, }, - { .chan = 9, .c1 = -64, .c0 = 12, }, - { .chan = 10, .c1 = -64, .c0 = 11, }, - { .chan = 11, .c1 = -64, .c0 = 11, }, - { .chan = 12, .c1 = -64, .c0 = 11, }, - { .chan = 13, .c1 = -64, .c0 = 11, }, - { .chan = 14, .c1 = -64, .c0 = 10, }, - { .chan = 34, .c1 = -62, .c0 = 24, }, - { .chan = 38, .c1 = -62, .c0 = 24, }, - { .chan = 42, .c1 = -62, .c0 = 24, }, - { .chan = 46, .c1 = -62, .c0 = 23, }, - { .chan = 36, .c1 = -62, .c0 = 24, }, - { .chan = 40, .c1 = -62, .c0 = 24, }, - { .chan = 44, .c1 = -62, .c0 = 23, }, - { .chan = 48, .c1 = -62, .c0 = 23, }, - { .chan = 52, .c1 = -62, .c0 = 23, }, - { .chan = 56, .c1 = -62, .c0 = 22, }, - { .chan = 60, .c1 = -62, .c0 = 22, }, - { .chan = 64, .c1 = -62, .c0 = 22, }, - { .chan = 100, .c1 = -62, .c0 = 16, }, - { .chan = 104, .c1 = -62, .c0 = 16, }, - { .chan = 108, .c1 = -62, .c0 = 15, }, - { .chan = 112, .c1 = -62, .c0 = 14, }, - { .chan = 116, .c1 = -62, .c0 = 14, }, - { .chan = 120, .c1 = -62, .c0 = 13, }, - { .chan = 124, .c1 = -62, .c0 = 12, }, - { .chan = 128, .c1 = -62, .c0 = 12, }, - { .chan = 132, .c1 = -62, .c0 = 12, }, - { .chan = 136, .c1 = -62, .c0 = 11, }, - { .chan = 140, .c1 = -62, .c0 = 10, }, - { .chan = 149, .c1 = -61, .c0 = 9, }, - { .chan = 153, .c1 = -61, .c0 = 9, }, - { .chan = 157, .c1 = -61, .c0 = 9, }, - { .chan = 161, .c1 = -61, .c0 = 8, }, - { .chan = 165, .c1 = -61, .c0 = 8, }, - { .chan = 184, .c1 = -62, .c0 = 25, }, - { .chan = 188, .c1 = -62, .c0 = 25, }, - { .chan = 192, .c1 = -62, .c0 = 25, }, - { .chan = 196, .c1 = -62, .c0 = 25, }, - { .chan = 200, .c1 = -62, .c0 = 25, }, - { .chan = 204, .c1 = -62, .c0 = 25, }, - { .chan = 208, .c1 = -62, .c0 = 25, }, - { .chan = 212, .c1 = -62, .c0 = 25, }, - { .chan = 216, .c1 = -62, .c0 = 26, }, -}; - -static const struct lpphy_rx_iq_comp lpphy_rev2plus_iq_comp = { - .chan = 0, - .c1 = -64, - .c0 = 0, -}; - -static int lpphy_calc_rx_iq_comp(struct b43_wldev *dev, u16 samples) -{ - struct lpphy_iq_est iq_est; - u16 c0, c1; - int prod, ipwr, qpwr, prod_msb, q_msb, tmp1, tmp2, tmp3, tmp4, ret; - - c1 = b43_phy_read(dev, B43_LPPHY_RX_COMP_COEFF_S); - c0 = c1 >> 8; - c1 |= 0xFF; - - b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, 0x00C0); - b43_phy_mask(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF); - - ret = lpphy_rx_iq_est(dev, samples, 32, &iq_est); - if (!ret) - goto out; - - prod = iq_est.iq_prod; - ipwr = iq_est.i_pwr; - qpwr = iq_est.q_pwr; - - if (ipwr + qpwr < 2) { - ret = 0; - goto out; - } - - prod_msb = fls(abs(prod)); - q_msb = fls(abs(qpwr)); - tmp1 = prod_msb - 20; - - if (tmp1 >= 0) { - tmp3 = ((prod << (30 - prod_msb)) + (ipwr >> (1 + tmp1))) / - (ipwr >> tmp1); - } else { - tmp3 = ((prod << (30 - prod_msb)) + (ipwr << (-1 - tmp1))) / - (ipwr << -tmp1); - } - - tmp2 = q_msb - 11; - - if (tmp2 >= 0) - tmp4 = (qpwr << (31 - q_msb)) / (ipwr >> tmp2); - else - tmp4 = (qpwr << (31 - q_msb)) / (ipwr << -tmp2); - - tmp4 -= tmp3 * tmp3; - tmp4 = -int_sqrt(tmp4); - - c0 = tmp3 >> 3; - c1 = tmp4 >> 4; - -out: - b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, c1); - b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0x00FF, c0 << 8); - return ret; -} - -static void lpphy_run_samples(struct b43_wldev *dev, u16 samples, u16 loops, - u16 wait) -{ - b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, - 0xFFC0, samples - 1); - if (loops != 0xFFFF) - loops--; - b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000, loops); - b43_phy_maskset(dev, B43_LPPHY_SMPL_PLAY_BUFFER_CTL, 0x3F, wait << 6); - b43_phy_set(dev, B43_LPPHY_A_PHY_CTL_ADDR, 0x1); -} - -//SPEC FIXME what does a negative freq mean? -static void lpphy_start_tx_tone(struct b43_wldev *dev, s32 freq, u16 max) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - u16 buf[64]; - int i, samples = 0, angle = 0; - int rotation = (((36 * freq) / 20) << 16) / 100; - struct b43_c32 sample; - - lpphy->tx_tone_freq = freq; - - if (freq) { - /* Find i for which abs(freq) integrally divides 20000 * i */ - for (i = 1; samples * abs(freq) != 20000 * i; i++) { - samples = (20000 * i) / abs(freq); - if(B43_WARN_ON(samples > 63)) - return; - } - } else { - samples = 2; - } - - for (i = 0; i < samples; i++) { - sample = b43_cordic(angle); - angle += rotation; - buf[i] = CORDIC_CONVERT((sample.i * max) & 0xFF) << 8; - buf[i] |= CORDIC_CONVERT((sample.q * max) & 0xFF); - } - - b43_lptab_write_bulk(dev, B43_LPTAB16(5, 0), samples, buf); - - lpphy_run_samples(dev, samples, 0xFFFF, 0); -} - -static void lpphy_stop_tx_tone(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - int i; - - lpphy->tx_tone_freq = 0; - - b43_phy_mask(dev, B43_LPPHY_SMPL_PLAY_COUNT, 0xF000); - for (i = 0; i < 31; i++) { - if (!(b43_phy_read(dev, B43_LPPHY_A_PHY_CTL_ADDR) & 0x1)) - break; - udelay(100); - } -} - - -static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains, - int mode, bool useindex, u8 index) -{ - //TODO -} - -static void lpphy_papd_cal_txpwr(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - struct lpphy_tx_gains gains, oldgains; - int old_txpctl, old_afe_ovr, old_rf, old_bbmult; - - lpphy_read_tx_pctl_mode_from_hardware(dev); - old_txpctl = lpphy->txpctl_mode; - old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40; - if (old_afe_ovr) - oldgains = lpphy_get_tx_gains(dev); - old_rf = b43_phy_read(dev, B43_LPPHY_RF_PWR_OVERRIDE) & 0xFF; - old_bbmult = lpphy_get_bb_mult(dev); - - lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); - - if (dev->dev->chip_id == 0x4325 && dev->dev->chip_rev == 0) - lpphy_papd_cal(dev, gains, 0, 1, 30); - else - lpphy_papd_cal(dev, gains, 0, 1, 65); - - if (old_afe_ovr) - lpphy_set_tx_gains(dev, oldgains); - lpphy_set_bb_mult(dev, old_bbmult); - lpphy_set_tx_power_control(dev, old_txpctl); - b43_phy_maskset(dev, B43_LPPHY_RF_PWR_OVERRIDE, 0xFF00, old_rf); -} - -static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx, - bool rx, bool pa, struct lpphy_tx_gains *gains) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - const struct lpphy_rx_iq_comp *iqcomp = NULL; - struct lpphy_tx_gains nogains, oldgains; - u16 tmp; - int i, ret; - - memset(&nogains, 0, sizeof(nogains)); - memset(&oldgains, 0, sizeof(oldgains)); - - if (dev->dev->chip_id == 0x5354) { - for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) { - if (lpphy_5354_iq_table[i].chan == lpphy->channel) { - iqcomp = &lpphy_5354_iq_table[i]; - } - } - } else if (dev->phy.rev >= 2) { - iqcomp = &lpphy_rev2plus_iq_comp; - } else { - for (i = 0; i < ARRAY_SIZE(lpphy_rev0_1_iq_table); i++) { - if (lpphy_rev0_1_iq_table[i].chan == lpphy->channel) { - iqcomp = &lpphy_rev0_1_iq_table[i]; - } - } - } - - if (B43_WARN_ON(!iqcomp)) - return 0; - - b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, 0xFF00, iqcomp->c1); - b43_phy_maskset(dev, B43_LPPHY_RX_COMP_COEFF_S, - 0x00FF, iqcomp->c0 << 8); - - if (noise) { - tx = true; - rx = false; - pa = false; - } - - lpphy_set_trsw_over(dev, tx, rx); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, - 0xFFF7, pa << 3); - } else { - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20); - b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, - 0xFFDF, pa << 5); - } - - tmp = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40; - - if (noise) - lpphy_set_rx_gain(dev, 0x2D5D); - else { - if (tmp) - oldgains = lpphy_get_tx_gains(dev); - if (!gains) - gains = &nogains; - lpphy_set_tx_gains(dev, *gains); - } - - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800); - b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800); - lpphy_set_deaf(dev, false); - if (noise) - ret = lpphy_calc_rx_iq_comp(dev, 0xFFF0); - else { - lpphy_start_tx_tone(dev, 4000, 100); - ret = lpphy_calc_rx_iq_comp(dev, 0x4000); - lpphy_stop_tx_tone(dev); - } - lpphy_clear_deaf(dev, false); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFC); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFF7); - b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFDF); - if (!noise) { - if (tmp) - lpphy_set_tx_gains(dev, oldgains); - else - lpphy_disable_tx_gain_override(dev); - } - lpphy_disable_rx_gain_override(dev); - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFFE); - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xF7FF); - return ret; -} - -static void lpphy_calibration(struct b43_wldev *dev) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - enum b43_lpphy_txpctl_mode saved_pctl_mode; - bool full_cal = false; - - if (lpphy->full_calib_chan != lpphy->channel) { - full_cal = true; - lpphy->full_calib_chan = lpphy->channel; - } - - b43_mac_suspend(dev); - - lpphy_btcoex_override(dev); - if (dev->phy.rev >= 2) - lpphy_save_dig_flt_state(dev); - lpphy_read_tx_pctl_mode_from_hardware(dev); - saved_pctl_mode = lpphy->txpctl_mode; - lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); - //TODO Perform transmit power table I/Q LO calibration - if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF)) - lpphy_pr41573_workaround(dev); - if ((dev->phy.rev >= 2) && full_cal) { - lpphy_papd_cal_txpwr(dev); - } - lpphy_set_tx_power_control(dev, saved_pctl_mode); - if (dev->phy.rev >= 2) - lpphy_restore_dig_flt_state(dev); - lpphy_rx_iq_cal(dev, true, true, false, false, NULL); - - b43_mac_enable(dev); -} - -static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, - u16 set) -{ - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, - (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set); -} - -static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - /* LP-PHY needs a special bit set for read access */ - if (dev->phy.rev < 2) { - if (reg != 0x4001) - reg |= 0x100; - } else - reg |= 0x200; - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); -} - -static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); -} - -struct b206x_channel { - u8 channel; - u16 freq; - u8 data[12]; -}; - -static const struct b206x_channel b2062_chantbl[] = { - { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF, - .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32, - .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, }, - { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22, - .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11, - .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11, - .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11, - .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11, - .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11, - .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00, - .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77, - .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77, - .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66, - .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66, - .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55, - .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55, - .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44, - .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, }, - { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44, - .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, - { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44, - .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77, - .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, }, -}; - -static const struct b206x_channel b2063_chantbl[] = { - { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C, - .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C, - .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C, - .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C, - .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C, - .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C, - .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C, - .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C, - .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C, - .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C, - .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C, - .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C, - .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C, - .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05, - .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x80, .data[11] = 0x70, }, - { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05, - .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05, - .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04, - .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04, - .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04, - .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04, - .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03, - .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03, - .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02, - .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60, - .data[10] = 0x20, .data[11] = 0x00, }, - { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01, - .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50, - .data[10] = 0x10, .data[11] = 0x00, }, - { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01, - .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50, - .data[10] = 0x10, .data[11] = 0x00, }, - { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50, - .data[10] = 0x10, .data[11] = 0x00, }, - { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00, - .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00, - .data[10] = 0x00, .data[11] = 0x00, }, - { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0, - .data[10] = 0x50, .data[11] = 0x00, }, - { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0, - .data[10] = 0x50, .data[11] = 0x00, }, - { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0, - .data[10] = 0x50, .data[11] = 0x00, }, - { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0, - .data[10] = 0x40, .data[11] = 0x00, }, - { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0, - .data[10] = 0x40, .data[11] = 0x00, }, - { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0, - .data[10] = 0x40, .data[11] = 0x00, }, - { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90, - .data[10] = 0x40, .data[11] = 0x00, }, - { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90, - .data[10] = 0x40, .data[11] = 0x00, }, - { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C, - .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08, - .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90, - .data[10] = 0x40, .data[11] = 0x00, }, -}; - -static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev) -{ - b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF); - udelay(20); - if (dev->dev->chip_id == 0x5354) { - b43_radio_write(dev, B2062_N_COMM1, 4); - b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4); - } else { - b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0); - } - udelay(5); -} - -static void lpphy_b2062_vco_calib(struct b43_wldev *dev) -{ - b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42); - b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62); - udelay(200); -} - -static int lpphy_b2062_tune(struct b43_wldev *dev, - unsigned int channel) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - struct ssb_bus *bus = dev->dev->sdev->bus; - const struct b206x_channel *chandata = NULL; - u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; - u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9; - int i, err = 0; - - for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) { - if (b2062_chantbl[i].channel == channel) { - chandata = &b2062_chantbl[i]; - break; - } - } - - if (B43_WARN_ON(!chandata)) - return -EINVAL; - - b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04); - b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]); - b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]); - b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]); - b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]); - b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]); - b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]); - b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]); - b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]); - b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]); - - tmp1 = crystal_freq / 1000; - tmp2 = lpphy->pdiv * 1000; - b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC); - b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07); - lpphy_b2062_reset_pll_bias(dev); - tmp3 = tmp2 * channel2freq_lp(channel); - if (channel2freq_lp(channel) < 4000) - tmp3 *= 2; - tmp4 = 48 * tmp1; - tmp6 = tmp3 / tmp4; - tmp7 = tmp3 % tmp4; - b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6); - tmp5 = tmp7 * 0x100; - tmp6 = tmp5 / tmp4; - tmp7 = tmp5 % tmp4; - b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6); - tmp5 = tmp7 * 0x100; - tmp6 = tmp5 / tmp4; - tmp7 = tmp5 % tmp4; - b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6); - tmp5 = tmp7 * 0x100; - tmp6 = tmp5 / tmp4; - tmp7 = tmp5 % tmp4; - b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4)); - tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19); - tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1); - b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16); - b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF); - - lpphy_b2062_vco_calib(dev); - if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) { - b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC); - b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0); - lpphy_b2062_reset_pll_bias(dev); - lpphy_b2062_vco_calib(dev); - if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) - err = -EIO; - } - - b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04); - return err; -} - -static void lpphy_b2063_vco_calib(struct b43_wldev *dev) -{ - u16 tmp; - - b43_radio_mask(dev, B2063_PLL_SP1, ~0x40); - tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8; - b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp); - udelay(1); - b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4); - udelay(1); - b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6); - udelay(1); - b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7); - udelay(300); - b43_radio_set(dev, B2063_PLL_SP1, 0x40); -} - -static int lpphy_b2063_tune(struct b43_wldev *dev, - unsigned int channel) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - - static const struct b206x_channel *chandata = NULL; - u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; - u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count; - u16 old_comm15, scale; - u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; - int i, div = (crystal_freq <= 26000000 ? 1 : 2); - - for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) { - if (b2063_chantbl[i].channel == channel) { - chandata = &b2063_chantbl[i]; - break; - } - } - - if (B43_WARN_ON(!chandata)) - return -EINVAL; - - b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]); - b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]); - b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]); - b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]); - b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]); - b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]); - b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]); - b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]); - b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]); - b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]); - b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]); - b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]); - - old_comm15 = b43_radio_read(dev, B2063_COMM15); - b43_radio_set(dev, B2063_COMM15, 0x1E); - - if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */ - vco_freq = chandata->freq << 1; - else - vco_freq = chandata->freq << 2; - - freqref = crystal_freq * 3; - val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16); - val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16); - val3 = lpphy_qdiv_roundup(vco_freq, 3, 16); - timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1; - b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6, - 0xFFF8, timeout >> 2); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7, - 0xFF9F,timeout << 5); - - timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) + - 999999) / 1000000) + 1; - b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref); - - count = lpphy_qdiv_roundup(val3, val2 + 16, 16); - count *= (timeout + 1) * (timeoutref + 1); - count--; - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7, - 0xF0, count >> 8); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF); - - tmp1 = ((val3 * 62500) / freqref) << 4; - tmp2 = ((val3 * 62500) % freqref) << 4; - while (tmp2 >= freqref) { - tmp1++; - tmp2 -= freqref; - } - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF); - - b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28); - b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63); - - tmp3 = ((41 * (val3 - 3000)) /1200) + 27; - tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16); - - if ((tmp4 + tmp3 - 1) / tmp3 > 60) { - scale = 1; - tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8; - } else { - scale = 0; - tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8; - } - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6); - - tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16); - tmp6 *= (tmp5 * 8) * (scale + 1); - if (tmp6 > 150) - tmp6 = 0; - - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6); - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5); - - b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4); - if (crystal_freq > 26000000) - b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2); - else - b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD); - - if (val1 == 45) - b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2); - else - b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD); - - b43_radio_set(dev, B2063_PLL_SP2, 0x3); - udelay(1); - b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC); - lpphy_b2063_vco_calib(dev); - b43_radio_write(dev, B2063_COMM15, old_comm15); - - return 0; -} - -static int b43_lpphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - struct b43_phy_lp *lpphy = dev->phy.lp; - int err; - - if (dev->phy.radio_ver == 0x2063) { - err = lpphy_b2063_tune(dev, new_channel); - if (err) - return err; - } else { - err = lpphy_b2062_tune(dev, new_channel); - if (err) - return err; - lpphy_set_analog_filter(dev, new_channel); - lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel)); - } - - lpphy->channel = new_channel; - b43_write16(dev, B43_MMIO_CHANNEL, new_channel); - - return 0; -} - -static int b43_lpphy_op_init(struct b43_wldev *dev) -{ - int err; - - if (dev->dev->bus_type != B43_BUS_SSB) { - b43err(dev->wl, "LP-PHY is supported only on SSB!\n"); - return -EOPNOTSUPP; - } - - lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs? - lpphy_baseband_init(dev); - lpphy_radio_init(dev); - lpphy_calibrate_rc(dev); - err = b43_lpphy_op_switch_channel(dev, 7); - if (err) { - b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n", - err); - } - lpphy_tx_pctl_init(dev); - lpphy_calibration(dev); - //TODO ACI init - - return 0; -} - -static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev) -{ - //TODO -} - -static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev, - bool ignore_tssi) -{ - //TODO - return B43_TXPWR_RES_DONE; -} - -static void b43_lpphy_op_switch_analog(struct b43_wldev *dev, bool on) -{ - if (on) { - b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVR, 0xfff8); - } else { - b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0x0007); - b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 0x0007); - } -} - -static void b43_lpphy_op_pwork_15sec(struct b43_wldev *dev) -{ - //TODO -} - -const struct b43_phy_operations b43_phyops_lp = { - .allocate = b43_lpphy_op_allocate, - .free = b43_lpphy_op_free, - .prepare_structs = b43_lpphy_op_prepare_structs, - .init = b43_lpphy_op_init, - .phy_maskset = b43_lpphy_op_maskset, - .radio_read = b43_lpphy_op_radio_read, - .radio_write = b43_lpphy_op_radio_write, - .software_rfkill = b43_lpphy_op_software_rfkill, - .switch_analog = b43_lpphy_op_switch_analog, - .switch_channel = b43_lpphy_op_switch_channel, - .get_default_chan = b43_lpphy_op_get_default_chan, - .set_rx_antenna = b43_lpphy_op_set_rx_antenna, - .recalc_txpower = b43_lpphy_op_recalc_txpower, - .adjust_txpower = b43_lpphy_op_adjust_txpower, - .pwork_15sec = b43_lpphy_op_pwork_15sec, - .pwork_60sec = lpphy_calibration, -}; diff --git a/drivers/net/wireless/b43/phy_lp.h b/drivers/net/wireless/b43/phy_lp.h deleted file mode 100644 index 62737f700..000000000 --- a/drivers/net/wireless/b43/phy_lp.h +++ /dev/null @@ -1,912 +0,0 @@ -#ifndef LINUX_B43_PHY_LP_H_ -#define LINUX_B43_PHY_LP_H_ - -/* Definitions for the LP-PHY */ - - -/* The CCK PHY register range. */ -#define B43_LPPHY_B_VERSION B43_PHY_CCK(0x00) /* B PHY version */ -#define B43_LPPHY_B_BBCONFIG B43_PHY_CCK(0x01) /* B PHY BBConfig */ -#define B43_LPPHY_B_RX_STAT0 B43_PHY_CCK(0x04) /* B PHY RX Status0 */ -#define B43_LPPHY_B_RX_STAT1 B43_PHY_CCK(0x05) /* B PHY RX Status1 */ -#define B43_LPPHY_B_CRS_THRESH B43_PHY_CCK(0x06) /* B PHY CRS Thresh */ -#define B43_LPPHY_B_TXERROR B43_PHY_CCK(0x07) /* B PHY TxError */ -#define B43_LPPHY_B_CHANNEL B43_PHY_CCK(0x08) /* B PHY Channel */ -#define B43_LPPHY_B_WORKAROUND B43_PHY_CCK(0x09) /* B PHY workaround */ -#define B43_LPPHY_B_TEST B43_PHY_CCK(0x0A) /* B PHY Test */ -#define B43_LPPHY_B_FOURWIRE_ADDR B43_PHY_CCK(0x0B) /* B PHY Fourwire Address */ -#define B43_LPPHY_B_FOURWIRE_DATA_HI B43_PHY_CCK(0x0C) /* B PHY Fourwire Data Hi */ -#define B43_LPPHY_B_FOURWIRE_DATA_LO B43_PHY_CCK(0x0D) /* B PHY Fourwire Data Lo */ -#define B43_LPPHY_B_BIST_STAT B43_PHY_CCK(0x0E) /* B PHY Bist Status */ -#define B43_LPPHY_PA_RAMP_TX_TO B43_PHY_CCK(0x10) /* PA Ramp TX Timeout */ -#define B43_LPPHY_RF_SYNTH_DC_TIMER B43_PHY_CCK(0x11) /* RF Synth DC Timer */ -#define B43_LPPHY_PA_RAMP_TX_TIME_IN B43_PHY_CCK(0x12) /* PA ramp TX Time in */ -#define B43_LPPHY_RX_FILTER_TIME_IN B43_PHY_CCK(0x13) /* RX Filter Time in */ -#define B43_LPPHY_PLL_COEFF_S B43_PHY_CCK(0x18) /* PLL Coefficient(s) */ -#define B43_LPPHY_PLL_OUT B43_PHY_CCK(0x19) /* PLL Out */ -#define B43_LPPHY_RSSI_THRES B43_PHY_CCK(0x20) /* RSSI Threshold */ -#define B43_LPPHY_IQ_THRES_HH B43_PHY_CCK(0x21) /* IQ Threshold HH */ -#define B43_LPPHY_IQ_THRES_H B43_PHY_CCK(0x22) /* IQ Threshold H */ -#define B43_LPPHY_IQ_THRES_L B43_PHY_CCK(0x23) /* IQ Threshold L */ -#define B43_LPPHY_IQ_THRES_LL B43_PHY_CCK(0x24) /* IQ Threshold LL */ -#define B43_LPPHY_AGC_GAIN B43_PHY_CCK(0x25) /* AGC Gain */ -#define B43_LPPHY_LNA_GAIN_RANGE B43_PHY_CCK(0x26) /* LNA Gain Range */ -#define B43_LPPHY_JSSI B43_PHY_CCK(0x27) /* JSSI */ -#define B43_LPPHY_TSSI_CTL B43_PHY_CCK(0x28) /* TSSI Control */ -#define B43_LPPHY_TSSI B43_PHY_CCK(0x29) /* TSSI */ -#define B43_LPPHY_TR_LOSS B43_PHY_CCK(0x2A) /* TR Loss */ -#define B43_LPPHY_LO_LEAKAGE B43_PHY_CCK(0x2B) /* LO Leakage */ -#define B43_LPPHY_LO_RSSIACC B43_PHY_CCK(0x2C) /* LO RSSIAcc */ -#define B43_LPPHY_LO_IQ_MAG_ACC B43_PHY_CCK(0x2D) /* LO IQ Mag Acc */ -#define B43_LPPHY_TX_DCOFFSET1 B43_PHY_CCK(0x2E) /* TX DCOffset1 */ -#define B43_LPPHY_TX_DCOFFSET2 B43_PHY_CCK(0x2F) /* TX DCOffset2 */ -#define B43_LPPHY_SYNCPEAKCNT B43_PHY_CCK(0x30) /* SyncPeakCnt */ -#define B43_LPPHY_SYNCFREQ B43_PHY_CCK(0x31) /* SyncFreq */ -#define B43_LPPHY_SYNCDIVERSITYCTL B43_PHY_CCK(0x32) /* SyncDiversityControl */ -#define B43_LPPHY_PEAKENERGYL B43_PHY_CCK(0x33) /* PeakEnergyL */ -#define B43_LPPHY_PEAKENERGYH B43_PHY_CCK(0x34) /* PeakEnergyH */ -#define B43_LPPHY_SYNCCTL B43_PHY_CCK(0x35) /* SyncControl */ -#define B43_LPPHY_DSSSSTEP B43_PHY_CCK(0x38) /* DsssStep */ -#define B43_LPPHY_DSSSWARMUP B43_PHY_CCK(0x39) /* DsssWarmup */ -#define B43_LPPHY_DSSSSIGPOW B43_PHY_CCK(0x3D) /* DsssSigPow */ -#define B43_LPPHY_SFDDETECTBLOCKTIME B43_PHY_CCK(0x40) /* SfdDetectBlockTIme */ -#define B43_LPPHY_SFDTO B43_PHY_CCK(0x41) /* SFDTimeOut */ -#define B43_LPPHY_SFDCTL B43_PHY_CCK(0x42) /* SFDControl */ -#define B43_LPPHY_RXDBG B43_PHY_CCK(0x43) /* rxDebug */ -#define B43_LPPHY_RX_DELAYCOMP B43_PHY_CCK(0x44) /* RX DelayComp */ -#define B43_LPPHY_CRSDROPOUTTO B43_PHY_CCK(0x45) /* CRSDropoutTimeout */ -#define B43_LPPHY_PSEUDOSHORTTO B43_PHY_CCK(0x46) /* PseudoShortTimeout */ -#define B43_LPPHY_PR3931 B43_PHY_CCK(0x47) /* PR3931 */ -#define B43_LPPHY_DSSSCOEFF1 B43_PHY_CCK(0x48) /* DSSSCoeff1 */ -#define B43_LPPHY_DSSSCOEFF2 B43_PHY_CCK(0x49) /* DSSSCoeff2 */ -#define B43_LPPHY_CCKCOEFF1 B43_PHY_CCK(0x4A) /* CCKCoeff1 */ -#define B43_LPPHY_CCKCOEFF2 B43_PHY_CCK(0x4B) /* CCKCoeff2 */ -#define B43_LPPHY_TRCORR B43_PHY_CCK(0x4C) /* TRCorr */ -#define B43_LPPHY_ANGLESCALE B43_PHY_CCK(0x4D) /* AngleScale */ -#define B43_LPPHY_OPTIONALMODES2 B43_PHY_CCK(0x4F) /* OptionalModes2 */ -#define B43_LPPHY_CCKLMSSTEPSIZE B43_PHY_CCK(0x50) /* CCKLMSStepSize */ -#define B43_LPPHY_DFEBYPASS B43_PHY_CCK(0x51) /* DFEBypass */ -#define B43_LPPHY_CCKSTARTDELAYLONG B43_PHY_CCK(0x52) /* CCKStartDelayLong */ -#define B43_LPPHY_CCKSTARTDELAYSHORT B43_PHY_CCK(0x53) /* CCKStartDelayShort */ -#define B43_LPPHY_PPROCCHDELAY B43_PHY_CCK(0x54) /* PprocChDelay */ -#define B43_LPPHY_PPROCONOFF B43_PHY_CCK(0x55) /* PProcOnOff */ -#define B43_LPPHY_LNAGAINTWOBIT10 B43_PHY_CCK(0x5B) /* LNAGainTwoBit10 */ -#define B43_LPPHY_LNAGAINTWOBIT32 B43_PHY_CCK(0x5C) /* LNAGainTwoBit32 */ -#define B43_LPPHY_OPTIONALMODES B43_PHY_CCK(0x5D) /* OptionalModes */ -#define B43_LPPHY_B_RX_STAT2 B43_PHY_CCK(0x5E) /* B PHY RX Status2 */ -#define B43_LPPHY_B_RX_STAT3 B43_PHY_CCK(0x5F) /* B PHY RX Status3 */ -#define B43_LPPHY_PWDNDACDELAY B43_PHY_CCK(0x63) /* pwdnDacDelay */ -#define B43_LPPHY_FINEDIGIGAIN_CTL B43_PHY_CCK(0x67) /* FineDigiGain Control */ -#define B43_LPPHY_LG2GAINTBLLNA8 B43_PHY_CCK(0x68) /* Lg2GainTblLNA8 */ -#define B43_LPPHY_LG2GAINTBLLNA28 B43_PHY_CCK(0x69) /* Lg2GainTblLNA28 */ -#define B43_LPPHY_GAINTBLLNATRSW B43_PHY_CCK(0x6A) /* GainTblLNATrSw */ -#define B43_LPPHY_PEAKENERGY B43_PHY_CCK(0x6B) /* PeakEnergy */ -#define B43_LPPHY_LG2INITGAIN B43_PHY_CCK(0x6C) /* lg2InitGain */ -#define B43_LPPHY_BLANKCOUNTLNAPGA B43_PHY_CCK(0x6D) /* BlankCountLnaPga */ -#define B43_LPPHY_LNAGAINTWOBIT54 B43_PHY_CCK(0x6E) /* LNAGainTwoBit54 */ -#define B43_LPPHY_LNAGAINTWOBIT76 B43_PHY_CCK(0x6F) /* LNAGainTwoBit76 */ -#define B43_LPPHY_JSSICTL B43_PHY_CCK(0x70) /* JSSIControl */ -#define B43_LPPHY_LG2GAINTBLLNA44 B43_PHY_CCK(0x71) /* Lg2GainTblLNA44 */ -#define B43_LPPHY_LG2GAINTBLLNA62 B43_PHY_CCK(0x72) /* Lg2GainTblLNA62 */ - -/* The OFDM PHY register range. */ -#define B43_LPPHY_VERSION B43_PHY_OFDM(0x00) /* Version */ -#define B43_LPPHY_BBCONFIG B43_PHY_OFDM(0x01) /* BBConfig */ -#define B43_LPPHY_RX_STAT0 B43_PHY_OFDM(0x04) /* RX Status0 */ -#define B43_LPPHY_RX_STAT1 B43_PHY_OFDM(0x05) /* RX Status1 */ -#define B43_LPPHY_TX_ERROR B43_PHY_OFDM(0x07) /* TX Error */ -#define B43_LPPHY_CHANNEL B43_PHY_OFDM(0x08) /* Channel */ -#define B43_LPPHY_WORKAROUND B43_PHY_OFDM(0x09) /* workaround */ -#define B43_LPPHY_FOURWIRE_ADDR B43_PHY_OFDM(0x0B) /* Fourwire Address */ -#define B43_LPPHY_FOURWIREDATAHI B43_PHY_OFDM(0x0C) /* FourwireDataHi */ -#define B43_LPPHY_FOURWIREDATALO B43_PHY_OFDM(0x0D) /* FourwireDataLo */ -#define B43_LPPHY_BISTSTAT0 B43_PHY_OFDM(0x0E) /* BistStatus0 */ -#define B43_LPPHY_BISTSTAT1 B43_PHY_OFDM(0x0F) /* BistStatus1 */ -#define B43_LPPHY_CRSGAIN_CTL B43_PHY_OFDM(0x10) /* crsgain Control */ -#define B43_LPPHY_OFDMPWR_THRESH0 B43_PHY_OFDM(0x11) /* ofdmPower Thresh0 */ -#define B43_LPPHY_OFDMPWR_THRESH1 B43_PHY_OFDM(0x12) /* ofdmPower Thresh1 */ -#define B43_LPPHY_OFDMPWR_THRESH2 B43_PHY_OFDM(0x13) /* ofdmPower Thresh2 */ -#define B43_LPPHY_DSSSPWR_THRESH0 B43_PHY_OFDM(0x14) /* dsssPower Thresh0 */ -#define B43_LPPHY_DSSSPWR_THRESH1 B43_PHY_OFDM(0x15) /* dsssPower Thresh1 */ -#define B43_LPPHY_MINPWR_LEVEL B43_PHY_OFDM(0x16) /* MinPower Level */ -#define B43_LPPHY_OFDMSYNCTHRESH0 B43_PHY_OFDM(0x17) /* ofdmSyncThresh0 */ -#define B43_LPPHY_OFDMSYNCTHRESH1 B43_PHY_OFDM(0x18) /* ofdmSyncThresh1 */ -#define B43_LPPHY_FINEFREQEST B43_PHY_OFDM(0x19) /* FineFreqEst */ -#define B43_LPPHY_IDLEAFTERPKTRXTO B43_PHY_OFDM(0x1A) /* IDLEafterPktRXTimeout */ -#define B43_LPPHY_LTRN_CTL B43_PHY_OFDM(0x1B) /* LTRN Control */ -#define B43_LPPHY_DCOFFSETTRANSIENT B43_PHY_OFDM(0x1C) /* DCOffsetTransient */ -#define B43_LPPHY_PREAMBLEINTO B43_PHY_OFDM(0x1D) /* PreambleInTimeout */ -#define B43_LPPHY_PREAMBLECONFIRMTO B43_PHY_OFDM(0x1E) /* PreambleConfirmTimeout */ -#define B43_LPPHY_CLIPTHRESH B43_PHY_OFDM(0x1F) /* ClipThresh */ -#define B43_LPPHY_CLIPCTRTHRESH B43_PHY_OFDM(0x20) /* ClipCtrThresh */ -#define B43_LPPHY_OFDMSYNCTIMER_CTL B43_PHY_OFDM(0x21) /* ofdmSyncTimer Control */ -#define B43_LPPHY_WAITFORPHYSELTO B43_PHY_OFDM(0x22) /* WaitforPHYSelTimeout */ -#define B43_LPPHY_HIGAINDB B43_PHY_OFDM(0x23) /* HiGainDB */ -#define B43_LPPHY_LOWGAINDB B43_PHY_OFDM(0x24) /* LowGainDB */ -#define B43_LPPHY_VERYLOWGAINDB B43_PHY_OFDM(0x25) /* VeryLowGainDB */ -#define B43_LPPHY_GAINMISMATCH B43_PHY_OFDM(0x26) /* gainMismatch */ -#define B43_LPPHY_GAINDIRECTMISMATCH B43_PHY_OFDM(0x27) /* gaindirectMismatch */ -#define B43_LPPHY_PWR_THRESH0 B43_PHY_OFDM(0x28) /* Power Thresh0 */ -#define B43_LPPHY_PWR_THRESH1 B43_PHY_OFDM(0x29) /* Power Thresh1 */ -#define B43_LPPHY_DETECTOR_DELAY_ADJUST B43_PHY_OFDM(0x2A) /* Detector Delay Adjust */ -#define B43_LPPHY_REDUCED_DETECTOR_DELAY B43_PHY_OFDM(0x2B) /* Reduced Detector Delay */ -#define B43_LPPHY_DATA_TO B43_PHY_OFDM(0x2C) /* data Timeout */ -#define B43_LPPHY_CORRELATOR_DIS_DELAY B43_PHY_OFDM(0x2D) /* correlator Dis Delay */ -#define B43_LPPHY_DIVERSITY_GAINBACK B43_PHY_OFDM(0x2E) /* Diversity GainBack */ -#define B43_LPPHY_DSSS_CONFIRM_CNT B43_PHY_OFDM(0x2F) /* DSSS Confirm Cnt */ -#define B43_LPPHY_DC_BLANK_INT B43_PHY_OFDM(0x30) /* DC Blank Interval */ -#define B43_LPPHY_GAIN_MISMATCH_LIMIT B43_PHY_OFDM(0x31) /* gain Mismatch Limit */ -#define B43_LPPHY_CRS_ED_THRESH B43_PHY_OFDM(0x32) /* crs ed thresh */ -#define B43_LPPHY_PHASE_SHIFT_CTL B43_PHY_OFDM(0x33) /* phase shift Control */ -#define B43_LPPHY_INPUT_PWRDB B43_PHY_OFDM(0x34) /* Input PowerDB */ -#define B43_LPPHY_OFDM_SYNC_CTL B43_PHY_OFDM(0x35) /* ofdm sync Control */ -#define B43_LPPHY_AFE_ADC_CTL_0 B43_PHY_OFDM(0x36) /* Afe ADC Control 0 */ -#define B43_LPPHY_AFE_ADC_CTL_1 B43_PHY_OFDM(0x37) /* Afe ADC Control 1 */ -#define B43_LPPHY_AFE_ADC_CTL_2 B43_PHY_OFDM(0x38) /* Afe ADC Control 2 */ -#define B43_LPPHY_AFE_DAC_CTL B43_PHY_OFDM(0x39) /* Afe DAC Control */ -#define B43_LPPHY_AFE_CTL B43_PHY_OFDM(0x3A) /* Afe Control */ -#define B43_LPPHY_AFE_CTL_OVR B43_PHY_OFDM(0x3B) /* Afe Control Ovr */ -#define B43_LPPHY_AFE_CTL_OVRVAL B43_PHY_OFDM(0x3C) /* Afe Control OvrVal */ -#define B43_LPPHY_AFE_RSSI_CTL_0 B43_PHY_OFDM(0x3D) /* Afe RSSI Control 0 */ -#define B43_LPPHY_AFE_RSSI_CTL_1 B43_PHY_OFDM(0x3E) /* Afe RSSI Control 1 */ -#define B43_LPPHY_AFE_RSSI_SEL B43_PHY_OFDM(0x3F) /* Afe RSSI Sel */ -#define B43_LPPHY_RADAR_THRESH B43_PHY_OFDM(0x40) /* Radar Thresh */ -#define B43_LPPHY_RADAR_BLANK_INT B43_PHY_OFDM(0x41) /* Radar blank Interval */ -#define B43_LPPHY_RADAR_MIN_FM_INT B43_PHY_OFDM(0x42) /* Radar min fm Interval */ -#define B43_LPPHY_RADAR_GAIN_TO B43_PHY_OFDM(0x43) /* Radar gain timeout */ -#define B43_LPPHY_RADAR_PULSE_TO B43_PHY_OFDM(0x44) /* Radar pulse timeout */ -#define B43_LPPHY_RADAR_DETECT_FM_CTL B43_PHY_OFDM(0x45) /* Radar detect FM Control */ -#define B43_LPPHY_RADAR_DETECT_EN B43_PHY_OFDM(0x46) /* Radar detect En */ -#define B43_LPPHY_RADAR_RD_DATA_REG B43_PHY_OFDM(0x47) /* Radar Rd Data Reg */ -#define B43_LPPHY_LP_PHY_CTL B43_PHY_OFDM(0x48) /* LP PHY Control */ -#define B43_LPPHY_CLASSIFIER_CTL B43_PHY_OFDM(0x49) /* classifier Control */ -#define B43_LPPHY_RESET_CTL B43_PHY_OFDM(0x4A) /* reset Control */ -#define B43_LPPHY_CLKEN_CTL B43_PHY_OFDM(0x4B) /* ClkEn Control */ -#define B43_LPPHY_RF_OVERRIDE_0 B43_PHY_OFDM(0x4C) /* RF Override 0 */ -#define B43_LPPHY_RF_OVERRIDE_VAL_0 B43_PHY_OFDM(0x4D) /* RF Override Val 0 */ -#define B43_LPPHY_TR_LOOKUP_1 B43_PHY_OFDM(0x4E) /* TR Lookup 1 */ -#define B43_LPPHY_TR_LOOKUP_2 B43_PHY_OFDM(0x4F) /* TR Lookup 2 */ -#define B43_LPPHY_RSSISELLOOKUP1 B43_PHY_OFDM(0x50) /* RssiSelLookup1 */ -#define B43_LPPHY_IQLO_CAL_CMD B43_PHY_OFDM(0x51) /* iqlo Cal Cmd */ -#define B43_LPPHY_IQLO_CAL_CMD_N_NUM B43_PHY_OFDM(0x52) /* iqlo Cal Cmd N num */ -#define B43_LPPHY_IQLO_CAL_CMD_G_CTL B43_PHY_OFDM(0x53) /* iqlo Cal Cmd G control */ -#define B43_LPPHY_MACINT_DBG_REGISTER B43_PHY_OFDM(0x54) /* macint Debug Register */ -#define B43_LPPHY_TABLE_ADDR B43_PHY_OFDM(0x55) /* Table Address */ -#define B43_LPPHY_TABLEDATALO B43_PHY_OFDM(0x56) /* TabledataLo */ -#define B43_LPPHY_TABLEDATAHI B43_PHY_OFDM(0x57) /* TabledataHi */ -#define B43_LPPHY_PHY_CRS_ENABLE_ADDR B43_PHY_OFDM(0x58) /* phy CRS Enable Address */ -#define B43_LPPHY_IDLETIME_CTL B43_PHY_OFDM(0x59) /* Idletime Control */ -#define B43_LPPHY_IDLETIME_CRS_ON_LO B43_PHY_OFDM(0x5A) /* Idletime CRS On Lo */ -#define B43_LPPHY_IDLETIME_CRS_ON_HI B43_PHY_OFDM(0x5B) /* Idletime CRS On Hi */ -#define B43_LPPHY_IDLETIME_MEAS_TIME_LO B43_PHY_OFDM(0x5C) /* Idletime Meas Time Lo */ -#define B43_LPPHY_IDLETIME_MEAS_TIME_HI B43_PHY_OFDM(0x5D) /* Idletime Meas Time Hi */ -#define B43_LPPHY_RESET_LEN_OFDM_TX_ADDR B43_PHY_OFDM(0x5E) /* Reset len Ofdm TX Address */ -#define B43_LPPHY_RESET_LEN_OFDM_RX_ADDR B43_PHY_OFDM(0x5F) /* Reset len Ofdm RX Address */ -#define B43_LPPHY_REG_CRS_ENABLE B43_PHY_OFDM(0x60) /* reg crs enable */ -#define B43_LPPHY_PLCP_TMT_STR0_CTR_MIN B43_PHY_OFDM(0x61) /* PLCP Tmt Str0 Ctr Min */ -#define B43_LPPHY_PKT_FSM_RESET_LEN_VAL B43_PHY_OFDM(0x62) /* Pkt fsm Reset Len Value */ -#define B43_LPPHY_READSYM2RESET_CTL B43_PHY_OFDM(0x63) /* readsym2reset Control */ -#define B43_LPPHY_DC_FILTER_DELAY1 B43_PHY_OFDM(0x64) /* Dc filter delay1 */ -#define B43_LPPHY_PACKET_RX_ACTIVE_TO B43_PHY_OFDM(0x65) /* packet rx Active timeout */ -#define B43_LPPHY_ED_TOVAL B43_PHY_OFDM(0x66) /* ed timeoutValue */ -#define B43_LPPHY_HOLD_CRS_ON_VAL B43_PHY_OFDM(0x67) /* hold CRS On Value */ -#define B43_LPPHY_OFDM_TX_PHY_CRS_DELAY_VAL B43_PHY_OFDM(0x69) /* ofdm tx phy CRS Delay Value */ -#define B43_LPPHY_CCK_TX_PHY_CRS_DELAY_VAL B43_PHY_OFDM(0x6A) /* cck tx phy CRS Delay Value */ -#define B43_LPPHY_ED_ON_CONFIRM_TIMER_VAL B43_PHY_OFDM(0x6B) /* Ed on confirm Timer Value */ -#define B43_LPPHY_ED_OFFSET_CONFIRM_TIMER_VAL B43_PHY_OFDM(0x6C) /* Ed offset confirm Timer Value */ -#define B43_LPPHY_PHY_CRS_OFFSET_TIMER_VAL B43_PHY_OFDM(0x6D) /* phy CRS offset Timer Value */ -#define B43_LPPHY_ADC_COMPENSATION_CTL B43_PHY_OFDM(0x70) /* ADC Compensation Control */ -#define B43_LPPHY_LOG2_RBPSK_ADDR B43_PHY_OFDM(0x71) /* log2 RBPSK Address */ -#define B43_LPPHY_LOG2_RQPSK_ADDR B43_PHY_OFDM(0x72) /* log2 RQPSK Address */ -#define B43_LPPHY_LOG2_R16QAM_ADDR B43_PHY_OFDM(0x73) /* log2 R16QAM Address */ -#define B43_LPPHY_LOG2_R64QAM_ADDR B43_PHY_OFDM(0x74) /* log2 R64QAM Address */ -#define B43_LPPHY_OFFSET_BPSK_ADDR B43_PHY_OFDM(0x75) /* offset BPSK Address */ -#define B43_LPPHY_OFFSET_QPSK_ADDR B43_PHY_OFDM(0x76) /* offset QPSK Address */ -#define B43_LPPHY_OFFSET_16QAM_ADDR B43_PHY_OFDM(0x77) /* offset 16QAM Address */ -#define B43_LPPHY_OFFSET_64QAM_ADDR B43_PHY_OFDM(0x78) /* offset 64QAM Address */ -#define B43_LPPHY_ALPHA1 B43_PHY_OFDM(0x79) /* Alpha1 */ -#define B43_LPPHY_ALPHA2 B43_PHY_OFDM(0x7A) /* Alpha2 */ -#define B43_LPPHY_BETA1 B43_PHY_OFDM(0x7B) /* Beta1 */ -#define B43_LPPHY_BETA2 B43_PHY_OFDM(0x7C) /* Beta2 */ -#define B43_LPPHY_LOOP_NUM_ADDR B43_PHY_OFDM(0x7D) /* Loop Num Address */ -#define B43_LPPHY_STR_COLLMAX_SMPL_ADDR B43_PHY_OFDM(0x7E) /* Str Collmax Sample Address */ -#define B43_LPPHY_MAX_SMPL_COARSE_FINE_ADDR B43_PHY_OFDM(0x7F) /* Max Sample Coarse/Fine Address */ -#define B43_LPPHY_MAX_SMPL_COARSE_STR0CTR_ADDR B43_PHY_OFDM(0x80) /* Max Sample Coarse/Str0Ctr Address */ -#define B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR B43_PHY_OFDM(0x81) /* IQ Enable Wait Time Address */ -#define B43_LPPHY_IQ_NUM_SMPLS_ADDR B43_PHY_OFDM(0x82) /* IQ Num Samples Address */ -#define B43_LPPHY_IQ_ACC_HI_ADDR B43_PHY_OFDM(0x83) /* IQ Acc Hi Address */ -#define B43_LPPHY_IQ_ACC_LO_ADDR B43_PHY_OFDM(0x84) /* IQ Acc Lo Address */ -#define B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR B43_PHY_OFDM(0x85) /* IQ I PWR Acc Hi Address */ -#define B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR B43_PHY_OFDM(0x86) /* IQ I PWR Acc Lo Address */ -#define B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR B43_PHY_OFDM(0x87) /* IQ Q PWR Acc Hi Address */ -#define B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR B43_PHY_OFDM(0x88) /* IQ Q PWR Acc Lo Address */ -#define B43_LPPHY_MAXNUMSTEPS B43_PHY_OFDM(0x89) /* MaxNumsteps */ -#define B43_LPPHY_ROTORPHASE_ADDR B43_PHY_OFDM(0x8A) /* RotorPhase Address */ -#define B43_LPPHY_ADVANCEDRETARDROTOR_ADDR B43_PHY_OFDM(0x8B) /* AdvancedRetardRotor Address */ -#define B43_LPPHY_RSSIADCDELAY_CTL_ADDR B43_PHY_OFDM(0x8D) /* rssiAdcdelay Control Address */ -#define B43_LPPHY_TSSISTAT_ADDR B43_PHY_OFDM(0x8E) /* tssiStatus Address */ -#define B43_LPPHY_TEMPSENSESTAT_ADDR B43_PHY_OFDM(0x8F) /* tempsenseStatus Address */ -#define B43_LPPHY_TEMPSENSE_CTL_ADDR B43_PHY_OFDM(0x90) /* tempsense Control Address */ -#define B43_LPPHY_WRSSISTAT_ADDR B43_PHY_OFDM(0x91) /* wrssistatus Address */ -#define B43_LPPHY_MUFACTORADDR B43_PHY_OFDM(0x92) /* mufactoraddr */ -#define B43_LPPHY_SCRAMSTATE_ADDR B43_PHY_OFDM(0x93) /* scramstate Address */ -#define B43_LPPHY_TXHOLDOFFADDR B43_PHY_OFDM(0x94) /* txholdoffaddr */ -#define B43_LPPHY_PKTGAINVAL_ADDR B43_PHY_OFDM(0x95) /* pktgainval Address */ -#define B43_LPPHY_COARSEESTIM_ADDR B43_PHY_OFDM(0x96) /* Coarseestim Address */ -#define B43_LPPHY_STATE_TRANSITION_ADDR B43_PHY_OFDM(0x97) /* state Transition Address */ -#define B43_LPPHY_TRN_OFFSET_ADDR B43_PHY_OFDM(0x98) /* TRN offset Address */ -#define B43_LPPHY_NUM_ROTOR_ADDR B43_PHY_OFDM(0x99) /* Num Rotor Address */ -#define B43_LPPHY_VITERBI_OFFSET_ADDR B43_PHY_OFDM(0x9A) /* Viterbi Offset Address */ -#define B43_LPPHY_SMPL_COLLECT_WAIT_ADDR B43_PHY_OFDM(0x9B) /* Sample collect wait Address */ -#define B43_LPPHY_A_PHY_CTL_ADDR B43_PHY_OFDM(0x9C) /* A PHY Control Address */ -#define B43_LPPHY_NUM_PASS_THROUGH_ADDR B43_PHY_OFDM(0x9D) /* Num Pass Through Address */ -#define B43_LPPHY_RX_COMP_COEFF_S B43_PHY_OFDM(0x9E) /* RX Comp coefficient(s) */ -#define B43_LPPHY_CPAROTATEVAL B43_PHY_OFDM(0x9F) /* cpaRotateValue */ -#define B43_LPPHY_SMPL_PLAY_COUNT B43_PHY_OFDM(0xA0) /* Sample play count */ -#define B43_LPPHY_SMPL_PLAY_BUFFER_CTL B43_PHY_OFDM(0xA1) /* Sample play Buffer Control */ -#define B43_LPPHY_FOURWIRE_CTL B43_PHY_OFDM(0xA2) /* fourwire Control */ -#define B43_LPPHY_CPA_TAILCOUNT_VAL B43_PHY_OFDM(0xA3) /* CPA TailCount Value */ -#define B43_LPPHY_TX_PWR_CTL_CMD B43_PHY_OFDM(0xA4) /* TX Power Control Cmd */ -#define B43_LPPHY_TX_PWR_CTL_CMD_MODE 0xE000 /* TX power control mode mask */ -#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF 0x0000 /* TX power control is OFF */ -#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW 0x8000 /* TX power control is SOFTWARE */ -#define B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW 0xE000 /* TX power control is HARDWARE */ -#define B43_LPPHY_TX_PWR_CTL_NNUM B43_PHY_OFDM(0xA5) /* TX Power Control Nnum */ -#define B43_LPPHY_TX_PWR_CTL_IDLETSSI B43_PHY_OFDM(0xA6) /* TX Power Control IdleTssi */ -#define B43_LPPHY_TX_PWR_CTL_TARGETPWR B43_PHY_OFDM(0xA7) /* TX Power Control TargetPower */ -#define B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT B43_PHY_OFDM(0xA8) /* TX Power Control DeltaPower Limit */ -#define B43_LPPHY_TX_PWR_CTL_BASEINDEX B43_PHY_OFDM(0xA9) /* TX Power Control BaseIndex */ -#define B43_LPPHY_TX_PWR_CTL_PWR_INDEX B43_PHY_OFDM(0xAA) /* TX Power Control Power Index */ -#define B43_LPPHY_TX_PWR_CTL_STAT B43_PHY_OFDM(0xAB) /* TX Power Control Status */ -#define B43_LPPHY_LP_RF_SIGNAL_LUT B43_PHY_OFDM(0xAC) /* LP RF signal LUT */ -#define B43_LPPHY_RX_RADIO_CTL_FILTER_STATE B43_PHY_OFDM(0xAD) /* RX Radio Control Filter State */ -#define B43_LPPHY_RX_RADIO_CTL B43_PHY_OFDM(0xAE) /* RX Radio Control */ -#define B43_LPPHY_NRSSI_STAT_ADDR B43_PHY_OFDM(0xAF) /* NRSSI status Address */ -#define B43_LPPHY_RF_OVERRIDE_2 B43_PHY_OFDM(0xB0) /* RF override 2 */ -#define B43_LPPHY_RF_OVERRIDE_2_VAL B43_PHY_OFDM(0xB1) /* RF override 2 val */ -#define B43_LPPHY_PS_CTL_OVERRIDE_VAL0 B43_PHY_OFDM(0xB2) /* PS Control override val0 */ -#define B43_LPPHY_PS_CTL_OVERRIDE_VAL1 B43_PHY_OFDM(0xB3) /* PS Control override val1 */ -#define B43_LPPHY_PS_CTL_OVERRIDE_VAL2 B43_PHY_OFDM(0xB4) /* PS Control override val2 */ -#define B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL B43_PHY_OFDM(0xB5) /* TX gain Control override val */ -#define B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL B43_PHY_OFDM(0xB6) /* RX gain Control override val */ -#define B43_LPPHY_AFE_DDFS B43_PHY_OFDM(0xB7) /* AFE DDFS */ -#define B43_LPPHY_AFE_DDFS_POINTER_INIT B43_PHY_OFDM(0xB8) /* AFE DDFS pointer init */ -#define B43_LPPHY_AFE_DDFS_INCR_INIT B43_PHY_OFDM(0xB9) /* AFE DDFS incr init */ -#define B43_LPPHY_MRCNOISEREDUCTION B43_PHY_OFDM(0xBA) /* mrcNoiseReduction */ -#define B43_LPPHY_TR_LOOKUP_3 B43_PHY_OFDM(0xBB) /* TR Lookup 3 */ -#define B43_LPPHY_TR_LOOKUP_4 B43_PHY_OFDM(0xBC) /* TR Lookup 4 */ -#define B43_LPPHY_RADAR_FIFO_STAT B43_PHY_OFDM(0xBD) /* Radar FIFO Status */ -#define B43_LPPHY_GPIO_OUTEN B43_PHY_OFDM(0xBE) /* GPIO Out enable */ -#define B43_LPPHY_GPIO_SELECT B43_PHY_OFDM(0xBF) /* GPIO Select */ -#define B43_LPPHY_GPIO_OUT B43_PHY_OFDM(0xC0) /* GPIO Out */ -#define B43_LPPHY_4C3 B43_PHY_OFDM(0xC3) /* unknown, used during BB init */ -#define B43_LPPHY_4C4 B43_PHY_OFDM(0xC4) /* unknown, used during BB init */ -#define B43_LPPHY_4C5 B43_PHY_OFDM(0xC5) /* unknown, used during BB init */ -#define B43_LPPHY_TR_LOOKUP_5 B43_PHY_OFDM(0xC7) /* TR Lookup 5 */ -#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */ -#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */ -#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */ -#define B43_LPPHY_RF_PWR_OVERRIDE B43_PHY_OFDM(0xD3) /* RF power override */ - - - -/* Radio register access decorators. */ -#define B43_LP_RADIO(radio_reg) (radio_reg) -#define B43_LP_NORTH(radio_reg) B43_LP_RADIO(radio_reg) -#define B43_LP_SOUTH(radio_reg) B43_LP_RADIO((radio_reg) | 0x4000) - - -/*** Broadcom 2062 NORTH radio registers ***/ -#define B2062_N_COMM1 B43_LP_NORTH(0x000) /* Common 01 (north) */ -#define B2062_N_COMM2 B43_LP_NORTH(0x002) /* Common 02 (north) */ -#define B2062_N_COMM3 B43_LP_NORTH(0x003) /* Common 03 (north) */ -#define B2062_N_COMM4 B43_LP_NORTH(0x004) /* Common 04 (north) */ -#define B2062_N_COMM5 B43_LP_NORTH(0x005) /* Common 05 (north) */ -#define B2062_N_COMM6 B43_LP_NORTH(0x006) /* Common 06 (north) */ -#define B2062_N_COMM7 B43_LP_NORTH(0x007) /* Common 07 (north) */ -#define B2062_N_COMM8 B43_LP_NORTH(0x008) /* Common 08 (north) */ -#define B2062_N_COMM9 B43_LP_NORTH(0x009) /* Common 09 (north) */ -#define B2062_N_COMM10 B43_LP_NORTH(0x00A) /* Common 10 (north) */ -#define B2062_N_COMM11 B43_LP_NORTH(0x00B) /* Common 11 (north) */ -#define B2062_N_COMM12 B43_LP_NORTH(0x00C) /* Common 12 (north) */ -#define B2062_N_COMM13 B43_LP_NORTH(0x00D) /* Common 13 (north) */ -#define B2062_N_COMM14 B43_LP_NORTH(0x00E) /* Common 14 (north) */ -#define B2062_N_COMM15 B43_LP_NORTH(0x00F) /* Common 15 (north) */ -#define B2062_N_PDN_CTL0 B43_LP_NORTH(0x010) /* PDN Control 0 (north) */ -#define B2062_N_PDN_CTL1 B43_LP_NORTH(0x011) /* PDN Control 1 (north) */ -#define B2062_N_PDN_CTL2 B43_LP_NORTH(0x012) /* PDN Control 2 (north) */ -#define B2062_N_PDN_CTL3 B43_LP_NORTH(0x013) /* PDN Control 3 (north) */ -#define B2062_N_PDN_CTL4 B43_LP_NORTH(0x014) /* PDN Control 4 (north) */ -#define B2062_N_GEN_CTL0 B43_LP_NORTH(0x015) /* GEN Control 0 (north) */ -#define B2062_N_IQ_CALIB B43_LP_NORTH(0x016) /* IQ Calibration (north) */ -#define B2062_N_LGENC B43_LP_NORTH(0x017) /* LGENC (north) */ -#define B2062_N_LGENA_LPF B43_LP_NORTH(0x018) /* LGENA LPF (north) */ -#define B2062_N_LGENA_BIAS0 B43_LP_NORTH(0x019) /* LGENA Bias 0 (north) */ -#define B2062_N_LGNEA_BIAS1 B43_LP_NORTH(0x01A) /* LGNEA Bias 1 (north) */ -#define B2062_N_LGENA_CTL0 B43_LP_NORTH(0x01B) /* LGENA Control 0 (north) */ -#define B2062_N_LGENA_CTL1 B43_LP_NORTH(0x01C) /* LGENA Control 1 (north) */ -#define B2062_N_LGENA_CTL2 B43_LP_NORTH(0x01D) /* LGENA Control 2 (north) */ -#define B2062_N_LGENA_TUNE0 B43_LP_NORTH(0x01E) /* LGENA Tune 0 (north) */ -#define B2062_N_LGENA_TUNE1 B43_LP_NORTH(0x01F) /* LGENA Tune 1 (north) */ -#define B2062_N_LGENA_TUNE2 B43_LP_NORTH(0x020) /* LGENA Tune 2 (north) */ -#define B2062_N_LGENA_TUNE3 B43_LP_NORTH(0x021) /* LGENA Tune 3 (north) */ -#define B2062_N_LGENA_CTL3 B43_LP_NORTH(0x022) /* LGENA Control 3 (north) */ -#define B2062_N_LGENA_CTL4 B43_LP_NORTH(0x023) /* LGENA Control 4 (north) */ -#define B2062_N_LGENA_CTL5 B43_LP_NORTH(0x024) /* LGENA Control 5 (north) */ -#define B2062_N_LGENA_CTL6 B43_LP_NORTH(0x025) /* LGENA Control 6 (north) */ -#define B2062_N_LGENA_CTL7 B43_LP_NORTH(0x026) /* LGENA Control 7 (north) */ -#define B2062_N_RXA_CTL0 B43_LP_NORTH(0x027) /* RXA Control 0 (north) */ -#define B2062_N_RXA_CTL1 B43_LP_NORTH(0x028) /* RXA Control 1 (north) */ -#define B2062_N_RXA_CTL2 B43_LP_NORTH(0x029) /* RXA Control 2 (north) */ -#define B2062_N_RXA_CTL3 B43_LP_NORTH(0x02A) /* RXA Control 3 (north) */ -#define B2062_N_RXA_CTL4 B43_LP_NORTH(0x02B) /* RXA Control 4 (north) */ -#define B2062_N_RXA_CTL5 B43_LP_NORTH(0x02C) /* RXA Control 5 (north) */ -#define B2062_N_RXA_CTL6 B43_LP_NORTH(0x02D) /* RXA Control 6 (north) */ -#define B2062_N_RXA_CTL7 B43_LP_NORTH(0x02E) /* RXA Control 7 (north) */ -#define B2062_N_RXBB_CTL0 B43_LP_NORTH(0x02F) /* RXBB Control 0 (north) */ -#define B2062_N_RXBB_CTL1 B43_LP_NORTH(0x030) /* RXBB Control 1 (north) */ -#define B2062_N_RXBB_CTL2 B43_LP_NORTH(0x031) /* RXBB Control 2 (north) */ -#define B2062_N_RXBB_GAIN0 B43_LP_NORTH(0x032) /* RXBB Gain 0 (north) */ -#define B2062_N_RXBB_GAIN1 B43_LP_NORTH(0x033) /* RXBB Gain 1 (north) */ -#define B2062_N_RXBB_GAIN2 B43_LP_NORTH(0x034) /* RXBB Gain 2 (north) */ -#define B2062_N_RXBB_GAIN3 B43_LP_NORTH(0x035) /* RXBB Gain 3 (north) */ -#define B2062_N_RXBB_RSSI0 B43_LP_NORTH(0x036) /* RXBB RSSI 0 (north) */ -#define B2062_N_RXBB_RSSI1 B43_LP_NORTH(0x037) /* RXBB RSSI 1 (north) */ -#define B2062_N_RXBB_CALIB0 B43_LP_NORTH(0x038) /* RXBB Calibration0 (north) */ -#define B2062_N_RXBB_CALIB1 B43_LP_NORTH(0x039) /* RXBB Calibration1 (north) */ -#define B2062_N_RXBB_CALIB2 B43_LP_NORTH(0x03A) /* RXBB Calibration2 (north) */ -#define B2062_N_RXBB_BIAS0 B43_LP_NORTH(0x03B) /* RXBB Bias 0 (north) */ -#define B2062_N_RXBB_BIAS1 B43_LP_NORTH(0x03C) /* RXBB Bias 1 (north) */ -#define B2062_N_RXBB_BIAS2 B43_LP_NORTH(0x03D) /* RXBB Bias 2 (north) */ -#define B2062_N_RXBB_BIAS3 B43_LP_NORTH(0x03E) /* RXBB Bias 3 (north) */ -#define B2062_N_RXBB_BIAS4 B43_LP_NORTH(0x03F) /* RXBB Bias 4 (north) */ -#define B2062_N_RXBB_BIAS5 B43_LP_NORTH(0x040) /* RXBB Bias 5 (north) */ -#define B2062_N_RXBB_RSSI2 B43_LP_NORTH(0x041) /* RXBB RSSI 2 (north) */ -#define B2062_N_RXBB_RSSI3 B43_LP_NORTH(0x042) /* RXBB RSSI 3 (north) */ -#define B2062_N_RXBB_RSSI4 B43_LP_NORTH(0x043) /* RXBB RSSI 4 (north) */ -#define B2062_N_RXBB_RSSI5 B43_LP_NORTH(0x044) /* RXBB RSSI 5 (north) */ -#define B2062_N_TX_CTL0 B43_LP_NORTH(0x045) /* TX Control 0 (north) */ -#define B2062_N_TX_CTL1 B43_LP_NORTH(0x046) /* TX Control 1 (north) */ -#define B2062_N_TX_CTL2 B43_LP_NORTH(0x047) /* TX Control 2 (north) */ -#define B2062_N_TX_CTL3 B43_LP_NORTH(0x048) /* TX Control 3 (north) */ -#define B2062_N_TX_CTL4 B43_LP_NORTH(0x049) /* TX Control 4 (north) */ -#define B2062_N_TX_CTL5 B43_LP_NORTH(0x04A) /* TX Control 5 (north) */ -#define B2062_N_TX_CTL6 B43_LP_NORTH(0x04B) /* TX Control 6 (north) */ -#define B2062_N_TX_CTL7 B43_LP_NORTH(0x04C) /* TX Control 7 (north) */ -#define B2062_N_TX_CTL8 B43_LP_NORTH(0x04D) /* TX Control 8 (north) */ -#define B2062_N_TX_CTL9 B43_LP_NORTH(0x04E) /* TX Control 9 (north) */ -#define B2062_N_TX_CTL_A B43_LP_NORTH(0x04F) /* TX Control A (north) */ -#define B2062_N_TX_GC2G B43_LP_NORTH(0x050) /* TX GC2G (north) */ -#define B2062_N_TX_GC5G B43_LP_NORTH(0x051) /* TX GC5G (north) */ -#define B2062_N_TX_TUNE B43_LP_NORTH(0x052) /* TX Tune (north) */ -#define B2062_N_TX_PAD B43_LP_NORTH(0x053) /* TX PAD (north) */ -#define B2062_N_TX_PGA B43_LP_NORTH(0x054) /* TX PGA (north) */ -#define B2062_N_TX_PADAUX B43_LP_NORTH(0x055) /* TX PADAUX (north) */ -#define B2062_N_TX_PGAAUX B43_LP_NORTH(0x056) /* TX PGAAUX (north) */ -#define B2062_N_TSSI_CTL0 B43_LP_NORTH(0x057) /* TSSI Control 0 (north) */ -#define B2062_N_TSSI_CTL1 B43_LP_NORTH(0x058) /* TSSI Control 1 (north) */ -#define B2062_N_TSSI_CTL2 B43_LP_NORTH(0x059) /* TSSI Control 2 (north) */ -#define B2062_N_IQ_CALIB_CTL0 B43_LP_NORTH(0x05A) /* IQ Calibration Control 0 (north) */ -#define B2062_N_IQ_CALIB_CTL1 B43_LP_NORTH(0x05B) /* IQ Calibration Control 1 (north) */ -#define B2062_N_IQ_CALIB_CTL2 B43_LP_NORTH(0x05C) /* IQ Calibration Control 2 (north) */ -#define B2062_N_CALIB_TS B43_LP_NORTH(0x05D) /* Calibration TS (north) */ -#define B2062_N_CALIB_CTL0 B43_LP_NORTH(0x05E) /* Calibration Control 0 (north) */ -#define B2062_N_CALIB_CTL1 B43_LP_NORTH(0x05F) /* Calibration Control 1 (north) */ -#define B2062_N_CALIB_CTL2 B43_LP_NORTH(0x060) /* Calibration Control 2 (north) */ -#define B2062_N_CALIB_CTL3 B43_LP_NORTH(0x061) /* Calibration Control 3 (north) */ -#define B2062_N_CALIB_CTL4 B43_LP_NORTH(0x062) /* Calibration Control 4 (north) */ -#define B2062_N_CALIB_DBG0 B43_LP_NORTH(0x063) /* Calibration Debug 0 (north) */ -#define B2062_N_CALIB_DBG1 B43_LP_NORTH(0x064) /* Calibration Debug 1 (north) */ -#define B2062_N_CALIB_DBG2 B43_LP_NORTH(0x065) /* Calibration Debug 2 (north) */ -#define B2062_N_CALIB_DBG3 B43_LP_NORTH(0x066) /* Calibration Debug 3 (north) */ -#define B2062_N_PSENSE_CTL0 B43_LP_NORTH(0x069) /* PSENSE Control 0 (north) */ -#define B2062_N_PSENSE_CTL1 B43_LP_NORTH(0x06A) /* PSENSE Control 1 (north) */ -#define B2062_N_PSENSE_CTL2 B43_LP_NORTH(0x06B) /* PSENSE Control 2 (north) */ -#define B2062_N_TEST_BUF0 B43_LP_NORTH(0x06C) /* TEST BUF0 (north) */ - -/*** Broadcom 2062 SOUTH radio registers ***/ -#define B2062_S_COMM1 B43_LP_SOUTH(0x000) /* Common 01 (south) */ -#define B2062_S_RADIO_ID_CODE B43_LP_SOUTH(0x001) /* Radio ID code (south) */ -#define B2062_S_COMM2 B43_LP_SOUTH(0x002) /* Common 02 (south) */ -#define B2062_S_COMM3 B43_LP_SOUTH(0x003) /* Common 03 (south) */ -#define B2062_S_COMM4 B43_LP_SOUTH(0x004) /* Common 04 (south) */ -#define B2062_S_COMM5 B43_LP_SOUTH(0x005) /* Common 05 (south) */ -#define B2062_S_COMM6 B43_LP_SOUTH(0x006) /* Common 06 (south) */ -#define B2062_S_COMM7 B43_LP_SOUTH(0x007) /* Common 07 (south) */ -#define B2062_S_COMM8 B43_LP_SOUTH(0x008) /* Common 08 (south) */ -#define B2062_S_COMM9 B43_LP_SOUTH(0x009) /* Common 09 (south) */ -#define B2062_S_COMM10 B43_LP_SOUTH(0x00A) /* Common 10 (south) */ -#define B2062_S_COMM11 B43_LP_SOUTH(0x00B) /* Common 11 (south) */ -#define B2062_S_COMM12 B43_LP_SOUTH(0x00C) /* Common 12 (south) */ -#define B2062_S_COMM13 B43_LP_SOUTH(0x00D) /* Common 13 (south) */ -#define B2062_S_COMM14 B43_LP_SOUTH(0x00E) /* Common 14 (south) */ -#define B2062_S_COMM15 B43_LP_SOUTH(0x00F) /* Common 15 (south) */ -#define B2062_S_PDS_CTL0 B43_LP_SOUTH(0x010) /* PDS Control 0 (south) */ -#define B2062_S_PDS_CTL1 B43_LP_SOUTH(0x011) /* PDS Control 1 (south) */ -#define B2062_S_PDS_CTL2 B43_LP_SOUTH(0x012) /* PDS Control 2 (south) */ -#define B2062_S_PDS_CTL3 B43_LP_SOUTH(0x013) /* PDS Control 3 (south) */ -#define B2062_S_BG_CTL0 B43_LP_SOUTH(0x014) /* BG Control 0 (south) */ -#define B2062_S_BG_CTL1 B43_LP_SOUTH(0x015) /* BG Control 1 (south) */ -#define B2062_S_BG_CTL2 B43_LP_SOUTH(0x016) /* BG Control 2 (south) */ -#define B2062_S_LGENG_CTL0 B43_LP_SOUTH(0x017) /* LGENG Control 00 (south) */ -#define B2062_S_LGENG_CTL1 B43_LP_SOUTH(0x018) /* LGENG Control 01 (south) */ -#define B2062_S_LGENG_CTL2 B43_LP_SOUTH(0x019) /* LGENG Control 02 (south) */ -#define B2062_S_LGENG_CTL3 B43_LP_SOUTH(0x01A) /* LGENG Control 03 (south) */ -#define B2062_S_LGENG_CTL4 B43_LP_SOUTH(0x01B) /* LGENG Control 04 (south) */ -#define B2062_S_LGENG_CTL5 B43_LP_SOUTH(0x01C) /* LGENG Control 05 (south) */ -#define B2062_S_LGENG_CTL6 B43_LP_SOUTH(0x01D) /* LGENG Control 06 (south) */ -#define B2062_S_LGENG_CTL7 B43_LP_SOUTH(0x01E) /* LGENG Control 07 (south) */ -#define B2062_S_LGENG_CTL8 B43_LP_SOUTH(0x01F) /* LGENG Control 08 (south) */ -#define B2062_S_LGENG_CTL9 B43_LP_SOUTH(0x020) /* LGENG Control 09 (south) */ -#define B2062_S_LGENG_CTL10 B43_LP_SOUTH(0x021) /* LGENG Control 10 (south) */ -#define B2062_S_LGENG_CTL11 B43_LP_SOUTH(0x022) /* LGENG Control 11 (south) */ -#define B2062_S_REFPLL_CTL0 B43_LP_SOUTH(0x023) /* REFPLL Control 00 (south) */ -#define B2062_S_REFPLL_CTL1 B43_LP_SOUTH(0x024) /* REFPLL Control 01 (south) */ -#define B2062_S_REFPLL_CTL2 B43_LP_SOUTH(0x025) /* REFPLL Control 02 (south) */ -#define B2062_S_REFPLL_CTL3 B43_LP_SOUTH(0x026) /* REFPLL Control 03 (south) */ -#define B2062_S_REFPLL_CTL4 B43_LP_SOUTH(0x027) /* REFPLL Control 04 (south) */ -#define B2062_S_REFPLL_CTL5 B43_LP_SOUTH(0x028) /* REFPLL Control 05 (south) */ -#define B2062_S_REFPLL_CTL6 B43_LP_SOUTH(0x029) /* REFPLL Control 06 (south) */ -#define B2062_S_REFPLL_CTL7 B43_LP_SOUTH(0x02A) /* REFPLL Control 07 (south) */ -#define B2062_S_REFPLL_CTL8 B43_LP_SOUTH(0x02B) /* REFPLL Control 08 (south) */ -#define B2062_S_REFPLL_CTL9 B43_LP_SOUTH(0x02C) /* REFPLL Control 09 (south) */ -#define B2062_S_REFPLL_CTL10 B43_LP_SOUTH(0x02D) /* REFPLL Control 10 (south) */ -#define B2062_S_REFPLL_CTL11 B43_LP_SOUTH(0x02E) /* REFPLL Control 11 (south) */ -#define B2062_S_REFPLL_CTL12 B43_LP_SOUTH(0x02F) /* REFPLL Control 12 (south) */ -#define B2062_S_REFPLL_CTL13 B43_LP_SOUTH(0x030) /* REFPLL Control 13 (south) */ -#define B2062_S_REFPLL_CTL14 B43_LP_SOUTH(0x031) /* REFPLL Control 14 (south) */ -#define B2062_S_REFPLL_CTL15 B43_LP_SOUTH(0x032) /* REFPLL Control 15 (south) */ -#define B2062_S_REFPLL_CTL16 B43_LP_SOUTH(0x033) /* REFPLL Control 16 (south) */ -#define B2062_S_RFPLL_CTL0 B43_LP_SOUTH(0x034) /* RFPLL Control 00 (south) */ -#define B2062_S_RFPLL_CTL1 B43_LP_SOUTH(0x035) /* RFPLL Control 01 (south) */ -#define B2062_S_RFPLL_CTL2 B43_LP_SOUTH(0x036) /* RFPLL Control 02 (south) */ -#define B2062_S_RFPLL_CTL3 B43_LP_SOUTH(0x037) /* RFPLL Control 03 (south) */ -#define B2062_S_RFPLL_CTL4 B43_LP_SOUTH(0x038) /* RFPLL Control 04 (south) */ -#define B2062_S_RFPLL_CTL5 B43_LP_SOUTH(0x039) /* RFPLL Control 05 (south) */ -#define B2062_S_RFPLL_CTL6 B43_LP_SOUTH(0x03A) /* RFPLL Control 06 (south) */ -#define B2062_S_RFPLL_CTL7 B43_LP_SOUTH(0x03B) /* RFPLL Control 07 (south) */ -#define B2062_S_RFPLL_CTL8 B43_LP_SOUTH(0x03C) /* RFPLL Control 08 (south) */ -#define B2062_S_RFPLL_CTL9 B43_LP_SOUTH(0x03D) /* RFPLL Control 09 (south) */ -#define B2062_S_RFPLL_CTL10 B43_LP_SOUTH(0x03E) /* RFPLL Control 10 (south) */ -#define B2062_S_RFPLL_CTL11 B43_LP_SOUTH(0x03F) /* RFPLL Control 11 (south) */ -#define B2062_S_RFPLL_CTL12 B43_LP_SOUTH(0x040) /* RFPLL Control 12 (south) */ -#define B2062_S_RFPLL_CTL13 B43_LP_SOUTH(0x041) /* RFPLL Control 13 (south) */ -#define B2062_S_RFPLL_CTL14 B43_LP_SOUTH(0x042) /* RFPLL Control 14 (south) */ -#define B2062_S_RFPLL_CTL15 B43_LP_SOUTH(0x043) /* RFPLL Control 15 (south) */ -#define B2062_S_RFPLL_CTL16 B43_LP_SOUTH(0x044) /* RFPLL Control 16 (south) */ -#define B2062_S_RFPLL_CTL17 B43_LP_SOUTH(0x045) /* RFPLL Control 17 (south) */ -#define B2062_S_RFPLL_CTL18 B43_LP_SOUTH(0x046) /* RFPLL Control 18 (south) */ -#define B2062_S_RFPLL_CTL19 B43_LP_SOUTH(0x047) /* RFPLL Control 19 (south) */ -#define B2062_S_RFPLL_CTL20 B43_LP_SOUTH(0x048) /* RFPLL Control 20 (south) */ -#define B2062_S_RFPLL_CTL21 B43_LP_SOUTH(0x049) /* RFPLL Control 21 (south) */ -#define B2062_S_RFPLL_CTL22 B43_LP_SOUTH(0x04A) /* RFPLL Control 22 (south) */ -#define B2062_S_RFPLL_CTL23 B43_LP_SOUTH(0x04B) /* RFPLL Control 23 (south) */ -#define B2062_S_RFPLL_CTL24 B43_LP_SOUTH(0x04C) /* RFPLL Control 24 (south) */ -#define B2062_S_RFPLL_CTL25 B43_LP_SOUTH(0x04D) /* RFPLL Control 25 (south) */ -#define B2062_S_RFPLL_CTL26 B43_LP_SOUTH(0x04E) /* RFPLL Control 26 (south) */ -#define B2062_S_RFPLL_CTL27 B43_LP_SOUTH(0x04F) /* RFPLL Control 27 (south) */ -#define B2062_S_RFPLL_CTL28 B43_LP_SOUTH(0x050) /* RFPLL Control 28 (south) */ -#define B2062_S_RFPLL_CTL29 B43_LP_SOUTH(0x051) /* RFPLL Control 29 (south) */ -#define B2062_S_RFPLL_CTL30 B43_LP_SOUTH(0x052) /* RFPLL Control 30 (south) */ -#define B2062_S_RFPLL_CTL31 B43_LP_SOUTH(0x053) /* RFPLL Control 31 (south) */ -#define B2062_S_RFPLL_CTL32 B43_LP_SOUTH(0x054) /* RFPLL Control 32 (south) */ -#define B2062_S_RFPLL_CTL33 B43_LP_SOUTH(0x055) /* RFPLL Control 33 (south) */ -#define B2062_S_RFPLL_CTL34 B43_LP_SOUTH(0x056) /* RFPLL Control 34 (south) */ -#define B2062_S_RXG_CNT0 B43_LP_SOUTH(0x057) /* RXG Counter 00 (south) */ -#define B2062_S_RXG_CNT1 B43_LP_SOUTH(0x058) /* RXG Counter 01 (south) */ -#define B2062_S_RXG_CNT2 B43_LP_SOUTH(0x059) /* RXG Counter 02 (south) */ -#define B2062_S_RXG_CNT3 B43_LP_SOUTH(0x05A) /* RXG Counter 03 (south) */ -#define B2062_S_RXG_CNT4 B43_LP_SOUTH(0x05B) /* RXG Counter 04 (south) */ -#define B2062_S_RXG_CNT5 B43_LP_SOUTH(0x05C) /* RXG Counter 05 (south) */ -#define B2062_S_RXG_CNT6 B43_LP_SOUTH(0x05D) /* RXG Counter 06 (south) */ -#define B2062_S_RXG_CNT7 B43_LP_SOUTH(0x05E) /* RXG Counter 07 (south) */ -#define B2062_S_RXG_CNT8 B43_LP_SOUTH(0x05F) /* RXG Counter 08 (south) */ -#define B2062_S_RXG_CNT9 B43_LP_SOUTH(0x060) /* RXG Counter 09 (south) */ -#define B2062_S_RXG_CNT10 B43_LP_SOUTH(0x061) /* RXG Counter 10 (south) */ -#define B2062_S_RXG_CNT11 B43_LP_SOUTH(0x062) /* RXG Counter 11 (south) */ -#define B2062_S_RXG_CNT12 B43_LP_SOUTH(0x063) /* RXG Counter 12 (south) */ -#define B2062_S_RXG_CNT13 B43_LP_SOUTH(0x064) /* RXG Counter 13 (south) */ -#define B2062_S_RXG_CNT14 B43_LP_SOUTH(0x065) /* RXG Counter 14 (south) */ -#define B2062_S_RXG_CNT15 B43_LP_SOUTH(0x066) /* RXG Counter 15 (south) */ -#define B2062_S_RXG_CNT16 B43_LP_SOUTH(0x067) /* RXG Counter 16 (south) */ -#define B2062_S_RXG_CNT17 B43_LP_SOUTH(0x068) /* RXG Counter 17 (south) */ - - - -/*** Broadcom 2063 radio registers ***/ -#define B2063_RADIO_ID_CODE B43_LP_RADIO(0x001) /* Radio ID code */ -#define B2063_COMM1 B43_LP_RADIO(0x000) /* Common 01 */ -#define B2063_COMM2 B43_LP_RADIO(0x002) /* Common 02 */ -#define B2063_COMM3 B43_LP_RADIO(0x003) /* Common 03 */ -#define B2063_COMM4 B43_LP_RADIO(0x004) /* Common 04 */ -#define B2063_COMM5 B43_LP_RADIO(0x005) /* Common 05 */ -#define B2063_COMM6 B43_LP_RADIO(0x006) /* Common 06 */ -#define B2063_COMM7 B43_LP_RADIO(0x007) /* Common 07 */ -#define B2063_COMM8 B43_LP_RADIO(0x008) /* Common 08 */ -#define B2063_COMM9 B43_LP_RADIO(0x009) /* Common 09 */ -#define B2063_COMM10 B43_LP_RADIO(0x00A) /* Common 10 */ -#define B2063_COMM11 B43_LP_RADIO(0x00B) /* Common 11 */ -#define B2063_COMM12 B43_LP_RADIO(0x00C) /* Common 12 */ -#define B2063_COMM13 B43_LP_RADIO(0x00D) /* Common 13 */ -#define B2063_COMM14 B43_LP_RADIO(0x00E) /* Common 14 */ -#define B2063_COMM15 B43_LP_RADIO(0x00F) /* Common 15 */ -#define B2063_COMM16 B43_LP_RADIO(0x010) /* Common 16 */ -#define B2063_COMM17 B43_LP_RADIO(0x011) /* Common 17 */ -#define B2063_COMM18 B43_LP_RADIO(0x012) /* Common 18 */ -#define B2063_COMM19 B43_LP_RADIO(0x013) /* Common 19 */ -#define B2063_COMM20 B43_LP_RADIO(0x014) /* Common 20 */ -#define B2063_COMM21 B43_LP_RADIO(0x015) /* Common 21 */ -#define B2063_COMM22 B43_LP_RADIO(0x016) /* Common 22 */ -#define B2063_COMM23 B43_LP_RADIO(0x017) /* Common 23 */ -#define B2063_COMM24 B43_LP_RADIO(0x018) /* Common 24 */ -#define B2063_PWR_SWITCH_CTL B43_LP_RADIO(0x019) /* POWER SWITCH Control */ -#define B2063_PLL_SP1 B43_LP_RADIO(0x01A) /* PLL SP 1 */ -#define B2063_PLL_SP2 B43_LP_RADIO(0x01B) /* PLL SP 2 */ -#define B2063_LOGEN_SP1 B43_LP_RADIO(0x01C) /* LOGEN SP 1 */ -#define B2063_LOGEN_SP2 B43_LP_RADIO(0x01D) /* LOGEN SP 2 */ -#define B2063_LOGEN_SP3 B43_LP_RADIO(0x01E) /* LOGEN SP 3 */ -#define B2063_LOGEN_SP4 B43_LP_RADIO(0x01F) /* LOGEN SP 4 */ -#define B2063_LOGEN_SP5 B43_LP_RADIO(0x020) /* LOGEN SP 5 */ -#define B2063_G_RX_SP1 B43_LP_RADIO(0x021) /* G RX SP 1 */ -#define B2063_G_RX_SP2 B43_LP_RADIO(0x022) /* G RX SP 2 */ -#define B2063_G_RX_SP3 B43_LP_RADIO(0x023) /* G RX SP 3 */ -#define B2063_G_RX_SP4 B43_LP_RADIO(0x024) /* G RX SP 4 */ -#define B2063_G_RX_SP5 B43_LP_RADIO(0x025) /* G RX SP 5 */ -#define B2063_G_RX_SP6 B43_LP_RADIO(0x026) /* G RX SP 6 */ -#define B2063_G_RX_SP7 B43_LP_RADIO(0x027) /* G RX SP 7 */ -#define B2063_G_RX_SP8 B43_LP_RADIO(0x028) /* G RX SP 8 */ -#define B2063_G_RX_SP9 B43_LP_RADIO(0x029) /* G RX SP 9 */ -#define B2063_G_RX_SP10 B43_LP_RADIO(0x02A) /* G RX SP 10 */ -#define B2063_G_RX_SP11 B43_LP_RADIO(0x02B) /* G RX SP 11 */ -#define B2063_A_RX_SP1 B43_LP_RADIO(0x02C) /* A RX SP 1 */ -#define B2063_A_RX_SP2 B43_LP_RADIO(0x02D) /* A RX SP 2 */ -#define B2063_A_RX_SP3 B43_LP_RADIO(0x02E) /* A RX SP 3 */ -#define B2063_A_RX_SP4 B43_LP_RADIO(0x02F) /* A RX SP 4 */ -#define B2063_A_RX_SP5 B43_LP_RADIO(0x030) /* A RX SP 5 */ -#define B2063_A_RX_SP6 B43_LP_RADIO(0x031) /* A RX SP 6 */ -#define B2063_A_RX_SP7 B43_LP_RADIO(0x032) /* A RX SP 7 */ -#define B2063_RX_BB_SP1 B43_LP_RADIO(0x033) /* RX BB SP 1 */ -#define B2063_RX_BB_SP2 B43_LP_RADIO(0x034) /* RX BB SP 2 */ -#define B2063_RX_BB_SP3 B43_LP_RADIO(0x035) /* RX BB SP 3 */ -#define B2063_RX_BB_SP4 B43_LP_RADIO(0x036) /* RX BB SP 4 */ -#define B2063_RX_BB_SP5 B43_LP_RADIO(0x037) /* RX BB SP 5 */ -#define B2063_RX_BB_SP6 B43_LP_RADIO(0x038) /* RX BB SP 6 */ -#define B2063_RX_BB_SP7 B43_LP_RADIO(0x039) /* RX BB SP 7 */ -#define B2063_RX_BB_SP8 B43_LP_RADIO(0x03A) /* RX BB SP 8 */ -#define B2063_TX_RF_SP1 B43_LP_RADIO(0x03B) /* TX RF SP 1 */ -#define B2063_TX_RF_SP2 B43_LP_RADIO(0x03C) /* TX RF SP 2 */ -#define B2063_TX_RF_SP3 B43_LP_RADIO(0x03D) /* TX RF SP 3 */ -#define B2063_TX_RF_SP4 B43_LP_RADIO(0x03E) /* TX RF SP 4 */ -#define B2063_TX_RF_SP5 B43_LP_RADIO(0x03F) /* TX RF SP 5 */ -#define B2063_TX_RF_SP6 B43_LP_RADIO(0x040) /* TX RF SP 6 */ -#define B2063_TX_RF_SP7 B43_LP_RADIO(0x041) /* TX RF SP 7 */ -#define B2063_TX_RF_SP8 B43_LP_RADIO(0x042) /* TX RF SP 8 */ -#define B2063_TX_RF_SP9 B43_LP_RADIO(0x043) /* TX RF SP 9 */ -#define B2063_TX_RF_SP10 B43_LP_RADIO(0x044) /* TX RF SP 10 */ -#define B2063_TX_RF_SP11 B43_LP_RADIO(0x045) /* TX RF SP 11 */ -#define B2063_TX_RF_SP12 B43_LP_RADIO(0x046) /* TX RF SP 12 */ -#define B2063_TX_RF_SP13 B43_LP_RADIO(0x047) /* TX RF SP 13 */ -#define B2063_TX_RF_SP14 B43_LP_RADIO(0x048) /* TX RF SP 14 */ -#define B2063_TX_RF_SP15 B43_LP_RADIO(0x049) /* TX RF SP 15 */ -#define B2063_TX_RF_SP16 B43_LP_RADIO(0x04A) /* TX RF SP 16 */ -#define B2063_TX_RF_SP17 B43_LP_RADIO(0x04B) /* TX RF SP 17 */ -#define B2063_PA_SP1 B43_LP_RADIO(0x04C) /* PA SP 1 */ -#define B2063_PA_SP2 B43_LP_RADIO(0x04D) /* PA SP 2 */ -#define B2063_PA_SP3 B43_LP_RADIO(0x04E) /* PA SP 3 */ -#define B2063_PA_SP4 B43_LP_RADIO(0x04F) /* PA SP 4 */ -#define B2063_PA_SP5 B43_LP_RADIO(0x050) /* PA SP 5 */ -#define B2063_PA_SP6 B43_LP_RADIO(0x051) /* PA SP 6 */ -#define B2063_PA_SP7 B43_LP_RADIO(0x052) /* PA SP 7 */ -#define B2063_TX_BB_SP1 B43_LP_RADIO(0x053) /* TX BB SP 1 */ -#define B2063_TX_BB_SP2 B43_LP_RADIO(0x054) /* TX BB SP 2 */ -#define B2063_TX_BB_SP3 B43_LP_RADIO(0x055) /* TX BB SP 3 */ -#define B2063_REG_SP1 B43_LP_RADIO(0x056) /* REG SP 1 */ -#define B2063_BANDGAP_CTL1 B43_LP_RADIO(0x057) /* BANDGAP Control 1 */ -#define B2063_BANDGAP_CTL2 B43_LP_RADIO(0x058) /* BANDGAP Control 2 */ -#define B2063_LPO_CTL1 B43_LP_RADIO(0x059) /* LPO Control 1 */ -#define B2063_RC_CALIB_CTL1 B43_LP_RADIO(0x05A) /* RC Calibration Control 1 */ -#define B2063_RC_CALIB_CTL2 B43_LP_RADIO(0x05B) /* RC Calibration Control 2 */ -#define B2063_RC_CALIB_CTL3 B43_LP_RADIO(0x05C) /* RC Calibration Control 3 */ -#define B2063_RC_CALIB_CTL4 B43_LP_RADIO(0x05D) /* RC Calibration Control 4 */ -#define B2063_RC_CALIB_CTL5 B43_LP_RADIO(0x05E) /* RC Calibration Control 5 */ -#define B2063_RC_CALIB_CTL6 B43_LP_RADIO(0x05F) /* RC Calibration Control 6 */ -#define B2063_RC_CALIB_CTL7 B43_LP_RADIO(0x060) /* RC Calibration Control 7 */ -#define B2063_RC_CALIB_CTL8 B43_LP_RADIO(0x061) /* RC Calibration Control 8 */ -#define B2063_RC_CALIB_CTL9 B43_LP_RADIO(0x062) /* RC Calibration Control 9 */ -#define B2063_RC_CALIB_CTL10 B43_LP_RADIO(0x063) /* RC Calibration Control 10 */ -#define B2063_PLL_JTAG_CALNRST B43_LP_RADIO(0x064) /* PLL JTAG CALNRST */ -#define B2063_PLL_JTAG_IN_PLL1 B43_LP_RADIO(0x065) /* PLL JTAG IN PLL 1 */ -#define B2063_PLL_JTAG_IN_PLL2 B43_LP_RADIO(0x066) /* PLL JTAG IN PLL 2 */ -#define B2063_PLL_JTAG_PLL_CP1 B43_LP_RADIO(0x067) /* PLL JTAG PLL CP 1 */ -#define B2063_PLL_JTAG_PLL_CP2 B43_LP_RADIO(0x068) /* PLL JTAG PLL CP 2 */ -#define B2063_PLL_JTAG_PLL_CP3 B43_LP_RADIO(0x069) /* PLL JTAG PLL CP 3 */ -#define B2063_PLL_JTAG_PLL_CP4 B43_LP_RADIO(0x06A) /* PLL JTAG PLL CP 4 */ -#define B2063_PLL_JTAG_PLL_CTL1 B43_LP_RADIO(0x06B) /* PLL JTAG PLL Control 1 */ -#define B2063_PLL_JTAG_PLL_LF1 B43_LP_RADIO(0x06C) /* PLL JTAG PLL LF 1 */ -#define B2063_PLL_JTAG_PLL_LF2 B43_LP_RADIO(0x06D) /* PLL JTAG PLL LF 2 */ -#define B2063_PLL_JTAG_PLL_LF3 B43_LP_RADIO(0x06E) /* PLL JTAG PLL LF 3 */ -#define B2063_PLL_JTAG_PLL_LF4 B43_LP_RADIO(0x06F) /* PLL JTAG PLL LF 4 */ -#define B2063_PLL_JTAG_PLL_SG1 B43_LP_RADIO(0x070) /* PLL JTAG PLL SG 1 */ -#define B2063_PLL_JTAG_PLL_SG2 B43_LP_RADIO(0x071) /* PLL JTAG PLL SG 2 */ -#define B2063_PLL_JTAG_PLL_SG3 B43_LP_RADIO(0x072) /* PLL JTAG PLL SG 3 */ -#define B2063_PLL_JTAG_PLL_SG4 B43_LP_RADIO(0x073) /* PLL JTAG PLL SG 4 */ -#define B2063_PLL_JTAG_PLL_SG5 B43_LP_RADIO(0x074) /* PLL JTAG PLL SG 5 */ -#define B2063_PLL_JTAG_PLL_VCO1 B43_LP_RADIO(0x075) /* PLL JTAG PLL VCO 1 */ -#define B2063_PLL_JTAG_PLL_VCO2 B43_LP_RADIO(0x076) /* PLL JTAG PLL VCO 2 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB1 B43_LP_RADIO(0x077) /* PLL JTAG PLL VCO Calibration 1 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB2 B43_LP_RADIO(0x078) /* PLL JTAG PLL VCO Calibration 2 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB3 B43_LP_RADIO(0x079) /* PLL JTAG PLL VCO Calibration 3 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB4 B43_LP_RADIO(0x07A) /* PLL JTAG PLL VCO Calibration 4 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB5 B43_LP_RADIO(0x07B) /* PLL JTAG PLL VCO Calibration 5 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB6 B43_LP_RADIO(0x07C) /* PLL JTAG PLL VCO Calibration 6 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB7 B43_LP_RADIO(0x07D) /* PLL JTAG PLL VCO Calibration 7 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB8 B43_LP_RADIO(0x07E) /* PLL JTAG PLL VCO Calibration 8 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB9 B43_LP_RADIO(0x07F) /* PLL JTAG PLL VCO Calibration 9 */ -#define B2063_PLL_JTAG_PLL_VCO_CALIB10 B43_LP_RADIO(0x080) /* PLL JTAG PLL VCO Calibration 10 */ -#define B2063_PLL_JTAG_PLL_XTAL_12 B43_LP_RADIO(0x081) /* PLL JTAG PLL XTAL 1 2 */ -#define B2063_PLL_JTAG_PLL_XTAL3 B43_LP_RADIO(0x082) /* PLL JTAG PLL XTAL 3 */ -#define B2063_LOGEN_ACL1 B43_LP_RADIO(0x083) /* LOGEN ACL 1 */ -#define B2063_LOGEN_ACL2 B43_LP_RADIO(0x084) /* LOGEN ACL 2 */ -#define B2063_LOGEN_ACL3 B43_LP_RADIO(0x085) /* LOGEN ACL 3 */ -#define B2063_LOGEN_ACL4 B43_LP_RADIO(0x086) /* LOGEN ACL 4 */ -#define B2063_LOGEN_ACL5 B43_LP_RADIO(0x087) /* LOGEN ACL 5 */ -#define B2063_LO_CALIB_INPUTS B43_LP_RADIO(0x088) /* LO Calibration INPUTS */ -#define B2063_LO_CALIB_CTL1 B43_LP_RADIO(0x089) /* LO Calibration Control 1 */ -#define B2063_LO_CALIB_CTL2 B43_LP_RADIO(0x08A) /* LO Calibration Control 2 */ -#define B2063_LO_CALIB_CTL3 B43_LP_RADIO(0x08B) /* LO Calibration Control 3 */ -#define B2063_LO_CALIB_WAITCNT B43_LP_RADIO(0x08C) /* LO Calibration WAITCNT */ -#define B2063_LO_CALIB_OVR1 B43_LP_RADIO(0x08D) /* LO Calibration OVR 1 */ -#define B2063_LO_CALIB_OVR2 B43_LP_RADIO(0x08E) /* LO Calibration OVR 2 */ -#define B2063_LO_CALIB_OVAL1 B43_LP_RADIO(0x08F) /* LO Calibration OVAL 1 */ -#define B2063_LO_CALIB_OVAL2 B43_LP_RADIO(0x090) /* LO Calibration OVAL 2 */ -#define B2063_LO_CALIB_OVAL3 B43_LP_RADIO(0x091) /* LO Calibration OVAL 3 */ -#define B2063_LO_CALIB_OVAL4 B43_LP_RADIO(0x092) /* LO Calibration OVAL 4 */ -#define B2063_LO_CALIB_OVAL5 B43_LP_RADIO(0x093) /* LO Calibration OVAL 5 */ -#define B2063_LO_CALIB_OVAL6 B43_LP_RADIO(0x094) /* LO Calibration OVAL 6 */ -#define B2063_LO_CALIB_OVAL7 B43_LP_RADIO(0x095) /* LO Calibration OVAL 7 */ -#define B2063_LO_CALIB_CALVLD1 B43_LP_RADIO(0x096) /* LO Calibration CALVLD 1 */ -#define B2063_LO_CALIB_CALVLD2 B43_LP_RADIO(0x097) /* LO Calibration CALVLD 2 */ -#define B2063_LO_CALIB_CVAL1 B43_LP_RADIO(0x098) /* LO Calibration CVAL 1 */ -#define B2063_LO_CALIB_CVAL2 B43_LP_RADIO(0x099) /* LO Calibration CVAL 2 */ -#define B2063_LO_CALIB_CVAL3 B43_LP_RADIO(0x09A) /* LO Calibration CVAL 3 */ -#define B2063_LO_CALIB_CVAL4 B43_LP_RADIO(0x09B) /* LO Calibration CVAL 4 */ -#define B2063_LO_CALIB_CVAL5 B43_LP_RADIO(0x09C) /* LO Calibration CVAL 5 */ -#define B2063_LO_CALIB_CVAL6 B43_LP_RADIO(0x09D) /* LO Calibration CVAL 6 */ -#define B2063_LO_CALIB_CVAL7 B43_LP_RADIO(0x09E) /* LO Calibration CVAL 7 */ -#define B2063_LOGEN_CALIB_EN B43_LP_RADIO(0x09F) /* LOGEN Calibration EN */ -#define B2063_LOGEN_PEAKDET1 B43_LP_RADIO(0x0A0) /* LOGEN PEAKDET 1 */ -#define B2063_LOGEN_RCCR1 B43_LP_RADIO(0x0A1) /* LOGEN RCCR 1 */ -#define B2063_LOGEN_VCOBUF1 B43_LP_RADIO(0x0A2) /* LOGEN VCOBUF 1 */ -#define B2063_LOGEN_MIXER1 B43_LP_RADIO(0x0A3) /* LOGEN MIXER 1 */ -#define B2063_LOGEN_MIXER2 B43_LP_RADIO(0x0A4) /* LOGEN MIXER 2 */ -#define B2063_LOGEN_BUF1 B43_LP_RADIO(0x0A5) /* LOGEN BUF 1 */ -#define B2063_LOGEN_BUF2 B43_LP_RADIO(0x0A6) /* LOGEN BUF 2 */ -#define B2063_LOGEN_DIV1 B43_LP_RADIO(0x0A7) /* LOGEN DIV 1 */ -#define B2063_LOGEN_DIV2 B43_LP_RADIO(0x0A8) /* LOGEN DIV 2 */ -#define B2063_LOGEN_DIV3 B43_LP_RADIO(0x0A9) /* LOGEN DIV 3 */ -#define B2063_LOGEN_CBUFRX1 B43_LP_RADIO(0x0AA) /* LOGEN CBUFRX 1 */ -#define B2063_LOGEN_CBUFRX2 B43_LP_RADIO(0x0AB) /* LOGEN CBUFRX 2 */ -#define B2063_LOGEN_CBUFTX1 B43_LP_RADIO(0x0AC) /* LOGEN CBUFTX 1 */ -#define B2063_LOGEN_CBUFTX2 B43_LP_RADIO(0x0AD) /* LOGEN CBUFTX 2 */ -#define B2063_LOGEN_IDAC1 B43_LP_RADIO(0x0AE) /* LOGEN IDAC 1 */ -#define B2063_LOGEN_SPARE1 B43_LP_RADIO(0x0AF) /* LOGEN SPARE 1 */ -#define B2063_LOGEN_SPARE2 B43_LP_RADIO(0x0B0) /* LOGEN SPARE 2 */ -#define B2063_LOGEN_SPARE3 B43_LP_RADIO(0x0B1) /* LOGEN SPARE 3 */ -#define B2063_G_RX_1ST1 B43_LP_RADIO(0x0B2) /* G RX 1ST 1 */ -#define B2063_G_RX_1ST2 B43_LP_RADIO(0x0B3) /* G RX 1ST 2 */ -#define B2063_G_RX_1ST3 B43_LP_RADIO(0x0B4) /* G RX 1ST 3 */ -#define B2063_G_RX_2ND1 B43_LP_RADIO(0x0B5) /* G RX 2ND 1 */ -#define B2063_G_RX_2ND2 B43_LP_RADIO(0x0B6) /* G RX 2ND 2 */ -#define B2063_G_RX_2ND3 B43_LP_RADIO(0x0B7) /* G RX 2ND 3 */ -#define B2063_G_RX_2ND4 B43_LP_RADIO(0x0B8) /* G RX 2ND 4 */ -#define B2063_G_RX_2ND5 B43_LP_RADIO(0x0B9) /* G RX 2ND 5 */ -#define B2063_G_RX_2ND6 B43_LP_RADIO(0x0BA) /* G RX 2ND 6 */ -#define B2063_G_RX_2ND7 B43_LP_RADIO(0x0BB) /* G RX 2ND 7 */ -#define B2063_G_RX_2ND8 B43_LP_RADIO(0x0BC) /* G RX 2ND 8 */ -#define B2063_G_RX_PS1 B43_LP_RADIO(0x0BD) /* G RX PS 1 */ -#define B2063_G_RX_PS2 B43_LP_RADIO(0x0BE) /* G RX PS 2 */ -#define B2063_G_RX_PS3 B43_LP_RADIO(0x0BF) /* G RX PS 3 */ -#define B2063_G_RX_PS4 B43_LP_RADIO(0x0C0) /* G RX PS 4 */ -#define B2063_G_RX_PS5 B43_LP_RADIO(0x0C1) /* G RX PS 5 */ -#define B2063_G_RX_MIX1 B43_LP_RADIO(0x0C2) /* G RX MIX 1 */ -#define B2063_G_RX_MIX2 B43_LP_RADIO(0x0C3) /* G RX MIX 2 */ -#define B2063_G_RX_MIX3 B43_LP_RADIO(0x0C4) /* G RX MIX 3 */ -#define B2063_G_RX_MIX4 B43_LP_RADIO(0x0C5) /* G RX MIX 4 */ -#define B2063_G_RX_MIX5 B43_LP_RADIO(0x0C6) /* G RX MIX 5 */ -#define B2063_G_RX_MIX6 B43_LP_RADIO(0x0C7) /* G RX MIX 6 */ -#define B2063_G_RX_MIX7 B43_LP_RADIO(0x0C8) /* G RX MIX 7 */ -#define B2063_G_RX_MIX8 B43_LP_RADIO(0x0C9) /* G RX MIX 8 */ -#define B2063_G_RX_PDET1 B43_LP_RADIO(0x0CA) /* G RX PDET 1 */ -#define B2063_G_RX_SPARES1 B43_LP_RADIO(0x0CB) /* G RX SPARES 1 */ -#define B2063_G_RX_SPARES2 B43_LP_RADIO(0x0CC) /* G RX SPARES 2 */ -#define B2063_G_RX_SPARES3 B43_LP_RADIO(0x0CD) /* G RX SPARES 3 */ -#define B2063_A_RX_1ST1 B43_LP_RADIO(0x0CE) /* A RX 1ST 1 */ -#define B2063_A_RX_1ST2 B43_LP_RADIO(0x0CF) /* A RX 1ST 2 */ -#define B2063_A_RX_1ST3 B43_LP_RADIO(0x0D0) /* A RX 1ST 3 */ -#define B2063_A_RX_1ST4 B43_LP_RADIO(0x0D1) /* A RX 1ST 4 */ -#define B2063_A_RX_1ST5 B43_LP_RADIO(0x0D2) /* A RX 1ST 5 */ -#define B2063_A_RX_2ND1 B43_LP_RADIO(0x0D3) /* A RX 2ND 1 */ -#define B2063_A_RX_2ND2 B43_LP_RADIO(0x0D4) /* A RX 2ND 2 */ -#define B2063_A_RX_2ND3 B43_LP_RADIO(0x0D5) /* A RX 2ND 3 */ -#define B2063_A_RX_2ND4 B43_LP_RADIO(0x0D6) /* A RX 2ND 4 */ -#define B2063_A_RX_2ND5 B43_LP_RADIO(0x0D7) /* A RX 2ND 5 */ -#define B2063_A_RX_2ND6 B43_LP_RADIO(0x0D8) /* A RX 2ND 6 */ -#define B2063_A_RX_2ND7 B43_LP_RADIO(0x0D9) /* A RX 2ND 7 */ -#define B2063_A_RX_PS1 B43_LP_RADIO(0x0DA) /* A RX PS 1 */ -#define B2063_A_RX_PS2 B43_LP_RADIO(0x0DB) /* A RX PS 2 */ -#define B2063_A_RX_PS3 B43_LP_RADIO(0x0DC) /* A RX PS 3 */ -#define B2063_A_RX_PS4 B43_LP_RADIO(0x0DD) /* A RX PS 4 */ -#define B2063_A_RX_PS5 B43_LP_RADIO(0x0DE) /* A RX PS 5 */ -#define B2063_A_RX_PS6 B43_LP_RADIO(0x0DF) /* A RX PS 6 */ -#define B2063_A_RX_MIX1 B43_LP_RADIO(0x0E0) /* A RX MIX 1 */ -#define B2063_A_RX_MIX2 B43_LP_RADIO(0x0E1) /* A RX MIX 2 */ -#define B2063_A_RX_MIX3 B43_LP_RADIO(0x0E2) /* A RX MIX 3 */ -#define B2063_A_RX_MIX4 B43_LP_RADIO(0x0E3) /* A RX MIX 4 */ -#define B2063_A_RX_MIX5 B43_LP_RADIO(0x0E4) /* A RX MIX 5 */ -#define B2063_A_RX_MIX6 B43_LP_RADIO(0x0E5) /* A RX MIX 6 */ -#define B2063_A_RX_MIX7 B43_LP_RADIO(0x0E6) /* A RX MIX 7 */ -#define B2063_A_RX_MIX8 B43_LP_RADIO(0x0E7) /* A RX MIX 8 */ -#define B2063_A_RX_PWRDET1 B43_LP_RADIO(0x0E8) /* A RX PWRDET 1 */ -#define B2063_A_RX_SPARE1 B43_LP_RADIO(0x0E9) /* A RX SPARE 1 */ -#define B2063_A_RX_SPARE2 B43_LP_RADIO(0x0EA) /* A RX SPARE 2 */ -#define B2063_A_RX_SPARE3 B43_LP_RADIO(0x0EB) /* A RX SPARE 3 */ -#define B2063_RX_TIA_CTL1 B43_LP_RADIO(0x0EC) /* RX TIA Control 1 */ -#define B2063_RX_TIA_CTL2 B43_LP_RADIO(0x0ED) /* RX TIA Control 2 */ -#define B2063_RX_TIA_CTL3 B43_LP_RADIO(0x0EE) /* RX TIA Control 3 */ -#define B2063_RX_TIA_CTL4 B43_LP_RADIO(0x0EF) /* RX TIA Control 4 */ -#define B2063_RX_TIA_CTL5 B43_LP_RADIO(0x0F0) /* RX TIA Control 5 */ -#define B2063_RX_TIA_CTL6 B43_LP_RADIO(0x0F1) /* RX TIA Control 6 */ -#define B2063_RX_BB_CTL1 B43_LP_RADIO(0x0F2) /* RX BB Control 1 */ -#define B2063_RX_BB_CTL2 B43_LP_RADIO(0x0F3) /* RX BB Control 2 */ -#define B2063_RX_BB_CTL3 B43_LP_RADIO(0x0F4) /* RX BB Control 3 */ -#define B2063_RX_BB_CTL4 B43_LP_RADIO(0x0F5) /* RX BB Control 4 */ -#define B2063_RX_BB_CTL5 B43_LP_RADIO(0x0F6) /* RX BB Control 5 */ -#define B2063_RX_BB_CTL6 B43_LP_RADIO(0x0F7) /* RX BB Control 6 */ -#define B2063_RX_BB_CTL7 B43_LP_RADIO(0x0F8) /* RX BB Control 7 */ -#define B2063_RX_BB_CTL8 B43_LP_RADIO(0x0F9) /* RX BB Control 8 */ -#define B2063_RX_BB_CTL9 B43_LP_RADIO(0x0FA) /* RX BB Control 9 */ -#define B2063_TX_RF_CTL1 B43_LP_RADIO(0x0FB) /* TX RF Control 1 */ -#define B2063_TX_RF_IDAC_LO_RF_I B43_LP_RADIO(0x0FC) /* TX RF IDAC LO RF I */ -#define B2063_TX_RF_IDAC_LO_RF_Q B43_LP_RADIO(0x0FD) /* TX RF IDAC LO RF Q */ -#define B2063_TX_RF_IDAC_LO_BB_I B43_LP_RADIO(0x0FE) /* TX RF IDAC LO BB I */ -#define B2063_TX_RF_IDAC_LO_BB_Q B43_LP_RADIO(0x0FF) /* TX RF IDAC LO BB Q */ -#define B2063_TX_RF_CTL2 B43_LP_RADIO(0x100) /* TX RF Control 2 */ -#define B2063_TX_RF_CTL3 B43_LP_RADIO(0x101) /* TX RF Control 3 */ -#define B2063_TX_RF_CTL4 B43_LP_RADIO(0x102) /* TX RF Control 4 */ -#define B2063_TX_RF_CTL5 B43_LP_RADIO(0x103) /* TX RF Control 5 */ -#define B2063_TX_RF_CTL6 B43_LP_RADIO(0x104) /* TX RF Control 6 */ -#define B2063_TX_RF_CTL7 B43_LP_RADIO(0x105) /* TX RF Control 7 */ -#define B2063_TX_RF_CTL8 B43_LP_RADIO(0x106) /* TX RF Control 8 */ -#define B2063_TX_RF_CTL9 B43_LP_RADIO(0x107) /* TX RF Control 9 */ -#define B2063_TX_RF_CTL10 B43_LP_RADIO(0x108) /* TX RF Control 10 */ -#define B2063_TX_RF_CTL14 B43_LP_RADIO(0x109) /* TX RF Control 14 */ -#define B2063_TX_RF_CTL15 B43_LP_RADIO(0x10A) /* TX RF Control 15 */ -#define B2063_PA_CTL1 B43_LP_RADIO(0x10B) /* PA Control 1 */ -#define B2063_PA_CTL2 B43_LP_RADIO(0x10C) /* PA Control 2 */ -#define B2063_PA_CTL3 B43_LP_RADIO(0x10D) /* PA Control 3 */ -#define B2063_PA_CTL4 B43_LP_RADIO(0x10E) /* PA Control 4 */ -#define B2063_PA_CTL5 B43_LP_RADIO(0x10F) /* PA Control 5 */ -#define B2063_PA_CTL6 B43_LP_RADIO(0x110) /* PA Control 6 */ -#define B2063_PA_CTL7 B43_LP_RADIO(0x111) /* PA Control 7 */ -#define B2063_PA_CTL8 B43_LP_RADIO(0x112) /* PA Control 8 */ -#define B2063_PA_CTL9 B43_LP_RADIO(0x113) /* PA Control 9 */ -#define B2063_PA_CTL10 B43_LP_RADIO(0x114) /* PA Control 10 */ -#define B2063_PA_CTL11 B43_LP_RADIO(0x115) /* PA Control 11 */ -#define B2063_PA_CTL12 B43_LP_RADIO(0x116) /* PA Control 12 */ -#define B2063_PA_CTL13 B43_LP_RADIO(0x117) /* PA Control 13 */ -#define B2063_TX_BB_CTL1 B43_LP_RADIO(0x118) /* TX BB Control 1 */ -#define B2063_TX_BB_CTL2 B43_LP_RADIO(0x119) /* TX BB Control 2 */ -#define B2063_TX_BB_CTL3 B43_LP_RADIO(0x11A) /* TX BB Control 3 */ -#define B2063_TX_BB_CTL4 B43_LP_RADIO(0x11B) /* TX BB Control 4 */ -#define B2063_GPIO_CTL1 B43_LP_RADIO(0x11C) /* GPIO Control 1 */ -#define B2063_VREG_CTL1 B43_LP_RADIO(0x11D) /* VREG Control 1 */ -#define B2063_AMUX_CTL1 B43_LP_RADIO(0x11E) /* AMUX Control 1 */ -#define B2063_IQ_CALIB_GVAR B43_LP_RADIO(0x11F) /* IQ Calibration GVAR */ -#define B2063_IQ_CALIB_CTL1 B43_LP_RADIO(0x120) /* IQ Calibration Control 1 */ -#define B2063_IQ_CALIB_CTL2 B43_LP_RADIO(0x121) /* IQ Calibration Control 2 */ -#define B2063_TEMPSENSE_CTL1 B43_LP_RADIO(0x122) /* TEMPSENSE Control 1 */ -#define B2063_TEMPSENSE_CTL2 B43_LP_RADIO(0x123) /* TEMPSENSE Control 2 */ -#define B2063_TX_RX_LOOPBACK1 B43_LP_RADIO(0x124) /* TX/RX LOOPBACK 1 */ -#define B2063_TX_RX_LOOPBACK2 B43_LP_RADIO(0x125) /* TX/RX LOOPBACK 2 */ -#define B2063_EXT_TSSI_CTL1 B43_LP_RADIO(0x126) /* EXT TSSI Control 1 */ -#define B2063_EXT_TSSI_CTL2 B43_LP_RADIO(0x127) /* EXT TSSI Control 2 */ -#define B2063_AFE_CTL B43_LP_RADIO(0x128) /* AFE Control */ - - - -enum b43_lpphy_txpctl_mode { - B43_LPPHY_TXPCTL_UNKNOWN = 0, - B43_LPPHY_TXPCTL_OFF, /* TX power control is OFF */ - B43_LPPHY_TXPCTL_SW, /* TX power control is set to Software */ - B43_LPPHY_TXPCTL_HW, /* TX power control is set to Hardware */ -}; - -struct b43_phy_lp { - /* Current TX power control mode. */ - enum b43_lpphy_txpctl_mode txpctl_mode; - - /* Transmit isolation medium band */ - u8 tx_isolation_med_band; - /* Transmit isolation low band */ - u8 tx_isolation_low_band; - /* Transmit isolation high band */ - u8 tx_isolation_hi_band; - - /* Max transmit power medium band */ - u16 max_tx_pwr_med_band; - /* Max transmit power low band */ - u16 max_tx_pwr_low_band; - /* Max transmit power high band */ - u16 max_tx_pwr_hi_band; - - /* FIXME What are these used for? */ - /* FIXME Is 15 the correct array size? */ - u16 tx_max_rate[15]; - u16 tx_max_ratel[15]; - u16 tx_max_rateh[15]; - - /* Transmit power arrays */ - s16 txpa[3], txpal[3], txpah[3]; - - /* Receive power offset */ - u8 rx_pwr_offset; - - /* TSSI transmit count */ - u16 tssi_tx_count; - /* TSSI index */ - u16 tssi_idx; /* FIXME initial value? */ - /* TSSI npt */ - u16 tssi_npt; /* FIXME initial value? */ - - /* Target TX frequency */ - u16 tgt_tx_freq; /* FIXME initial value? */ - - /* Transmit power index override */ - s8 tx_pwr_idx_over; /* FIXME initial value? */ - - /* RSSI vf */ - u8 rssi_vf; - /* RSSI vc */ - u8 rssi_vc; - /* RSSI gs */ - u8 rssi_gs; - - /* RC cap */ - u8 rc_cap; - /* BX arch */ - u8 bx_arch; - - /* Full calibration channel */ - u8 full_calib_chan; - - /* Transmit iqlocal best coeffs */ - bool tx_iqloc_best_coeffs_valid; - u8 tx_iqloc_best_coeffs[11]; - - /* Used for "Save/Restore Dig Filt State" */ - u16 dig_flt_state[9]; - - bool crs_usr_disable, crs_sys_disable; - - unsigned int pdiv; - - /* The channel we are tuned to */ - u8 channel; - - /* The active antenna diversity mode */ - int antenna; - - /* Frequency of the active TX tone */ - int tx_tone_freq; -}; - -enum tssi_mux_mode { - TSSI_MUX_PREPA, - TSSI_MUX_POSTPA, - TSSI_MUX_EXT, -}; - -struct b43_phy_operations; -extern const struct b43_phy_operations b43_phyops_lp; - -#endif /* LINUX_B43_PHY_LP_H_ */ diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c deleted file mode 100644 index 9f0bcf3b8..000000000 --- a/drivers/net/wireless/b43/phy_n.c +++ /dev/null @@ -1,6726 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n PHY support - - Copyright (c) 2008 Michael Buesch <m@bues.ch> - Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/delay.h> -#include <linux/slab.h> -#include <linux/types.h> - -#include "b43.h" -#include "phy_n.h" -#include "tables_nphy.h" -#include "radio_2055.h" -#include "radio_2056.h" -#include "radio_2057.h" -#include "main.h" -#include "ppr.h" - -struct nphy_txgains { - u16 tx_lpf[2]; - u16 txgm[2]; - u16 pga[2]; - u16 pad[2]; - u16 ipa[2]; -}; - -struct nphy_iqcal_params { - u16 tx_lpf; - u16 txgm; - u16 pga; - u16 pad; - u16 ipa; - u16 cal_gain; - u16 ncorr[5]; -}; - -struct nphy_iq_est { - s32 iq0_prod; - u32 i0_pwr; - u32 q0_pwr; - s32 iq1_prod; - u32 i1_pwr; - u32 q1_pwr; -}; - -enum b43_nphy_rf_sequence { - B43_RFSEQ_RX2TX, - B43_RFSEQ_TX2RX, - B43_RFSEQ_RESET2RX, - B43_RFSEQ_UPDATE_GAINH, - B43_RFSEQ_UPDATE_GAINL, - B43_RFSEQ_UPDATE_GAINU, -}; - -enum n_rf_ctl_over_cmd { - N_RF_CTL_OVER_CMD_RXRF_PU = 0, - N_RF_CTL_OVER_CMD_RX_PU = 1, - N_RF_CTL_OVER_CMD_TX_PU = 2, - N_RF_CTL_OVER_CMD_RX_GAIN = 3, - N_RF_CTL_OVER_CMD_TX_GAIN = 4, -}; - -enum n_intc_override { - N_INTC_OVERRIDE_OFF = 0, - N_INTC_OVERRIDE_TRSW = 1, - N_INTC_OVERRIDE_PA = 2, - N_INTC_OVERRIDE_EXT_LNA_PU = 3, - N_INTC_OVERRIDE_EXT_LNA_GAIN = 4, -}; - -enum n_rssi_type { - N_RSSI_W1 = 0, - N_RSSI_W2, - N_RSSI_NB, - N_RSSI_IQ, - N_RSSI_TSSI_2G, - N_RSSI_TSSI_5G, - N_RSSI_TBD, -}; - -enum n_rail_type { - N_RAIL_I = 0, - N_RAIL_Q = 1, -}; - -static inline bool b43_nphy_ipa(struct b43_wldev *dev) -{ - enum ieee80211_band band = b43_current_band(dev->wl); - return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) || - (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */ -static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) -{ - return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> - B43_NPHY_RFSEQCA_RXEN_SHIFT; -} - -/************************************************** - * RF (just without b43_nphy_rf_ctl_intc_override) - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ -static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, - enum b43_nphy_rf_sequence seq) -{ - static const u16 trigger[] = { - [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, - [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, - [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, - [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, - [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, - [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, - }; - int i; - u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); - - B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); - - b43_phy_set(dev, B43_NPHY_RFSEQMODE, - B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); - b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); - for (i = 0; i < 200; i++) { - if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) - goto ok; - msleep(1); - } - b43err(dev->wl, "RF sequence status timeout\n"); -ok: - b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); -} - -static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, - u16 value, u8 core, bool off, - u8 override_id) -{ - /* TODO */ -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ -static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, - u16 value, u8 core, bool off, - u8 override) -{ - struct b43_phy *phy = &dev->phy; - const struct nphy_rf_control_override_rev7 *e; - u16 en_addrs[3][2] = { - { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } - }; - u16 en_addr; - u16 en_mask = field; - u16 val_addr; - u8 i; - - if (phy->rev >= 19 || phy->rev < 3) { - B43_WARN_ON(1); - return; - } - - /* Remember: we can get NULL! */ - e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); - - for (i = 0; i < 2; i++) { - if (override >= ARRAY_SIZE(en_addrs)) { - b43err(dev->wl, "Invalid override value %d\n", override); - return; - } - en_addr = en_addrs[override][i]; - - if (e) - val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; - - if (off) { - b43_phy_mask(dev, en_addr, ~en_mask); - if (e) /* Do it safer, better than wl */ - b43_phy_mask(dev, val_addr, ~e->val_mask); - } else { - if (!core || (core & (1 << i))) { - b43_phy_set(dev, en_addr, en_mask); - if (e) - b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); - } - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ -static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, - enum n_rf_ctl_over_cmd cmd, - u16 value, u8 core, bool off) -{ - struct b43_phy *phy = &dev->phy; - u16 tmp; - - B43_WARN_ON(phy->rev < 7); - - switch (cmd) { - case N_RF_CTL_OVER_CMD_RXRF_PU: - b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); - break; - case N_RF_CTL_OVER_CMD_RX_PU: - b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); - b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); - break; - case N_RF_CTL_OVER_CMD_TX_PU: - b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); - b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); - b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); - b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); - break; - case N_RF_CTL_OVER_CMD_RX_GAIN: - tmp = value & 0xFF; - b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); - tmp = value >> 8; - b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); - break; - case N_RF_CTL_OVER_CMD_TX_GAIN: - tmp = value & 0x7FFF; - b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); - tmp = value >> 14; - b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); - break; - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ -static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, - u16 value, u8 core, bool off) -{ - int i; - u8 index = fls(field); - u8 addr, en_addr, val_addr; - /* we expect only one bit set */ - B43_WARN_ON(field & (~(1 << (index - 1)))); - - if (dev->phy.rev >= 3) { - const struct nphy_rf_control_override_rev3 *rf_ctrl; - for (i = 0; i < 2; i++) { - if (index == 0 || index == 16) { - b43err(dev->wl, - "Unsupported RF Ctrl Override call\n"); - return; - } - - rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; - en_addr = B43_PHY_N((i == 0) ? - rf_ctrl->en_addr0 : rf_ctrl->en_addr1); - val_addr = B43_PHY_N((i == 0) ? - rf_ctrl->val_addr0 : rf_ctrl->val_addr1); - - if (off) { - b43_phy_mask(dev, en_addr, ~(field)); - b43_phy_mask(dev, val_addr, - ~(rf_ctrl->val_mask)); - } else { - if (core == 0 || ((1 << i) & core)) { - b43_phy_set(dev, en_addr, field); - b43_phy_maskset(dev, val_addr, - ~(rf_ctrl->val_mask), - (value << rf_ctrl->val_shift)); - } - } - } - } else { - const struct nphy_rf_control_override_rev2 *rf_ctrl; - if (off) { - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); - value = 0; - } else { - b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); - } - - for (i = 0; i < 2; i++) { - if (index <= 1 || index == 16) { - b43err(dev->wl, - "Unsupported RF Ctrl Override call\n"); - return; - } - - if (index == 2 || index == 10 || - (index >= 13 && index <= 15)) { - core = 1; - } - - rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; - addr = B43_PHY_N((i == 0) ? - rf_ctrl->addr0 : rf_ctrl->addr1); - - if ((1 << i) & core) - b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), - (value << rf_ctrl->shift)); - - b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_START); - udelay(1); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); - } - } -} - -static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, - enum n_intc_override intc_override, - u16 value, u8 core_sel) -{ - u16 reg, tmp, tmp2, val; - int core; - - /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */ - - for (core = 0; core < 2; core++) { - if ((core_sel == 1 && core != 0) || - (core_sel == 2 && core != 1)) - continue; - - reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; - - switch (intc_override) { - case N_INTC_OVERRIDE_OFF: - b43_phy_write(dev, reg, 0); - b43_phy_mask(dev, 0x2ff, ~0x2000); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - break; - case N_INTC_OVERRIDE_TRSW: - b43_phy_maskset(dev, reg, ~0xC0, value << 6); - b43_phy_set(dev, reg, 0x400); - - b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); - b43_phy_set(dev, 0x2ff, 0x2000); - b43_phy_set(dev, 0x2ff, 0x0001); - break; - case N_INTC_OVERRIDE_PA: - tmp = 0x0030; - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - val = value << 5; - else - val = value << 4; - b43_phy_maskset(dev, reg, ~tmp, val); - b43_phy_set(dev, reg, 0x1000); - break; - case N_INTC_OVERRIDE_EXT_LNA_PU: - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - tmp = 0x0001; - tmp2 = 0x0004; - val = value; - } else { - tmp = 0x0004; - tmp2 = 0x0001; - val = value << 2; - } - b43_phy_maskset(dev, reg, ~tmp, val); - b43_phy_mask(dev, reg, ~tmp2); - break; - case N_INTC_OVERRIDE_EXT_LNA_GAIN: - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - tmp = 0x0002; - tmp2 = 0x0008; - val = value << 1; - } else { - tmp = 0x0008; - tmp2 = 0x0002; - val = value << 3; - } - b43_phy_maskset(dev, reg, ~tmp, val); - b43_phy_mask(dev, reg, ~tmp2); - break; - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ -static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, - enum n_intc_override intc_override, - u16 value, u8 core) -{ - u8 i, j; - u16 reg, tmp, val; - - if (dev->phy.rev >= 7) { - b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, - core); - return; - } - - B43_WARN_ON(dev->phy.rev < 3); - - for (i = 0; i < 2; i++) { - if ((core == 1 && i == 1) || (core == 2 && !i)) - continue; - - reg = (i == 0) ? - B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; - b43_phy_set(dev, reg, 0x400); - - switch (intc_override) { - case N_INTC_OVERRIDE_OFF: - b43_phy_write(dev, reg, 0); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - break; - case N_INTC_OVERRIDE_TRSW: - if (!i) { - b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, - 0xFC3F, (value << 6)); - b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, - 0xFFFE, 1); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_START); - for (j = 0; j < 100; j++) { - if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { - j = 0; - break; - } - udelay(10); - } - if (j) - b43err(dev->wl, - "intc override timeout\n"); - b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, - 0xFFFE); - } else { - b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, - 0xFC3F, (value << 6)); - b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, - 0xFFFE, 1); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_RXTX); - for (j = 0; j < 100; j++) { - if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { - j = 0; - break; - } - udelay(10); - } - if (j) - b43err(dev->wl, - "intc override timeout\n"); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, - 0xFFFE); - } - break; - case N_INTC_OVERRIDE_PA: - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - tmp = 0x0020; - val = value << 5; - } else { - tmp = 0x0010; - val = value << 4; - } - b43_phy_maskset(dev, reg, ~tmp, val); - break; - case N_INTC_OVERRIDE_EXT_LNA_PU: - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - tmp = 0x0001; - val = value; - } else { - tmp = 0x0004; - val = value << 2; - } - b43_phy_maskset(dev, reg, ~tmp, val); - break; - case N_INTC_OVERRIDE_EXT_LNA_GAIN: - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - tmp = 0x0002; - val = value << 1; - } else { - tmp = 0x0008; - val = value << 3; - } - b43_phy_maskset(dev, reg, ~tmp, val); - break; - } - } -} - -/************************************************** - * Various PHY ops - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ -static void b43_nphy_write_clip_detection(struct b43_wldev *dev, - const u16 *clip_st) -{ - b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); - b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ -static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) -{ - clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); - clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ -static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) -{ - u16 tmp; - - if (dev->dev->core_rev == 16) - b43_mac_suspend(dev); - - tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); - tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | - B43_NPHY_CLASSCTL_WAITEDEN); - tmp &= ~mask; - tmp |= (val & mask); - b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); - - if (dev->dev->core_rev == 16) - b43_mac_enable(dev); - - return tmp; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ -static void b43_nphy_reset_cca(struct b43_wldev *dev) -{ - u16 bbcfg; - - b43_phy_force_clock(dev, 1); - bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); - b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); - udelay(1); - b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); - b43_phy_force_clock(dev, 0); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ -static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - - if (enable) { - static const u16 clip[] = { 0xFFFF, 0xFFFF }; - if (nphy->deaf_count++ == 0) { - nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); - b43_nphy_classifier(dev, 0x7, - B43_NPHY_CLASSCTL_WAITEDEN); - b43_nphy_read_clip_detection(dev, nphy->clip_state); - b43_nphy_write_clip_detection(dev, clip); - } - b43_nphy_reset_cca(dev); - } else { - if (--nphy->deaf_count == 0) { - b43_nphy_classifier(dev, 0x7, nphy->classifier_state); - b43_nphy_write_clip_detection(dev, nphy->clip_state); - } - } -} - -/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ -static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) -{ - if (!offset) - offset = b43_is_40mhz(dev) ? 0x159 : 0x154; - return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ -static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u8 i; - s16 tmp; - u16 data[4]; - s16 gain[2]; - u16 minmax[2]; - static const u16 lna_gain[4] = { -2, 10, 19, 25 }; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - if (nphy->gain_boost) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - gain[0] = 6; - gain[1] = 6; - } else { - tmp = 40370 - 315 * dev->phy.channel; - gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); - tmp = 23242 - 224 * dev->phy.channel; - gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); - } - } else { - gain[0] = 0; - gain[1] = 0; - } - - for (i = 0; i < 2; i++) { - if (nphy->elna_gain_config) { - data[0] = 19 + gain[i]; - data[1] = 25 + gain[i]; - data[2] = 25 + gain[i]; - data[3] = 25 + gain[i]; - } else { - data[0] = lna_gain[0] + gain[i]; - data[1] = lna_gain[1] + gain[i]; - data[2] = lna_gain[2] + gain[i]; - data[3] = lna_gain[3] + gain[i]; - } - b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); - - minmax[i] = 23 + gain[i]; - } - - b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, - minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); - b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, - minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ -static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, - u8 *events, u8 *delays, u8 length) -{ - struct b43_phy_n *nphy = dev->phy.n; - u8 i; - u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; - u16 offset1 = cmd << 4; - u16 offset2 = offset1 + 0x80; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, true); - - b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); - b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); - - for (i = length; i < 16; i++) { - b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); - b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, false); -} - -/************************************************** - * Radio 0x2057 - **************************************************/ - -static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, - const struct b43_nphy_chantabent_rev7 *e_r7, - const struct b43_nphy_chantabent_rev7_2g *e_r7_2g) -{ - if (e_r7_2g) { - b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); - b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); - b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); - b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); - b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); - b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); - b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); - b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); - b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0); - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); - b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1); - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); - b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); - - } else { - b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); - b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); - b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); - b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); - b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); - b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); - b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); - b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); - b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); - b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); - b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); - b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); - b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); - b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); - b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); - b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); - b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); - b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); - b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); - b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); - b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); - } -} - -static void b43_radio_2057_setup(struct b43_wldev *dev, - const struct b43_nphy_chantabent_rev7 *tabent_r7, - const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g) -{ - struct b43_phy *phy = &dev->phy; - - b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); - - switch (phy->radio_rev) { - case 0 ... 4: - case 6: - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); - b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); - } else { - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); - b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); - } - break; - case 9: /* e.g. PHY rev 16 */ - b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); - b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); - b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); - - if (b43_is_40mhz(dev)) { - /* TODO */ - } else { - b43_radio_write(dev, - R2057_PAD_BIAS_FILTER_BWS_CORE0, - 0x3c); - b43_radio_write(dev, - R2057_PAD_BIAS_FILTER_BWS_CORE1, - 0x3c); - } - } - break; - case 14: /* 2 GHz only */ - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); - b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); - b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); - break; - } - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - u16 txmix2g_tune_boost_pu = 0; - u16 pad2g_tune_pus = 0; - - if (b43_nphy_ipa(dev)) { - switch (phy->radio_rev) { - case 9: - txmix2g_tune_boost_pu = 0x0041; - /* TODO */ - break; - case 14: - txmix2g_tune_boost_pu = 0x21; - pad2g_tune_pus = 0x23; - break; - } - } - - if (txmix2g_tune_boost_pu) - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, - txmix2g_tune_boost_pu); - if (pad2g_tune_pus) - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, - pad2g_tune_pus); - if (txmix2g_tune_boost_pu) - b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, - txmix2g_tune_boost_pu); - if (pad2g_tune_pus) - b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, - pad2g_tune_pus); - } - - usleep_range(50, 100); - - /* VCO calibration */ - b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); - b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); - b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); - b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); - usleep_range(300, 600); -} - -/* Calibrate resistors in LPF of PLL? - * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal - */ -static u8 b43_radio_2057_rcal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 saved_regs_phy[12]; - u16 saved_regs_phy_rf[6]; - u16 saved_regs_radio[2] = { }; - static const u16 phy_to_store[] = { - B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2, - B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2, - B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2, - B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2, - B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, - B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, - }; - static const u16 phy_to_store_rf[] = { - B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1, - B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, - B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, - }; - u16 tmp; - int i; - - /* Save */ - for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) - saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); - for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) - saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); - - /* Set */ - for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) - b43_phy_write(dev, phy_to_store[i], 0); - b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); - b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); - - switch (phy->radio_rev) { - case 5: - b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); - udelay(10); - b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); - b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); - break; - case 9: - b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); - b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); - saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); - b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); - break; - case 14: - saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); - saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); - b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); - b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); - b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); - b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); - break; - } - - /* Enable */ - b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); - udelay(10); - - /* Start */ - b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); - usleep_range(100, 200); - - /* Stop */ - b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); - - /* Wait and check for result */ - if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { - b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); - return 0; - } - tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; - - /* Disable */ - b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); - - /* Restore */ - for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) - b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); - for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) - b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); - - switch (phy->radio_rev) { - case 0 ... 4: - case 6: - b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); - b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, - tmp << 2); - break; - case 5: - b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); - b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); - break; - case 9: - b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); - break; - case 14: - b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); - b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); - break; - } - - return tmp & 0x3e; -} - -/* Calibrate the internal RC oscillator? - * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal - */ -static u16 b43_radio_2057_rccal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 || - phy->radio_rev == 6); - u16 tmp; - - /* Setup cal */ - if (special) { - b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); - } else { - b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); - } - b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); - - /* Start, wait, stop */ - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); - if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, - 5000000)) - b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); - usleep_range(35, 70); - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); - usleep_range(70, 140); - - /* Setup cal */ - if (special) { - b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); - } else { - b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); - } - b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); - - /* Start, wait, stop */ - usleep_range(35, 70); - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); - usleep_range(70, 140); - if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, - 5000000)) - b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); - usleep_range(35, 70); - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); - usleep_range(70, 140); - - /* Setup cal */ - if (special) { - b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); - b43_radio_write(dev, R2057_RCCAL_X1, 0x28); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); - } else { - b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); - b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); - b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); - } - - /* Start, wait, stop */ - usleep_range(35, 70); - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); - usleep_range(70, 140); - if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, - 5000000)) { - b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); - return 0; - } - tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); - usleep_range(35, 70); - b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); - usleep_range(70, 140); - - if (special) - b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); - else - b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); - - return tmp; -} - -static void b43_radio_2057_init_pre(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); - /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); -} - -static void b43_radio_2057_init_post(struct b43_wldev *dev) -{ - b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); - - if (0) /* FIXME: Is this BCM43217 specific? */ - b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); - - b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); - b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); - mdelay(2); - b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); - b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); - - if (dev->phy.do_full_init) { - b43_radio_2057_rcal(dev); - b43_radio_2057_rccal(dev); - } - b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); -} - -/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */ -static void b43_radio_2057_init(struct b43_wldev *dev) -{ - b43_radio_2057_init_pre(dev); - r2057_upload_inittabs(dev); - b43_radio_2057_init_post(dev); -} - -/************************************************** - * Radio 0x2056 - **************************************************/ - -static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, - const struct b43_nphy_channeltab_entry_rev3 *e) -{ - b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); - b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); - b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); - b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); - b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, - e->radio_syn_pll_loopfilter1); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, - e->radio_syn_pll_loopfilter2); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, - e->radio_syn_pll_loopfilter3); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, - e->radio_syn_pll_loopfilter4); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, - e->radio_syn_pll_loopfilter5); - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, - e->radio_syn_reserved_addr27); - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, - e->radio_syn_reserved_addr28); - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, - e->radio_syn_reserved_addr29); - b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, - e->radio_syn_logen_vcobuf1); - b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); - b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); - b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); - - b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, - e->radio_rx0_lnaa_tune); - b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, - e->radio_rx0_lnag_tune); - - b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, - e->radio_tx0_intpaa_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, - e->radio_tx0_intpag_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, - e->radio_tx0_pada_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, - e->radio_tx0_padg_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, - e->radio_tx0_pgaa_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, - e->radio_tx0_pgag_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, - e->radio_tx0_mixa_boost_tune); - b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, - e->radio_tx0_mixg_boost_tune); - - b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, - e->radio_rx1_lnaa_tune); - b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, - e->radio_rx1_lnag_tune); - - b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, - e->radio_tx1_intpaa_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, - e->radio_tx1_intpag_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, - e->radio_tx1_pada_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, - e->radio_tx1_padg_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, - e->radio_tx1_pgaa_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, - e->radio_tx1_pgag_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, - e->radio_tx1_mixa_boost_tune); - b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, - e->radio_tx1_mixg_boost_tune); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */ -static void b43_radio_2056_setup(struct b43_wldev *dev, - const struct b43_nphy_channeltab_entry_rev3 *e) -{ - struct b43_phy *phy = &dev->phy; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - enum ieee80211_band band = b43_current_band(dev->wl); - u16 offset; - u8 i; - u16 bias, cbias; - u16 pag_boost, padg_boost, pgag_boost, mixg_boost; - u16 paa_boost, pada_boost, pgaa_boost, mixa_boost; - bool is_pkg_fab_smic; - - B43_WARN_ON(dev->phy.rev < 3); - - is_pkg_fab_smic = - ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || - dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || - dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && - dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); - - b43_chantab_radio_2056_upload(dev, e); - b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ); - - if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && - b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); - if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || - dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); - b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); - } else { - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); - b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); - } - } - if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 && - b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); - b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); - } - if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR && - b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); - b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); - b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); - } - - if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) { - for (i = 0; i < 2; i++) { - offset = i ? B2056_TX1 : B2056_TX0; - if (dev->phy.rev >= 5) { - b43_radio_write(dev, - offset | B2056_TX_PADG_IDAC, 0xcc); - - if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || - dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { - bias = 0x40; - cbias = 0x45; - pag_boost = 0x5; - pgag_boost = 0x33; - mixg_boost = 0x55; - } else { - bias = 0x25; - cbias = 0x20; - if (is_pkg_fab_smic) { - bias = 0x2a; - cbias = 0x38; - } - pag_boost = 0x4; - pgag_boost = 0x03; - mixg_boost = 0x65; - } - padg_boost = 0x77; - - b43_radio_write(dev, - offset | B2056_TX_INTPAG_IMAIN_STAT, - bias); - b43_radio_write(dev, - offset | B2056_TX_INTPAG_IAUX_STAT, - bias); - b43_radio_write(dev, - offset | B2056_TX_INTPAG_CASCBIAS, - cbias); - b43_radio_write(dev, - offset | B2056_TX_INTPAG_BOOST_TUNE, - pag_boost); - b43_radio_write(dev, - offset | B2056_TX_PGAG_BOOST_TUNE, - pgag_boost); - b43_radio_write(dev, - offset | B2056_TX_PADG_BOOST_TUNE, - padg_boost); - b43_radio_write(dev, - offset | B2056_TX_MIXG_BOOST_TUNE, - mixg_boost); - } else { - bias = b43_is_40mhz(dev) ? 0x40 : 0x20; - b43_radio_write(dev, - offset | B2056_TX_INTPAG_IMAIN_STAT, - bias); - b43_radio_write(dev, - offset | B2056_TX_INTPAG_IAUX_STAT, - bias); - b43_radio_write(dev, - offset | B2056_TX_INTPAG_CASCBIAS, - 0x30); - } - b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); - } - } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) { - u16 freq = phy->chandef->chan->center_freq; - if (freq < 5100) { - paa_boost = 0xA; - pada_boost = 0x77; - pgaa_boost = 0xF; - mixa_boost = 0xF; - } else if (freq < 5340) { - paa_boost = 0x8; - pada_boost = 0x77; - pgaa_boost = 0xFB; - mixa_boost = 0xF; - } else if (freq < 5650) { - paa_boost = 0x0; - pada_boost = 0x77; - pgaa_boost = 0xB; - mixa_boost = 0xF; - } else { - paa_boost = 0x0; - pada_boost = 0x77; - if (freq != 5825) - pgaa_boost = -(freq - 18) / 36 + 168; - else - pgaa_boost = 6; - mixa_boost = 0xF; - } - - cbias = is_pkg_fab_smic ? 0x35 : 0x30; - - for (i = 0; i < 2; i++) { - offset = i ? B2056_TX1 : B2056_TX0; - - b43_radio_write(dev, - offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost); - b43_radio_write(dev, - offset | B2056_TX_PADA_BOOST_TUNE, pada_boost); - b43_radio_write(dev, - offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost); - b43_radio_write(dev, - offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost); - b43_radio_write(dev, - offset | B2056_TX_TXSPARE1, 0x30); - b43_radio_write(dev, - offset | B2056_TX_PA_SPARE2, 0xee); - b43_radio_write(dev, - offset | B2056_TX_PADA_CASCBIAS, 0x03); - b43_radio_write(dev, - offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); - b43_radio_write(dev, - offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); - b43_radio_write(dev, - offset | B2056_TX_INTPAA_CASCBIAS, cbias); - } - } - - udelay(50); - /* VCO calibration */ - b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); - b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); - b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); - b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); - b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); - udelay(300); -} - -static u8 b43_radio_2056_rcal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 mast2, tmp; - - if (phy->rev != 3) - return 0; - - mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); - b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); - - udelay(10); - b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); - udelay(10); - b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); - - if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, - 1000000)) { - b43err(dev->wl, "Radio recalibration timeout\n"); - return 0; - } - - b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); - tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); - b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); - - b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); - - return tmp & 0x1f; -} - -static void b43_radio_init2056_pre(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_CHIP0PU); - /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_OEPORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_OEPORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_CHIP0PU); -} - -static void b43_radio_init2056_post(struct b43_wldev *dev) -{ - b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); - b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); - b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); - msleep(1); - b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); - b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); - b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); - if (dev->phy.do_full_init) - b43_radio_2056_rcal(dev); -} - -/* - * Initialize a Broadcom 2056 N-radio - * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init - */ -static void b43_radio_init2056(struct b43_wldev *dev) -{ - b43_radio_init2056_pre(dev); - b2056_upload_inittabs(dev, 0, 0); - b43_radio_init2056_post(dev); -} - -/************************************************** - * Radio 0x2055 - **************************************************/ - -static void b43_chantab_radio_upload(struct b43_wldev *dev, - const struct b43_nphy_channeltab_entry_rev2 *e) -{ - b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); - b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); - b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); - b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - - b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); - b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); - b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); - b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - - b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); - b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); - b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); - b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - - b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); - b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); - b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); - b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - - b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); - b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); - b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); - b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - - b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); - b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ -static void b43_radio_2055_setup(struct b43_wldev *dev, - const struct b43_nphy_channeltab_entry_rev2 *e) -{ - B43_WARN_ON(dev->phy.rev >= 3); - - b43_chantab_radio_upload(dev, e); - udelay(50); - b43_radio_write(dev, B2055_VCO_CAL10, 0x05); - b43_radio_write(dev, B2055_VCO_CAL10, 0x45); - b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ - b43_radio_write(dev, B2055_VCO_CAL10, 0x65); - udelay(300); -} - -static void b43_radio_init2055_pre(struct b43_wldev *dev) -{ - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_PORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_CHIP0PU | - B43_NPHY_RFCTL_CMD_OEPORFORCE); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_PORFORCE); -} - -static void b43_radio_init2055_post(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - bool workaround = false; - - if (sprom->revision < 4) - workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM - && dev->dev->board_type == SSB_BOARD_CB2_4321 - && dev->dev->board_rev >= 0x41); - else - workaround = - !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS); - - b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); - if (workaround) { - b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); - b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); - } - b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); - b43_radio_write(dev, B2055_CAL_MISC, 0x3C); - b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); - b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); - b43_radio_set(dev, B2055_CAL_MISC, 0x1); - msleep(1); - b43_radio_set(dev, B2055_CAL_MISC, 0x40); - if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) - b43err(dev->wl, "radio post init timeout\n"); - b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); - b43_switch_channel(dev, dev->phy.channel); - b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); - b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); - b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); - b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); - b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); - b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); - if (!nphy->gain_boost) { - b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); - b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); - } else { - b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); - b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); - } - udelay(2); -} - -/* - * Initialize a Broadcom 2055 N-radio - * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init - */ -static void b43_radio_init2055(struct b43_wldev *dev) -{ - b43_radio_init2055_pre(dev); - if (b43_status(dev) < B43_STAT_INITIALIZED) { - /* Follow wl, not specs. Do not force uploading all regs */ - b2055_upload_inittab(dev, 0, 0); - } else { - bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ; - b2055_upload_inittab(dev, ghz5, 0); - } - b43_radio_init2055_post(dev); -} - -/************************************************** - * Samples - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ -static int b43_nphy_load_samples(struct b43_wldev *dev, - struct b43_c32 *samples, u16 len) { - struct b43_phy_n *nphy = dev->phy.n; - u16 i; - u32 *data; - - data = kzalloc(len * sizeof(u32), GFP_KERNEL); - if (!data) { - b43err(dev->wl, "allocation for samples loading failed\n"); - return -ENOMEM; - } - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - for (i = 0; i < len; i++) { - data[i] = (samples[i].i & 0x3FF << 10); - data[i] |= samples[i].q & 0x3FF; - } - b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); - - kfree(data); - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); - return 0; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ -static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, - bool test) -{ - int i; - u16 bw, len, rot, angle; - struct b43_c32 *samples; - - bw = b43_is_40mhz(dev) ? 40 : 20; - len = bw << 3; - - if (test) { - if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) - bw = 82; - else - bw = 80; - - if (b43_is_40mhz(dev)) - bw <<= 1; - - len = bw << 1; - } - - samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL); - if (!samples) { - b43err(dev->wl, "allocation for samples generation failed\n"); - return 0; - } - rot = (((freq * 36) / bw) << 16) / 100; - angle = 0; - - for (i = 0; i < len; i++) { - samples[i] = b43_cordic(angle); - angle += rot; - samples[i].q = CORDIC_CONVERT(samples[i].q * max); - samples[i].i = CORDIC_CONVERT(samples[i].i * max); - } - - i = b43_nphy_load_samples(dev, samples, len); - kfree(samples); - return (i < 0) ? 0 : len; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ -static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, - u16 wait, bool iqmode, bool dac_test, - bool modify_bbmult) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - int i; - u16 seq_mode; - u32 tmp; - - b43_nphy_stay_in_carrier_search(dev, true); - - if (phy->rev >= 7) { - bool lpf_bw3, lpf_bw4; - - lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; - lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; - - if (lpf_bw3 || lpf_bw4) { - /* TODO */ - } else { - u16 value = b43_nphy_read_lpf_ctl(dev, 0); - if (phy->rev >= 19) - b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, - 0, false, 1); - else - b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, - 0, false, 1); - nphy->lpf_bw_overrode_for_sample_play = true; - } - } - - if ((nphy->bb_mult_save & 0x80000000) == 0) { - tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); - nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; - } - - if (modify_bbmult) { - tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; - b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); - } - - b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); - - if (loops != 0xFFFF) - b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); - else - b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); - - b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); - - seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); - - b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); - if (iqmode) { - b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); - b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); - } else { - tmp = dac_test ? 5 : 1; - b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); - } - for (i = 0; i < 100; i++) { - if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { - i = 0; - break; - } - udelay(10); - } - if (i) - b43err(dev->wl, "run samples timeout\n"); - - b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); - - b43_nphy_stay_in_carrier_search(dev, false); -} - -/************************************************** - * RSSI - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ -static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, - s8 offset, u8 core, - enum n_rail_type rail, - enum n_rssi_type rssi_type) -{ - u16 tmp; - bool core1or5 = (core == 1) || (core == 5); - bool core2or5 = (core == 2) || (core == 5); - - offset = clamp_val(offset, -32, 31); - tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); - - switch (rssi_type) { - case N_RSSI_NB: - if (core1or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); - if (core1or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); - if (core2or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); - if (core2or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); - break; - case N_RSSI_W1: - if (core1or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); - if (core1or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); - if (core2or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); - if (core2or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); - break; - case N_RSSI_W2: - if (core1or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); - if (core1or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); - if (core2or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); - if (core2or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); - break; - case N_RSSI_TBD: - if (core1or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); - if (core1or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); - if (core2or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); - if (core2or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); - break; - case N_RSSI_IQ: - if (core1or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); - if (core1or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); - if (core2or5 && rail == N_RAIL_I) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); - if (core2or5 && rail == N_RAIL_Q) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); - break; - case N_RSSI_TSSI_2G: - if (core1or5) - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); - if (core2or5) - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); - break; - case N_RSSI_TSSI_5G: - if (core1or5) - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); - if (core2or5) - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); - break; - } -} - -static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, - enum n_rssi_type rssi_type) -{ - /* TODO */ -} - -static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, - enum n_rssi_type rssi_type) -{ - u8 i; - u16 reg, val; - - if (code == 0) { - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); - b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); - b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); - b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); - b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); - b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); - b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); - } else { - for (i = 0; i < 2; i++) { - if ((code == 1 && i == 1) || (code == 2 && !i)) - continue; - - reg = (i == 0) ? - B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; - b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); - - if (rssi_type == N_RSSI_W1 || - rssi_type == N_RSSI_W2 || - rssi_type == N_RSSI_NB) { - reg = (i == 0) ? - B43_NPHY_AFECTL_C1 : - B43_NPHY_AFECTL_C2; - b43_phy_maskset(dev, reg, 0xFCFF, 0); - - reg = (i == 0) ? - B43_NPHY_RFCTL_LUT_TRSW_UP1 : - B43_NPHY_RFCTL_LUT_TRSW_UP2; - b43_phy_maskset(dev, reg, 0xFFC3, 0); - - if (rssi_type == N_RSSI_W1) - val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; - else if (rssi_type == N_RSSI_W2) - val = 16; - else - val = 32; - b43_phy_set(dev, reg, val); - - reg = (i == 0) ? - B43_NPHY_TXF_40CO_B1S0 : - B43_NPHY_TXF_40CO_B32S1; - b43_phy_set(dev, reg, 0x0020); - } else { - if (rssi_type == N_RSSI_TBD) - val = 0x0100; - else if (rssi_type == N_RSSI_IQ) - val = 0x0200; - else - val = 0x0300; - - reg = (i == 0) ? - B43_NPHY_AFECTL_C1 : - B43_NPHY_AFECTL_C2; - - b43_phy_maskset(dev, reg, 0xFCFF, val); - b43_phy_maskset(dev, reg, 0xF3FF, val << 2); - - if (rssi_type != N_RSSI_IQ && - rssi_type != N_RSSI_TBD) { - enum ieee80211_band band = - b43_current_band(dev->wl); - - if (dev->phy.rev < 7) { - if (b43_nphy_ipa(dev)) - val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; - else - val = 0x11; - reg = (i == 0) ? B2056_TX0 : B2056_TX1; - reg |= B2056_TX_TX_SSI_MUX; - b43_radio_write(dev, reg, val); - } - - reg = (i == 0) ? - B43_NPHY_AFECTL_OVER1 : - B43_NPHY_AFECTL_OVER; - b43_phy_set(dev, reg, 0x0200); - } - } - } - } -} - -static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, - enum n_rssi_type rssi_type) -{ - u16 val; - bool rssi_w1_w2_nb = false; - - switch (rssi_type) { - case N_RSSI_W1: - case N_RSSI_W2: - case N_RSSI_NB: - val = 0; - rssi_w1_w2_nb = true; - break; - case N_RSSI_TBD: - val = 1; - break; - case N_RSSI_IQ: - val = 2; - break; - default: - val = 3; - } - - val = (val << 12) | (val << 14); - b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); - b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); - - if (rssi_w1_w2_nb) { - b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, - (rssi_type + 1) << 4); - b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, - (rssi_type + 1) << 4); - } - - if (code == 0) { - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); - if (rssi_w1_w2_nb) { - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~(B43_NPHY_RFCTL_CMD_RXEN | - B43_NPHY_RFCTL_CMD_CORESEL)); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, - ~(0x1 << 12 | - 0x1 << 5 | - 0x1 << 1 | - 0x1)); - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_START); - udelay(20); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); - } - } else { - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); - if (rssi_w1_w2_nb) { - b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, - ~(B43_NPHY_RFCTL_CMD_RXEN | - B43_NPHY_RFCTL_CMD_CORESEL), - (B43_NPHY_RFCTL_CMD_RXEN | - code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT)); - b43_phy_set(dev, B43_NPHY_RFCTL_OVER, - (0x1 << 12 | - 0x1 << 5 | - 0x1 << 1 | - 0x1)); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_CMD_START); - udelay(20); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ -static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, - enum n_rssi_type type) -{ - if (dev->phy.rev >= 19) - b43_nphy_rssi_select_rev19(dev, code, type); - else if (dev->phy.rev >= 3) - b43_nphy_rev3_rssi_select(dev, code, type); - else - b43_nphy_rev2_rssi_select(dev, code, type); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ -static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, - enum n_rssi_type rssi_type, u8 *buf) -{ - int i; - for (i = 0; i < 2; i++) { - if (rssi_type == N_RSSI_NB) { - if (i == 0) { - b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, - 0xFC, buf[0]); - b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, - 0xFC, buf[1]); - } else { - b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, - 0xFC, buf[2 * i]); - b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, - 0xFC, buf[2 * i + 1]); - } - } else { - if (i == 0) - b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, - 0xF3, buf[0] << 2); - else - b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, - 0xF3, buf[2 * i + 1] << 2); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ -static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, - s32 *buf, u8 nsamp) -{ - int i; - int out; - u16 save_regs_phy[9]; - u16 s[2]; - - /* TODO: rev7+ is treated like rev3+, what about rev19+? */ - - if (dev->phy.rev >= 3) { - save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); - save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); - save_regs_phy[2] = b43_phy_read(dev, - B43_NPHY_RFCTL_LUT_TRSW_UP1); - save_regs_phy[3] = b43_phy_read(dev, - B43_NPHY_RFCTL_LUT_TRSW_UP2); - save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); - save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); - save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); - save_regs_phy[8] = 0; - } else { - save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); - save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); - save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); - save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); - save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); - save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); - save_regs_phy[7] = 0; - save_regs_phy[8] = 0; - } - - b43_nphy_rssi_select(dev, 5, rssi_type); - - if (dev->phy.rev < 2) { - save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); - b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); - } - - for (i = 0; i < 4; i++) - buf[i] = 0; - - for (i = 0; i < nsamp; i++) { - if (dev->phy.rev < 2) { - s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); - s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); - } else { - s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); - s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); - } - - buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; - buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; - buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; - buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; - } - out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | - (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); - - if (dev->phy.rev < 2) - b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); - - if (dev->phy.rev >= 3) { - b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); - b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, - save_regs_phy[2]); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, - save_regs_phy[3]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); - b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); - b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); - } else { - b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); - b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); - b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); - b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); - b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); - b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); - } - - return out; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ -static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - - u16 saved_regs_phy_rfctl[2]; - u16 saved_regs_phy[22]; - u16 regs_to_store_rev3[] = { - B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, - B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, - B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, - B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, - B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, - B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 - }; - u16 regs_to_store_rev7[] = { - B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, - B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, - B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, - B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, - B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, - 0x2ff, - B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, - B43_NPHY_RFCTL_CMD, - B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, - B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, - B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, - B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 - }; - u16 *regs_to_store; - int regs_amount; - - u16 class; - - u16 clip_state[2]; - u16 clip_off[2] = { 0xFFFF, 0xFFFF }; - - u8 vcm_final = 0; - s32 offset[4]; - s32 results[8][4] = { }; - s32 results_min[4] = { }; - s32 poll_results[4] = { }; - - u16 *rssical_radio_regs = NULL; - u16 *rssical_phy_regs = NULL; - - u16 r; /* routing */ - u8 rx_core_state; - int core, i, j, vcm; - - if (dev->phy.rev >= 7) { - regs_to_store = regs_to_store_rev7; - regs_amount = ARRAY_SIZE(regs_to_store_rev7); - } else { - regs_to_store = regs_to_store_rev3; - regs_amount = ARRAY_SIZE(regs_to_store_rev3); - } - BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy)); - - class = b43_nphy_classifier(dev, 0, 0); - b43_nphy_classifier(dev, 7, 4); - b43_nphy_read_clip_detection(dev, clip_state); - b43_nphy_write_clip_detection(dev, clip_off); - - saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); - saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); - for (i = 0; i < regs_amount; i++) - saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); - - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); - - if (dev->phy.rev >= 7) { - b43_nphy_rf_ctl_override_one_to_many(dev, - N_RF_CTL_OVER_CMD_RXRF_PU, - 0, 0, false); - b43_nphy_rf_ctl_override_one_to_many(dev, - N_RF_CTL_OVER_CMD_RX_PU, - 1, 0, false); - b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); - b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, - 0); - b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, - 0); - } else { - b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, - 0); - b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, - 0); - } - } else { - b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); - b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); - b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); - b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); - b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); - } else { - b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); - b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); - } - } - - rx_core_state = b43_nphy_get_rx_core_state(dev); - for (core = 0; core < 2; core++) { - if (!(rx_core_state & (1 << core))) - continue; - r = core ? B2056_RX1 : B2056_RX0; - b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, - N_RSSI_NB); - b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, - N_RSSI_NB); - - /* Grab RSSI results for every possible VCM */ - for (vcm = 0; vcm < 8; vcm++) { - if (dev->phy.rev >= 7) - b43_radio_maskset(dev, - core ? R2057_NB_MASTER_CORE1 : - R2057_NB_MASTER_CORE0, - ~R2057_VCM_MASK, vcm); - else - b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, - 0xE3, vcm << 2); - b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); - } - - /* Find out which VCM got the best results */ - for (i = 0; i < 4; i += 2) { - s32 currd; - s32 mind = 0x100000; - s32 minpoll = 249; - u8 minvcm = 0; - if (2 * core != i) - continue; - for (vcm = 0; vcm < 8; vcm++) { - currd = results[vcm][i] * results[vcm][i] + - results[vcm][i + 1] * results[vcm][i]; - if (currd < mind) { - mind = currd; - minvcm = vcm; - } - if (results[vcm][i] < minpoll) - minpoll = results[vcm][i]; - } - vcm_final = minvcm; - results_min[i] = minpoll; - } - - /* Select the best VCM */ - if (dev->phy.rev >= 7) - b43_radio_maskset(dev, - core ? R2057_NB_MASTER_CORE1 : - R2057_NB_MASTER_CORE0, - ~R2057_VCM_MASK, vcm); - else - b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, - 0xE3, vcm_final << 2); - - for (i = 0; i < 4; i++) { - if (core != i / 2) - continue; - offset[i] = -results[vcm_final][i]; - if (offset[i] < 0) - offset[i] = -((abs(offset[i]) + 4) / 8); - else - offset[i] = (offset[i] + 4) / 8; - if (results_min[i] == 248) - offset[i] = -32; - b43_nphy_scale_offset_rssi(dev, 0, offset[i], - (i / 2 == 0) ? 1 : 2, - (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, - N_RSSI_NB); - } - } - - for (core = 0; core < 2; core++) { - if (!(rx_core_state & (1 << core))) - continue; - for (i = 0; i < 2; i++) { - b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, - N_RAIL_I, i); - b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, - N_RAIL_Q, i); - b43_nphy_poll_rssi(dev, i, poll_results, 8); - for (j = 0; j < 4; j++) { - if (j / 2 == core) { - offset[j] = 232 - poll_results[j]; - if (offset[j] < 0) - offset[j] = -(abs(offset[j] + 4) / 8); - else - offset[j] = (offset[j] + 4) / 8; - b43_nphy_scale_offset_rssi(dev, 0, - offset[2 * core], core + 1, j % 2, i); - } - } - } - } - - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); - - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - - b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); - b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); - - b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); - b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); - b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); - - for (i = 0; i < regs_amount; i++) - b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); - - /* Store for future configuration */ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; - rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; - } else { - rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; - rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; - } - if (dev->phy.rev >= 7) { - rssical_radio_regs[0] = b43_radio_read(dev, - R2057_NB_MASTER_CORE0); - rssical_radio_regs[1] = b43_radio_read(dev, - R2057_NB_MASTER_CORE1); - } else { - rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | - B2056_RX_RSSI_MISC); - rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | - B2056_RX_RSSI_MISC); - } - rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); - rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); - rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); - rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); - rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); - rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); - rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); - rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); - rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); - rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); - rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); - rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); - - /* Remember for which channel we store configuration */ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq; - else - nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq; - - /* End of calibration, restore configuration */ - b43_nphy_classifier(dev, 7, class); - b43_nphy_write_clip_detection(dev, clip_state); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ -static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) -{ - int i, j, vcm; - u8 state[4]; - u8 code, val; - u16 class, override; - u8 regs_save_radio[2]; - u16 regs_save_phy[2]; - - s32 offset[4]; - u8 core; - u8 rail; - - u16 clip_state[2]; - u16 clip_off[2] = { 0xFFFF, 0xFFFF }; - s32 results_min[4] = { }; - u8 vcm_final[4] = { }; - s32 results[4][4] = { }; - s32 miniq[4][2] = { }; - - if (type == N_RSSI_NB) { - code = 0; - val = 6; - } else if (type == N_RSSI_W1 || type == N_RSSI_W2) { - code = 25; - val = 4; - } else { - B43_WARN_ON(1); - return; - } - - class = b43_nphy_classifier(dev, 0, 0); - b43_nphy_classifier(dev, 7, 4); - b43_nphy_read_clip_detection(dev, clip_state); - b43_nphy_write_clip_detection(dev, clip_off); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - override = 0x140; - else - override = 0x110; - - regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); - regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); - b43_radio_write(dev, B2055_C1_PD_RXTX, val); - - regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); - regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); - b43_radio_write(dev, B2055_C2_PD_RXTX, val); - - state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; - state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; - b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); - b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); - state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; - state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; - - b43_nphy_rssi_select(dev, 5, type); - b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); - b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); - - for (vcm = 0; vcm < 4; vcm++) { - u8 tmp[4]; - for (j = 0; j < 4; j++) - tmp[j] = vcm; - if (type != N_RSSI_W2) - b43_nphy_set_rssi_2055_vcm(dev, type, tmp); - b43_nphy_poll_rssi(dev, type, results[vcm], 8); - if (type == N_RSSI_W1 || type == N_RSSI_W2) - for (j = 0; j < 2; j++) - miniq[vcm][j] = min(results[vcm][2 * j], - results[vcm][2 * j + 1]); - } - - for (i = 0; i < 4; i++) { - s32 mind = 0x100000; - u8 minvcm = 0; - s32 minpoll = 249; - s32 currd; - for (vcm = 0; vcm < 4; vcm++) { - if (type == N_RSSI_NB) - currd = abs(results[vcm][i] - code * 8); - else - currd = abs(miniq[vcm][i / 2] - code * 8); - - if (currd < mind) { - mind = currd; - minvcm = vcm; - } - - if (results[vcm][i] < minpoll) - minpoll = results[vcm][i]; - } - results_min[i] = minpoll; - vcm_final[i] = minvcm; - } - - if (type != N_RSSI_W2) - b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); - - for (i = 0; i < 4; i++) { - offset[i] = (code * 8) - results[vcm_final[i]][i]; - - if (offset[i] < 0) - offset[i] = -((abs(offset[i]) + 4) / 8); - else - offset[i] = (offset[i] + 4) / 8; - - if (results_min[i] == 248) - offset[i] = code - 32; - - core = (i / 2) ? 2 : 1; - rail = (i % 2) ? N_RAIL_Q : N_RAIL_I; - - b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, - type); - } - - b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); - b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); - - switch (state[2]) { - case 1: - b43_nphy_rssi_select(dev, 1, N_RSSI_NB); - break; - case 4: - b43_nphy_rssi_select(dev, 1, N_RSSI_W1); - break; - case 2: - b43_nphy_rssi_select(dev, 1, N_RSSI_W2); - break; - default: - b43_nphy_rssi_select(dev, 1, N_RSSI_W2); - break; - } - - switch (state[3]) { - case 1: - b43_nphy_rssi_select(dev, 2, N_RSSI_NB); - break; - case 4: - b43_nphy_rssi_select(dev, 2, N_RSSI_W1); - break; - default: - b43_nphy_rssi_select(dev, 2, N_RSSI_W2); - break; - } - - b43_nphy_rssi_select(dev, 0, type); - - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); - b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); - b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); - - b43_nphy_classifier(dev, 7, class); - b43_nphy_write_clip_detection(dev, clip_state); - /* Specs don't say about reset here, but it makes wl and b43 dumps - identical, it really seems wl performs this */ - b43_nphy_reset_cca(dev); -} - -/* - * RSSI Calibration - * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal - */ -static void b43_nphy_rssi_cal(struct b43_wldev *dev) -{ - if (dev->phy.rev >= 19) { - /* TODO */ - } else if (dev->phy.rev >= 3) { - b43_nphy_rev3_rssi_cal(dev); - } else { - b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); - b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); - b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); - } -} - -/************************************************** - * Workarounds - **************************************************/ - -static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) -{ - /* TODO */ -} - -static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - switch (phy->rev) { - /* TODO */ - } -} - -static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - bool ghz5; - bool ext_lna; - u16 rssi_gain; - struct nphy_gain_ctl_workaround_entry *e; - u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; - u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; - - /* Prepare values */ - ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) - & B43_NPHY_BANDCTL_5GHZ; - ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ : - sprom->boardflags_lo & B43_BFL_EXTLNA; - e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); - if (ghz5 && dev->phy.rev >= 5) - rssi_gain = 0x90; - else - rssi_gain = 0x50; - - b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); - - /* Set Clip 2 detect */ - b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); - b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); - - b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, - 0x17); - b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, - 0x17); - b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); - b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); - b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); - b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); - b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, - rssi_gain); - b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, - rssi_gain); - b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, - 0x17); - b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, - 0x17); - b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); - b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); - - b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); - b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); - b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); - b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); - b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); - b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); - b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); - - b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); - b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); - - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, - e->rfseq_init); - - b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); - b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); - b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); - b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); - b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); - b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); - - b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); - b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); - b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); - b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); - b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); - b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, - ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip); - b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, - ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip); - b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); -} - -static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u8 i, j; - u8 code; - u16 tmp; - u8 rfseq_events[3] = { 6, 8, 7 }; - u8 rfseq_delays[3] = { 10, 30, 1 }; - - /* Set Clip 2 detect */ - b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); - b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); - - /* Set narrowband clip threshold */ - b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); - b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); - - if (!b43_is_40mhz(dev)) { - /* Set dwell lengths */ - b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); - b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); - b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); - b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); - } - - /* Set wideband clip 2 threshold */ - b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, - ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21); - b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, - ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21); - - if (!b43_is_40mhz(dev)) { - b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, - ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); - b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, - ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); - b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, - ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); - b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, - ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); - } - - b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); - - if (nphy->gain_boost) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && - b43_is_40mhz(dev)) - code = 4; - else - code = 5; - } else { - code = b43_is_40mhz(dev) ? 6 : 7; - } - - /* Set HPVGA2 index */ - b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, - code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); - b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, - code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); - /* specs say about 2 loops, but wl does 4 */ - for (i = 0; i < 4; i++) - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); - - b43_nphy_adjust_lna_gain_table(dev); - - if (nphy->elna_gain_config) { - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); - /* specs say about 2 loops, but wl does 4 */ - for (i = 0; i < 4; i++) - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, - (code << 8 | 0x74)); - } - - if (dev->phy.rev == 2) { - for (i = 0; i < 4; i++) { - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, - (0x0400 * i) + 0x0020); - for (j = 0; j < 21; j++) { - tmp = j * (i < 2 ? 3 : 1); - b43_phy_write(dev, - B43_NPHY_TABLE_DATALO, tmp); - } - } - } - - b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); - b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, - ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, - 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ -static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) -{ - if (dev->phy.rev >= 19) - b43_nphy_gain_ctl_workarounds_rev19(dev); - else if (dev->phy.rev >= 7) - b43_nphy_gain_ctl_workarounds_rev7(dev); - else if (dev->phy.rev >= 3) - b43_nphy_gain_ctl_workarounds_rev3(dev); - else - b43_nphy_gain_ctl_workarounds_rev1_2(dev); -} - -static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - - /* TX to RX */ - u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, }; - u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, }; - /* RX to TX */ - u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, - 0x1F }; - u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; - - static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; - u8 ntab7_138_146[] = { 0x11, 0x11 }; - u8 ntab7_133[] = { 0x77, 0x11, 0x11 }; - - u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2]; - u16 bcap_val; - s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2]; - u16 scap_val; - s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2]; - bool rccal_ovrd = false; - - u16 bias, conv, filt; - - u32 noise_tbl[2]; - - u32 tmp32; - u8 core; - - b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); - b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); - b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); - b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); - b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); - b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); - - if (phy->rev == 7) { - b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); - b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); - } - - if (phy->rev >= 16) { - b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); - b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); - } else if (phy->rev <= 8) { - b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); - b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); - } - - if (phy->rev >= 16) - b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); - else if (phy->rev >= 8) - b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); - - b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); - b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); - tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); - tmp32 &= 0xffffff; - b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); - - b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, - ARRAY_SIZE(tx2rx_events)); - if (b43_nphy_ipa(dev)) - b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, - rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); - - b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); - b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); - - for (core = 0; core < 2; core++) { - lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); - lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); - lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); - } - - bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); - scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); - - if (b43_nphy_ipa(dev)) { - bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ; - - switch (phy->radio_rev) { - case 5: - /* Check radio version (to be 0) by PHY rev for now */ - if (phy->rev == 8 && b43_is_40mhz(dev)) { - for (core = 0; core < 2; core++) { - scap_val_11b[core] = scap_val; - bcap_val_11b[core] = bcap_val; - scap_val_11n_20[core] = scap_val; - bcap_val_11n_20[core] = bcap_val; - scap_val_11n_40[core] = 0xc; - bcap_val_11n_40[core] = 0xc; - } - - rccal_ovrd = true; - } - if (phy->rev == 9) { - /* TODO: Radio version 1 (e.g. BCM5357B0) */ - } - break; - case 7: - case 8: - for (core = 0; core < 2; core++) { - scap_val_11b[core] = scap_val; - bcap_val_11b[core] = bcap_val; - lpf_ofdm_20mhz[core] = 4; - lpf_11b[core] = 1; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - scap_val_11n_20[core] = 0xc; - bcap_val_11n_20[core] = 0xc; - scap_val_11n_40[core] = 0xa; - bcap_val_11n_40[core] = 0xa; - } else { - scap_val_11n_20[core] = 0x14; - bcap_val_11n_20[core] = 0x14; - scap_val_11n_40[core] = 0xf; - bcap_val_11n_40[core] = 0xf; - } - } - - rccal_ovrd = true; - break; - case 9: - for (core = 0; core < 2; core++) { - bcap_val_11b[core] = bcap_val; - scap_val_11b[core] = scap_val; - lpf_11b[core] = 1; - - if (ghz2) { - bcap_val_11n_20[core] = bcap_val + 13; - scap_val_11n_20[core] = scap_val + 15; - } else { - bcap_val_11n_20[core] = bcap_val + 14; - scap_val_11n_20[core] = scap_val + 15; - } - lpf_ofdm_20mhz[core] = 4; - - if (ghz2) { - bcap_val_11n_40[core] = bcap_val - 7; - scap_val_11n_40[core] = scap_val - 5; - } else { - bcap_val_11n_40[core] = bcap_val + 2; - scap_val_11n_40[core] = scap_val + 4; - } - lpf_ofdm_40mhz[core] = 4; - } - - rccal_ovrd = true; - break; - case 14: - for (core = 0; core < 2; core++) { - bcap_val_11b[core] = bcap_val; - scap_val_11b[core] = scap_val; - lpf_11b[core] = 1; - } - - bcap_val_11n_20[0] = bcap_val + 20; - scap_val_11n_20[0] = scap_val + 20; - lpf_ofdm_20mhz[0] = 3; - - bcap_val_11n_20[1] = bcap_val + 16; - scap_val_11n_20[1] = scap_val + 16; - lpf_ofdm_20mhz[1] = 3; - - bcap_val_11n_40[0] = bcap_val + 20; - scap_val_11n_40[0] = scap_val + 20; - lpf_ofdm_40mhz[0] = 4; - - bcap_val_11n_40[1] = bcap_val + 10; - scap_val_11n_40[1] = scap_val + 10; - lpf_ofdm_40mhz[1] = 4; - - rccal_ovrd = true; - break; - } - } else { - if (phy->radio_rev == 5) { - for (core = 0; core < 2; core++) { - lpf_ofdm_20mhz[core] = 1; - lpf_ofdm_40mhz[core] = 3; - scap_val_11b[core] = scap_val; - bcap_val_11b[core] = bcap_val; - scap_val_11n_20[core] = 0x11; - scap_val_11n_40[core] = 0x11; - bcap_val_11n_20[core] = 0x13; - bcap_val_11n_40[core] = 0x13; - } - - rccal_ovrd = true; - } - } - if (rccal_ovrd) { - u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2]; - u8 rx2tx_lut_extra = 1; - - for (core = 0; core < 2; core++) { - bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f); - scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f); - bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f); - scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f); - bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f); - scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f); - - rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) | - (bcap_val_11b[core] << 8) | - (scap_val_11b[core] << 3) | - lpf_11b[core]; - rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) | - (bcap_val_11n_20[core] << 8) | - (scap_val_11n_20[core] << 3) | - lpf_ofdm_20mhz[core]; - rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) | - (bcap_val_11n_40[core] << 8) | - (scap_val_11n_40[core] << 3) | - lpf_ofdm_40mhz[core]; - } - - for (core = 0; core < 2; core++) { - b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), - rx2tx_lut_20_11b[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), - rx2tx_lut_20_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), - rx2tx_lut_20_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), - rx2tx_lut_40_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), - rx2tx_lut_40_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), - rx2tx_lut_40_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), - rx2tx_lut_40_11n[core]); - b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), - rx2tx_lut_40_11n[core]); - } - } - - b43_phy_write(dev, 0x32F, 0x3); - - if (phy->radio_rev == 4 || phy->radio_rev == 6) - b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); - - if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { - if (sprom->revision && - sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) { - b43_radio_write(dev, 0x5, 0x05); - b43_radio_write(dev, 0x6, 0x30); - b43_radio_write(dev, 0x7, 0x00); - b43_radio_set(dev, 0x4f, 0x1); - b43_radio_set(dev, 0xd4, 0x1); - bias = 0x1f; - conv = 0x6f; - filt = 0xaa; - } else { - bias = 0x2b; - conv = 0x7f; - filt = 0xee; - } - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - for (core = 0; core < 2; core++) { - if (core == 0) { - b43_radio_write(dev, 0x5F, bias); - b43_radio_write(dev, 0x64, conv); - b43_radio_write(dev, 0x66, filt); - } else { - b43_radio_write(dev, 0xE8, bias); - b43_radio_write(dev, 0xE9, conv); - b43_radio_write(dev, 0xEB, filt); - } - } - } - } - - if (b43_nphy_ipa(dev)) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (phy->radio_rev == 3 || phy->radio_rev == 4 || - phy->radio_rev == 6) { - for (core = 0; core < 2; core++) { - if (core == 0) - b43_radio_write(dev, 0x51, - 0x7f); - else - b43_radio_write(dev, 0xd6, - 0x7f); - } - } - switch (phy->radio_rev) { - case 3: - for (core = 0; core < 2; core++) { - if (core == 0) { - b43_radio_write(dev, 0x64, - 0x13); - b43_radio_write(dev, 0x5F, - 0x1F); - b43_radio_write(dev, 0x66, - 0xEE); - b43_radio_write(dev, 0x59, - 0x8A); - b43_radio_write(dev, 0x80, - 0x3E); - } else { - b43_radio_write(dev, 0x69, - 0x13); - b43_radio_write(dev, 0xE8, - 0x1F); - b43_radio_write(dev, 0xEB, - 0xEE); - b43_radio_write(dev, 0xDE, - 0x8A); - b43_radio_write(dev, 0x105, - 0x3E); - } - } - break; - case 7: - case 8: - if (!b43_is_40mhz(dev)) { - b43_radio_write(dev, 0x5F, 0x14); - b43_radio_write(dev, 0xE8, 0x12); - } else { - b43_radio_write(dev, 0x5F, 0x16); - b43_radio_write(dev, 0xE8, 0x16); - } - break; - case 14: - for (core = 0; core < 2; core++) { - int o = core ? 0x85 : 0; - - b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); - b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); - b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); - b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); - b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); - b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); - b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); - b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); - } - break; - } - } else { - u16 freq = phy->chandef->chan->center_freq; - if ((freq >= 5180 && freq <= 5230) || - (freq >= 5745 && freq <= 5805)) { - b43_radio_write(dev, 0x7D, 0xFF); - b43_radio_write(dev, 0xFE, 0xFF); - } - } - } else { - if (phy->radio_rev != 5) { - for (core = 0; core < 2; core++) { - if (core == 0) { - b43_radio_write(dev, 0x5c, 0x61); - b43_radio_write(dev, 0x51, 0x70); - } else { - b43_radio_write(dev, 0xe1, 0x61); - b43_radio_write(dev, 0xd6, 0x70); - } - } - } - } - - if (phy->radio_rev == 4) { - b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); - b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); - for (core = 0; core < 2; core++) { - if (core == 0) { - b43_radio_write(dev, 0x1a1, 0x00); - b43_radio_write(dev, 0x1a2, 0x3f); - b43_radio_write(dev, 0x1a6, 0x3f); - } else { - b43_radio_write(dev, 0x1a7, 0x00); - b43_radio_write(dev, 0x1ab, 0x3f); - b43_radio_write(dev, 0x1ac, 0x3f); - } - } - } else { - b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); - b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); - - b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); - b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); - b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); - b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); - - b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); - b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); - } - - b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); - - b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); - b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); - b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); - b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); - b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); - b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); - b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); - - b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); - noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; - b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); - - b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); - noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; - b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); - - b43_nphy_gain_ctl_workarounds(dev); - - /* TODO - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, - aux_adc_vmid_rev7_core0); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, - aux_adc_vmid_rev7_core1); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4, - aux_adc_gain_rev7); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4, - aux_adc_gain_rev7); - */ -} - -static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - /* TX to RX */ - u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; - u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 }; - /* RX to TX */ - u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, - 0x1F }; - u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; - u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; - u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; - - u16 vmids[5][4] = { - { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ - { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ - { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ - { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ - { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ - }; - u16 gains[5][4] = { - { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ - { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ - { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ - { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ - { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ - }; - u16 *vmid, *gain; - - u8 pdet_range; - u16 tmp16; - u32 tmp32; - - b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); - b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); - - tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); - tmp32 &= 0xffffff; - b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); - - b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); - b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); - b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); - b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); - b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); - b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); - - b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); - b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); - - /* TX to RX */ - b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, - ARRAY_SIZE(tx2rx_events)); - - /* RX to TX */ - if (b43_nphy_ipa(dev)) - b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, - rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); - if (nphy->hw_phyrxchain != 3 && - nphy->hw_phyrxchain != nphy->hw_phytxchain) { - if (b43_nphy_ipa(dev)) { - rx2tx_delays[5] = 59; - rx2tx_delays[6] = 1; - rx2tx_events[7] = 0x1F; - } - b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, - ARRAY_SIZE(rx2tx_events)); - } - - tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? - 0x2 : 0x9C40; - b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); - - b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); - - if (!b43_is_40mhz(dev)) { - b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); - b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); - } else { - b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); - b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); - } - - b43_nphy_gain_ctl_workarounds(dev); - - b43_ntab_write(dev, B43_NTAB16(8, 0), 2); - b43_ntab_write(dev, B43_NTAB16(8, 16), 2); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - pdet_range = sprom->fem.ghz2.pdet_range; - else - pdet_range = sprom->fem.ghz5.pdet_range; - vmid = vmids[min_t(u16, pdet_range, 4)]; - gain = gains[min_t(u16, pdet_range, 4)]; - switch (pdet_range) { - case 3: - if (!(dev->phy.rev >= 4 && - b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) - break; - /* FALL THROUGH */ - case 0: - case 1: - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); - break; - case 2: - if (dev->phy.rev >= 6) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - vmid[3] = 0x94; - else - vmid[3] = 0x8e; - gain[3] = 3; - } else if (dev->phy.rev == 5) { - vmid[3] = 0x84; - gain[3] = 2; - } - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); - break; - case 4: - case 5: - if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) { - if (pdet_range == 4) { - vmid[3] = 0x8e; - tmp16 = 0x96; - gain[3] = 0x2; - } else { - vmid[3] = 0x89; - tmp16 = 0x89; - gain[3] = 0; - } - } else { - if (pdet_range == 4) { - vmid[3] = 0x89; - tmp16 = 0x8b; - gain[3] = 0x2; - } else { - vmid[3] = 0x74; - tmp16 = 0x70; - gain[3] = 0; - } - } - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); - vmid[3] = tmp16; - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); - b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); - break; - } - - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); - b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); - b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); - - /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ - - if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && - b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || - (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && - b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) - tmp32 = 0x00088888; - else - tmp32 = 0x88888888; - b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); - b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); - b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); - - if (dev->phy.rev == 4 && - b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, - 0x70); - b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, - 0x70); - } - - /* Dropped probably-always-true condition */ - b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); - b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); - b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); - b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); - b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); - b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); - b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); - b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); - b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); - b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); - b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); - b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); - - if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) - ; /* TODO: 0x0080000000000000 HF */ -} - -static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - - u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; - u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; - - u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; - u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; - - if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || - dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { - delays1[0] = 0x1; - delays1[5] = 0x14; - } - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && - nphy->band5g_pwrgain) { - b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); - b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); - } else { - b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); - b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); - } - - b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); - b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); - if (dev->phy.rev < 3) { - b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); - b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); - } - - if (dev->phy.rev < 2) { - b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); - b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); - b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); - b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); - b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); - b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); - } - - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); - - b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); - b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); - - b43_nphy_gain_ctl_workarounds(dev); - - if (dev->phy.rev < 2) { - if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) - b43_hf_write(dev, b43_hf_read(dev) | - B43_HF_MLADVW); - } else if (dev->phy.rev == 2) { - b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); - b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); - } - - if (dev->phy.rev < 2) - b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, - ~B43_NPHY_SCRAM_SIGCTL_SCM); - - /* Set phase track alpha and beta */ - b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); - b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); - b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); - b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); - b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); - b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); - - if (dev->phy.rev < 3) { - b43_phy_mask(dev, B43_NPHY_PIL_DW1, - ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); - b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); - b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); - b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); - } - - if (dev->phy.rev == 2) - b43_phy_set(dev, B43_NPHY_FINERX2_CGC, - B43_NPHY_FINERX2_CGC_DECGC); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ -static void b43_nphy_workarounds(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - b43_nphy_classifier(dev, 1, 0); - else - b43_nphy_classifier(dev, 1, 1); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - b43_phy_set(dev, B43_NPHY_IQFLIP, - B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); - - /* TODO: rev19+ */ - if (dev->phy.rev >= 7) - b43_nphy_workarounds_rev7plus(dev); - else if (dev->phy.rev >= 3) - b43_nphy_workarounds_rev3plus(dev); - else - b43_nphy_workarounds_rev1_2(dev); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/************************************************** - * Tx/Rx common - **************************************************/ - -/* - * Transmits a known value for LO calibration - * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone - */ -static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, - bool iqmode, bool dac_test, bool modify_bbmult) -{ - u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); - if (samp == 0) - return -1; - b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, - modify_bbmult); - return 0; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ -static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - bool override = false; - u16 chain = 0x33; - - if (nphy->txrx_chain == 0) { - chain = 0x11; - override = true; - } else if (nphy->txrx_chain == 1) { - chain = 0x22; - override = true; - } - - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, - ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), - chain); - - if (override) - b43_phy_set(dev, B43_NPHY_RFSEQMODE, - B43_NPHY_RFSEQMODE_CAOVER); - else - b43_phy_mask(dev, B43_NPHY_RFSEQMODE, - ~B43_NPHY_RFSEQMODE_CAOVER); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ -static void b43_nphy_stop_playback(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - u16 tmp; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); - if (tmp & 0x1) - b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); - else if (tmp & 0x2) - b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); - - b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); - - if (nphy->bb_mult_save & 0x80000000) { - tmp = nphy->bb_mult_save & 0xFFFF; - b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); - nphy->bb_mult_save = 0; - } - - if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) { - if (phy->rev >= 19) - b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, - 1); - else - b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); - nphy->lpf_bw_overrode_for_sample_play = false; - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ -static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, - struct nphy_txgains target, - struct nphy_iqcal_params *params) -{ - struct b43_phy *phy = &dev->phy; - int i, j, indx; - u16 gain; - - if (dev->phy.rev >= 3) { - params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ - params->txgm = target.txgm[core]; - params->pga = target.pga[core]; - params->pad = target.pad[core]; - params->ipa = target.ipa[core]; - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); - } else { - params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); - } - for (j = 0; j < 5; j++) - params->ncorr[j] = 0x79; - } else { - gain = (target.pad[core]) | (target.pga[core] << 4) | - (target.txgm[core] << 8); - - indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? - 1 : 0; - for (i = 0; i < 9; i++) - if (tbl_iqcal_gainparams[indx][i][0] == gain) - break; - i = min(i, 8); - - params->txgm = tbl_iqcal_gainparams[indx][i][1]; - params->pga = tbl_iqcal_gainparams[indx][i][2]; - params->pad = tbl_iqcal_gainparams[indx][i][3]; - params->cal_gain = (params->txgm << 7) | (params->pga << 4) | - (params->pad << 2); - for (j = 0; j < 4; j++) - params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; - } -} - -/************************************************** - * Tx and Rx - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ -static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - u8 i; - u16 bmask, val, tmp; - enum ieee80211_band band = b43_current_band(dev->wl); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - nphy->txpwrctrl = enable; - if (!enable) { - if (dev->phy.rev >= 3 && - (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & - (B43_NPHY_TXPCTL_CMD_COEFF | - B43_NPHY_TXPCTL_CMD_HWPCTLEN | - B43_NPHY_TXPCTL_CMD_PCTLEN))) { - /* We disable enabled TX pwr ctl, save it's state */ - nphy->tx_pwr_idx[0] = b43_phy_read(dev, - B43_NPHY_C1_TXPCTL_STAT) & 0x7f; - nphy->tx_pwr_idx[1] = b43_phy_read(dev, - B43_NPHY_C2_TXPCTL_STAT) & 0x7f; - } - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); - for (i = 0; i < 84; i++) - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); - for (i = 0; i < 84; i++) - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); - - tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; - if (dev->phy.rev >= 3) - tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN; - b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); - - if (dev->phy.rev >= 3) { - b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); - } else { - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); - } - - if (dev->phy.rev == 2) - b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, - ~B43_NPHY_BPHY_CTL3_SCALE, 0x53); - else if (dev->phy.rev < 2) - b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, - ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); - - if (dev->phy.rev < 2 && b43_is_40mhz(dev)) - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); - } else { - b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, - nphy->adj_pwr_tbl); - b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, - nphy->adj_pwr_tbl); - - bmask = B43_NPHY_TXPCTL_CMD_COEFF | - B43_NPHY_TXPCTL_CMD_HWPCTLEN; - /* wl does useless check for "enable" param here */ - val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; - if (dev->phy.rev >= 3) { - bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN; - if (val) - val |= B43_NPHY_TXPCTL_CMD_PCTLEN; - } - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); - - if (band == IEEE80211_BAND_5GHZ) { - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_INIT, - 0x32); - b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, - ~B43_NPHY_TXPCTL_INIT_PIDXI1, - 0x32); - } else { - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_INIT, - 0x64); - if (phy->rev > 1) - b43_phy_maskset(dev, - B43_NPHY_TXPCTL_INIT, - ~B43_NPHY_TXPCTL_INIT_PIDXI1, - 0x64); - } - } - - if (dev->phy.rev >= 3) { - if (nphy->tx_pwr_idx[0] != 128 && - nphy->tx_pwr_idx[1] != 128) { - /* Recover TX pwr ctl state */ - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_INIT, - nphy->tx_pwr_idx[0]); - if (dev->phy.rev > 1) - b43_phy_maskset(dev, - B43_NPHY_TXPCTL_INIT, - ~0xff, nphy->tx_pwr_idx[1]); - } - } - - if (phy->rev >= 7) { - /* TODO */ - } - - if (dev->phy.rev >= 3) { - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); - } else { - b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); - } - - if (dev->phy.rev == 2) - b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); - else if (dev->phy.rev < 2) - b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); - - if (dev->phy.rev < 2 && b43_is_40mhz(dev)) - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); - - if (b43_nphy_ipa(dev)) { - b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); - b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); - } - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ -static void b43_nphy_tx_power_fix(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - u8 txpi[2], bbmult, i; - u16 tmp, radio_gain, dac_gain; - u16 freq = phy->chandef->chan->center_freq; - u32 txgain; - /* u32 gaintbl; rev3+ */ - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - /* TODO: rev19+ */ - if (dev->phy.rev >= 7) { - txpi[0] = txpi[1] = 30; - } else if (dev->phy.rev >= 3) { - txpi[0] = 40; - txpi[1] = 40; - } else if (sprom->revision < 4) { - txpi[0] = 72; - txpi[1] = 72; - } else { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - txpi[0] = sprom->txpid2g[0]; - txpi[1] = sprom->txpid2g[1]; - } else if (freq >= 4900 && freq < 5100) { - txpi[0] = sprom->txpid5gl[0]; - txpi[1] = sprom->txpid5gl[1]; - } else if (freq >= 5100 && freq < 5500) { - txpi[0] = sprom->txpid5g[0]; - txpi[1] = sprom->txpid5g[1]; - } else if (freq >= 5500) { - txpi[0] = sprom->txpid5gh[0]; - txpi[1] = sprom->txpid5gh[1]; - } else { - txpi[0] = 91; - txpi[1] = 91; - } - } - if (dev->phy.rev < 7 && - (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) - txpi[0] = txpi[1] = 91; - - /* - for (i = 0; i < 2; i++) { - nphy->txpwrindex[i].index_internal = txpi[i]; - nphy->txpwrindex[i].index_internal_save = txpi[i]; - } - */ - - for (i = 0; i < 2; i++) { - const u32 *table = b43_nphy_get_tx_gain_table(dev); - - if (!table) - break; - txgain = *(table + txpi[i]); - - if (dev->phy.rev >= 3) - radio_gain = (txgain >> 16) & 0x1FFFF; - else - radio_gain = (txgain >> 16) & 0x1FFF; - - if (dev->phy.rev >= 7) - dac_gain = (txgain >> 8) & 0x7; - else - dac_gain = (txgain >> 8) & 0x3F; - bbmult = txgain & 0xFF; - - if (dev->phy.rev >= 3) { - if (i == 0) - b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); - else - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); - } else { - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); - } - - if (i == 0) - b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); - else - b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); - - b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); - - tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); - if (i == 0) - tmp = (tmp & 0x00FF) | (bbmult << 8); - else - tmp = (tmp & 0xFF00) | bbmult; - b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); - - if (b43_nphy_ipa(dev)) { - u32 tmp32; - u16 reg = (i == 0) ? - B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; - tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, - 576 + txpi[i])); - b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); - b43_phy_set(dev, reg, 0x4); - } - } - - b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - u8 core; - u16 r; /* routing */ - - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - for (core = 0; core < 2; core++) { - r = core ? 0x190 : 0x170; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, r + 0x5, 0x5); - b43_radio_write(dev, r + 0x9, 0xE); - if (phy->rev != 5) - b43_radio_write(dev, r + 0xA, 0); - if (phy->rev != 7) - b43_radio_write(dev, r + 0xB, 1); - else - b43_radio_write(dev, r + 0xB, 0x31); - } else { - b43_radio_write(dev, r + 0x5, 0x9); - b43_radio_write(dev, r + 0x9, 0xC); - b43_radio_write(dev, r + 0xB, 0x0); - if (phy->rev != 5) - b43_radio_write(dev, r + 0xA, 1); - else - b43_radio_write(dev, r + 0xA, 0x31); - } - b43_radio_write(dev, r + 0x6, 0); - b43_radio_write(dev, r + 0x7, 0); - b43_radio_write(dev, r + 0x8, 3); - b43_radio_write(dev, r + 0xC, 0); - } - } else { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); - else - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); - b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); - b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); - - for (core = 0; core < 2; core++) { - r = core ? B2056_TX1 : B2056_TX0; - - b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); - b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); - b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); - b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); - b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); - b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); - b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, - 0x5); - if (phy->rev != 5) - b43_radio_write(dev, r | B2056_TX_TSSIA, - 0x00); - if (phy->rev >= 5) - b43_radio_write(dev, r | B2056_TX_TSSIG, - 0x31); - else - b43_radio_write(dev, r | B2056_TX_TSSIG, - 0x11); - b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, - 0xE); - } else { - b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, - 0x9); - b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); - b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); - b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, - 0xC); - } - } - } -} - -/* - * Stop radio and transmit known signal. Then check received signal strength to - * get TSSI (Transmit Signal Strength Indicator). - * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi - */ -static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - - u32 tmp; - s32 rssi[4] = { }; - - if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR) - return; - - if (b43_nphy_ipa(dev)) - b43_nphy_ipa_internal_tssi_setup(dev); - - if (phy->rev >= 19) - b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); - else if (phy->rev >= 7) - b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); - else if (phy->rev >= 3) - b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); - - b43_nphy_stop_playback(dev); - b43_nphy_tx_tone(dev, 4000, 0, false, false, false); - udelay(20); - tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); - b43_nphy_stop_playback(dev); - - b43_nphy_rssi_select(dev, 0, N_RSSI_W1); - - if (phy->rev >= 19) - b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); - else if (phy->rev >= 7) - b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); - else if (phy->rev >= 3) - b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); - - if (phy->rev >= 19) { - /* TODO */ - return; - } else if (phy->rev >= 3) { - nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; - nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; - } else { - nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; - nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; - } - nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; - nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; -} - -/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */ -static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u8 idx, delta; - u8 i, stf_mode; - - /* Array adj_pwr_tbl corresponds to the hardware table. It consists of - * 21 groups, each containing 4 entries. - * - * First group has entries for CCK modulation. - * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM). - * - * Group 0 is for CCK - * Groups 1..4 use BPSK (group per coding rate) - * Groups 5..8 use QPSK (group per coding rate) - * Groups 9..12 use 16-QAM (group per coding rate) - * Groups 13..16 use 64-QAM (group per coding rate) - * Groups 17..20 are unknown - */ - - for (i = 0; i < 4; i++) - nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i]; - - for (stf_mode = 0; stf_mode < 4; stf_mode++) { - delta = 0; - switch (stf_mode) { - case 0: - if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { - idx = 68; - } else { - delta = 1; - idx = b43_is_40mhz(dev) ? 52 : 4; - } - break; - case 1: - idx = b43_is_40mhz(dev) ? 76 : 28; - break; - case 2: - idx = b43_is_40mhz(dev) ? 84 : 36; - break; - case 3: - idx = b43_is_40mhz(dev) ? 92 : 44; - break; - } - - for (i = 0; i < 20; i++) { - nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] = - nphy->tx_power_offset[idx]; - if (i == 0) - idx += delta; - if (i == 14) - idx += 1 - delta; - if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 || - i == 13) - idx += 1; - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */ -static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - s16 a1[2], b0[2], b1[2]; - u8 idle[2]; - u8 ppr_max; - s8 target[2]; - s32 num, den, pwr; - u32 regval[64]; - - u16 freq = phy->chandef->chan->center_freq; - u16 tmp; - u16 r; /* routing */ - u8 i, c; - - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); - b43_read32(dev, B43_MMIO_MACCTL); - udelay(1); - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, true); - - b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); - if (dev->phy.rev >= 3) - b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); - else - b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, - B43_NPHY_TXPCTL_CMD_PCTLEN); - - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) - b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); - - if (sprom->revision < 4) { - idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; - idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g; - target[0] = target[1] = 52; - a1[0] = a1[1] = -424; - b0[0] = b0[1] = 5612; - b1[0] = b1[1] = -1393; - } else { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - for (c = 0; c < 2; c++) { - idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g; - target[c] = sprom->core_pwr_info[c].maxpwr_2g; - a1[c] = sprom->core_pwr_info[c].pa_2g[0]; - b0[c] = sprom->core_pwr_info[c].pa_2g[1]; - b1[c] = sprom->core_pwr_info[c].pa_2g[2]; - } - } else if (freq >= 4900 && freq < 5100) { - for (c = 0; c < 2; c++) { - idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; - target[c] = sprom->core_pwr_info[c].maxpwr_5gl; - a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; - b0[c] = sprom->core_pwr_info[c].pa_5gl[1]; - b1[c] = sprom->core_pwr_info[c].pa_5gl[2]; - } - } else if (freq >= 5100 && freq < 5500) { - for (c = 0; c < 2; c++) { - idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; - target[c] = sprom->core_pwr_info[c].maxpwr_5g; - a1[c] = sprom->core_pwr_info[c].pa_5g[0]; - b0[c] = sprom->core_pwr_info[c].pa_5g[1]; - b1[c] = sprom->core_pwr_info[c].pa_5g[2]; - } - } else if (freq >= 5500) { - for (c = 0; c < 2; c++) { - idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; - target[c] = sprom->core_pwr_info[c].maxpwr_5gh; - a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; - b0[c] = sprom->core_pwr_info[c].pa_5gh[1]; - b1[c] = sprom->core_pwr_info[c].pa_5gh[2]; - } - } else { - idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; - idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g; - target[0] = target[1] = 52; - a1[0] = a1[1] = -424; - b0[0] = b0[1] = 5612; - b1[0] = b1[1] = -1393; - } - } - - ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); - if (ppr_max) { - target[0] = ppr_max; - target[1] = ppr_max; - } - - if (dev->phy.rev >= 3) { - if (sprom->fem.ghz2.tssipos) - b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); - if (dev->phy.rev >= 7) { - for (c = 0; c < 2; c++) { - r = c ? 0x190 : 0x170; - if (b43_nphy_ipa(dev)) - b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC); - } - } else { - if (b43_nphy_ipa(dev)) { - tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; - b43_radio_write(dev, - B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp); - b43_radio_write(dev, - B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp); - } else { - b43_radio_write(dev, - B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); - b43_radio_write(dev, - B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); - } - } - } - - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); - b43_read32(dev, B43_MMIO_MACCTL); - udelay(1); - } - - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_INIT, 0x19); - b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, - ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19); - } else { - b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, - ~B43_NPHY_TXPCTL_CMD_INIT, 0x40); - if (dev->phy.rev > 1) - b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, - ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40); - } - - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) - b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); - - b43_phy_write(dev, B43_NPHY_TXPCTL_N, - 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT | - 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT); - b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, - idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT | - idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT | - B43_NPHY_TXPCTL_ITSSI_BINF); - b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, - target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT | - target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT); - - for (c = 0; c < 2; c++) { - for (i = 0; i < 64; i++) { - num = 8 * (16 * b0[c] + b1[c] * i); - den = 32768 + a1[c] * i; - pwr = max((4 * num + den / 2) / den, -8); - if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) - pwr = max(pwr, target[c] + 1); - regval[i] = pwr; - } - b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); - } - - b43_nphy_tx_prepare_adjusted_power_table(dev); - b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); - b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, false); -} - -static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - const u32 *table = NULL; - u32 rfpwr_offset; - u8 pga_gain, pad_gain; - int i; - const s16 *uninitialized_var(rf_pwr_offset_table); - - table = b43_nphy_get_tx_gain_table(dev); - if (!table) - return; - - b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); - b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); - - if (phy->rev < 3) - return; - -#if 0 - nphy->gmval = (table[0] >> 16) & 0x7000; -#endif - - if (phy->rev >= 19) { - return; - } else if (phy->rev >= 7) { - rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); - if (!rf_pwr_offset_table) - return; - /* TODO: Enable this once we have gains configured */ - return; - } - - for (i = 0; i < 128; i++) { - if (phy->rev >= 19) { - /* TODO */ - return; - } else if (phy->rev >= 7) { - pga_gain = (table[i] >> 24) & 0xf; - pad_gain = (table[i] >> 19) & 0x1f; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - rfpwr_offset = rf_pwr_offset_table[pad_gain]; - else - rfpwr_offset = rf_pwr_offset_table[pga_gain]; - } else { - pga_gain = (table[i] >> 24) & 0xF; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; - else - rfpwr_offset = 0; /* FIXME */ - } - - b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); - b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ -static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) -{ - struct b43_phy_n *nphy = dev->phy.n; - enum ieee80211_band band; - u16 tmp; - - if (!enable) { - nphy->rfctrl_intc1_save = b43_phy_read(dev, - B43_NPHY_RFCTL_INTC1); - nphy->rfctrl_intc2_save = b43_phy_read(dev, - B43_NPHY_RFCTL_INTC2); - band = b43_current_band(dev->wl); - if (dev->phy.rev >= 7) { - tmp = 0x1480; - } else if (dev->phy.rev >= 3) { - if (band == IEEE80211_BAND_5GHZ) - tmp = 0x600; - else - tmp = 0x480; - } else { - if (band == IEEE80211_BAND_5GHZ) - tmp = 0x180; - else - tmp = 0x120; - } - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); - } else { - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, - nphy->rfctrl_intc1_save); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, - nphy->rfctrl_intc2_save); - } -} - -/* - * TX low-pass filter bandwidth setup - * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw - */ -static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) -{ - u16 tmp; - - if (dev->phy.rev < 3 || dev->phy.rev >= 7) - return; - - if (b43_nphy_ipa(dev)) - tmp = b43_is_40mhz(dev) ? 5 : 4; - else - tmp = b43_is_40mhz(dev) ? 3 : 1; - b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, - (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); - - if (b43_nphy_ipa(dev)) { - tmp = b43_is_40mhz(dev) ? 4 : 1; - b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, - (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ -static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, - u16 samps, u8 time, bool wait) -{ - int i; - u16 tmp; - - b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); - b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); - if (wait) - b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); - else - b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); - - b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); - - for (i = 1000; i; i--) { - tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); - if (!(tmp & B43_NPHY_IQEST_CMD_START)) { - est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); - est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); - est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); - - est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); - est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); - est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | - b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); - return; - } - udelay(10); - } - memset(est, 0, sizeof(*est)); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ -static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, - struct b43_phy_n_iq_comp *pcomp) -{ - if (write) { - b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); - b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); - b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); - b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); - } else { - pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); - pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); - pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); - pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); - } -} - -#if 0 -/* Ready but not used anywhere */ -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ -static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) -{ - u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; - - b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); - if (core == 0) { - b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); - } else { - b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); - } - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); - b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); - b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); - b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); - b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); - b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); - b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ -static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) -{ - u8 rxval, txval; - u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; - - regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); - if (core == 0) { - regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); - regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); - } else { - regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); - regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - } - regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); - regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); - regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); - regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); - regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); - regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); - regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); - regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); - - b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); - b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); - - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, - ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, - ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, - ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, - (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, - (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); - - if (core == 0) { - b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); - } else { - b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); - } - - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3); - b43_nphy_rf_ctl_override(dev, 8, 0, 3, false); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); - - if (core == 0) { - rxval = 1; - txval = 8; - } else { - rxval = 4; - txval = 2; - } - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval, - core + 1); - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval, - 2 - core); -} -#endif - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ -static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) -{ - int i; - s32 iq; - u32 ii; - u32 qq; - int iq_nbits, qq_nbits; - int arsh, brsh; - u16 tmp, a, b; - - struct nphy_iq_est est; - struct b43_phy_n_iq_comp old; - struct b43_phy_n_iq_comp new = { }; - bool error = false; - - if (mask == 0) - return; - - b43_nphy_rx_iq_coeffs(dev, false, &old); - b43_nphy_rx_iq_coeffs(dev, true, &new); - b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); - new = old; - - for (i = 0; i < 2; i++) { - if (i == 0 && (mask & 1)) { - iq = est.iq0_prod; - ii = est.i0_pwr; - qq = est.q0_pwr; - } else if (i == 1 && (mask & 2)) { - iq = est.iq1_prod; - ii = est.i1_pwr; - qq = est.q1_pwr; - } else { - continue; - } - - if (ii + qq < 2) { - error = true; - break; - } - - iq_nbits = fls(abs(iq)); - qq_nbits = fls(qq); - - arsh = iq_nbits - 20; - if (arsh >= 0) { - a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); - tmp = ii >> arsh; - } else { - a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); - tmp = ii << -arsh; - } - if (tmp == 0) { - error = true; - break; - } - a /= tmp; - - brsh = qq_nbits - 11; - if (brsh >= 0) { - b = (qq << (31 - qq_nbits)); - tmp = ii >> brsh; - } else { - b = (qq << (31 - qq_nbits)); - tmp = ii << -brsh; - } - if (tmp == 0) { - error = true; - break; - } - b = int_sqrt(b / tmp - a * a) - (1 << 10); - - if (i == 0 && (mask & 0x1)) { - if (dev->phy.rev >= 3) { - new.a0 = a & 0x3FF; - new.b0 = b & 0x3FF; - } else { - new.a0 = b & 0x3FF; - new.b0 = a & 0x3FF; - } - } else if (i == 1 && (mask & 0x2)) { - if (dev->phy.rev >= 3) { - new.a1 = a & 0x3FF; - new.b1 = b & 0x3FF; - } else { - new.a1 = b & 0x3FF; - new.b1 = a & 0x3FF; - } - } - } - - if (error) - new = old; - - b43_nphy_rx_iq_coeffs(dev, true, &new); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ -static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) -{ - u16 array[4]; - b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); - - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ -static void b43_nphy_spur_workaround(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u8 channel = dev->phy.channel; - int tone[2] = { 57, 58 }; - u32 noise[2] = { 0x3FF, 0x3FF }; - - B43_WARN_ON(dev->phy.rev < 3); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - if (nphy->gband_spurwar_en) { - /* TODO: N PHY Adjust Analog Pfbw (7) */ - if (channel == 11 && b43_is_40mhz(dev)) - ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ - else - ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ - /* TODO: N PHY Adjust CRS Min Power (0x1E) */ - } - - if (nphy->aband_spurwar_en) { - if (channel == 54) { - tone[0] = 0x20; - noise[0] = 0x25F; - } else if (channel == 38 || channel == 102 || channel == 118) { - if (0 /* FIXME */) { - tone[0] = 0x20; - noise[0] = 0x21F; - } else { - tone[0] = 0; - noise[0] = 0; - } - } else if (channel == 134) { - tone[0] = 0x20; - noise[0] = 0x21F; - } else if (channel == 151) { - tone[0] = 0x10; - noise[0] = 0x23F; - } else if (channel == 153 || channel == 161) { - tone[0] = 0x30; - noise[0] = 0x23F; - } else { - tone[0] = 0; - noise[0] = 0; - } - - if (!tone[0] && !noise[0]) - ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ - else - ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ -static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - int i, j; - u32 tmp; - u32 cur_real, cur_imag, real_part, imag_part; - - u16 buffer[7]; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, true); - - b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); - - for (i = 0; i < 2; i++) { - tmp = ((buffer[i * 2] & 0x3FF) << 10) | - (buffer[i * 2 + 1] & 0x3FF); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, - (((i + 26) << 10) | 320)); - for (j = 0; j < 128; j++) { - b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, - ((tmp >> 16) & 0xFFFF)); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, - (tmp & 0xFFFF)); - } - } - - for (i = 0; i < 2; i++) { - tmp = buffer[5 + i]; - real_part = (tmp >> 8) & 0xFF; - imag_part = (tmp & 0xFF); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, - (((i + 26) << 10) | 448)); - - if (dev->phy.rev >= 3) { - cur_real = real_part; - cur_imag = imag_part; - tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); - } - - for (j = 0; j < 128; j++) { - if (dev->phy.rev < 3) { - cur_real = (real_part * loscale[j] + 128) >> 8; - cur_imag = (imag_part * loscale[j] + 128) >> 8; - tmp = ((cur_real & 0xFF) << 8) | - (cur_imag & 0xFF); - } - b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, - ((tmp >> 16) & 0xFFFF)); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, - (tmp & 0xFFFF)); - } - } - - if (dev->phy.rev >= 3) { - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); - } - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, false); -} - -/* - * Restore RSSI Calibration - * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal - */ -static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u16 *rssical_radio_regs = NULL; - u16 *rssical_phy_regs = NULL; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (!nphy->rssical_chanspec_2G.center_freq) - return; - rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; - rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; - } else { - if (!nphy->rssical_chanspec_5G.center_freq) - return; - rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; - rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; - } - - if (dev->phy.rev >= 19) { - /* TODO */ - } else if (dev->phy.rev >= 7) { - b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, - rssical_radio_regs[0]); - b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, - rssical_radio_regs[1]); - } else { - b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, - rssical_radio_regs[0]); - b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, - rssical_radio_regs[1]); - } - - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); - - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); - - b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); - b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); - b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); -} - -static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) -{ - /* TODO */ -} - -static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - u16 *save = nphy->tx_rx_cal_radio_saveregs; - int core, off; - u16 r, tmp; - - for (core = 0; core < 2; core++) { - r = core ? 0x20 : 0; - off = core * 11; - - save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); - save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); - save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); - save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); - save[off + 4] = 0; - save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); - if (phy->radio_rev != 5) - save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); - save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); - save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); - b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); - b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); - b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); - b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); - if (nphy->use_int_tx_iq_lo_cal) { - b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); - tmp = true ? 0x31 : 0x21; /* TODO */ - b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); - } - b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); - } else { - b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); - b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); - b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); - b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); - - if (phy->radio_rev != 5) - b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); - if (nphy->use_int_tx_iq_lo_cal) { - b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); - tmp = true ? 0x31 : 0x21; /* TODO */ - b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); - } - b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ -static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - u16 *save = nphy->tx_rx_cal_radio_saveregs; - u16 tmp; - u8 offset, i; - - if (phy->rev >= 19) { - b43_nphy_tx_cal_radio_setup_rev19(dev); - } else if (phy->rev >= 7) { - b43_nphy_tx_cal_radio_setup_rev7(dev); - } else if (phy->rev >= 3) { - for (i = 0; i < 2; i++) { - tmp = (i == 0) ? 0x2000 : 0x3000; - offset = i * 11; - - save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); - save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); - save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); - save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); - save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); - save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); - save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); - save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); - save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); - save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); - save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); - b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); - b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); - b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); - b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); - if (nphy->ipa5g_on) { - b43_radio_write(dev, tmp | B2055_PADDRV, 4); - b43_radio_write(dev, tmp | B2055_XOCTL1, 1); - } else { - b43_radio_write(dev, tmp | B2055_PADDRV, 0); - b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); - } - b43_radio_write(dev, tmp | B2055_XOCTL2, 0); - } else { - b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); - b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); - b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); - b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); - b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); - b43_radio_write(dev, tmp | B2055_XOCTL1, 0); - if (nphy->ipa2g_on) { - b43_radio_write(dev, tmp | B2055_PADDRV, 6); - b43_radio_write(dev, tmp | B2055_XOCTL2, - (dev->phy.rev < 5) ? 0x11 : 0x01); - } else { - b43_radio_write(dev, tmp | B2055_PADDRV, 0); - b43_radio_write(dev, tmp | B2055_XOCTL2, 0); - } - } - b43_radio_write(dev, tmp | B2055_XOREGUL, 0); - b43_radio_write(dev, tmp | B2055_XOMISC, 0); - b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); - } - } else { - save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); - b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); - - save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); - b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); - - save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); - b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); - - save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); - b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); - - save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); - save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); - - if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & - B43_NPHY_BANDCTL_5GHZ)) { - b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); - b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); - } else { - b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); - b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); - } - - if (dev->phy.rev < 2) { - b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); - b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); - } else { - b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); - b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ -static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) -{ - struct b43_phy_n *nphy = dev->phy.n; - int i; - u16 scale, entry; - - u16 tmp = nphy->txcal_bbmult; - if (core == 0) - tmp >>= 8; - tmp &= 0xff; - - for (i = 0; i < 18; i++) { - scale = (ladder_lo[i].percent * tmp) / 100; - entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; - b43_ntab_write(dev, B43_NTAB16(15, i), entry); - - scale = (ladder_iq[i].percent * tmp) / 100; - entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; - b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); - } -} - -static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, - const s16 *filter) -{ - int i; - - offset = B43_PHY_N(offset); - - for (i = 0; i < 15; i++, offset++) - b43_phy_write(dev, offset, filter[i]); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ -static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) -{ - b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, - tbl_tx_filter_coef_rev4[2]); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ -static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) -{ - /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ - static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; - static const s16 dig_filter_phy_rev16[] = { - -375, 136, -407, 208, -1527, - 956, 93, 186, 93, 230, - -44, 230, 201, -191, 201, - }; - int i; - - for (i = 0; i < 3; i++) - b43_nphy_pa_set_tx_dig_filter(dev, offset[i], - tbl_tx_filter_coef_rev4[i]); - - /* Verified with BCM43227 and BCM43228 */ - if (dev->phy.rev == 16) - b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); - - /* Verified with BCM43131 and BCM43217 */ - if (dev->phy.rev == 17) { - b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); - b43_nphy_pa_set_tx_dig_filter(dev, 0x195, - tbl_tx_filter_coef_rev4[1]); - } - - if (b43_is_40mhz(dev)) { - b43_nphy_pa_set_tx_dig_filter(dev, 0x186, - tbl_tx_filter_coef_rev4[3]); - } else { - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - b43_nphy_pa_set_tx_dig_filter(dev, 0x186, - tbl_tx_filter_coef_rev4[5]); - if (dev->phy.channel == 14) - b43_nphy_pa_set_tx_dig_filter(dev, 0x186, - tbl_tx_filter_coef_rev4[6]); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ -static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - - u16 curr_gain[2]; - struct nphy_txgains target; - const u32 *table = NULL; - - if (!nphy->txpwrctrl) { - int i; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, true); - b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, false); - - for (i = 0; i < 2; ++i) { - if (dev->phy.rev >= 7) { - target.ipa[i] = curr_gain[i] & 0x0007; - target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; - target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; - target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; - target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; - } else if (dev->phy.rev >= 3) { - target.ipa[i] = curr_gain[i] & 0x000F; - target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; - target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; - target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; - } else { - target.ipa[i] = curr_gain[i] & 0x0003; - target.pad[i] = (curr_gain[i] & 0x000C) >> 2; - target.pga[i] = (curr_gain[i] & 0x0070) >> 4; - target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; - } - } - } else { - int i; - u16 index[2]; - index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & - B43_NPHY_TXPCTL_STAT_BIDX) >> - B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; - index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & - B43_NPHY_TXPCTL_STAT_BIDX) >> - B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; - - for (i = 0; i < 2; ++i) { - table = b43_nphy_get_tx_gain_table(dev); - if (!table) - break; - - if (dev->phy.rev >= 7) { - target.ipa[i] = (table[index[i]] >> 16) & 0x7; - target.pad[i] = (table[index[i]] >> 19) & 0x1F; - target.pga[i] = (table[index[i]] >> 24) & 0xF; - target.txgm[i] = (table[index[i]] >> 28) & 0x7; - target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; - } else if (dev->phy.rev >= 3) { - target.ipa[i] = (table[index[i]] >> 16) & 0xF; - target.pad[i] = (table[index[i]] >> 20) & 0xF; - target.pga[i] = (table[index[i]] >> 24) & 0xF; - target.txgm[i] = (table[index[i]] >> 28) & 0xF; - } else { - target.ipa[i] = (table[index[i]] >> 16) & 0x3; - target.pad[i] = (table[index[i]] >> 18) & 0x3; - target.pga[i] = (table[index[i]] >> 20) & 0x7; - target.txgm[i] = (table[index[i]] >> 23) & 0x7; - } - } - } - - return target; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ -static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) -{ - u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; - - if (dev->phy.rev >= 3) { - b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); - b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); - b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); - b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); - b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); - b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); - b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); - b43_nphy_reset_cca(dev); - } else { - b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); - b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); - b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); - b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ -static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; - u16 tmp; - - regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); - regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); - if (dev->phy.rev >= 3) { - b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); - b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); - - tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); - regs[2] = tmp; - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); - - tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - regs[3] = tmp; - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); - - regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); - b43_phy_mask(dev, B43_NPHY_BBCFG, - ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); - - tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); - regs[5] = tmp; - b43_ntab_write(dev, B43_NTAB16(8, 3), 0); - - tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); - regs[6] = tmp; - b43_ntab_write(dev, B43_NTAB16(8, 19), 0); - regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); - regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); - - if (!nphy->use_int_tx_iq_lo_cal) - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, - 1, 3); - else - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, - 0, 3); - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); - b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); - - regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); - regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); - b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); - b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); - - tmp = b43_nphy_read_lpf_ctl(dev, 0); - if (phy->rev >= 19) - b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, - 1); - else if (phy->rev >= 7) - b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, - 1); - - if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { - if (phy->rev >= 19) { - b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, - false, 0); - } else if (phy->rev >= 8) { - b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, - false, 0); - } else if (phy->rev == 7) { - b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); - b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); - } else { - b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); - b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); - } - } - } - } else { - b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); - b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); - tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - regs[2] = tmp; - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); - tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); - regs[3] = tmp; - tmp |= 0x2000; - b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); - tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); - regs[4] = tmp; - tmp |= 0x2000; - b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); - regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); - regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - tmp = 0x0180; - else - tmp = 0x0120; - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ -static void b43_nphy_save_cal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - - struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; - u16 *txcal_radio_regs = NULL; - struct b43_chanspec *iqcal_chanspec; - u16 *table = NULL; - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 1); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; - txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; - iqcal_chanspec = &nphy->iqcal_chanspec_2G; - table = nphy->cal_cache.txcal_coeffs_2G; - } else { - rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; - txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; - iqcal_chanspec = &nphy->iqcal_chanspec_5G; - table = nphy->cal_cache.txcal_coeffs_5G; - } - - b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); - /* TODO use some definitions */ - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - txcal_radio_regs[0] = b43_radio_read(dev, - R2057_TX0_LOFT_FINE_I); - txcal_radio_regs[1] = b43_radio_read(dev, - R2057_TX0_LOFT_FINE_Q); - txcal_radio_regs[4] = b43_radio_read(dev, - R2057_TX0_LOFT_COARSE_I); - txcal_radio_regs[5] = b43_radio_read(dev, - R2057_TX0_LOFT_COARSE_Q); - txcal_radio_regs[2] = b43_radio_read(dev, - R2057_TX1_LOFT_FINE_I); - txcal_radio_regs[3] = b43_radio_read(dev, - R2057_TX1_LOFT_FINE_Q); - txcal_radio_regs[6] = b43_radio_read(dev, - R2057_TX1_LOFT_COARSE_I); - txcal_radio_regs[7] = b43_radio_read(dev, - R2057_TX1_LOFT_COARSE_Q); - } else if (phy->rev >= 3) { - txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); - txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); - txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); - txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); - txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); - txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); - txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); - txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); - } else { - txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); - txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); - txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); - txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); - } - iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; - iqcal_chanspec->channel_type = - cfg80211_get_chandef_type(dev->phy.chandef); - b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, 0); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ -static void b43_nphy_restore_cal(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - - u16 coef[4]; - u16 *loft = NULL; - u16 *table = NULL; - - int i; - u16 *txcal_radio_regs = NULL; - struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (!nphy->iqcal_chanspec_2G.center_freq) - return; - table = nphy->cal_cache.txcal_coeffs_2G; - loft = &nphy->cal_cache.txcal_coeffs_2G[5]; - } else { - if (!nphy->iqcal_chanspec_5G.center_freq) - return; - table = nphy->cal_cache.txcal_coeffs_5G; - loft = &nphy->cal_cache.txcal_coeffs_5G[5]; - } - - b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); - - for (i = 0; i < 4; i++) { - if (dev->phy.rev >= 3) - table[i] = coef[i]; - else - coef[i] = 0; - } - - b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); - - if (dev->phy.rev < 2) - b43_nphy_tx_iq_workaround(dev); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; - rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; - } else { - txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; - rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; - } - - /* TODO use some definitions */ - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, - txcal_radio_regs[0]); - b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, - txcal_radio_regs[1]); - b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, - txcal_radio_regs[4]); - b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, - txcal_radio_regs[5]); - b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, - txcal_radio_regs[2]); - b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, - txcal_radio_regs[3]); - b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, - txcal_radio_regs[6]); - b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, - txcal_radio_regs[7]); - } else if (phy->rev >= 3) { - b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); - b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); - b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); - b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); - b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); - b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); - b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); - b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); - } else { - b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); - b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); - b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); - b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); - } - b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ -static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, - struct nphy_txgains target, - bool full, bool mphase) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - int i; - int error = 0; - int freq; - bool avoid = false; - u8 length; - u16 tmp, core, type, count, max, numb, last = 0, cmd; - const u16 *table; - bool phy6or5x; - - u16 buffer[11]; - u16 diq_start = 0; - u16 save[2]; - u16 gain[2]; - struct nphy_iqcal_params params[2]; - bool updated[2] = { }; - - b43_nphy_stay_in_carrier_search(dev, true); - - if (dev->phy.rev >= 4) { - avoid = nphy->hang_avoid; - nphy->hang_avoid = false; - } - - b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); - - for (i = 0; i < 2; i++) { - b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); - gain[i] = params[i].cal_gain; - } - - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); - - b43_nphy_tx_cal_radio_setup(dev); - b43_nphy_tx_cal_phy_setup(dev); - - phy6or5x = dev->phy.rev >= 6 || - (dev->phy.rev == 5 && nphy->ipa2g_on && - b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); - if (phy6or5x) { - if (b43_is_40mhz(dev)) { - b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, - tbl_tx_iqlo_cal_loft_ladder_40); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, - tbl_tx_iqlo_cal_iqimb_ladder_40); - } else { - b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, - tbl_tx_iqlo_cal_loft_ladder_20); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, - tbl_tx_iqlo_cal_iqimb_ladder_20); - } - } - - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); - } else { - b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); - } - - if (!b43_is_40mhz(dev)) - freq = 2500; - else - freq = 5000; - - if (nphy->mphase_cal_phase_id > 2) - b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, - 0xFFFF, 0, true, false, false); - else - error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); - - if (error == 0) { - if (nphy->mphase_cal_phase_id > 2) { - table = nphy->mphase_txcal_bestcoeffs; - length = 11; - if (dev->phy.rev < 3) - length -= 2; - } else { - if (!full && nphy->txiqlocal_coeffsvalid) { - table = nphy->txiqlocal_bestc; - length = 11; - if (dev->phy.rev < 3) - length -= 2; - } else { - full = true; - if (dev->phy.rev >= 3) { - table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; - length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; - } else { - table = tbl_tx_iqlo_cal_startcoefs; - length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; - } - } - } - - b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); - - if (full) { - if (dev->phy.rev >= 3) - max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; - else - max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; - } else { - if (dev->phy.rev >= 3) - max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; - else - max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; - } - - if (mphase) { - count = nphy->mphase_txcal_cmdidx; - numb = min(max, - (u16)(count + nphy->mphase_txcal_numcmds)); - } else { - count = 0; - numb = max; - } - - for (; count < numb; count++) { - if (full) { - if (dev->phy.rev >= 3) - cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; - else - cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; - } else { - if (dev->phy.rev >= 3) - cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; - else - cmd = tbl_tx_iqlo_cal_cmds_recal[count]; - } - - core = (cmd & 0x3000) >> 12; - type = (cmd & 0x0F00) >> 8; - - if (phy6or5x && updated[core] == 0) { - b43_nphy_update_tx_cal_ladder(dev, core); - updated[core] = true; - } - - tmp = (params[core].ncorr[type] << 8) | 0x66; - b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); - - if (type == 1 || type == 3 || type == 4) { - buffer[0] = b43_ntab_read(dev, - B43_NTAB16(15, 69 + core)); - diq_start = buffer[0]; - buffer[0] = 0; - b43_ntab_write(dev, B43_NTAB16(15, 69 + core), - 0); - } - - b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); - for (i = 0; i < 2000; i++) { - tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); - if (tmp & 0xC000) - break; - udelay(10); - } - - b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, - buffer); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, - buffer); - - if (type == 1 || type == 3 || type == 4) - buffer[0] = diq_start; - } - - if (mphase) - nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; - - last = (dev->phy.rev < 3) ? 6 : 7; - - if (!mphase || nphy->mphase_cal_phase_id == last) { - b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); - b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); - if (dev->phy.rev < 3) { - buffer[0] = 0; - buffer[1] = 0; - buffer[2] = 0; - buffer[3] = 0; - } - b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, - buffer); - b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, - buffer); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, - buffer); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, - buffer); - length = 11; - if (dev->phy.rev < 3) - length -= 2; - b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, - nphy->txiqlocal_bestc); - nphy->txiqlocal_coeffsvalid = true; - nphy->txiqlocal_chanspec.center_freq = - phy->chandef->chan->center_freq; - nphy->txiqlocal_chanspec.channel_type = - cfg80211_get_chandef_type(phy->chandef); - } else { - length = 11; - if (dev->phy.rev < 3) - length -= 2; - b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, - nphy->mphase_txcal_bestcoeffs); - } - - b43_nphy_stop_playback(dev); - b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); - } - - b43_nphy_tx_cal_phy_cleanup(dev); - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); - - if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) - b43_nphy_tx_iq_workaround(dev); - - if (dev->phy.rev >= 4) - nphy->hang_avoid = avoid; - - b43_nphy_stay_in_carrier_search(dev, false); - - return error; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ -static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy = dev->phy.n; - u8 i; - u16 buffer[7]; - bool equal = true; - - if (!nphy->txiqlocal_coeffsvalid || - nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || - nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) - return; - - b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); - for (i = 0; i < 4; i++) { - if (buffer[i] != nphy->txiqlocal_bestc[i]) { - equal = false; - break; - } - } - - if (!equal) { - b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, - nphy->txiqlocal_bestc); - for (i = 0; i < 4; i++) - buffer[i] = 0; - b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, - buffer); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, - &nphy->txiqlocal_bestc[5]); - b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, - &nphy->txiqlocal_bestc[5]); - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ -static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, - struct nphy_txgains target, u8 type, bool debug) -{ - struct b43_phy_n *nphy = dev->phy.n; - int i, j, index; - u8 rfctl[2]; - u8 afectl_core; - u16 tmp[6]; - u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; - u32 real, imag; - enum ieee80211_band band; - - u8 use; - u16 cur_hpf; - u16 lna[3] = { 3, 3, 1 }; - u16 hpf1[3] = { 7, 2, 0 }; - u16 hpf2[3] = { 2, 0, 0 }; - u32 power[3] = { }; - u16 gain_save[2]; - u16 cal_gain[2]; - struct nphy_iqcal_params cal_params[2]; - struct nphy_iq_est est; - int ret = 0; - bool playtone = true; - int desired = 13; - - b43_nphy_stay_in_carrier_search(dev, 1); - - if (dev->phy.rev < 2) - b43_nphy_reapply_tx_cal_coeffs(dev); - b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); - for (i = 0; i < 2; i++) { - b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); - cal_gain[i] = cal_params[i].cal_gain; - } - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); - - for (i = 0; i < 2; i++) { - if (i == 0) { - rfctl[0] = B43_NPHY_RFCTL_INTC1; - rfctl[1] = B43_NPHY_RFCTL_INTC2; - afectl_core = B43_NPHY_AFECTL_C1; - } else { - rfctl[0] = B43_NPHY_RFCTL_INTC2; - rfctl[1] = B43_NPHY_RFCTL_INTC1; - afectl_core = B43_NPHY_AFECTL_C2; - } - - tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); - tmp[2] = b43_phy_read(dev, afectl_core); - tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); - tmp[4] = b43_phy_read(dev, rfctl[0]); - tmp[5] = b43_phy_read(dev, rfctl[1]); - - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, - ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, - ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, - (1 - i)); - b43_phy_set(dev, afectl_core, 0x0006); - b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); - - band = b43_current_band(dev->wl); - - if (nphy->rxcalparams & 0xFF000000) { - if (band == IEEE80211_BAND_5GHZ) - b43_phy_write(dev, rfctl[0], 0x140); - else - b43_phy_write(dev, rfctl[0], 0x110); - } else { - if (band == IEEE80211_BAND_5GHZ) - b43_phy_write(dev, rfctl[0], 0x180); - else - b43_phy_write(dev, rfctl[0], 0x120); - } - - if (band == IEEE80211_BAND_5GHZ) - b43_phy_write(dev, rfctl[1], 0x148); - else - b43_phy_write(dev, rfctl[1], 0x114); - - if (nphy->rxcalparams & 0x10000) { - b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, - (i + 1)); - b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, - (2 - i)); - } - - for (j = 0; j < 4; j++) { - if (j < 3) { - cur_lna = lna[j]; - cur_hpf1 = hpf1[j]; - cur_hpf2 = hpf2[j]; - } else { - if (power[1] > 10000) { - use = 1; - cur_hpf = cur_hpf1; - index = 2; - } else { - if (power[0] > 10000) { - use = 1; - cur_hpf = cur_hpf1; - index = 1; - } else { - index = 0; - use = 2; - cur_hpf = cur_hpf2; - } - } - cur_lna = lna[index]; - cur_hpf1 = hpf1[index]; - cur_hpf2 = hpf2[index]; - cur_hpf += desired - hweight32(power[index]); - cur_hpf = clamp_val(cur_hpf, 0, 10); - if (use == 1) - cur_hpf1 = cur_hpf; - else - cur_hpf2 = cur_hpf; - } - - tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | - (cur_lna << 2)); - b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, - false); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - b43_nphy_stop_playback(dev); - - if (playtone) { - ret = b43_nphy_tx_tone(dev, 4000, - (nphy->rxcalparams & 0xFFFF), - false, false, true); - playtone = false; - } else { - b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, - false, true); - } - - if (ret == 0) { - if (j < 3) { - b43_nphy_rx_iq_est(dev, &est, 1024, 32, - false); - if (i == 0) { - real = est.i0_pwr; - imag = est.q0_pwr; - } else { - real = est.i1_pwr; - imag = est.q1_pwr; - } - power[i] = ((real + imag) / 1024) + 1; - } else { - b43_nphy_calc_rx_iq_comp(dev, 1 << i); - } - b43_nphy_stop_playback(dev); - } - - if (ret != 0) - break; - } - - b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); - b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); - b43_phy_write(dev, rfctl[1], tmp[5]); - b43_phy_write(dev, rfctl[0], tmp[4]); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); - b43_phy_write(dev, afectl_core, tmp[2]); - b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); - - if (ret != 0) - break; - } - - b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); - - b43_nphy_stay_in_carrier_search(dev, 0); - - return ret; -} - -static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, - struct nphy_txgains target, u8 type, bool debug) -{ - return -1; -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ -static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, - struct nphy_txgains target, u8 type, bool debug) -{ - if (dev->phy.rev >= 7) - type = 0; - - if (dev->phy.rev >= 3) - return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); - else - return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ -static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - /* u16 buf[16]; it's rev3+ */ - - nphy->phyrxchain = mask; - - if (0 /* FIXME clk */) - return; - - b43_mac_suspend(dev); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, true); - - b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, - (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); - - if ((mask & 0x3) != 0x3) { - b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); - if (dev->phy.rev >= 3) { - /* TODO */ - } - } else { - b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); - if (dev->phy.rev >= 3) { - /* TODO */ - } - } - - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - - if (nphy->hang_avoid) - b43_nphy_stay_in_carrier_search(dev, false); - - b43_mac_enable(dev); -} - -static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, - bool ignore_tssi) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; - struct b43_ppr *ppr = &nphy->tx_pwr_max_ppr; - u8 max; /* qdBm */ - bool tx_pwr_state; - - if (nphy->tx_pwr_last_recalc_freq == channel->center_freq && - nphy->tx_pwr_last_recalc_limit == phy->desired_txpower) - return B43_TXPWR_RES_DONE; - - /* Make sure we have a clean PPR */ - b43_ppr_clear(dev, ppr); - - /* HW limitations */ - b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); - - /* Regulatory & user settings */ - max = INT_TO_Q52(phy->chandef->chan->max_power); - if (phy->desired_txpower) - max = min_t(u8, max, INT_TO_Q52(phy->desired_txpower)); - b43_ppr_apply_max(dev, ppr, max); - if (b43_debug(dev, B43_DBG_XMITPOWER)) - b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", - Q52_ARG(b43_ppr_get_max(dev, ppr))); - - /* TODO: Enable this once we get gains working */ -#if 0 - /* Some extra gains */ - hw_gain = 6; /* N-PHY specific */ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - hw_gain += sprom->antenna_gain.a0; - else - hw_gain += sprom->antenna_gain.a1; - b43_ppr_add(dev, ppr, -hw_gain); -#endif - - /* Make sure we didn't go too low */ - b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); - - /* Apply */ - tx_pwr_state = nphy->txpwrctrl; - b43_mac_suspend(dev); - b43_nphy_tx_power_ctl_setup(dev); - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { - b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); - b43_read32(dev, B43_MMIO_MACCTL); - udelay(1); - } - b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); - if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); - b43_mac_enable(dev); - - nphy->tx_pwr_last_recalc_freq = channel->center_freq; - nphy->tx_pwr_last_recalc_limit = phy->desired_txpower; - - return B43_TXPWR_RES_DONE; -} - -/************************************************** - * N-PHY init - **************************************************/ - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ -static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) -{ - u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); - - mimocfg |= B43_NPHY_MIMOCFG_AUTO; - if (preamble == 1) - mimocfg |= B43_NPHY_MIMOCFG_GFMIX; - else - mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; - - b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ -static void b43_nphy_bphy_init(struct b43_wldev *dev) -{ - unsigned int i; - u16 val; - - val = 0x1E1F; - for (i = 0; i < 16; i++) { - b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); - val -= 0x202; - } - val = 0x3E3F; - for (i = 0; i < 16; i++) { - b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); - val -= 0x202; - } - b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ -static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) -{ - if (dev->phy.rev >= 7) - return; - - if (dev->phy.rev >= 3) { - if (!init) - return; - if (0 /* FIXME */) { - b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); - b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); - b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); - b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); - } - } else { - b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); - b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); - - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, - 0xFC00, 0xFC00); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, - 0xFC00, 0xFC00); - break; -#endif - } - - b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); - b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); - b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), - 0); - - if (init) { - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); - b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ -static int b43_phy_initn(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - u8 tx_pwr_state; - struct nphy_txgains target; - u16 tmp; - enum ieee80211_band tmp2; - bool do_rssi_cal; - - u16 clip[2]; - bool do_cal = false; - - if ((dev->phy.rev >= 3) && - (sprom->boardflags_lo & B43_BFL_EXTLNA) && - (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, - BCMA_CC_CHIPCTL, 0x40); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - chipco_set32(&dev->dev->sdev->bus->chipco, - SSB_CHIPCO_CHIPCTL, 0x40); - break; -#endif - } - } - nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || - phy->rev >= 7 || - (phy->rev >= 5 && - sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL); - nphy->deaf_count = 0; - b43_nphy_tables_init(dev); - nphy->crsminpwr_adjusted = false; - nphy->noisevars_adjusted = false; - - /* Clear all overrides */ - if (dev->phy.rev >= 3) { - b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); - b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); - if (phy->rev >= 7) { - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); - b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); - } - if (phy->rev >= 19) { - /* TODO */ - } - - b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); - b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); - } else { - b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); - } - b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); - if (dev->phy.rev < 6) { - b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); - b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); - } - b43_phy_mask(dev, B43_NPHY_RFSEQMODE, - ~(B43_NPHY_RFSEQMODE_CAOVER | - B43_NPHY_RFSEQMODE_TROVER)); - if (dev->phy.rev >= 3) - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); - - if (dev->phy.rev <= 2) { - tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; - b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, - ~B43_NPHY_BPHY_CTL3_SCALE, - tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); - } - b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); - b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); - - if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || - (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && - dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) - b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); - else - b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); - b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); - b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); - b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); - - if (phy->rev < 8) - b43_nphy_update_mimo_config(dev, nphy->preamble_override); - - b43_nphy_update_txrx_chain(dev); - - if (phy->rev < 2) { - b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); - b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); - } - - tmp2 = b43_current_band(dev->wl); - if (b43_nphy_ipa(dev)) { - b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); - b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, - nphy->papd_epsilon_offset[0] << 7); - b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); - b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, - nphy->papd_epsilon_offset[1] << 7); - b43_nphy_int_pa_set_tx_dig_filters(dev); - } else if (phy->rev >= 5) { - b43_nphy_ext_pa_set_tx_dig_filters(dev); - } - - b43_nphy_workarounds(dev); - - /* Reset CCA, in init code it differs a little from standard way */ - b43_phy_force_clock(dev, 1); - tmp = b43_phy_read(dev, B43_NPHY_BBCFG); - b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); - b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); - b43_phy_force_clock(dev, 0); - - b43_mac_phy_clock_set(dev, true); - - if (phy->rev < 7) { - b43_nphy_pa_override(dev, false); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); - b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); - b43_nphy_pa_override(dev, true); - } - - b43_nphy_classifier(dev, 0, 0); - b43_nphy_read_clip_detection(dev, clip); - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - b43_nphy_bphy_init(dev); - - tx_pwr_state = nphy->txpwrctrl; - b43_nphy_tx_power_ctrl(dev, false); - b43_nphy_tx_power_fix(dev); - b43_nphy_tx_power_ctl_idle_tssi(dev); - b43_nphy_tx_power_ctl_setup(dev); - b43_nphy_tx_gain_table_upload(dev); - - if (nphy->phyrxchain != 3) - b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); - if (nphy->mphase_cal_phase_id > 0) - ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ - - do_rssi_cal = false; - if (phy->rev >= 3) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; - else - do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; - - if (do_rssi_cal) - b43_nphy_rssi_cal(dev); - else - b43_nphy_restore_rssi_cal(dev); - } else { - b43_nphy_rssi_cal(dev); - } - - if (!((nphy->measure_hold & 0x6) != 0)) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - do_cal = !nphy->iqcal_chanspec_2G.center_freq; - else - do_cal = !nphy->iqcal_chanspec_5G.center_freq; - - if (nphy->mute) - do_cal = false; - - if (do_cal) { - target = b43_nphy_get_tx_gains(dev); - - if (nphy->antsel_type == 2) - b43_nphy_superswitch_init(dev, true); - if (nphy->perical != 2) { - b43_nphy_rssi_cal(dev); - if (phy->rev >= 3) { - nphy->cal_orig_pwr_idx[0] = - nphy->txpwrindex[0].index_internal; - nphy->cal_orig_pwr_idx[1] = - nphy->txpwrindex[1].index_internal; - /* TODO N PHY Pre Calibrate TX Gain */ - target = b43_nphy_get_tx_gains(dev); - } - if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) - if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) - b43_nphy_save_cal(dev); - } else if (nphy->mphase_cal_phase_id == 0) - ;/* N PHY Periodic Calibration with arg 3 */ - } else { - b43_nphy_restore_cal(dev); - } - } - - b43_nphy_tx_pwr_ctrl_coef_setup(dev); - b43_nphy_tx_power_ctrl(dev, tx_pwr_state); - b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); - b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); - if (phy->rev >= 3 && phy->rev <= 6) - b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); - b43_nphy_tx_lpf_bw(dev); - if (phy->rev >= 3) - b43_nphy_spur_workaround(dev); - - return 0; -} - -/************************************************** - * Channel switching ops. - **************************************************/ - -static void b43_chantab_phy_upload(struct b43_wldev *dev, - const struct b43_phy_n_sfo_cfg *e) -{ - b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); - b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); - b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); - b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); - b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); - b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ -static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) -{ - switch (dev->dev->bus_type) { -#ifdef CONFIG_B43_BCMA - case B43_BUS_BCMA: - bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, - avoid); - break; -#endif -#ifdef CONFIG_B43_SSB - case B43_BUS_SSB: - ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, - avoid); - break; -#endif - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ -static void b43_nphy_channel_setup(struct b43_wldev *dev, - const struct b43_phy_n_sfo_cfg *e, - struct ieee80211_channel *new_channel) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = dev->phy.n; - int ch = new_channel->hw_value; - u16 tmp16; - - if (new_channel->band == IEEE80211_BAND_5GHZ) { - /* Switch to 2 GHz for a moment to access B43_PHY_B_BBCFG */ - b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); - - tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); - /* Put BPHY in the reset */ - b43_phy_set(dev, B43_PHY_B_BBCFG, - B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX); - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); - b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); - } else if (new_channel->band == IEEE80211_BAND_2GHZ) { - b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); - tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); - /* Take BPHY out of the reset */ - b43_phy_mask(dev, B43_PHY_B_BBCFG, - (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX)); - b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); - } - - b43_chantab_phy_upload(dev, e); - - if (new_channel->hw_value == 14) { - b43_nphy_classifier(dev, 2, 0); - b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); - } else { - b43_nphy_classifier(dev, 2, 2); - if (new_channel->band == IEEE80211_BAND_2GHZ) - b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); - } - - if (!nphy->txpwrctrl) - b43_nphy_tx_power_fix(dev); - - if (dev->phy.rev < 3) - b43_nphy_adjust_lna_gain_table(dev); - - b43_nphy_tx_lpf_bw(dev); - - if (dev->phy.rev >= 3 && - dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { - u8 spuravoid = 0; - - if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { - spuravoid = 1; - } else if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 18) { - /* TODO */ - } else if (phy->rev >= 17) { - /* TODO: Off for channels 1-11, but check 12-14! */ - } else if (phy->rev >= 16) { - /* TODO: Off for 2 GHz, but check 5 GHz! */ - } else if (phy->rev >= 7) { - if (!b43_is_40mhz(dev)) { /* 20MHz */ - if (ch == 13 || ch == 14 || ch == 153) - spuravoid = 1; - } else { /* 40 MHz */ - if (ch == 54) - spuravoid = 1; - } - } else { - if (!b43_is_40mhz(dev)) { /* 20MHz */ - if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14) - spuravoid = 1; - } else { /* 40MHz */ - if (nphy->aband_spurwar_en && - (ch == 38 || ch == 102 || ch == 118)) - spuravoid = dev->dev->chip_id == 0x4716; - } - } - - b43_nphy_pmu_spur_avoid(dev, spuravoid); - - b43_mac_switch_freq(dev, spuravoid); - - if (dev->phy.rev == 3 || dev->phy.rev == 4) - b43_wireless_core_phy_pll_reset(dev); - - if (spuravoid) - b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); - else - b43_phy_mask(dev, B43_NPHY_BBCFG, - ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); - - b43_nphy_reset_cca(dev); - - /* wl sets useless phy_isspuravoid here */ - } - - b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); - - if (phy->rev >= 3) - b43_nphy_spur_workaround(dev); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ -static int b43_nphy_set_channel(struct b43_wldev *dev, - struct ieee80211_channel *channel, - enum nl80211_channel_type channel_type) -{ - struct b43_phy *phy = &dev->phy; - - const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL; - const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL; - const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL; - const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL; - - u8 tmp; - - if (phy->rev >= 19) { - return -ESRCH; - /* TODO */ - } else if (phy->rev >= 7) { - r2057_get_chantabent_rev7(dev, channel->center_freq, - &tabent_r7, &tabent_r7_2g); - if (!tabent_r7 && !tabent_r7_2g) - return -ESRCH; - } else if (phy->rev >= 3) { - tabent_r3 = b43_nphy_get_chantabent_rev3(dev, - channel->center_freq); - if (!tabent_r3) - return -ESRCH; - } else { - tabent_r2 = b43_nphy_get_chantabent_rev2(dev, - channel->hw_value); - if (!tabent_r2) - return -ESRCH; - } - - /* Channel is set later in common code, but we need to set it on our - own to let this function's subcalls work properly. */ - phy->channel = channel->hw_value; - -#if 0 - if (b43_channel_type_is_40mhz(phy->channel_type) != - b43_channel_type_is_40mhz(channel_type)) - ; /* TODO: BMAC BW Set (channel_type) */ -#endif - - if (channel_type == NL80211_CHAN_HT40PLUS) { - b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); - if (phy->rev >= 7) - b43_phy_set(dev, 0x310, 0x8000); - } else if (channel_type == NL80211_CHAN_HT40MINUS) { - b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); - if (phy->rev >= 7) - b43_phy_mask(dev, 0x310, (u16)~0x8000); - } - - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ? - &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs); - - if (phy->radio_rev <= 4 || phy->radio_rev == 6) { - tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0; - b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); - b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); - } - - b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); - b43_nphy_channel_setup(dev, phy_regs, channel); - } else if (phy->rev >= 3) { - tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0; - b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); - b43_radio_2056_setup(dev, tabent_r3); - b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); - } else { - tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050; - b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); - b43_radio_2055_setup(dev, tabent_r2); - b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); - } - - return 0; -} - -/************************************************** - * Basic PHY ops. - **************************************************/ - -static int b43_nphy_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_n *nphy; - - nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); - if (!nphy) - return -ENOMEM; - - dev->phy.n = nphy; - - return 0; -} - -static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - memset(nphy, 0, sizeof(*nphy)); - - nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); - nphy->spur_avoid = (phy->rev >= 3) ? - B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE; - nphy->gain_boost = true; /* this way we follow wl, assume it is true */ - nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ - nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ - nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ - /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is - * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ - nphy->tx_pwr_idx[0] = 128; - nphy->tx_pwr_idx[1] = 128; - - /* Hardware TX power control and 5GHz power gain */ - nphy->txpwrctrl = false; - nphy->pwg_gain_5ghz = false; - if (dev->phy.rev >= 3 || - (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && - (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { - nphy->txpwrctrl = true; - nphy->pwg_gain_5ghz = true; - } else if (sprom->revision >= 4) { - if (dev->phy.rev >= 2 && - (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) { - nphy->txpwrctrl = true; -#ifdef CONFIG_B43_SSB - if (dev->dev->bus_type == B43_BUS_SSB && - dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { - struct pci_dev *pdev = - dev->dev->sdev->bus->host_pci; - if (pdev->device == 0x4328 || - pdev->device == 0x432a) - nphy->pwg_gain_5ghz = true; - } -#endif - } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) { - nphy->pwg_gain_5ghz = true; - } - } - - if (dev->phy.rev >= 3) { - nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2; - nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2; - } -} - -static void b43_nphy_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_n *nphy = phy->n; - - kfree(nphy); - phy->n = NULL; -} - -static int b43_nphy_op_init(struct b43_wldev *dev) -{ - return b43_phy_initn(dev); -} - -static inline void check_phyreg(struct b43_wldev *dev, u16 offset) -{ -#if B43_DEBUG - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { - /* OFDM registers are onnly available on A/G-PHYs */ - b43err(dev->wl, "Invalid OFDM PHY access at " - "0x%04X on N-PHY\n", offset); - dump_stack(); - } - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { - /* Ext-G registers are only available on G-PHYs */ - b43err(dev->wl, "Invalid EXT-G PHY access at " - "0x%04X on N-PHY\n", offset); - dump_stack(); - } -#endif /* B43_DEBUG */ -} - -static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, - u16 set) -{ - check_phyreg(dev, reg); - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); - dev->phy.writes_counter = 1; -} - -static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(dev->phy.rev < 7 && reg == 1); - - if (dev->phy.rev >= 7) - reg |= 0x200; /* Radio 0x2057 */ - else - reg |= 0x100; - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); -} - -static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(dev->phy.rev < 7 && reg == 1); - - b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); -} - -/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ -static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - struct b43_phy *phy = &dev->phy; - - if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) - b43err(dev->wl, "MAC not suspended\n"); - - if (blocked) { - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 8) { - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_CHIP0PU); - } else if (phy->rev >= 7) { - /* Nothing needed */ - } else if (phy->rev >= 3) { - b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, - ~B43_NPHY_RFCTL_CMD_CHIP0PU); - - b43_radio_mask(dev, 0x09, ~0x2); - - b43_radio_write(dev, 0x204D, 0); - b43_radio_write(dev, 0x2053, 0); - b43_radio_write(dev, 0x2058, 0); - b43_radio_write(dev, 0x205E, 0); - b43_radio_mask(dev, 0x2062, ~0xF0); - b43_radio_write(dev, 0x2064, 0); - - b43_radio_write(dev, 0x304D, 0); - b43_radio_write(dev, 0x3053, 0); - b43_radio_write(dev, 0x3058, 0); - b43_radio_write(dev, 0x305E, 0); - b43_radio_mask(dev, 0x3062, ~0xF0); - b43_radio_write(dev, 0x3064, 0); - } - } else { - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 7) { - if (!dev->phy.radio_on) - b43_radio_2057_init(dev); - b43_switch_channel(dev, dev->phy.channel); - } else if (phy->rev >= 3) { - if (!dev->phy.radio_on) - b43_radio_init2056(dev); - b43_switch_channel(dev, dev->phy.channel); - } else { - b43_radio_init2055(dev); - } - } -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ -static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) -{ - struct b43_phy *phy = &dev->phy; - u16 override = on ? 0x0 : 0x7FFF; - u16 core = on ? 0xD : 0x00FD; - - if (phy->rev >= 19) { - /* TODO */ - } else if (phy->rev >= 3) { - if (on) { - b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); - b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); - } else { - b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); - b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); - b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); - } - } else { - b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); - } -} - -static int b43_nphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; - enum nl80211_channel_type channel_type = - cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if ((new_channel < 1) || (new_channel > 14)) - return -EINVAL; - } else { - if (new_channel > 200) - return -EINVAL; - } - - return b43_nphy_set_channel(dev, channel, channel_type); -} - -static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) -{ - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - return 1; - return 36; -} - -const struct b43_phy_operations b43_phyops_n = { - .allocate = b43_nphy_op_allocate, - .free = b43_nphy_op_free, - .prepare_structs = b43_nphy_op_prepare_structs, - .init = b43_nphy_op_init, - .phy_maskset = b43_nphy_op_maskset, - .radio_read = b43_nphy_op_radio_read, - .radio_write = b43_nphy_op_radio_write, - .software_rfkill = b43_nphy_op_software_rfkill, - .switch_analog = b43_nphy_op_switch_analog, - .switch_channel = b43_nphy_op_switch_channel, - .get_default_chan = b43_nphy_op_get_default_chan, - .recalc_txpower = b43_nphy_op_recalc_txpower, -}; diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h deleted file mode 100644 index a6da2c31a..000000000 --- a/drivers/net/wireless/b43/phy_n.h +++ /dev/null @@ -1,1007 +0,0 @@ -#ifndef B43_NPHY_H_ -#define B43_NPHY_H_ - -#include "phy_common.h" -#include "ppr.h" - - -/* N-PHY registers. */ - -#define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */ -#define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */ -#define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ -#define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */ -#define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */ -#define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */ -#define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ -#define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */ -#define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */ -#define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */ -#define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */ -#define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */ - -#define B43_NPHY_C1_DESPWR B43_PHY_N(0x018) /* Core 1 desired power */ -#define B43_NPHY_C1_CCK_DESPWR B43_PHY_N(0x019) /* Core 1 CCK desired power */ -#define B43_NPHY_C1_BCLIPBKOFF B43_PHY_N(0x01A) /* Core 1 barely clip backoff */ -#define B43_NPHY_C1_CCK_BCLIPBKOFF B43_PHY_N(0x01B) /* Core 1 CCK barely clip backoff */ -#define B43_NPHY_C1_CGAINI B43_PHY_N(0x01C) /* Core 1 compute gain info */ -#define B43_NPHY_C1_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ -#define B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT 0 -#define B43_NPHY_C1_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ -#define B43_NPHY_C1_CGAINI_CLIPGBKOFF_SHIFT 5 -#define B43_NPHY_C1_CGAINI_GAINSTEP 0x1C00 /* Gain step */ -#define B43_NPHY_C1_CGAINI_GAINSTEP_SHIFT 10 -#define B43_NPHY_C1_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ -#define B43_NPHY_C1_CCK_CGAINI B43_PHY_N(0x01D) /* Core 1 CCK compute gain info */ -#define B43_NPHY_C1_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ -#define B43_NPHY_C1_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ -#define B43_NPHY_C1_MINMAX_GAIN B43_PHY_N(0x01E) /* Core 1 min/max gain */ -#define B43_NPHY_C1_MINGAIN 0x00FF /* Minimum gain */ -#define B43_NPHY_C1_MINGAIN_SHIFT 0 -#define B43_NPHY_C1_MAXGAIN 0xFF00 /* Maximum gain */ -#define B43_NPHY_C1_MAXGAIN_SHIFT 8 -#define B43_NPHY_C1_CCK_MINMAX_GAIN B43_PHY_N(0x01F) /* Core 1 CCK min/max gain */ -#define B43_NPHY_C1_CCK_MINGAIN 0x00FF /* Minimum gain */ -#define B43_NPHY_C1_CCK_MINGAIN_SHIFT 0 -#define B43_NPHY_C1_CCK_MAXGAIN 0xFF00 /* Maximum gain */ -#define B43_NPHY_C1_CCK_MAXGAIN_SHIFT 8 -#define B43_NPHY_C1_INITGAIN B43_PHY_N(0x020) /* Core 1 initial gain code */ -#define B43_NPHY_C1_INITGAIN_EXTLNA 0x0001 /* External LNA index */ -#define B43_NPHY_C1_INITGAIN_LNA 0x0006 /* LNA index */ -#define B43_NPHY_C1_INITGAIN_LNAIDX_SHIFT 1 -#define B43_NPHY_C1_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ -#define B43_NPHY_C1_INITGAIN_HPVGA1_SHIFT 3 -#define B43_NPHY_C1_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ -#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 -#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ -#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ -#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020) -#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ -#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021) -#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ -#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022) -#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ -#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023) -#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ -#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024) -#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ -#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ -#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ -#define B43_NPHY_C1_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ -#define B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT 0 -#define B43_NPHY_C1_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ -#define B43_NPHY_C1_CLIPWBTHRES_CLIP1_SHIFT 6 -#define B43_NPHY_C1_W1THRES B43_PHY_N(0x028) /* Core 1 W1 threshold */ -#define B43_NPHY_C1_EDTHRES B43_PHY_N(0x029) /* Core 1 ED threshold */ -#define B43_NPHY_C1_SMSIGTHRES B43_PHY_N(0x02A) /* Core 1 small sig threshold */ -#define B43_NPHY_C1_NBCLIPTHRES B43_PHY_N(0x02B) /* Core 1 NB clip threshold */ -#define B43_NPHY_C1_CLIP1THRES B43_PHY_N(0x02C) /* Core 1 clip1 threshold */ -#define B43_NPHY_C1_CLIP2THRES B43_PHY_N(0x02D) /* Core 1 clip2 threshold */ - -#define B43_NPHY_C2_DESPWR B43_PHY_N(0x02E) /* Core 2 desired power */ -#define B43_NPHY_C2_CCK_DESPWR B43_PHY_N(0x02F) /* Core 2 CCK desired power */ -#define B43_NPHY_C2_BCLIPBKOFF B43_PHY_N(0x030) /* Core 2 barely clip backoff */ -#define B43_NPHY_C2_CCK_BCLIPBKOFF B43_PHY_N(0x031) /* Core 2 CCK barely clip backoff */ -#define B43_NPHY_C2_CGAINI B43_PHY_N(0x032) /* Core 2 compute gain info */ -#define B43_NPHY_C2_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ -#define B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT 0 -#define B43_NPHY_C2_CGAINI_CLIPGBKOFF 0x03E0 /* Clip gain backoff */ -#define B43_NPHY_C2_CGAINI_CLIPGBKOFF_SHIFT 5 -#define B43_NPHY_C2_CGAINI_GAINSTEP 0x1C00 /* Gain step */ -#define B43_NPHY_C2_CGAINI_GAINSTEP_SHIFT 10 -#define B43_NPHY_C2_CGAINI_CL2DETECT 0x2000 /* Clip 2 detect mask */ -#define B43_NPHY_C2_CCK_CGAINI B43_PHY_N(0x033) /* Core 2 CCK compute gain info */ -#define B43_NPHY_C2_CCK_CGAINI_GAINBKOFF 0x001F /* Gain backoff */ -#define B43_NPHY_C2_CCK_CGAINI_CLIPGBKOFF 0x01E0 /* CCK barely clip gain backoff */ -#define B43_NPHY_C2_MINMAX_GAIN B43_PHY_N(0x034) /* Core 2 min/max gain */ -#define B43_NPHY_C2_MINGAIN 0x00FF /* Minimum gain */ -#define B43_NPHY_C2_MINGAIN_SHIFT 0 -#define B43_NPHY_C2_MAXGAIN 0xFF00 /* Maximum gain */ -#define B43_NPHY_C2_MAXGAIN_SHIFT 8 -#define B43_NPHY_C2_CCK_MINMAX_GAIN B43_PHY_N(0x035) /* Core 2 CCK min/max gain */ -#define B43_NPHY_C2_CCK_MINGAIN 0x00FF /* Minimum gain */ -#define B43_NPHY_C2_CCK_MINGAIN_SHIFT 0 -#define B43_NPHY_C2_CCK_MAXGAIN 0xFF00 /* Maximum gain */ -#define B43_NPHY_C2_CCK_MAXGAIN_SHIFT 8 -#define B43_NPHY_C2_INITGAIN B43_PHY_N(0x036) /* Core 2 initial gain code */ -#define B43_NPHY_C2_INITGAIN_EXTLNA 0x0001 /* External LNA index */ -#define B43_NPHY_C2_INITGAIN_LNA 0x0006 /* LNA index */ -#define B43_NPHY_C2_INITGAIN_LNAIDX_SHIFT 1 -#define B43_NPHY_C2_INITGAIN_HPVGA1 0x0078 /* HPVGA1 index */ -#define B43_NPHY_C2_INITGAIN_HPVGA1_SHIFT 3 -#define B43_NPHY_C2_INITGAIN_HPVGA2 0x0F80 /* HPVGA2 index */ -#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 -#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ -#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ -#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036) -#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ -#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037) -#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ -#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038) -#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ -#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039) -#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ -#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A) -#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ -#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ -#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ -#define B43_NPHY_C2_CLIPWBTHRES_CLIP2 0x003F /* Clip 2 */ -#define B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT 0 -#define B43_NPHY_C2_CLIPWBTHRES_CLIP1 0x0FC0 /* Clip 1 */ -#define B43_NPHY_C2_CLIPWBTHRES_CLIP1_SHIFT 6 -#define B43_NPHY_C2_W1THRES B43_PHY_N(0x03E) /* Core 2 W1 threshold */ -#define B43_NPHY_C2_EDTHRES B43_PHY_N(0x03F) /* Core 2 ED threshold */ -#define B43_NPHY_C2_SMSIGTHRES B43_PHY_N(0x040) /* Core 2 small sig threshold */ -#define B43_NPHY_C2_NBCLIPTHRES B43_PHY_N(0x041) /* Core 2 NB clip threshold */ -#define B43_NPHY_C2_CLIP1THRES B43_PHY_N(0x042) /* Core 2 clip1 threshold */ -#define B43_NPHY_C2_CLIP2THRES B43_PHY_N(0x043) /* Core 2 clip2 threshold */ - -#define B43_NPHY_CRS_THRES1 B43_PHY_N(0x044) /* CRS threshold 1 */ -#define B43_NPHY_CRS_THRES2 B43_PHY_N(0x045) /* CRS threshold 2 */ -#define B43_NPHY_CRS_THRES3 B43_PHY_N(0x046) /* CRS threshold 3 */ -#define B43_NPHY_CRSCTL B43_PHY_N(0x047) /* CRS control */ -#define B43_NPHY_DCFADDR B43_PHY_N(0x048) /* DC filter address */ -#define B43_NPHY_RXF20_NUM0 B43_PHY_N(0x049) /* RX filter 20 numerator 0 */ -#define B43_NPHY_RXF20_NUM1 B43_PHY_N(0x04A) /* RX filter 20 numerator 1 */ -#define B43_NPHY_RXF20_NUM2 B43_PHY_N(0x04B) /* RX filter 20 numerator 2 */ -#define B43_NPHY_RXF20_DENOM0 B43_PHY_N(0x04C) /* RX filter 20 denominator 0 */ -#define B43_NPHY_RXF20_DENOM1 B43_PHY_N(0x04D) /* RX filter 20 denominator 1 */ -#define B43_NPHY_RXF20_NUM10 B43_PHY_N(0x04E) /* RX filter 20 numerator 10 */ -#define B43_NPHY_RXF20_NUM11 B43_PHY_N(0x04F) /* RX filter 20 numerator 11 */ -#define B43_NPHY_RXF20_NUM12 B43_PHY_N(0x050) /* RX filter 20 numerator 12 */ -#define B43_NPHY_RXF20_DENOM10 B43_PHY_N(0x051) /* RX filter 20 denominator 10 */ -#define B43_NPHY_RXF20_DENOM11 B43_PHY_N(0x052) /* RX filter 20 denominator 11 */ -#define B43_NPHY_RXF40_NUM0 B43_PHY_N(0x053) /* RX filter 40 numerator 0 */ -#define B43_NPHY_RXF40_NUM1 B43_PHY_N(0x054) /* RX filter 40 numerator 1 */ -#define B43_NPHY_RXF40_NUM2 B43_PHY_N(0x055) /* RX filter 40 numerator 2 */ -#define B43_NPHY_RXF40_DENOM0 B43_PHY_N(0x056) /* RX filter 40 denominator 0 */ -#define B43_NPHY_RXF40_DENOM1 B43_PHY_N(0x057) /* RX filter 40 denominator 1 */ -#define B43_NPHY_RXF40_NUM10 B43_PHY_N(0x058) /* RX filter 40 numerator 10 */ -#define B43_NPHY_RXF40_NUM11 B43_PHY_N(0x059) /* RX filter 40 numerator 11 */ -#define B43_NPHY_RXF40_NUM12 B43_PHY_N(0x05A) /* RX filter 40 numerator 12 */ -#define B43_NPHY_RXF40_DENOM10 B43_PHY_N(0x05B) /* RX filter 40 denominator 10 */ -#define B43_NPHY_RXF40_DENOM11 B43_PHY_N(0x05C) /* RX filter 40 denominator 11 */ -#define B43_NPHY_PPROC_RSTLEN B43_PHY_N(0x060) /* Packet processing reset length */ -#define B43_NPHY_INITCARR_DLEN B43_PHY_N(0x061) /* Initial carrier detection length */ -#define B43_NPHY_CLIP1CARR_DLEN B43_PHY_N(0x062) /* Clip1 carrier detection length */ -#define B43_NPHY_CLIP2CARR_DLEN B43_PHY_N(0x063) /* Clip2 carrier detection length */ -#define B43_NPHY_INITGAIN_SLEN B43_PHY_N(0x064) /* Initial gain settle length */ -#define B43_NPHY_CLIP1GAIN_SLEN B43_PHY_N(0x065) /* Clip1 gain settle length */ -#define B43_NPHY_CLIP2GAIN_SLEN B43_PHY_N(0x066) /* Clip2 gain settle length */ -#define B43_NPHY_PACKGAIN_SLEN B43_PHY_N(0x067) /* Packet gain settle length */ -#define B43_NPHY_CARRSRC_TLEN B43_PHY_N(0x068) /* Carrier search timeout length */ -#define B43_NPHY_TISRC_TLEN B43_PHY_N(0x069) /* Timing search timeout length */ -#define B43_NPHY_ENDROP_TLEN B43_PHY_N(0x06A) /* Energy drop timeout length */ -#define B43_NPHY_CLIP1_NBDWELL_LEN B43_PHY_N(0x06B) /* Clip1 NB dwell length */ -#define B43_NPHY_CLIP2_NBDWELL_LEN B43_PHY_N(0x06C) /* Clip2 NB dwell length */ -#define B43_NPHY_W1CLIP1_DWELL_LEN B43_PHY_N(0x06D) /* W1 clip1 dwell length */ -#define B43_NPHY_W1CLIP2_DWELL_LEN B43_PHY_N(0x06E) /* W1 clip2 dwell length */ -#define B43_NPHY_W2CLIP1_DWELL_LEN B43_PHY_N(0x06F) /* W2 clip1 dwell length */ -#define B43_NPHY_PLOAD_CSENSE_EXTLEN B43_PHY_N(0x070) /* Payload carrier sense extension length */ -#define B43_NPHY_EDROP_CSENSE_EXTLEN B43_PHY_N(0x071) /* Energy drop carrier sense extension length */ -#define B43_NPHY_TABLE_ADDR B43_PHY_N(0x072) /* Table address */ -#define B43_NPHY_TABLE_DATALO B43_PHY_N(0x073) /* Table data low */ -#define B43_NPHY_TABLE_DATAHI B43_PHY_N(0x074) /* Table data high */ -#define B43_NPHY_WWISE_LENIDX B43_PHY_N(0x075) /* WWiSE length index */ -#define B43_NPHY_TGNSYNC_LENIDX B43_PHY_N(0x076) /* TGNsync length index */ -#define B43_NPHY_TXMACIF_HOLDOFF B43_PHY_N(0x077) /* TX MAC IF Hold off */ -#define B43_NPHY_RFCTL_CMD B43_PHY_N(0x078) /* RF control (command) */ -#define B43_NPHY_RFCTL_CMD_START 0x0001 /* Start sequence */ -#define B43_NPHY_RFCTL_CMD_RXTX 0x0002 /* RX/TX */ -#define B43_NPHY_RFCTL_CMD_CORESEL 0x0038 /* Core select */ -#define B43_NPHY_RFCTL_CMD_CORESEL_SHIFT 3 -#define B43_NPHY_RFCTL_CMD_PORFORCE 0x0040 /* POR force */ -#define B43_NPHY_RFCTL_CMD_OEPORFORCE 0x0080 /* OE POR force */ -#define B43_NPHY_RFCTL_CMD_RXEN 0x0100 /* RX enable */ -#define B43_NPHY_RFCTL_CMD_TXEN 0x0200 /* TX enable */ -#define B43_NPHY_RFCTL_CMD_CHIP0PU 0x0400 /* Chip0 PU */ -#define B43_NPHY_RFCTL_CMD_EN 0x0800 /* Radio enabled */ -#define B43_NPHY_RFCTL_CMD_SEQENCORE 0xF000 /* Seq en core */ -#define B43_NPHY_RFCTL_CMD_SEQENCORE_SHIFT 12 -#define B43_NPHY_RFCTL_RSSIO1 B43_PHY_N(0x07A) /* RF control (RSSI others 1) */ -#define B43_NPHY_RFCTL_RSSIO1_RXPD 0x0001 /* RX PD */ -#define B43_NPHY_RFCTL_RSSIO1_TXPD 0x0002 /* TX PD */ -#define B43_NPHY_RFCTL_RSSIO1_PAPD 0x0004 /* PA PD */ -#define B43_NPHY_RFCTL_RSSIO1_RSSICTL 0x0030 /* RSSI control */ -#define B43_NPHY_RFCTL_RSSIO1_LPFBW 0x00C0 /* LPF bandwidth */ -#define B43_NPHY_RFCTL_RSSIO1_HPFBWHI 0x0100 /* HPF bandwidth high */ -#define B43_NPHY_RFCTL_RSSIO1_HIQDISCO 0x0200 /* HIQ dis core */ -#define B43_NPHY_RFCTL_RXG1 B43_PHY_N(0x07B) /* RF control (RX gain 1) */ -#define B43_NPHY_RFCTL_TXG1 B43_PHY_N(0x07C) /* RF control (TX gain 1) */ -#define B43_NPHY_RFCTL_RSSIO2 B43_PHY_N(0x07D) /* RF control (RSSI others 2) */ -#define B43_NPHY_RFCTL_RSSIO2_RXPD 0x0001 /* RX PD */ -#define B43_NPHY_RFCTL_RSSIO2_TXPD 0x0002 /* TX PD */ -#define B43_NPHY_RFCTL_RSSIO2_PAPD 0x0004 /* PA PD */ -#define B43_NPHY_RFCTL_RSSIO2_RSSICTL 0x0030 /* RSSI control */ -#define B43_NPHY_RFCTL_RSSIO2_LPFBW 0x00C0 /* LPF bandwidth */ -#define B43_NPHY_RFCTL_RSSIO2_HPFBWHI 0x0100 /* HPF bandwidth high */ -#define B43_NPHY_RFCTL_RSSIO2_HIQDISCO 0x0200 /* HIQ dis core */ -#define B43_NPHY_RFCTL_RXG2 B43_PHY_N(0x07E) /* RF control (RX gain 2) */ -#define B43_NPHY_RFCTL_TXG2 B43_PHY_N(0x07F) /* RF control (TX gain 2) */ -#define B43_NPHY_RFCTL_RSSIO3 B43_PHY_N(0x080) /* RF control (RSSI others 3) */ -#define B43_NPHY_RFCTL_RSSIO3_RXPD 0x0001 /* RX PD */ -#define B43_NPHY_RFCTL_RSSIO3_TXPD 0x0002 /* TX PD */ -#define B43_NPHY_RFCTL_RSSIO3_PAPD 0x0004 /* PA PD */ -#define B43_NPHY_RFCTL_RSSIO3_RSSICTL 0x0030 /* RSSI control */ -#define B43_NPHY_RFCTL_RSSIO3_LPFBW 0x00C0 /* LPF bandwidth */ -#define B43_NPHY_RFCTL_RSSIO3_HPFBWHI 0x0100 /* HPF bandwidth high */ -#define B43_NPHY_RFCTL_RSSIO3_HIQDISCO 0x0200 /* HIQ dis core */ -#define B43_NPHY_RFCTL_RXG3 B43_PHY_N(0x081) /* RF control (RX gain 3) */ -#define B43_NPHY_RFCTL_TXG3 B43_PHY_N(0x082) /* RF control (TX gain 3) */ -#define B43_NPHY_RFCTL_RSSIO4 B43_PHY_N(0x083) /* RF control (RSSI others 4) */ -#define B43_NPHY_RFCTL_RSSIO4_RXPD 0x0001 /* RX PD */ -#define B43_NPHY_RFCTL_RSSIO4_TXPD 0x0002 /* TX PD */ -#define B43_NPHY_RFCTL_RSSIO4_PAPD 0x0004 /* PA PD */ -#define B43_NPHY_RFCTL_RSSIO4_RSSICTL 0x0030 /* RSSI control */ -#define B43_NPHY_RFCTL_RSSIO4_LPFBW 0x00C0 /* LPF bandwidth */ -#define B43_NPHY_RFCTL_RSSIO4_HPFBWHI 0x0100 /* HPF bandwidth high */ -#define B43_NPHY_RFCTL_RSSIO4_HIQDISCO 0x0200 /* HIQ dis core */ -#define B43_NPHY_RFCTL_RXG4 B43_PHY_N(0x084) /* RF control (RX gain 4) */ -#define B43_NPHY_RFCTL_TXG4 B43_PHY_N(0x085) /* RF control (TX gain 4) */ -#define B43_NPHY_C1_TXIQ_COMP_OFF B43_PHY_N(0x087) /* Core 1 TX I/Q comp offset */ -#define B43_NPHY_C2_TXIQ_COMP_OFF B43_PHY_N(0x088) /* Core 2 TX I/Q comp offset */ -#define B43_NPHY_C1_TXCTL B43_PHY_N(0x08B) /* Core 1 TX control */ -#define B43_NPHY_C2_TXCTL B43_PHY_N(0x08C) /* Core 2 TX control */ -#define B43_NPHY_AFECTL_OVER1 B43_PHY_N(0x08F) /* AFE control override 1 */ -#define B43_NPHY_SCRAM_SIGCTL B43_PHY_N(0x090) /* Scram signal control */ -#define B43_NPHY_SCRAM_SIGCTL_INITST 0x007F /* Initial state value */ -#define B43_NPHY_SCRAM_SIGCTL_INITST_SHIFT 0 -#define B43_NPHY_SCRAM_SIGCTL_SCM 0x0080 /* Scram control mode */ -#define B43_NPHY_SCRAM_SIGCTL_SICE 0x0100 /* Scram index control enable */ -#define B43_NPHY_SCRAM_SIGCTL_START 0xFE00 /* Scram start bit */ -#define B43_NPHY_SCRAM_SIGCTL_START_SHIFT 9 -#define B43_NPHY_RFCTL_INTC1 B43_PHY_N(0x091) /* RF control (intc 1) */ -#define B43_NPHY_RFCTL_INTC2 B43_PHY_N(0x092) /* RF control (intc 2) */ -#define B43_NPHY_RFCTL_INTC3 B43_PHY_N(0x093) /* RF control (intc 3) */ -#define B43_NPHY_RFCTL_INTC4 B43_PHY_N(0x094) /* RF control (intc 4) */ -#define B43_NPHY_NRDTO_WWISE B43_PHY_N(0x095) /* # datatones WWiSE */ -#define B43_NPHY_NRDTO_TGNSYNC B43_PHY_N(0x096) /* # datatones TGNsync */ -#define B43_NPHY_SIGFMOD_WWISE B43_PHY_N(0x097) /* Signal field mod WWiSE */ -#define B43_NPHY_LEG_SIGFMOD_11N B43_PHY_N(0x098) /* Legacy signal field mod 11n */ -#define B43_NPHY_HT_SIGFMOD_11N B43_PHY_N(0x099) /* HT signal field mod 11n */ -#define B43_NPHY_C1_RXIQ_COMPA0 B43_PHY_N(0x09A) /* Core 1 RX I/Q comp A0 */ -#define B43_NPHY_C1_RXIQ_COMPB0 B43_PHY_N(0x09B) /* Core 1 RX I/Q comp B0 */ -#define B43_NPHY_C2_RXIQ_COMPA1 B43_PHY_N(0x09C) /* Core 2 RX I/Q comp A1 */ -#define B43_NPHY_C2_RXIQ_COMPB1 B43_PHY_N(0x09D) /* Core 2 RX I/Q comp B1 */ -#define B43_NPHY_RXCTL B43_PHY_N(0x0A0) /* RX control */ -#define B43_NPHY_RXCTL_BSELU20 0x0010 /* Band select upper 20 */ -#define B43_NPHY_RXCTL_RIFSEN 0x0080 /* RIFS enable */ -#define B43_NPHY_RFSEQMODE B43_PHY_N(0x0A1) /* RF seq mode */ -#define B43_NPHY_RFSEQMODE_CAOVER 0x0001 /* Core active override */ -#define B43_NPHY_RFSEQMODE_TROVER 0x0002 /* Trigger override */ -#define B43_NPHY_RFSEQCA B43_PHY_N(0x0A2) /* RF seq core active */ -#define B43_NPHY_RFSEQCA_TXEN 0x000F /* TX enable */ -#define B43_NPHY_RFSEQCA_TXEN_SHIFT 0 -#define B43_NPHY_RFSEQCA_RXEN 0x00F0 /* RX enable */ -#define B43_NPHY_RFSEQCA_RXEN_SHIFT 4 -#define B43_NPHY_RFSEQCA_TXDIS 0x0F00 /* TX disable */ -#define B43_NPHY_RFSEQCA_TXDIS_SHIFT 8 -#define B43_NPHY_RFSEQCA_RXDIS 0xF000 /* RX disable */ -#define B43_NPHY_RFSEQCA_RXDIS_SHIFT 12 -#define B43_NPHY_RFSEQTR B43_PHY_N(0x0A3) /* RF seq trigger */ -#define B43_NPHY_RFSEQTR_RX2TX 0x0001 /* RX2TX */ -#define B43_NPHY_RFSEQTR_TX2RX 0x0002 /* TX2RX */ -#define B43_NPHY_RFSEQTR_UPGH 0x0004 /* Update gain H */ -#define B43_NPHY_RFSEQTR_UPGL 0x0008 /* Update gain L */ -#define B43_NPHY_RFSEQTR_UPGU 0x0010 /* Update gain U */ -#define B43_NPHY_RFSEQTR_RST2RX 0x0020 /* Reset to RX */ -#define B43_NPHY_RFSEQST B43_PHY_N(0x0A4) /* RF seq status. Values same as trigger. */ -#define B43_NPHY_AFECTL_OVER B43_PHY_N(0x0A5) /* AFE control override */ -#define B43_NPHY_AFECTL_C1 B43_PHY_N(0x0A6) /* AFE control core 1 */ -#define B43_NPHY_AFECTL_C2 B43_PHY_N(0x0A7) /* AFE control core 2 */ -#define B43_NPHY_AFECTL_C3 B43_PHY_N(0x0A8) /* AFE control core 3 */ -#define B43_NPHY_AFECTL_C4 B43_PHY_N(0x0A9) /* AFE control core 4 */ -#define B43_NPHY_AFECTL_DACGAIN1 B43_PHY_N(0x0AA) /* AFE control DAC gain 1 */ -#define B43_NPHY_AFECTL_DACGAIN2 B43_PHY_N(0x0AB) /* AFE control DAC gain 2 */ -#define B43_NPHY_AFECTL_DACGAIN3 B43_PHY_N(0x0AC) /* AFE control DAC gain 3 */ -#define B43_NPHY_AFECTL_DACGAIN4 B43_PHY_N(0x0AD) /* AFE control DAC gain 4 */ -#define B43_NPHY_STR_ADDR1 B43_PHY_N(0x0AE) /* STR address 1 */ -#define B43_NPHY_STR_ADDR2 B43_PHY_N(0x0AF) /* STR address 2 */ -#define B43_NPHY_CLASSCTL B43_PHY_N(0x0B0) /* Classifier control */ -#define B43_NPHY_CLASSCTL_CCKEN 0x0001 /* CCK enable */ -#define B43_NPHY_CLASSCTL_OFDMEN 0x0002 /* OFDM enable */ -#define B43_NPHY_CLASSCTL_WAITEDEN 0x0004 /* Waited enable */ -#define B43_NPHY_IQFLIP B43_PHY_N(0x0B1) /* I/Q flip */ -#define B43_NPHY_IQFLIP_ADC1 0x0001 /* ADC1 */ -#define B43_NPHY_IQFLIP_ADC2 0x0010 /* ADC2 */ -#define B43_NPHY_SISO_SNR_THRES B43_PHY_N(0x0B2) /* SISO SNR threshold */ -#define B43_NPHY_SIGMA_N_MULT B43_PHY_N(0x0B3) /* Sigma N multiplier */ -#define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */ -#define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */ -#define B43_NPHY_MLPARM B43_PHY_N(0x0B6) /* ML parameters */ -#define B43_NPHY_MLCTL B43_PHY_N(0x0B7) /* ML control */ -#define B43_NPHY_WWISE_20NCYCDAT B43_PHY_N(0x0B8) /* WWiSE 20 N cyc data */ -#define B43_NPHY_WWISE_40NCYCDAT B43_PHY_N(0x0B9) /* WWiSE 40 N cyc data */ -#define B43_NPHY_TGNSYNC_20NCYCDAT B43_PHY_N(0x0BA) /* TGNsync 20 N cyc data */ -#define B43_NPHY_TGNSYNC_40NCYCDAT B43_PHY_N(0x0BB) /* TGNsync 40 N cyc data */ -#define B43_NPHY_INITSWIZP B43_PHY_N(0x0BC) /* Initial swizzle pattern */ -#define B43_NPHY_TXTAILCNT B43_PHY_N(0x0BD) /* TX tail count value */ -#define B43_NPHY_BPHY_CTL1 B43_PHY_N(0x0BE) /* B PHY control 1 */ -#define B43_NPHY_BPHY_CTL2 B43_PHY_N(0x0BF) /* B PHY control 2 */ -#define B43_NPHY_BPHY_CTL2_LUT 0x001F /* LUT index */ -#define B43_NPHY_BPHY_CTL2_LUT_SHIFT 0 -#define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */ -#define B43_NPHY_BPHY_CTL2_MACDEL_SHIFT 5 -#define B43_NPHY_IQLOCAL_CMD B43_PHY_N(0x0C0) /* I/Q LO cal command */ -#define B43_NPHY_IQLOCAL_CMD_EN 0x8000 -#define B43_NPHY_IQLOCAL_CMDNNUM B43_PHY_N(0x0C1) /* I/Q LO cal command N num */ -#define B43_NPHY_IQLOCAL_CMDGCTL B43_PHY_N(0x0C2) /* I/Q LO cal command G control */ -#define B43_NPHY_SAMP_CMD B43_PHY_N(0x0C3) /* Sample command */ -#define B43_NPHY_SAMP_CMD_STOP 0x0002 /* Stop */ -#define B43_NPHY_SAMP_LOOPCNT B43_PHY_N(0x0C4) /* Sample loop count */ -#define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */ -#define B43_NPHY_SAMP_DEPCNT B43_PHY_N(0x0C6) /* Sample depth count */ -#define B43_NPHY_SAMP_STAT B43_PHY_N(0x0C7) /* Sample status */ -#define B43_NPHY_GPIO_LOOEN B43_PHY_N(0x0C8) /* GPIO low out enable */ -#define B43_NPHY_GPIO_HIOEN B43_PHY_N(0x0C9) /* GPIO high out enable */ -#define B43_NPHY_GPIO_SEL B43_PHY_N(0x0CA) /* GPIO select */ -#define B43_NPHY_GPIO_CLKCTL B43_PHY_N(0x0CB) /* GPIO clock control */ -#define B43_NPHY_TXF_20CO_AS0 B43_PHY_N(0x0CC) /* TX filter 20 coeff A stage 0 */ -#define B43_NPHY_TXF_20CO_AS1 B43_PHY_N(0x0CD) /* TX filter 20 coeff A stage 1 */ -#define B43_NPHY_TXF_20CO_AS2 B43_PHY_N(0x0CE) /* TX filter 20 coeff A stage 2 */ -#define B43_NPHY_TXF_20CO_B32S0 B43_PHY_N(0x0CF) /* TX filter 20 coeff B32 stage 0 */ -#define B43_NPHY_TXF_20CO_B1S0 B43_PHY_N(0x0D0) /* TX filter 20 coeff B1 stage 0 */ -#define B43_NPHY_TXF_20CO_B32S1 B43_PHY_N(0x0D1) /* TX filter 20 coeff B32 stage 1 */ -#define B43_NPHY_TXF_20CO_B1S1 B43_PHY_N(0x0D2) /* TX filter 20 coeff B1 stage 1 */ -#define B43_NPHY_TXF_20CO_B32S2 B43_PHY_N(0x0D3) /* TX filter 20 coeff B32 stage 2 */ -#define B43_NPHY_TXF_20CO_B1S2 B43_PHY_N(0x0D4) /* TX filter 20 coeff B1 stage 2 */ -#define B43_NPHY_SIGFLDTOL B43_PHY_N(0x0D5) /* Signal fld tolerance */ -#define B43_NPHY_TXSERFLD B43_PHY_N(0x0D6) /* TX service field */ -#define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */ -#define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */ -#define B43_NPHY_TGNSYNC_SCRAMI0 B43_PHY_N(0x0D9) /* TGNsync scram init 0 */ -#define B43_NPHY_TGNSYNC_SCRAMI1 B43_PHY_N(0x0DA) /* TGNsync scram init 1 */ -#define B43_NPHY_INITSWIZPATTLEG B43_PHY_N(0x0DB) /* Initial swizzle pattern leg */ -#define B43_NPHY_BPHY_CTL3 B43_PHY_N(0x0DC) /* B PHY control 3 */ -#define B43_NPHY_BPHY_CTL3_SCALE 0x00FF /* Scale */ -#define B43_NPHY_BPHY_CTL3_SCALE_SHIFT 0 -#define B43_NPHY_BPHY_CTL3_FSC 0xFF00 /* Frame start count value */ -#define B43_NPHY_BPHY_CTL3_FSC_SHIFT 8 -#define B43_NPHY_BPHY_CTL4 B43_PHY_N(0x0DD) /* B PHY control 4 */ -#define B43_NPHY_C1_TXBBMULT B43_PHY_N(0x0DE) /* Core 1 TX BB multiplier */ -#define B43_NPHY_C2_TXBBMULT B43_PHY_N(0x0DF) /* Core 2 TX BB multiplier */ -#define B43_NPHY_TXF_40CO_AS0 B43_PHY_N(0x0E1) /* TX filter 40 coeff A stage 0 */ -#define B43_NPHY_TXF_40CO_AS1 B43_PHY_N(0x0E2) /* TX filter 40 coeff A stage 1 */ -#define B43_NPHY_TXF_40CO_AS2 B43_PHY_N(0x0E3) /* TX filter 40 coeff A stage 2 */ -#define B43_NPHY_TXF_40CO_B32S0 B43_PHY_N(0x0E4) /* TX filter 40 coeff B32 stage 0 */ -#define B43_NPHY_TXF_40CO_B1S0 B43_PHY_N(0x0E5) /* TX filter 40 coeff B1 stage 0 */ -#define B43_NPHY_TXF_40CO_B32S1 B43_PHY_N(0x0E6) /* TX filter 40 coeff B32 stage 1 */ -#define B43_NPHY_TXF_40CO_B1S1 B43_PHY_N(0x0E7) /* TX filter 40 coeff B1 stage 1 */ -#define B43_NPHY_REV3_RFCTL_OVER0 B43_PHY_N(0x0E7) -#define B43_NPHY_TXF_40CO_B32S2 B43_PHY_N(0x0E8) /* TX filter 40 coeff B32 stage 2 */ -#define B43_NPHY_TXF_40CO_B1S2 B43_PHY_N(0x0E9) /* TX filter 40 coeff B1 stage 2 */ -#define B43_NPHY_BIST_STAT2 B43_PHY_N(0x0EA) /* BIST status 2 */ -#define B43_NPHY_BIST_STAT3 B43_PHY_N(0x0EB) /* BIST status 3 */ -#define B43_NPHY_RFCTL_OVER B43_PHY_N(0x0EC) /* RF control override */ -#define B43_NPHY_REV3_RFCTL_OVER1 B43_PHY_N(0x0EC) -#define B43_NPHY_MIMOCFG B43_PHY_N(0x0ED) /* MIMO config */ -#define B43_NPHY_MIMOCFG_GFMIX 0x0004 /* Greenfield or mixed mode */ -#define B43_NPHY_MIMOCFG_AUTO 0x0100 /* Greenfield/mixed mode auto */ -#define B43_NPHY_RADAR_BLNKCTL B43_PHY_N(0x0EE) /* Radar blank control */ -#define B43_NPHY_A0RADAR_FIFOCTL B43_PHY_N(0x0EF) /* Antenna 0 radar FIFO control */ -#define B43_NPHY_A1RADAR_FIFOCTL B43_PHY_N(0x0F0) /* Antenna 1 radar FIFO control */ -#define B43_NPHY_A0RADAR_FIFODAT B43_PHY_N(0x0F1) /* Antenna 0 radar FIFO data */ -#define B43_NPHY_A1RADAR_FIFODAT B43_PHY_N(0x0F2) /* Antenna 1 radar FIFO data */ -#define B43_NPHY_RADAR_THRES0 B43_PHY_N(0x0F3) /* Radar threshold 0 */ -#define B43_NPHY_RADAR_THRES1 B43_PHY_N(0x0F4) /* Radar threshold 1 */ -#define B43_NPHY_RADAR_THRES0R B43_PHY_N(0x0F5) /* Radar threshold 0R */ -#define B43_NPHY_RADAR_THRES1R B43_PHY_N(0x0F6) /* Radar threshold 1R */ -#define B43_NPHY_CSEN_20IN40_DLEN B43_PHY_N(0x0F7) /* Carrier sense 20 in 40 dwell length */ -#define B43_NPHY_RFCTL_LUT_TRSW_LO1 B43_PHY_N(0x0F8) /* RF control LUT TRSW lower 1 */ -#define B43_NPHY_RFCTL_LUT_TRSW_UP1 B43_PHY_N(0x0F9) /* RF control LUT TRSW upper 1 */ -#define B43_NPHY_RFCTL_LUT_TRSW_LO2 B43_PHY_N(0x0FA) /* RF control LUT TRSW lower 2 */ -#define B43_NPHY_RFCTL_LUT_TRSW_UP2 B43_PHY_N(0x0FB) /* RF control LUT TRSW upper 2 */ -#define B43_NPHY_RFCTL_LUT_TRSW_LO3 B43_PHY_N(0x0FC) /* RF control LUT TRSW lower 3 */ -#define B43_NPHY_RFCTL_LUT_TRSW_UP3 B43_PHY_N(0x0FD) /* RF control LUT TRSW upper 3 */ -#define B43_NPHY_RFCTL_LUT_TRSW_LO4 B43_PHY_N(0x0FE) /* RF control LUT TRSW lower 4 */ -#define B43_NPHY_RFCTL_LUT_TRSW_UP4 B43_PHY_N(0x0FF) /* RF control LUT TRSW upper 4 */ -#define B43_NPHY_RFCTL_LUT_LNAPA1 B43_PHY_N(0x100) /* RF control LUT LNA PA 1 */ -#define B43_NPHY_RFCTL_LUT_LNAPA2 B43_PHY_N(0x101) /* RF control LUT LNA PA 2 */ -#define B43_NPHY_RFCTL_LUT_LNAPA3 B43_PHY_N(0x102) /* RF control LUT LNA PA 3 */ -#define B43_NPHY_RFCTL_LUT_LNAPA4 B43_PHY_N(0x103) /* RF control LUT LNA PA 4 */ -#define B43_NPHY_TGNSYNC_CRCM0 B43_PHY_N(0x104) /* TGNsync CRC mask 0 */ -#define B43_NPHY_TGNSYNC_CRCM1 B43_PHY_N(0x105) /* TGNsync CRC mask 1 */ -#define B43_NPHY_TGNSYNC_CRCM2 B43_PHY_N(0x106) /* TGNsync CRC mask 2 */ -#define B43_NPHY_TGNSYNC_CRCM3 B43_PHY_N(0x107) /* TGNsync CRC mask 3 */ -#define B43_NPHY_TGNSYNC_CRCM4 B43_PHY_N(0x108) /* TGNsync CRC mask 4 */ -#define B43_NPHY_CRCPOLY B43_PHY_N(0x109) /* CRC polynomial */ -#define B43_NPHY_SIGCNT B43_PHY_N(0x10A) /* # sig count */ -#define B43_NPHY_SIGSTARTBIT_CTL B43_PHY_N(0x10B) /* Sig start bit control */ -#define B43_NPHY_CRCPOLY_ORDER B43_PHY_N(0x10C) /* CRC polynomial order */ -#define B43_NPHY_RFCTL_CST0 B43_PHY_N(0x10D) /* RF control core swap table 0 */ -#define B43_NPHY_RFCTL_CST1 B43_PHY_N(0x10E) /* RF control core swap table 1 */ -#define B43_NPHY_RFCTL_CST2O B43_PHY_N(0x10F) /* RF control core swap table 2 + others */ -#define B43_NPHY_BPHY_CTL5 B43_PHY_N(0x111) /* B PHY control 5 */ -#define B43_NPHY_RFSEQ_LPFBW B43_PHY_N(0x112) /* RF seq LPF bandwidth */ -#define B43_NPHY_TSSIBIAS1 B43_PHY_N(0x114) /* TSSI bias val 1 */ -#define B43_NPHY_TSSIBIAS2 B43_PHY_N(0x115) /* TSSI bias val 2 */ -#define B43_NPHY_TSSIBIAS_BIAS 0x00FF /* Bias */ -#define B43_NPHY_TSSIBIAS_BIAS_SHIFT 0 -#define B43_NPHY_TSSIBIAS_VAL 0xFF00 /* Value */ -#define B43_NPHY_TSSIBIAS_VAL_SHIFT 8 -#define B43_NPHY_ESTPWR1 B43_PHY_N(0x118) /* Estimated power 1 */ -#define B43_NPHY_ESTPWR2 B43_PHY_N(0x119) /* Estimated power 2 */ -#define B43_NPHY_ESTPWR_PWR 0x00FF /* Estimated power */ -#define B43_NPHY_ESTPWR_PWR_SHIFT 0 -#define B43_NPHY_ESTPWR_VALID 0x0100 /* Estimated power valid */ -#define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */ -#define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */ -#define B43_NPHY_TSSI_MAXTXFDT_VAL_SHIFT 0 -#define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */ -#define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */ -#define B43_NPHY_TSSI_MAXTDT_VAL_SHIFT 0 -#define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */ -#define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */ -#define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */ -#define B43_NPHY_ITSSI_VAL_SHIFT 0 -#define B43_NPHY_TSSIMODE B43_PHY_N(0x122) /* TSSI mode */ -#define B43_NPHY_TSSIMODE_EN 0x0001 /* TSSI enable */ -#define B43_NPHY_TSSIMODE_PDEN 0x0002 /* Power det enable */ -#define B43_NPHY_RXMACIFM B43_PHY_N(0x123) /* RX Macif mode */ -#define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */ -#define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */ -#define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */ -#define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */ -#define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */ -#define B43_NPHY_IQEST_CMD B43_PHY_N(0x129) /* I/Q estimate command */ -#define B43_NPHY_IQEST_CMD_START 0x0001 /* Start */ -#define B43_NPHY_IQEST_CMD_MODE 0x0002 /* Mode */ -#define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */ -#define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */ -#define B43_NPHY_IQEST_WT_VAL_SHIFT 0 -#define B43_NPHY_IQEST_SAMCNT B43_PHY_N(0x12B) /* I/Q estimate sample count */ -#define B43_NPHY_IQEST_IQACC_LO0 B43_PHY_N(0x12C) /* I/Q estimate I/Q acc lo 0 */ -#define B43_NPHY_IQEST_IQACC_HI0 B43_PHY_N(0x12D) /* I/Q estimate I/Q acc hi 0 */ -#define B43_NPHY_IQEST_IPACC_LO0 B43_PHY_N(0x12E) /* I/Q estimate I power acc lo 0 */ -#define B43_NPHY_IQEST_IPACC_HI0 B43_PHY_N(0x12F) /* I/Q estimate I power acc hi 0 */ -#define B43_NPHY_IQEST_QPACC_LO0 B43_PHY_N(0x130) /* I/Q estimate Q power acc lo 0 */ -#define B43_NPHY_IQEST_QPACC_HI0 B43_PHY_N(0x131) /* I/Q estimate Q power acc hi 0 */ -#define B43_NPHY_IQEST_IQACC_LO1 B43_PHY_N(0x134) /* I/Q estimate I/Q acc lo 1 */ -#define B43_NPHY_IQEST_IQACC_HI1 B43_PHY_N(0x135) /* I/Q estimate I/Q acc hi 1 */ -#define B43_NPHY_IQEST_IPACC_LO1 B43_PHY_N(0x136) /* I/Q estimate I power acc lo 1 */ -#define B43_NPHY_IQEST_IPACC_HI1 B43_PHY_N(0x137) /* I/Q estimate I power acc hi 1 */ -#define B43_NPHY_IQEST_QPACC_LO1 B43_PHY_N(0x138) /* I/Q estimate Q power acc lo 1 */ -#define B43_NPHY_IQEST_QPACC_HI1 B43_PHY_N(0x139) /* I/Q estimate Q power acc hi 1 */ -#define B43_NPHY_MIMO_CRSTXEXT B43_PHY_N(0x13A) /* MIMO PHY CRS TX extension */ -#define B43_NPHY_PWRDET1 B43_PHY_N(0x13B) /* Power det 1 */ -#define B43_NPHY_PWRDET2 B43_PHY_N(0x13C) /* Power det 2 */ -#define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */ -#define B43_NPHY_PIL_DW0 B43_PHY_N(0x141) /* Pilot data weight 0 */ -#define B43_NPHY_PIL_DW1 B43_PHY_N(0x142) /* Pilot data weight 1 */ -#define B43_NPHY_PIL_DW2 B43_PHY_N(0x143) /* Pilot data weight 2 */ -#define B43_NPHY_PIL_DW_BPSK 0x000F /* BPSK */ -#define B43_NPHY_PIL_DW_BPSK_SHIFT 0 -#define B43_NPHY_PIL_DW_QPSK 0x00F0 /* QPSK */ -#define B43_NPHY_PIL_DW_QPSK_SHIFT 4 -#define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */ -#define B43_NPHY_PIL_DW_16QAM_SHIFT 8 -#define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */ -#define B43_NPHY_PIL_DW_64QAM_SHIFT 12 -#define B43_NPHY_FMDEM_CFG B43_PHY_N(0x144) /* FM demodulation config */ -#define B43_NPHY_PHASETR_A0 B43_PHY_N(0x145) /* Phase track alpha 0 */ -#define B43_NPHY_PHASETR_A1 B43_PHY_N(0x146) /* Phase track alpha 1 */ -#define B43_NPHY_PHASETR_A2 B43_PHY_N(0x147) /* Phase track alpha 2 */ -#define B43_NPHY_PHASETR_B0 B43_PHY_N(0x148) /* Phase track beta 0 */ -#define B43_NPHY_PHASETR_B1 B43_PHY_N(0x149) /* Phase track beta 1 */ -#define B43_NPHY_PHASETR_B2 B43_PHY_N(0x14A) /* Phase track beta 2 */ -#define B43_NPHY_PHASETR_CHG0 B43_PHY_N(0x14B) /* Phase track change 0 */ -#define B43_NPHY_PHASETR_CHG1 B43_PHY_N(0x14C) /* Phase track change 1 */ -#define B43_NPHY_PHASETW_OFF B43_PHY_N(0x14D) /* Phase track offset */ -#define B43_NPHY_RFCTL_DBG B43_PHY_N(0x14E) /* RF control debug */ -#define B43_NPHY_CCK_SHIFTB_REF B43_PHY_N(0x150) /* CCK shiftbits reference var */ -#define B43_NPHY_OVER_DGAIN0 B43_PHY_N(0x152) /* Override digital gain 0 */ -#define B43_NPHY_OVER_DGAIN1 B43_PHY_N(0x153) /* Override digital gain 1 */ -#define B43_NPHY_OVER_DGAIN_FDGV 0x0007 /* Force digital gain value */ -#define B43_NPHY_OVER_DGAIN_FDGV_SHIFT 0 -#define B43_NPHY_OVER_DGAIN_FDGEN 0x0008 /* Force digital gain enable */ -#define B43_NPHY_OVER_DGAIN_CCKDGECV 0xFF00 /* CCK digital gain enable count value */ -#define B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT 8 -#define B43_NPHY_BIST_STAT4 B43_PHY_N(0x156) /* BIST status 4 */ -#define B43_NPHY_RADAR_MAL B43_PHY_N(0x157) /* Radar MA length */ -#define B43_NPHY_RADAR_SRCCTL B43_PHY_N(0x158) /* Radar search control */ -#define B43_NPHY_VLD_DTSIG B43_PHY_N(0x159) /* VLD data tones sig */ -#define B43_NPHY_VLD_DTDAT B43_PHY_N(0x15A) /* VLD data tones data */ -#define B43_NPHY_C1_BPHY_RXIQCA0 B43_PHY_N(0x15B) /* Core 1 B PHY RX I/Q comp A0 */ -#define B43_NPHY_C1_BPHY_RXIQCB0 B43_PHY_N(0x15C) /* Core 1 B PHY RX I/Q comp B0 */ -#define B43_NPHY_C2_BPHY_RXIQCA1 B43_PHY_N(0x15D) /* Core 2 B PHY RX I/Q comp A1 */ -#define B43_NPHY_C2_BPHY_RXIQCB1 B43_PHY_N(0x15E) /* Core 2 B PHY RX I/Q comp B1 */ -#define B43_NPHY_FREQGAIN0 B43_PHY_N(0x160) /* Frequency gain 0 */ -#define B43_NPHY_FREQGAIN1 B43_PHY_N(0x161) /* Frequency gain 1 */ -#define B43_NPHY_FREQGAIN2 B43_PHY_N(0x162) /* Frequency gain 2 */ -#define B43_NPHY_FREQGAIN3 B43_PHY_N(0x163) /* Frequency gain 3 */ -#define B43_NPHY_FREQGAIN4 B43_PHY_N(0x164) /* Frequency gain 4 */ -#define B43_NPHY_FREQGAIN5 B43_PHY_N(0x165) /* Frequency gain 5 */ -#define B43_NPHY_FREQGAIN6 B43_PHY_N(0x166) /* Frequency gain 6 */ -#define B43_NPHY_FREQGAIN7 B43_PHY_N(0x167) /* Frequency gain 7 */ -#define B43_NPHY_FREQGAIN_BYPASS B43_PHY_N(0x168) /* Frequency gain bypass */ -#define B43_NPHY_TRLOSS B43_PHY_N(0x169) /* TR loss value */ -#define B43_NPHY_C1_ADCCLIP B43_PHY_N(0x16A) /* Core 1 ADC clip */ -#define B43_NPHY_C2_ADCCLIP B43_PHY_N(0x16B) /* Core 2 ADC clip */ -#define B43_NPHY_LTRN_OFFGAIN B43_PHY_N(0x16F) /* LTRN offset gain */ -#define B43_NPHY_LTRN_OFF B43_PHY_N(0x170) /* LTRN offset */ -#define B43_NPHY_NRDATAT_WWISE20SIG B43_PHY_N(0x171) /* # data tones WWiSE 20 sig */ -#define B43_NPHY_NRDATAT_WWISE40SIG B43_PHY_N(0x172) /* # data tones WWiSE 40 sig */ -#define B43_NPHY_NRDATAT_TGNSYNC20SIG B43_PHY_N(0x173) /* # data tones TGNsync 20 sig */ -#define B43_NPHY_NRDATAT_TGNSYNC40SIG B43_PHY_N(0x174) /* # data tones TGNsync 40 sig */ -#define B43_NPHY_WWISE_CRCM0 B43_PHY_N(0x175) /* WWiSE CRC mask 0 */ -#define B43_NPHY_WWISE_CRCM1 B43_PHY_N(0x176) /* WWiSE CRC mask 1 */ -#define B43_NPHY_WWISE_CRCM2 B43_PHY_N(0x177) /* WWiSE CRC mask 2 */ -#define B43_NPHY_WWISE_CRCM3 B43_PHY_N(0x178) /* WWiSE CRC mask 3 */ -#define B43_NPHY_WWISE_CRCM4 B43_PHY_N(0x179) /* WWiSE CRC mask 4 */ -#define B43_NPHY_CHANEST_CDDSH B43_PHY_N(0x17A) /* Channel estimate CDD shift */ -#define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */ -#define B43_NPHY_SQPARM B43_PHY_N(0x17C) /* SQ params */ -#define B43_NPHY_MCSDUP6M B43_PHY_N(0x17D) /* MCS dup 6M */ -#define B43_NPHY_NDATAT_DUP40 B43_PHY_N(0x17E) /* # data tones dup 40 */ -#define B43_NPHY_DUP40_TGNSYNC_CYCD B43_PHY_N(0x17F) /* Dup40 TGNsync cycle data */ -#define B43_NPHY_DUP40_GFBL B43_PHY_N(0x180) /* Dup40 GF format BL address */ -#define B43_NPHY_DUP40_BL B43_PHY_N(0x181) /* Dup40 format BL address */ -#define B43_NPHY_LEGDUP_FTA B43_PHY_N(0x182) /* Legacy dup frm table address */ -#define B43_NPHY_PACPROC_DBG B43_PHY_N(0x183) /* Packet processing debug */ -#define B43_NPHY_PIL_CYC1 B43_PHY_N(0x184) /* Pilot cycle counter 1 */ -#define B43_NPHY_PIL_CYC2 B43_PHY_N(0x185) /* Pilot cycle counter 2 */ -#define B43_NPHY_TXF_20CO_S0A1 B43_PHY_N(0x186) /* TX filter 20 coeff stage 0 A1 */ -#define B43_NPHY_TXF_20CO_S0A2 B43_PHY_N(0x187) /* TX filter 20 coeff stage 0 A2 */ -#define B43_NPHY_TXF_20CO_S1A1 B43_PHY_N(0x188) /* TX filter 20 coeff stage 1 A1 */ -#define B43_NPHY_TXF_20CO_S1A2 B43_PHY_N(0x189) /* TX filter 20 coeff stage 1 A2 */ -#define B43_NPHY_TXF_20CO_S2A1 B43_PHY_N(0x18A) /* TX filter 20 coeff stage 2 A1 */ -#define B43_NPHY_TXF_20CO_S2A2 B43_PHY_N(0x18B) /* TX filter 20 coeff stage 2 A2 */ -#define B43_NPHY_TXF_20CO_S0B1 B43_PHY_N(0x18C) /* TX filter 20 coeff stage 0 B1 */ -#define B43_NPHY_TXF_20CO_S0B2 B43_PHY_N(0x18D) /* TX filter 20 coeff stage 0 B2 */ -#define B43_NPHY_TXF_20CO_S0B3 B43_PHY_N(0x18E) /* TX filter 20 coeff stage 0 B3 */ -#define B43_NPHY_TXF_20CO_S1B1 B43_PHY_N(0x18F) /* TX filter 20 coeff stage 1 B1 */ -#define B43_NPHY_TXF_20CO_S1B2 B43_PHY_N(0x190) /* TX filter 20 coeff stage 1 B2 */ -#define B43_NPHY_TXF_20CO_S1B3 B43_PHY_N(0x191) /* TX filter 20 coeff stage 1 B3 */ -#define B43_NPHY_TXF_20CO_S2B1 B43_PHY_N(0x192) /* TX filter 20 coeff stage 2 B1 */ -#define B43_NPHY_TXF_20CO_S2B2 B43_PHY_N(0x193) /* TX filter 20 coeff stage 2 B2 */ -#define B43_NPHY_TXF_20CO_S2B3 B43_PHY_N(0x194) /* TX filter 20 coeff stage 2 B3 */ -#define B43_NPHY_TXF_40CO_S0A1 B43_PHY_N(0x195) /* TX filter 40 coeff stage 0 A1 */ -#define B43_NPHY_TXF_40CO_S0A2 B43_PHY_N(0x196) /* TX filter 40 coeff stage 0 A2 */ -#define B43_NPHY_TXF_40CO_S1A1 B43_PHY_N(0x197) /* TX filter 40 coeff stage 1 A1 */ -#define B43_NPHY_TXF_40CO_S1A2 B43_PHY_N(0x198) /* TX filter 40 coeff stage 1 A2 */ -#define B43_NPHY_TXF_40CO_S2A1 B43_PHY_N(0x199) /* TX filter 40 coeff stage 2 A1 */ -#define B43_NPHY_TXF_40CO_S2A2 B43_PHY_N(0x19A) /* TX filter 40 coeff stage 2 A2 */ -#define B43_NPHY_TXF_40CO_S0B1 B43_PHY_N(0x19B) /* TX filter 40 coeff stage 0 B1 */ -#define B43_NPHY_TXF_40CO_S0B2 B43_PHY_N(0x19C) /* TX filter 40 coeff stage 0 B2 */ -#define B43_NPHY_TXF_40CO_S0B3 B43_PHY_N(0x19D) /* TX filter 40 coeff stage 0 B3 */ -#define B43_NPHY_TXF_40CO_S1B1 B43_PHY_N(0x19E) /* TX filter 40 coeff stage 1 B1 */ -#define B43_NPHY_TXF_40CO_S1B2 B43_PHY_N(0x19F) /* TX filter 40 coeff stage 1 B2 */ -#define B43_NPHY_TXF_40CO_S1B3 B43_PHY_N(0x1A0) /* TX filter 40 coeff stage 1 B3 */ -#define B43_NPHY_TXF_40CO_S2B1 B43_PHY_N(0x1A1) /* TX filter 40 coeff stage 2 B1 */ -#define B43_NPHY_TXF_40CO_S2B2 B43_PHY_N(0x1A2) /* TX filter 40 coeff stage 2 B2 */ -#define B43_NPHY_TXF_40CO_S2B3 B43_PHY_N(0x1A3) /* TX filter 40 coeff stage 2 B3 */ -#define B43_NPHY_RSSIMC_0I_RSSI_X B43_PHY_N(0x1A4) /* RSSI multiplication coefficient 0 I RSSI X */ -#define B43_NPHY_RSSIMC_0I_RSSI_Y B43_PHY_N(0x1A5) /* RSSI multiplication coefficient 0 I RSSI Y */ -#define B43_NPHY_RSSIMC_0I_RSSI_Z B43_PHY_N(0x1A6) /* RSSI multiplication coefficient 0 I RSSI Z */ -#define B43_NPHY_RSSIMC_0I_TBD B43_PHY_N(0x1A7) /* RSSI multiplication coefficient 0 I TBD */ -#define B43_NPHY_RSSIMC_0I_PWRDET B43_PHY_N(0x1A8) /* RSSI multiplication coefficient 0 I power det */ -#define B43_NPHY_RSSIMC_0I_TSSI B43_PHY_N(0x1A9) /* RSSI multiplication coefficient 0 I TSSI */ -#define B43_NPHY_RSSIMC_0Q_RSSI_X B43_PHY_N(0x1AA) /* RSSI multiplication coefficient 0 Q RSSI X */ -#define B43_NPHY_RSSIMC_0Q_RSSI_Y B43_PHY_N(0x1AB) /* RSSI multiplication coefficient 0 Q RSSI Y */ -#define B43_NPHY_RSSIMC_0Q_RSSI_Z B43_PHY_N(0x1AC) /* RSSI multiplication coefficient 0 Q RSSI Z */ -#define B43_NPHY_RSSIMC_0Q_TBD B43_PHY_N(0x1AD) /* RSSI multiplication coefficient 0 Q TBD */ -#define B43_NPHY_RSSIMC_0Q_PWRDET B43_PHY_N(0x1AE) /* RSSI multiplication coefficient 0 Q power det */ -#define B43_NPHY_RSSIMC_0Q_TSSI B43_PHY_N(0x1AF) /* RSSI multiplication coefficient 0 Q TSSI */ -#define B43_NPHY_RSSIMC_1I_RSSI_X B43_PHY_N(0x1B0) /* RSSI multiplication coefficient 1 I RSSI X */ -#define B43_NPHY_RSSIMC_1I_RSSI_Y B43_PHY_N(0x1B1) /* RSSI multiplication coefficient 1 I RSSI Y */ -#define B43_NPHY_RSSIMC_1I_RSSI_Z B43_PHY_N(0x1B2) /* RSSI multiplication coefficient 1 I RSSI Z */ -#define B43_NPHY_RSSIMC_1I_TBD B43_PHY_N(0x1B3) /* RSSI multiplication coefficient 1 I TBD */ -#define B43_NPHY_RSSIMC_1I_PWRDET B43_PHY_N(0x1B4) /* RSSI multiplication coefficient 1 I power det */ -#define B43_NPHY_RSSIMC_1I_TSSI B43_PHY_N(0x1B5) /* RSSI multiplication coefficient 1 I TSSI */ -#define B43_NPHY_RSSIMC_1Q_RSSI_X B43_PHY_N(0x1B6) /* RSSI multiplication coefficient 1 Q RSSI X */ -#define B43_NPHY_RSSIMC_1Q_RSSI_Y B43_PHY_N(0x1B7) /* RSSI multiplication coefficient 1 Q RSSI Y */ -#define B43_NPHY_RSSIMC_1Q_RSSI_Z B43_PHY_N(0x1B8) /* RSSI multiplication coefficient 1 Q RSSI Z */ -#define B43_NPHY_RSSIMC_1Q_TBD B43_PHY_N(0x1B9) /* RSSI multiplication coefficient 1 Q TBD */ -#define B43_NPHY_RSSIMC_1Q_PWRDET B43_PHY_N(0x1BA) /* RSSI multiplication coefficient 1 Q power det */ -#define B43_NPHY_RSSIMC_1Q_TSSI B43_PHY_N(0x1BB) /* RSSI multiplication coefficient 1 Q TSSI */ -#define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */ -#define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */ -#define B43_NPHY_LTRN_OFF_G20L B43_PHY_N(0x1C4) /* LTRN offset gain 20L */ -#define B43_NPHY_LTRN_OFF_20L B43_PHY_N(0x1C5) /* LTRN offset 20L */ -#define B43_NPHY_LTRN_OFF_G20U B43_PHY_N(0x1C6) /* LTRN offset gain 20U */ -#define B43_NPHY_LTRN_OFF_20U B43_PHY_N(0x1C7) /* LTRN offset 20U */ -#define B43_NPHY_DSSSCCK_GAINSL B43_PHY_N(0x1C8) /* DSSS/CCK gain settle length */ -#define B43_NPHY_GPIO_LOOUT B43_PHY_N(0x1C9) /* GPIO low out */ -#define B43_NPHY_GPIO_HIOUT B43_PHY_N(0x1CA) /* GPIO high out */ -#define B43_NPHY_CRS_CHECK B43_PHY_N(0x1CB) /* CRS check */ -#define B43_NPHY_ML_LOGSS_RAT B43_PHY_N(0x1CC) /* ML/logss ratio */ -#define B43_NPHY_DUPSCALE B43_PHY_N(0x1CD) /* Dup scale */ -#define B43_NPHY_BW1A B43_PHY_N(0x1CE) /* BW 1A */ -#define B43_NPHY_BW2 B43_PHY_N(0x1CF) /* BW 2 */ -#define B43_NPHY_BW3 B43_PHY_N(0x1D0) /* BW 3 */ -#define B43_NPHY_BW4 B43_PHY_N(0x1D1) /* BW 4 */ -#define B43_NPHY_BW5 B43_PHY_N(0x1D2) /* BW 5 */ -#define B43_NPHY_BW6 B43_PHY_N(0x1D3) /* BW 6 */ -#define B43_NPHY_COALEN0 B43_PHY_N(0x1D4) /* Coarse length 0 */ -#define B43_NPHY_COALEN1 B43_PHY_N(0x1D5) /* Coarse length 1 */ -#define B43_NPHY_CRSTHRES_1U B43_PHY_N(0x1D6) /* CRS threshold 1 U */ -#define B43_NPHY_CRSTHRES_2U B43_PHY_N(0x1D7) /* CRS threshold 2 U */ -#define B43_NPHY_CRSTHRES_3U B43_PHY_N(0x1D8) /* CRS threshold 3 U */ -#define B43_NPHY_CRSCTL_U B43_PHY_N(0x1D9) /* CRS control U */ -#define B43_NPHY_CRSTHRES_1L B43_PHY_N(0x1DA) /* CRS threshold 1 L */ -#define B43_NPHY_CRSTHRES_2L B43_PHY_N(0x1DB) /* CRS threshold 2 L */ -#define B43_NPHY_CRSTHRES_3L B43_PHY_N(0x1DC) /* CRS threshold 3 L */ -#define B43_NPHY_CRSCTL_L B43_PHY_N(0x1DD) /* CRS control L */ -#define B43_NPHY_STRA_1U B43_PHY_N(0x1DE) /* STR address 1 U */ -#define B43_NPHY_STRA_2U B43_PHY_N(0x1DF) /* STR address 2 U */ -#define B43_NPHY_STRA_1L B43_PHY_N(0x1E0) /* STR address 1 L */ -#define B43_NPHY_STRA_2L B43_PHY_N(0x1E1) /* STR address 2 L */ -#define B43_NPHY_CRSCHECK1 B43_PHY_N(0x1E2) /* CRS check 1 */ -#define B43_NPHY_CRSCHECK2 B43_PHY_N(0x1E3) /* CRS check 2 */ -#define B43_NPHY_CRSCHECK3 B43_PHY_N(0x1E4) /* CRS check 3 */ -#define B43_NPHY_JMPSTP0 B43_PHY_N(0x1E5) /* Jump step 0 */ -#define B43_NPHY_JMPSTP1 B43_PHY_N(0x1E6) /* Jump step 1 */ -#define B43_NPHY_TXPCTL_CMD B43_PHY_N(0x1E7) /* TX power control command */ -#define B43_NPHY_TXPCTL_CMD_INIT 0x007F /* Init */ -#define B43_NPHY_TXPCTL_CMD_INIT_SHIFT 0 -#define B43_NPHY_TXPCTL_CMD_COEFF 0x2000 /* Power control coefficients */ -#define B43_NPHY_TXPCTL_CMD_HWPCTLEN 0x4000 /* Hardware TX power control enable */ -#define B43_NPHY_TXPCTL_CMD_PCTLEN 0x8000 /* TX power control enable */ -#define B43_NPHY_TXPCTL_N B43_PHY_N(0x1E8) /* TX power control N num */ -#define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ -#define B43_NPHY_TXPCTL_N_TSSID_SHIFT 0 -#define B43_NPHY_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ -#define B43_NPHY_TXPCTL_N_NPTIL2_SHIFT 8 -#define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */ -#define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */ -#define B43_NPHY_TXPCTL_ITSSI_0_SHIFT 0 -#define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */ -#define B43_NPHY_TXPCTL_ITSSI_1_SHIFT 8 -#define B43_NPHY_TXPCTL_ITSSI_BINF 0x8000 /* Raw TSSI offset bin format */ -#define B43_NPHY_TXPCTL_TPWR B43_PHY_N(0x1EA) /* TX power control target power */ -#define B43_NPHY_TXPCTL_TPWR_0 0x00FF /* Power 0 */ -#define B43_NPHY_TXPCTL_TPWR_0_SHIFT 0 -#define B43_NPHY_TXPCTL_TPWR_1 0xFF00 /* Power 1 */ -#define B43_NPHY_TXPCTL_TPWR_1_SHIFT 8 -#define B43_NPHY_TXPCTL_BIDX B43_PHY_N(0x1EB) /* TX power control base index */ -#define B43_NPHY_TXPCTL_BIDX_0 0x007F /* uC base index 0 */ -#define B43_NPHY_TXPCTL_BIDX_0_SHIFT 0 -#define B43_NPHY_TXPCTL_BIDX_1 0x7F00 /* uC base index 1 */ -#define B43_NPHY_TXPCTL_BIDX_1_SHIFT 8 -#define B43_NPHY_TXPCTL_BIDX_LOAD 0x8000 /* Load base index */ -#define B43_NPHY_TXPCTL_PIDX B43_PHY_N(0x1EC) /* TX power control power index */ -#define B43_NPHY_TXPCTL_PIDX_0 0x007F /* uC power index 0 */ -#define B43_NPHY_TXPCTL_PIDX_0_SHIFT 0 -#define B43_NPHY_TXPCTL_PIDX_1 0x7F00 /* uC power index 1 */ -#define B43_NPHY_TXPCTL_PIDX_1_SHIFT 8 -#define B43_NPHY_C1_TXPCTL_STAT B43_PHY_N(0x1ED) /* Core 1 TX power control status */ -#define B43_NPHY_C2_TXPCTL_STAT B43_PHY_N(0x1EE) /* Core 2 TX power control status */ -#define B43_NPHY_TXPCTL_STAT_EST 0x00FF /* Estimated power */ -#define B43_NPHY_TXPCTL_STAT_EST_SHIFT 0 -#define B43_NPHY_TXPCTL_STAT_BIDX 0x7F00 /* Base index */ -#define B43_NPHY_TXPCTL_STAT_BIDX_SHIFT 8 -#define B43_NPHY_TXPCTL_STAT_ESTVALID 0x8000 /* Estimated power valid */ -#define B43_NPHY_SMALLSGS_LEN B43_PHY_N(0x1EF) /* Small sig gain settle length */ -#define B43_NPHY_PHYSTAT_GAIN0 B43_PHY_N(0x1F0) /* PHY stats gain info 0 */ -#define B43_NPHY_PHYSTAT_GAIN1 B43_PHY_N(0x1F1) /* PHY stats gain info 1 */ -#define B43_NPHY_PHYSTAT_FREQEST B43_PHY_N(0x1F2) /* PHY stats frequency estimate */ -#define B43_NPHY_PHYSTAT_ADVRET B43_PHY_N(0x1F3) /* PHY stats ADV retard */ -#define B43_NPHY_PHYLB_MODE B43_PHY_N(0x1F4) /* PHY loopback mode */ -#define B43_NPHY_TONE_MIDX20_1 B43_PHY_N(0x1F5) /* Tone map index 20/1 */ -#define B43_NPHY_TONE_MIDX20_2 B43_PHY_N(0x1F6) /* Tone map index 20/2 */ -#define B43_NPHY_TONE_MIDX20_3 B43_PHY_N(0x1F7) /* Tone map index 20/3 */ -#define B43_NPHY_TONE_MIDX40_1 B43_PHY_N(0x1F8) /* Tone map index 40/1 */ -#define B43_NPHY_TONE_MIDX40_2 B43_PHY_N(0x1F9) /* Tone map index 40/2 */ -#define B43_NPHY_TONE_MIDX40_3 B43_PHY_N(0x1FA) /* Tone map index 40/3 */ -#define B43_NPHY_TONE_MIDX40_4 B43_PHY_N(0x1FB) /* Tone map index 40/4 */ -#define B43_NPHY_PILTONE_MIDX1 B43_PHY_N(0x1FC) /* Pilot tone map index 1 */ -#define B43_NPHY_PILTONE_MIDX2 B43_PHY_N(0x1FD) /* Pilot tone map index 2 */ -#define B43_NPHY_PILTONE_MIDX3 B43_PHY_N(0x1FE) /* Pilot tone map index 3 */ -#define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */ -#define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */ -#define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */ -#define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */ -#define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */ -#define B43_NPHY_RX_SIGCTL B43_PHY_N(0x204) /* RX signal control */ -#define B43_NPHY_RXPIL_CYCNT0 B43_PHY_N(0x205) /* RX pilot cycle counter 0 */ -#define B43_NPHY_RXPIL_CYCNT1 B43_PHY_N(0x206) /* RX pilot cycle counter 1 */ -#define B43_NPHY_RXPIL_CYCNT2 B43_PHY_N(0x207) /* RX pilot cycle counter 2 */ -#define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */ -#define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */ -#define B43_NPHY_DSSSCCK_CRSEXTL B43_PHY_N(0x20A) /* DSSS/CCK CRS extension length */ -#define B43_NPHY_ML_LOGSS_RATSLOPE B43_PHY_N(0x20B) /* ML/logss ratio slope */ -#define B43_NPHY_RIFS_SRCTL B43_PHY_N(0x20C) /* RIFS search timeout length */ -#define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */ -#define B43_NPHY_HPANT_SWTHRES B43_PHY_N(0x20E) /* High power antenna switch threshold */ -#define B43_NPHY_EDCRS_ASSTHRES0 B43_PHY_N(0x210) /* ED CRS assert threshold 0 */ -#define B43_NPHY_EDCRS_ASSTHRES1 B43_PHY_N(0x211) /* ED CRS assert threshold 1 */ -#define B43_NPHY_EDCRS_DEASSTHRES0 B43_PHY_N(0x212) /* ED CRS deassert threshold 0 */ -#define B43_NPHY_EDCRS_DEASSTHRES1 B43_PHY_N(0x213) /* ED CRS deassert threshold 1 */ -#define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */ -#define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */ -#define B43_NPHY_TONE_MIDX657M B43_PHY_N(0x216) /* Tone map index 657M */ -#define B43_NPHY_HTSIGTONES B43_PHY_N(0x217) /* HT signal tones */ -#define B43_NPHY_RSSI1 B43_PHY_N(0x219) /* RSSI value 1 */ -#define B43_NPHY_RSSI2 B43_PHY_N(0x21A) /* RSSI value 2 */ -#define B43_NPHY_CHAN_ESTHANG B43_PHY_N(0x21D) /* Channel estimate hang */ -#define B43_NPHY_FINERX2_CGC B43_PHY_N(0x221) /* Fine RX 2 clock gate control */ -#define B43_NPHY_FINERX2_CGC_DECGC 0x0008 /* Decode gated clocks */ -#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ -#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ -#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 -#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223) -#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224) -#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225) -#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226) -#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227) -#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228) -#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229) -#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A) -#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B) -#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C) -#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D) -#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E) -#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F) -#define B43_NPHY_ED_CRS B43_PHY_N(0x230) -#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231) -#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232) -#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233) -#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234) -#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235) -#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236) -#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237) -#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238) -#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239) -#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A) -#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B) -#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C) -#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D) -#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E) -/* REV3+ */ -#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F) -#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240) -#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241) -#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242) -#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243) -#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244) -#define B43_NPHY_CORECONFIG B43_PHY_N(0x245) -#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246) -#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247) -#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248) -#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249) -#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A) -#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B) -#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C) -#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250) -#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251) -#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252) -#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253) -#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254) -#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255) -#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256) -#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257) -#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258) -#define B43_NPHY_MLUA B43_PHY_N(0x259) -#define B43_NPHY_ZFUA B43_PHY_N(0x25A) -#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B) -#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C) -#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D) -#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E) -#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F) -#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260) -#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261) -#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262) -#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263) -#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264) -#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265) -#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266) -#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267) -#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268) -#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269) -#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A) -#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B) -#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C) -#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D) -#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E) -#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F) -#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272) -#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275) -#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277) -#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278) -#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279) -#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A) -#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B) -#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C) -#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D) -#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E) -#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F) -#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280) -#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281) -#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282) -#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283) -#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284) -#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285) -#define B43_NPHY_STRPARAM B43_PHY_N(0x286) -#define B43_NPHY_STRPARAML B43_PHY_N(0x287) -#define B43_NPHY_STRPARAMU B43_PHY_N(0x288) -#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289) -#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A) -#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B) -#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C) -#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D) -#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E) -#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F) -#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290) -#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291) -#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292) -#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293) -#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294) -#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295) -#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296) -#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ -#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ -#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299) -#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A) -#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ -#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ -#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D) -#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E) -#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F) -#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0) -#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1) -#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2) -#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3) -#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4) -#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5) -#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6) -#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7) -#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8) -#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9) -#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA) -#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB) -#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC) -#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD) -#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE) -#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF) -#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0) - -#define B43_NPHY_REV7_RF_CTL_MISC_REG3 B43_PHY_N(0x340) -#define B43_NPHY_REV7_RF_CTL_MISC_REG4 B43_PHY_N(0x341) -#define B43_NPHY_REV7_RF_CTL_OVER3 B43_PHY_N(0x342) -#define B43_NPHY_REV7_RF_CTL_OVER4 B43_PHY_N(0x343) -#define B43_NPHY_REV7_RF_CTL_MISC_REG5 B43_PHY_N(0x344) -#define B43_NPHY_REV7_RF_CTL_MISC_REG6 B43_PHY_N(0x345) -#define B43_NPHY_REV7_RF_CTL_OVER5 B43_PHY_N(0x346) -#define B43_NPHY_REV7_RF_CTL_OVER6 B43_PHY_N(0x347) - -#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ -#define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ -#define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ -#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) - -struct b43_wldev; - -enum b43_nphy_spur_avoid { - B43_SPUR_AVOID_DISABLE, - B43_SPUR_AVOID_AUTO, - B43_SPUR_AVOID_FORCE, -}; - -struct b43_chanspec { - u16 center_freq; - enum nl80211_channel_type channel_type; -}; - -struct b43_phy_n_iq_comp { - s16 a0; - s16 b0; - s16 a1; - s16 b1; -}; - -struct b43_phy_n_rssical_cache { - u16 rssical_radio_regs_2G[2]; - u16 rssical_phy_regs_2G[12]; - - u16 rssical_radio_regs_5G[2]; - u16 rssical_phy_regs_5G[12]; -}; - -struct b43_phy_n_cal_cache { - u16 txcal_radio_regs_2G[8]; - u16 txcal_coeffs_2G[8]; - struct b43_phy_n_iq_comp rxcal_coeffs_2G; - - u16 txcal_radio_regs_5G[8]; - u16 txcal_coeffs_5G[8]; - struct b43_phy_n_iq_comp rxcal_coeffs_5G; -}; - -struct b43_phy_n_txpwrindex { - s8 index; - s8 index_internal; - s8 index_internal_save; - u16 AfectrlOverride; - u16 AfeCtrlDacGain; - u16 rad_gain; - u8 bbmult; - u16 iqcomp_a; - u16 iqcomp_b; - u16 locomp; -}; - -struct b43_phy_n_pwr_ctl_info { - u8 idle_tssi_2g; - u8 idle_tssi_5g; -}; - -struct b43_phy_n { - u8 antsel_type; - u8 cal_orig_pwr_idx[2]; - u8 measure_hold; - u8 phyrxchain; - u8 hw_phyrxchain; - u8 hw_phytxchain; - u8 perical; - u32 deaf_count; - u32 rxcalparams; - bool hang_avoid; - bool mute; - u16 papd_epsilon_offset[2]; - s32 preamble_override; - u32 bb_mult_save; - - bool gain_boost; - bool elna_gain_config; - bool band5g_pwrgain; - bool use_int_tx_iq_lo_cal; - bool lpf_bw_overrode_for_sample_play; - - u8 mphase_cal_phase_id; - u16 mphase_txcal_cmdidx; - u16 mphase_txcal_numcmds; - u16 mphase_txcal_bestcoeffs[11]; - - bool txpwrctrl; - bool pwg_gain_5ghz; - u8 tx_pwr_idx[2]; - s8 tx_power_offset[101]; - u16 adj_pwr_tbl[84]; - u16 txcal_bbmult; - u16 txiqlocal_bestc[11]; - bool txiqlocal_coeffsvalid; - struct b43_phy_n_txpwrindex txpwrindex[2]; - struct b43_phy_n_pwr_ctl_info pwr_ctl_info[2]; - struct b43_chanspec txiqlocal_chanspec; - struct b43_ppr tx_pwr_max_ppr; - u16 tx_pwr_last_recalc_freq; - int tx_pwr_last_recalc_limit; - - u8 txrx_chain; - u16 tx_rx_cal_phy_saveregs[11]; - u16 tx_rx_cal_radio_saveregs[22]; - - u16 rfctrl_intc1_save; - u16 rfctrl_intc2_save; - - u16 classifier_state; - u16 clip_state[2]; - - enum b43_nphy_spur_avoid spur_avoid; - bool aband_spurwar_en; - bool gband_spurwar_en; - - bool ipa2g_on; - struct b43_chanspec iqcal_chanspec_2G; - struct b43_chanspec rssical_chanspec_2G; - - bool ipa5g_on; - struct b43_chanspec iqcal_chanspec_5G; - struct b43_chanspec rssical_chanspec_5G; - - struct b43_phy_n_rssical_cache rssical_cache; - struct b43_phy_n_cal_cache cal_cache; - bool crsminpwr_adjusted; - bool noisevars_adjusted; -}; - - -struct b43_phy_operations; -extern const struct b43_phy_operations b43_phyops_n; - -#endif /* B43_NPHY_H_ */ diff --git a/drivers/net/wireless/b43/pio.c b/drivers/net/wireless/b43/pio.c deleted file mode 100644 index a4ff5e2a4..000000000 --- a/drivers/net/wireless/b43/pio.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - - Broadcom B43 wireless driver - - PIO data transfer - - Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "pio.h" -#include "dma.h" -#include "main.h" -#include "xmit.h" - -#include <linux/delay.h> -#include <linux/sched.h> -#include <linux/slab.h> - - -static u16 generate_cookie(struct b43_pio_txqueue *q, - struct b43_pio_txpacket *pack) -{ - u16 cookie; - - /* Use the upper 4 bits of the cookie as - * PIO controller ID and store the packet index number - * in the lower 12 bits. - * Note that the cookie must never be 0, as this - * is a special value used in RX path. - * It can also not be 0xFFFF because that is special - * for multicast frames. - */ - cookie = (((u16)q->index + 1) << 12); - cookie |= pack->index; - - return cookie; -} - -static -struct b43_pio_txqueue *parse_cookie(struct b43_wldev *dev, - u16 cookie, - struct b43_pio_txpacket **pack) -{ - struct b43_pio *pio = &dev->pio; - struct b43_pio_txqueue *q = NULL; - unsigned int pack_index; - - switch (cookie & 0xF000) { - case 0x1000: - q = pio->tx_queue_AC_BK; - break; - case 0x2000: - q = pio->tx_queue_AC_BE; - break; - case 0x3000: - q = pio->tx_queue_AC_VI; - break; - case 0x4000: - q = pio->tx_queue_AC_VO; - break; - case 0x5000: - q = pio->tx_queue_mcast; - break; - } - if (B43_WARN_ON(!q)) - return NULL; - pack_index = (cookie & 0x0FFF); - if (B43_WARN_ON(pack_index >= ARRAY_SIZE(q->packets))) - return NULL; - *pack = &q->packets[pack_index]; - - return q; -} - -static u16 index_to_pioqueue_base(struct b43_wldev *dev, - unsigned int index) -{ - static const u16 bases[] = { - B43_MMIO_PIO_BASE0, - B43_MMIO_PIO_BASE1, - B43_MMIO_PIO_BASE2, - B43_MMIO_PIO_BASE3, - B43_MMIO_PIO_BASE4, - B43_MMIO_PIO_BASE5, - B43_MMIO_PIO_BASE6, - B43_MMIO_PIO_BASE7, - }; - static const u16 bases_rev11[] = { - B43_MMIO_PIO11_BASE0, - B43_MMIO_PIO11_BASE1, - B43_MMIO_PIO11_BASE2, - B43_MMIO_PIO11_BASE3, - B43_MMIO_PIO11_BASE4, - B43_MMIO_PIO11_BASE5, - }; - - if (dev->dev->core_rev >= 11) { - B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11)); - return bases_rev11[index]; - } - B43_WARN_ON(index >= ARRAY_SIZE(bases)); - return bases[index]; -} - -static u16 pio_txqueue_offset(struct b43_wldev *dev) -{ - if (dev->dev->core_rev >= 11) - return 0x18; - return 0; -} - -static u16 pio_rxqueue_offset(struct b43_wldev *dev) -{ - if (dev->dev->core_rev >= 11) - return 0x38; - return 8; -} - -static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev, - unsigned int index) -{ - struct b43_pio_txqueue *q; - struct b43_pio_txpacket *p; - unsigned int i; - - q = kzalloc(sizeof(*q), GFP_KERNEL); - if (!q) - return NULL; - q->dev = dev; - q->rev = dev->dev->core_rev; - q->mmio_base = index_to_pioqueue_base(dev, index) + - pio_txqueue_offset(dev); - q->index = index; - - q->free_packet_slots = B43_PIO_MAX_NR_TXPACKETS; - if (q->rev >= 8) { - q->buffer_size = 1920; //FIXME this constant is wrong. - } else { - q->buffer_size = b43_piotx_read16(q, B43_PIO_TXQBUFSIZE); - q->buffer_size -= 80; - } - - INIT_LIST_HEAD(&q->packets_list); - for (i = 0; i < ARRAY_SIZE(q->packets); i++) { - p = &(q->packets[i]); - INIT_LIST_HEAD(&p->list); - p->index = i; - p->queue = q; - list_add(&p->list, &q->packets_list); - } - - return q; -} - -static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev, - unsigned int index) -{ - struct b43_pio_rxqueue *q; - - q = kzalloc(sizeof(*q), GFP_KERNEL); - if (!q) - return NULL; - q->dev = dev; - q->rev = dev->dev->core_rev; - q->mmio_base = index_to_pioqueue_base(dev, index) + - pio_rxqueue_offset(dev); - - /* Enable Direct FIFO RX (PIO) on the engine. */ - b43_dma_direct_fifo_rx(dev, index, 1); - - return q; -} - -static void b43_pio_cancel_tx_packets(struct b43_pio_txqueue *q) -{ - struct b43_pio_txpacket *pack; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(q->packets); i++) { - pack = &(q->packets[i]); - if (pack->skb) { - ieee80211_free_txskb(q->dev->wl->hw, pack->skb); - pack->skb = NULL; - } - } -} - -static void b43_destroy_pioqueue_tx(struct b43_pio_txqueue *q, - const char *name) -{ - if (!q) - return; - b43_pio_cancel_tx_packets(q); - kfree(q); -} - -static void b43_destroy_pioqueue_rx(struct b43_pio_rxqueue *q, - const char *name) -{ - if (!q) - return; - kfree(q); -} - -#define destroy_queue_tx(pio, queue) do { \ - b43_destroy_pioqueue_tx((pio)->queue, __stringify(queue)); \ - (pio)->queue = NULL; \ - } while (0) - -#define destroy_queue_rx(pio, queue) do { \ - b43_destroy_pioqueue_rx((pio)->queue, __stringify(queue)); \ - (pio)->queue = NULL; \ - } while (0) - -void b43_pio_free(struct b43_wldev *dev) -{ - struct b43_pio *pio; - - if (!b43_using_pio_transfers(dev)) - return; - pio = &dev->pio; - - destroy_queue_rx(pio, rx_queue); - destroy_queue_tx(pio, tx_queue_mcast); - destroy_queue_tx(pio, tx_queue_AC_VO); - destroy_queue_tx(pio, tx_queue_AC_VI); - destroy_queue_tx(pio, tx_queue_AC_BE); - destroy_queue_tx(pio, tx_queue_AC_BK); -} - -int b43_pio_init(struct b43_wldev *dev) -{ - struct b43_pio *pio = &dev->pio; - int err = -ENOMEM; - - b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) - & ~B43_MACCTL_BE); - b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RXPADOFF, 0); - - pio->tx_queue_AC_BK = b43_setup_pioqueue_tx(dev, 0); - if (!pio->tx_queue_AC_BK) - goto out; - - pio->tx_queue_AC_BE = b43_setup_pioqueue_tx(dev, 1); - if (!pio->tx_queue_AC_BE) - goto err_destroy_bk; - - pio->tx_queue_AC_VI = b43_setup_pioqueue_tx(dev, 2); - if (!pio->tx_queue_AC_VI) - goto err_destroy_be; - - pio->tx_queue_AC_VO = b43_setup_pioqueue_tx(dev, 3); - if (!pio->tx_queue_AC_VO) - goto err_destroy_vi; - - pio->tx_queue_mcast = b43_setup_pioqueue_tx(dev, 4); - if (!pio->tx_queue_mcast) - goto err_destroy_vo; - - pio->rx_queue = b43_setup_pioqueue_rx(dev, 0); - if (!pio->rx_queue) - goto err_destroy_mcast; - - b43dbg(dev->wl, "PIO initialized\n"); - err = 0; -out: - return err; - -err_destroy_mcast: - destroy_queue_tx(pio, tx_queue_mcast); -err_destroy_vo: - destroy_queue_tx(pio, tx_queue_AC_VO); -err_destroy_vi: - destroy_queue_tx(pio, tx_queue_AC_VI); -err_destroy_be: - destroy_queue_tx(pio, tx_queue_AC_BE); -err_destroy_bk: - destroy_queue_tx(pio, tx_queue_AC_BK); - return err; -} - -/* Static mapping of mac80211's queues (priorities) to b43 PIO queues. */ -static struct b43_pio_txqueue *select_queue_by_priority(struct b43_wldev *dev, - u8 queue_prio) -{ - struct b43_pio_txqueue *q; - - if (dev->qos_enabled) { - /* 0 = highest priority */ - switch (queue_prio) { - default: - B43_WARN_ON(1); - /* fallthrough */ - case 0: - q = dev->pio.tx_queue_AC_VO; - break; - case 1: - q = dev->pio.tx_queue_AC_VI; - break; - case 2: - q = dev->pio.tx_queue_AC_BE; - break; - case 3: - q = dev->pio.tx_queue_AC_BK; - break; - } - } else - q = dev->pio.tx_queue_AC_BE; - - return q; -} - -static u16 tx_write_2byte_queue(struct b43_pio_txqueue *q, - u16 ctl, - const void *_data, - unsigned int data_len) -{ - struct b43_wldev *dev = q->dev; - struct b43_wl *wl = dev->wl; - const u8 *data = _data; - - ctl |= B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI; - b43_piotx_write16(q, B43_PIO_TXCTL, ctl); - - b43_block_write(dev, data, (data_len & ~1), - q->mmio_base + B43_PIO_TXDATA, - sizeof(u16)); - if (data_len & 1) { - u8 *tail = wl->pio_tailspace; - BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2); - - /* Write the last byte. */ - ctl &= ~B43_PIO_TXCTL_WRITEHI; - b43_piotx_write16(q, B43_PIO_TXCTL, ctl); - tail[0] = data[data_len - 1]; - tail[1] = 0; - b43_block_write(dev, tail, 2, - q->mmio_base + B43_PIO_TXDATA, - sizeof(u16)); - } - - return ctl; -} - -static void pio_tx_frame_2byte_queue(struct b43_pio_txpacket *pack, - const u8 *hdr, unsigned int hdrlen) -{ - struct b43_pio_txqueue *q = pack->queue; - const char *frame = pack->skb->data; - unsigned int frame_len = pack->skb->len; - u16 ctl; - - ctl = b43_piotx_read16(q, B43_PIO_TXCTL); - ctl |= B43_PIO_TXCTL_FREADY; - ctl &= ~B43_PIO_TXCTL_EOF; - - /* Transfer the header data. */ - ctl = tx_write_2byte_queue(q, ctl, hdr, hdrlen); - /* Transfer the frame data. */ - ctl = tx_write_2byte_queue(q, ctl, frame, frame_len); - - ctl |= B43_PIO_TXCTL_EOF; - b43_piotx_write16(q, B43_PIO_TXCTL, ctl); -} - -static u32 tx_write_4byte_queue(struct b43_pio_txqueue *q, - u32 ctl, - const void *_data, - unsigned int data_len) -{ - struct b43_wldev *dev = q->dev; - struct b43_wl *wl = dev->wl; - const u8 *data = _data; - - ctl |= B43_PIO8_TXCTL_0_7 | B43_PIO8_TXCTL_8_15 | - B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_24_31; - b43_piotx_write32(q, B43_PIO8_TXCTL, ctl); - - b43_block_write(dev, data, (data_len & ~3), - q->mmio_base + B43_PIO8_TXDATA, - sizeof(u32)); - if (data_len & 3) { - u8 *tail = wl->pio_tailspace; - BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4); - - memset(tail, 0, 4); - /* Write the last few bytes. */ - ctl &= ~(B43_PIO8_TXCTL_8_15 | B43_PIO8_TXCTL_16_23 | - B43_PIO8_TXCTL_24_31); - switch (data_len & 3) { - case 3: - ctl |= B43_PIO8_TXCTL_16_23 | B43_PIO8_TXCTL_8_15; - tail[0] = data[data_len - 3]; - tail[1] = data[data_len - 2]; - tail[2] = data[data_len - 1]; - break; - case 2: - ctl |= B43_PIO8_TXCTL_8_15; - tail[0] = data[data_len - 2]; - tail[1] = data[data_len - 1]; - break; - case 1: - tail[0] = data[data_len - 1]; - break; - } - b43_piotx_write32(q, B43_PIO8_TXCTL, ctl); - b43_block_write(dev, tail, 4, - q->mmio_base + B43_PIO8_TXDATA, - sizeof(u32)); - } - - return ctl; -} - -static void pio_tx_frame_4byte_queue(struct b43_pio_txpacket *pack, - const u8 *hdr, unsigned int hdrlen) -{ - struct b43_pio_txqueue *q = pack->queue; - const char *frame = pack->skb->data; - unsigned int frame_len = pack->skb->len; - u32 ctl; - - ctl = b43_piotx_read32(q, B43_PIO8_TXCTL); - ctl |= B43_PIO8_TXCTL_FREADY; - ctl &= ~B43_PIO8_TXCTL_EOF; - - /* Transfer the header data. */ - ctl = tx_write_4byte_queue(q, ctl, hdr, hdrlen); - /* Transfer the frame data. */ - ctl = tx_write_4byte_queue(q, ctl, frame, frame_len); - - ctl |= B43_PIO8_TXCTL_EOF; - b43_piotx_write32(q, B43_PIO_TXCTL, ctl); -} - -static int pio_tx_frame(struct b43_pio_txqueue *q, - struct sk_buff *skb) -{ - struct b43_wldev *dev = q->dev; - struct b43_wl *wl = dev->wl; - struct b43_pio_txpacket *pack; - u16 cookie; - int err; - unsigned int hdrlen; - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - struct b43_txhdr *txhdr = (struct b43_txhdr *)wl->pio_scratchspace; - - B43_WARN_ON(list_empty(&q->packets_list)); - pack = list_entry(q->packets_list.next, - struct b43_pio_txpacket, list); - - cookie = generate_cookie(q, pack); - hdrlen = b43_txhdr_size(dev); - BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(struct b43_txhdr)); - B43_WARN_ON(sizeof(wl->pio_scratchspace) < hdrlen); - err = b43_generate_txhdr(dev, (u8 *)txhdr, skb, - info, cookie); - if (err) - return err; - - if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { - /* Tell the firmware about the cookie of the last - * mcast frame, so it can clear the more-data bit in it. */ - b43_shm_write16(dev, B43_SHM_SHARED, - B43_SHM_SH_MCASTCOOKIE, cookie); - } - - pack->skb = skb; - if (q->rev >= 8) - pio_tx_frame_4byte_queue(pack, (const u8 *)txhdr, hdrlen); - else - pio_tx_frame_2byte_queue(pack, (const u8 *)txhdr, hdrlen); - - /* Remove it from the list of available packet slots. - * It will be put back when we receive the status report. */ - list_del(&pack->list); - - /* Update the queue statistics. */ - q->buffer_used += roundup(skb->len + hdrlen, 4); - q->free_packet_slots -= 1; - - return 0; -} - -int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb) -{ - struct b43_pio_txqueue *q; - struct ieee80211_hdr *hdr; - unsigned int hdrlen, total_len; - int err = 0; - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - - hdr = (struct ieee80211_hdr *)skb->data; - - if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { - /* The multicast queue will be sent after the DTIM. */ - q = dev->pio.tx_queue_mcast; - /* Set the frame More-Data bit. Ucode will clear it - * for us on the last frame. */ - hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); - } else { - /* Decide by priority where to put this frame. */ - q = select_queue_by_priority(dev, skb_get_queue_mapping(skb)); - } - - hdrlen = b43_txhdr_size(dev); - total_len = roundup(skb->len + hdrlen, 4); - - if (unlikely(total_len > q->buffer_size)) { - err = -ENOBUFS; - b43dbg(dev->wl, "PIO: TX packet longer than queue.\n"); - goto out; - } - if (unlikely(q->free_packet_slots == 0)) { - err = -ENOBUFS; - b43warn(dev->wl, "PIO: TX packet overflow.\n"); - goto out; - } - B43_WARN_ON(q->buffer_used > q->buffer_size); - - if (total_len > (q->buffer_size - q->buffer_used)) { - /* Not enough memory on the queue. */ - err = -EBUSY; - ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb)); - q->stopped = true; - goto out; - } - - /* Assign the queue number to the ring (if not already done before) - * so TX status handling can use it. The mac80211-queue to b43-queue - * mapping is static, so we don't need to store it per frame. */ - q->queue_prio = skb_get_queue_mapping(skb); - - err = pio_tx_frame(q, skb); - if (unlikely(err == -ENOKEY)) { - /* Drop this packet, as we don't have the encryption key - * anymore and must not transmit it unencrypted. */ - ieee80211_free_txskb(dev->wl->hw, skb); - err = 0; - goto out; - } - if (unlikely(err)) { - b43err(dev->wl, "PIO transmission failure\n"); - goto out; - } - - B43_WARN_ON(q->buffer_used > q->buffer_size); - if (((q->buffer_size - q->buffer_used) < roundup(2 + 2 + 6, 4)) || - (q->free_packet_slots == 0)) { - /* The queue is full. */ - ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb)); - q->stopped = true; - } - -out: - return err; -} - -void b43_pio_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status) -{ - struct b43_pio_txqueue *q; - struct b43_pio_txpacket *pack = NULL; - unsigned int total_len; - struct ieee80211_tx_info *info; - - q = parse_cookie(dev, status->cookie, &pack); - if (unlikely(!q)) - return; - B43_WARN_ON(!pack); - - info = IEEE80211_SKB_CB(pack->skb); - - b43_fill_txstatus_report(dev, info, status); - - total_len = pack->skb->len + b43_txhdr_size(dev); - total_len = roundup(total_len, 4); - q->buffer_used -= total_len; - q->free_packet_slots += 1; - - ieee80211_tx_status(dev->wl->hw, pack->skb); - pack->skb = NULL; - list_add(&pack->list, &q->packets_list); - - if (q->stopped) { - ieee80211_wake_queue(dev->wl->hw, q->queue_prio); - q->stopped = false; - } -} - -/* Returns whether we should fetch another frame. */ -static bool pio_rx_frame(struct b43_pio_rxqueue *q) -{ - struct b43_wldev *dev = q->dev; - struct b43_wl *wl = dev->wl; - u16 len; - u32 macstat = 0; - unsigned int i, padding; - struct sk_buff *skb; - const char *err_msg = NULL; - struct b43_rxhdr_fw4 *rxhdr = - (struct b43_rxhdr_fw4 *)wl->pio_scratchspace; - size_t rxhdr_size = sizeof(*rxhdr); - - BUILD_BUG_ON(sizeof(wl->pio_scratchspace) < sizeof(*rxhdr)); - switch (dev->fw.hdr_format) { - case B43_FW_HDR_410: - case B43_FW_HDR_351: - rxhdr_size -= sizeof(rxhdr->format_598) - - sizeof(rxhdr->format_351); - break; - case B43_FW_HDR_598: - break; - } - memset(rxhdr, 0, rxhdr_size); - - /* Check if we have data and wait for it to get ready. */ - if (q->rev >= 8) { - u32 ctl; - - ctl = b43_piorx_read32(q, B43_PIO8_RXCTL); - if (!(ctl & B43_PIO8_RXCTL_FRAMERDY)) - return false; - b43_piorx_write32(q, B43_PIO8_RXCTL, - B43_PIO8_RXCTL_FRAMERDY); - for (i = 0; i < 10; i++) { - ctl = b43_piorx_read32(q, B43_PIO8_RXCTL); - if (ctl & B43_PIO8_RXCTL_DATARDY) - goto data_ready; - udelay(10); - } - } else { - u16 ctl; - - ctl = b43_piorx_read16(q, B43_PIO_RXCTL); - if (!(ctl & B43_PIO_RXCTL_FRAMERDY)) - return false; - b43_piorx_write16(q, B43_PIO_RXCTL, - B43_PIO_RXCTL_FRAMERDY); - for (i = 0; i < 10; i++) { - ctl = b43_piorx_read16(q, B43_PIO_RXCTL); - if (ctl & B43_PIO_RXCTL_DATARDY) - goto data_ready; - udelay(10); - } - } - b43dbg(q->dev->wl, "PIO RX timed out\n"); - return true; -data_ready: - - /* Get the preamble (RX header) */ - if (q->rev >= 8) { - b43_block_read(dev, rxhdr, rxhdr_size, - q->mmio_base + B43_PIO8_RXDATA, - sizeof(u32)); - } else { - b43_block_read(dev, rxhdr, rxhdr_size, - q->mmio_base + B43_PIO_RXDATA, - sizeof(u16)); - } - /* Sanity checks. */ - len = le16_to_cpu(rxhdr->frame_len); - if (unlikely(len > 0x700)) { - err_msg = "len > 0x700"; - goto rx_error; - } - if (unlikely(len == 0)) { - err_msg = "len == 0"; - goto rx_error; - } - - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - macstat = le32_to_cpu(rxhdr->format_598.mac_status); - break; - case B43_FW_HDR_410: - case B43_FW_HDR_351: - macstat = le32_to_cpu(rxhdr->format_351.mac_status); - break; - } - if (macstat & B43_RX_MAC_FCSERR) { - if (!(q->dev->wl->filter_flags & FIF_FCSFAIL)) { - /* Drop frames with failed FCS. */ - err_msg = "Frame FCS error"; - goto rx_error; - } - } - - /* We always pad 2 bytes, as that's what upstream code expects - * due to the RX-header being 30 bytes. In case the frame is - * unaligned, we pad another 2 bytes. */ - padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0; - skb = dev_alloc_skb(len + padding + 2); - if (unlikely(!skb)) { - err_msg = "Out of memory"; - goto rx_error; - } - skb_reserve(skb, 2); - skb_put(skb, len + padding); - if (q->rev >= 8) { - b43_block_read(dev, skb->data + padding, (len & ~3), - q->mmio_base + B43_PIO8_RXDATA, - sizeof(u32)); - if (len & 3) { - u8 *tail = wl->pio_tailspace; - BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 4); - - /* Read the last few bytes. */ - b43_block_read(dev, tail, 4, - q->mmio_base + B43_PIO8_RXDATA, - sizeof(u32)); - switch (len & 3) { - case 3: - skb->data[len + padding - 3] = tail[0]; - skb->data[len + padding - 2] = tail[1]; - skb->data[len + padding - 1] = tail[2]; - break; - case 2: - skb->data[len + padding - 2] = tail[0]; - skb->data[len + padding - 1] = tail[1]; - break; - case 1: - skb->data[len + padding - 1] = tail[0]; - break; - } - } - } else { - b43_block_read(dev, skb->data + padding, (len & ~1), - q->mmio_base + B43_PIO_RXDATA, - sizeof(u16)); - if (len & 1) { - u8 *tail = wl->pio_tailspace; - BUILD_BUG_ON(sizeof(wl->pio_tailspace) < 2); - - /* Read the last byte. */ - b43_block_read(dev, tail, 2, - q->mmio_base + B43_PIO_RXDATA, - sizeof(u16)); - skb->data[len + padding - 1] = tail[0]; - } - } - - b43_rx(q->dev, skb, rxhdr); - - return true; - -rx_error: - if (err_msg) - b43dbg(q->dev->wl, "PIO RX error: %s\n", err_msg); - if (q->rev >= 8) - b43_piorx_write32(q, B43_PIO8_RXCTL, B43_PIO8_RXCTL_DATARDY); - else - b43_piorx_write16(q, B43_PIO_RXCTL, B43_PIO_RXCTL_DATARDY); - - return true; -} - -void b43_pio_rx(struct b43_pio_rxqueue *q) -{ - unsigned int count = 0; - bool stop; - - while (1) { - stop = (pio_rx_frame(q) == 0); - if (stop) - break; - cond_resched(); - if (WARN_ON_ONCE(++count > 10000)) - break; - } -} - -static void b43_pio_tx_suspend_queue(struct b43_pio_txqueue *q) -{ - if (q->rev >= 8) { - b43_piotx_write32(q, B43_PIO8_TXCTL, - b43_piotx_read32(q, B43_PIO8_TXCTL) - | B43_PIO8_TXCTL_SUSPREQ); - } else { - b43_piotx_write16(q, B43_PIO_TXCTL, - b43_piotx_read16(q, B43_PIO_TXCTL) - | B43_PIO_TXCTL_SUSPREQ); - } -} - -static void b43_pio_tx_resume_queue(struct b43_pio_txqueue *q) -{ - if (q->rev >= 8) { - b43_piotx_write32(q, B43_PIO8_TXCTL, - b43_piotx_read32(q, B43_PIO8_TXCTL) - & ~B43_PIO8_TXCTL_SUSPREQ); - } else { - b43_piotx_write16(q, B43_PIO_TXCTL, - b43_piotx_read16(q, B43_PIO_TXCTL) - & ~B43_PIO_TXCTL_SUSPREQ); - } -} - -void b43_pio_tx_suspend(struct b43_wldev *dev) -{ - b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); - b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BK); - b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_BE); - b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VI); - b43_pio_tx_suspend_queue(dev->pio.tx_queue_AC_VO); - b43_pio_tx_suspend_queue(dev->pio.tx_queue_mcast); -} - -void b43_pio_tx_resume(struct b43_wldev *dev) -{ - b43_pio_tx_resume_queue(dev->pio.tx_queue_mcast); - b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VO); - b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_VI); - b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BE); - b43_pio_tx_resume_queue(dev->pio.tx_queue_AC_BK); - b43_power_saving_ctl_bits(dev, 0); -} diff --git a/drivers/net/wireless/b43/pio.h b/drivers/net/wireless/b43/pio.h deleted file mode 100644 index 1e5161474..000000000 --- a/drivers/net/wireless/b43/pio.h +++ /dev/null @@ -1,165 +0,0 @@ -#ifndef B43_PIO_H_ -#define B43_PIO_H_ - -#include "b43.h" - -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/list.h> -#include <linux/skbuff.h> - - -/*** Registers for PIO queues up to revision 7. ***/ -/* TX queue. */ -#define B43_PIO_TXCTL 0x00 -#define B43_PIO_TXCTL_WRITELO 0x0001 -#define B43_PIO_TXCTL_WRITEHI 0x0002 -#define B43_PIO_TXCTL_EOF 0x0004 -#define B43_PIO_TXCTL_FREADY 0x0008 -#define B43_PIO_TXCTL_FLUSHREQ 0x0020 -#define B43_PIO_TXCTL_FLUSHPEND 0x0040 -#define B43_PIO_TXCTL_SUSPREQ 0x0080 -#define B43_PIO_TXCTL_QSUSP 0x0100 -#define B43_PIO_TXCTL_COMMCNT 0xFC00 -#define B43_PIO_TXCTL_COMMCNT_SHIFT 10 -#define B43_PIO_TXDATA 0x02 -#define B43_PIO_TXQBUFSIZE 0x04 -/* RX queue. */ -#define B43_PIO_RXCTL 0x00 -#define B43_PIO_RXCTL_FRAMERDY 0x0001 -#define B43_PIO_RXCTL_DATARDY 0x0002 -#define B43_PIO_RXDATA 0x02 - -/*** Registers for PIO queues revision 8 and later. ***/ -/* TX queue */ -#define B43_PIO8_TXCTL 0x00 -#define B43_PIO8_TXCTL_0_7 0x00000001 -#define B43_PIO8_TXCTL_8_15 0x00000002 -#define B43_PIO8_TXCTL_16_23 0x00000004 -#define B43_PIO8_TXCTL_24_31 0x00000008 -#define B43_PIO8_TXCTL_EOF 0x00000010 -#define B43_PIO8_TXCTL_FREADY 0x00000080 -#define B43_PIO8_TXCTL_SUSPREQ 0x00000100 -#define B43_PIO8_TXCTL_QSUSP 0x00000200 -#define B43_PIO8_TXCTL_FLUSHREQ 0x00000400 -#define B43_PIO8_TXCTL_FLUSHPEND 0x00000800 -#define B43_PIO8_TXDATA 0x04 -/* RX queue */ -#define B43_PIO8_RXCTL 0x00 -#define B43_PIO8_RXCTL_FRAMERDY 0x00000001 -#define B43_PIO8_RXCTL_DATARDY 0x00000002 -#define B43_PIO8_RXDATA 0x04 - - -/* The maximum number of TX-packets the HW can handle. */ -#define B43_PIO_MAX_NR_TXPACKETS 32 - - -struct b43_pio_txpacket { - /* Pointer to the TX queue we belong to. */ - struct b43_pio_txqueue *queue; - /* The TX data packet. */ - struct sk_buff *skb; - /* Index in the (struct b43_pio_txqueue)->packets array. */ - u8 index; - - struct list_head list; -}; - -struct b43_pio_txqueue { - struct b43_wldev *dev; - u16 mmio_base; - - /* The device queue buffer size in bytes. */ - u16 buffer_size; - /* The number of used bytes in the device queue buffer. */ - u16 buffer_used; - /* The number of packets that can still get queued. - * This is decremented on queueing a packet and incremented - * after receiving the transmit status. */ - u16 free_packet_slots; - - /* True, if the mac80211 queue was stopped due to overflow at TX. */ - bool stopped; - /* Our b43 queue index number */ - u8 index; - /* The mac80211 QoS queue priority. */ - u8 queue_prio; - - /* Buffer for TX packet meta data. */ - struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS]; - struct list_head packets_list; - - /* Shortcut to the 802.11 core revision. This is to - * avoid horrible pointer dereferencing in the fastpaths. */ - u8 rev; -}; - -struct b43_pio_rxqueue { - struct b43_wldev *dev; - u16 mmio_base; - - /* Shortcut to the 802.11 core revision. This is to - * avoid horrible pointer dereferencing in the fastpaths. */ - u8 rev; -}; - - -static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset) -{ - return b43_read16(q->dev, q->mmio_base + offset); -} - -static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset) -{ - return b43_read32(q->dev, q->mmio_base + offset); -} - -static inline void b43_piotx_write16(struct b43_pio_txqueue *q, - u16 offset, u16 value) -{ - b43_write16(q->dev, q->mmio_base + offset, value); -} - -static inline void b43_piotx_write32(struct b43_pio_txqueue *q, - u16 offset, u32 value) -{ - b43_write32(q->dev, q->mmio_base + offset, value); -} - - -static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset) -{ - return b43_read16(q->dev, q->mmio_base + offset); -} - -static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset) -{ - return b43_read32(q->dev, q->mmio_base + offset); -} - -static inline void b43_piorx_write16(struct b43_pio_rxqueue *q, - u16 offset, u16 value) -{ - b43_write16(q->dev, q->mmio_base + offset, value); -} - -static inline void b43_piorx_write32(struct b43_pio_rxqueue *q, - u16 offset, u32 value) -{ - b43_write32(q->dev, q->mmio_base + offset, value); -} - - -int b43_pio_init(struct b43_wldev *dev); -void b43_pio_free(struct b43_wldev *dev); - -int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb); -void b43_pio_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status); -void b43_pio_rx(struct b43_pio_rxqueue *q); - -void b43_pio_tx_suspend(struct b43_wldev *dev); -void b43_pio_tx_resume(struct b43_wldev *dev); - -#endif /* B43_PIO_H_ */ diff --git a/drivers/net/wireless/b43/ppr.c b/drivers/net/wireless/b43/ppr.c deleted file mode 100644 index 9a770279c..000000000 --- a/drivers/net/wireless/b43/ppr.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Broadcom B43 wireless driver - * PPR (Power Per Rate) management - * - * Copyright (c) 2014 Rafał Miłecki <zajec5@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "ppr.h" -#include "b43.h" - -#define ppr_for_each_entry(ppr, i, entry) \ - for (i = 0, entry = &(ppr)->__all_rates[i]; \ - i < B43_PPR_RATES_NUM; \ - i++, entry++) - -void b43_ppr_clear(struct b43_wldev *dev, struct b43_ppr *ppr) -{ - memset(ppr, 0, sizeof(*ppr)); - - /* Compile-time PPR check */ - BUILD_BUG_ON(sizeof(struct b43_ppr) != B43_PPR_RATES_NUM * sizeof(u8)); -} - -void b43_ppr_add(struct b43_wldev *dev, struct b43_ppr *ppr, int diff) -{ - int i; - u8 *rate; - - ppr_for_each_entry(ppr, i, rate) { - *rate = clamp_val(*rate + diff, 0, 127); - } -} - -void b43_ppr_apply_max(struct b43_wldev *dev, struct b43_ppr *ppr, u8 max) -{ - int i; - u8 *rate; - - ppr_for_each_entry(ppr, i, rate) { - *rate = min(*rate, max); - } -} - -void b43_ppr_apply_min(struct b43_wldev *dev, struct b43_ppr *ppr, u8 min) -{ - int i; - u8 *rate; - - ppr_for_each_entry(ppr, i, rate) { - *rate = max(*rate, min); - } -} - -u8 b43_ppr_get_max(struct b43_wldev *dev, struct b43_ppr *ppr) -{ - u8 res = 0; - int i; - u8 *rate; - - ppr_for_each_entry(ppr, i, rate) { - res = max(*rate, res); - } - - return res; -} - -bool b43_ppr_load_max_from_sprom(struct b43_wldev *dev, struct b43_ppr *ppr, - enum b43_band band) -{ - struct b43_ppr_rates *rates = &ppr->rates; - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - u8 maxpwr, off; - u32 sprom_ofdm_po; - u16 *sprom_mcs_po; - u8 extra_cdd_po, extra_stbc_po; - int i; - - switch (band) { - case B43_BAND_2G: - maxpwr = min(sprom->core_pwr_info[0].maxpwr_2g, - sprom->core_pwr_info[1].maxpwr_2g); - sprom_ofdm_po = sprom->ofdm2gpo; - sprom_mcs_po = sprom->mcs2gpo; - extra_cdd_po = (sprom->cddpo >> 0) & 0xf; - extra_stbc_po = (sprom->stbcpo >> 0) & 0xf; - break; - case B43_BAND_5G_LO: - maxpwr = min(sprom->core_pwr_info[0].maxpwr_5gl, - sprom->core_pwr_info[1].maxpwr_5gl); - sprom_ofdm_po = sprom->ofdm5glpo; - sprom_mcs_po = sprom->mcs5glpo; - extra_cdd_po = (sprom->cddpo >> 8) & 0xf; - extra_stbc_po = (sprom->stbcpo >> 8) & 0xf; - break; - case B43_BAND_5G_MI: - maxpwr = min(sprom->core_pwr_info[0].maxpwr_5g, - sprom->core_pwr_info[1].maxpwr_5g); - sprom_ofdm_po = sprom->ofdm5gpo; - sprom_mcs_po = sprom->mcs5gpo; - extra_cdd_po = (sprom->cddpo >> 4) & 0xf; - extra_stbc_po = (sprom->stbcpo >> 4) & 0xf; - break; - case B43_BAND_5G_HI: - maxpwr = min(sprom->core_pwr_info[0].maxpwr_5gh, - sprom->core_pwr_info[1].maxpwr_5gh); - sprom_ofdm_po = sprom->ofdm5ghpo; - sprom_mcs_po = sprom->mcs5ghpo; - extra_cdd_po = (sprom->cddpo >> 12) & 0xf; - extra_stbc_po = (sprom->stbcpo >> 12) & 0xf; - break; - default: - WARN_ON_ONCE(1); - return false; - } - - if (band == B43_BAND_2G) { - for (i = 0; i < 4; i++) { - off = ((sprom->cck2gpo >> (i * 4)) & 0xf) * 2; - rates->cck[i] = maxpwr - off; - } - } - - /* OFDM */ - for (i = 0; i < 8; i++) { - off = ((sprom_ofdm_po >> (i * 4)) & 0xf) * 2; - rates->ofdm[i] = maxpwr - off; - } - - /* MCS 20 SISO */ - rates->mcs_20[0] = rates->ofdm[0]; - rates->mcs_20[1] = rates->ofdm[2]; - rates->mcs_20[2] = rates->ofdm[3]; - rates->mcs_20[3] = rates->ofdm[4]; - rates->mcs_20[4] = rates->ofdm[5]; - rates->mcs_20[5] = rates->ofdm[6]; - rates->mcs_20[6] = rates->ofdm[7]; - rates->mcs_20[7] = rates->ofdm[7]; - - /* MCS 20 CDD */ - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_cdd[i] = maxpwr - off; - if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) - rates->mcs_20_cdd[i] -= extra_cdd_po; - } - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_cdd[4 + i] = maxpwr - off; - if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) - rates->mcs_20_cdd[4 + i] -= extra_cdd_po; - } - - /* OFDM 20 CDD */ - rates->ofdm_20_cdd[0] = rates->mcs_20_cdd[0]; - rates->ofdm_20_cdd[1] = rates->mcs_20_cdd[0]; - rates->ofdm_20_cdd[2] = rates->mcs_20_cdd[1]; - rates->ofdm_20_cdd[3] = rates->mcs_20_cdd[2]; - rates->ofdm_20_cdd[4] = rates->mcs_20_cdd[3]; - rates->ofdm_20_cdd[5] = rates->mcs_20_cdd[4]; - rates->ofdm_20_cdd[6] = rates->mcs_20_cdd[5]; - rates->ofdm_20_cdd[7] = rates->mcs_20_cdd[6]; - - /* MCS 20 STBC */ - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_stbc[i] = maxpwr - off; - if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) - rates->mcs_20_stbc[i] -= extra_stbc_po; - } - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_stbc[4 + i] = maxpwr - off; - if (phy->type == B43_PHYTYPE_N && phy->rev >= 3) - rates->mcs_20_stbc[4 + i] -= extra_stbc_po; - } - - /* MCS 20 SDM */ - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[2] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_sdm[i] = maxpwr - off; - } - for (i = 0; i < 4; i++) { - off = ((sprom_mcs_po[3] >> (i * 4)) & 0xf) * 2; - rates->mcs_20_sdm[4 + i] = maxpwr - off; - } - - return true; -} diff --git a/drivers/net/wireless/b43/ppr.h b/drivers/net/wireless/b43/ppr.h deleted file mode 100644 index 24d7447e9..000000000 --- a/drivers/net/wireless/b43/ppr.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef LINUX_B43_PPR_H_ -#define LINUX_B43_PPR_H_ - -#include <linux/types.h> - -#define B43_PPR_CCK_RATES_NUM 4 -#define B43_PPR_OFDM_RATES_NUM 8 -#define B43_PPR_MCS_RATES_NUM 8 - -#define B43_PPR_RATES_NUM (B43_PPR_CCK_RATES_NUM + \ - B43_PPR_OFDM_RATES_NUM * 2 + \ - B43_PPR_MCS_RATES_NUM * 4) - -struct b43_ppr_rates { - u8 cck[B43_PPR_CCK_RATES_NUM]; - u8 ofdm[B43_PPR_OFDM_RATES_NUM]; - u8 ofdm_20_cdd[B43_PPR_OFDM_RATES_NUM]; - u8 mcs_20[B43_PPR_MCS_RATES_NUM]; /* SISO */ - u8 mcs_20_cdd[B43_PPR_MCS_RATES_NUM]; - u8 mcs_20_stbc[B43_PPR_MCS_RATES_NUM]; - u8 mcs_20_sdm[B43_PPR_MCS_RATES_NUM]; -}; - -struct b43_ppr { - /* All powers are in qdbm (Q5.2) */ - union { - u8 __all_rates[B43_PPR_RATES_NUM]; - struct b43_ppr_rates rates; - }; -}; - -struct b43_wldev; -enum b43_band; - -void b43_ppr_clear(struct b43_wldev *dev, struct b43_ppr *ppr); - -void b43_ppr_add(struct b43_wldev *dev, struct b43_ppr *ppr, int diff); -void b43_ppr_apply_max(struct b43_wldev *dev, struct b43_ppr *ppr, u8 max); -void b43_ppr_apply_min(struct b43_wldev *dev, struct b43_ppr *ppr, u8 min); -u8 b43_ppr_get_max(struct b43_wldev *dev, struct b43_ppr *ppr); - -bool b43_ppr_load_max_from_sprom(struct b43_wldev *dev, struct b43_ppr *ppr, - enum b43_band band); - -#endif /* LINUX_B43_PPR_H_ */ diff --git a/drivers/net/wireless/b43/radio_2055.c b/drivers/net/wireless/b43/radio_2055.c deleted file mode 100644 index 5289a18dd..000000000 --- a/drivers/net/wireless/b43/radio_2055.c +++ /dev/null @@ -1,1335 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n PHY and radio device data tables - - Copyright (c) 2008 Michael Buesch <m@bues.ch> - Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "radio_2055.h" -#include "phy_common.h" - -struct b2055_inittab_entry { - /* Value to write if we use the 5GHz band. */ - u16 ghz5; - /* Value to write if we use the 2.4GHz band. */ - u16 ghz2; - /* Flags */ - u8 flags; -#define B2055_INITTAB_ENTRY_OK 0x01 -#define B2055_INITTAB_UPLOAD 0x02 -}; -#define UPLOAD .flags = B2055_INITTAB_ENTRY_OK | B2055_INITTAB_UPLOAD -#define NOUPLOAD .flags = B2055_INITTAB_ENTRY_OK - -static const struct b2055_inittab_entry b2055_inittab [] = { - [B2055_SP_PINPD] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, - [B2055_C1_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, }, - [B2055_C2_SP_RSSI] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_SP_PDMISC] = { .ghz5 = 0x0027, .ghz2 = 0x0027, NOUPLOAD, }, - [B2055_C1_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, }, - [B2055_C1_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2055_C2_SP_RXGC1] = { .ghz5 = 0x007F, .ghz2 = 0x007F, UPLOAD, }, - [B2055_C2_SP_RXGC2] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2055_C1_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2055_C2_SP_LPFBWSEL] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2055_C1_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, }, - [B2055_C1_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, - [B2055_C2_SP_TXGC1] = { .ghz5 = 0x004F, .ghz2 = 0x004F, UPLOAD, }, - [B2055_C2_SP_TXGC2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, - [B2055_MASTER1] = { .ghz5 = 0x00D0, .ghz2 = 0x00D0, NOUPLOAD, }, - [B2055_MASTER2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2055_PD_LGEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_PD_PLLTS] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2055_C1_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_PD_LGBUF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_PD_TX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_PD_RXTX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_PD_RSSIMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_PWRDET_LGEN] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, - [B2055_C1_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, - [B2055_C1_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, - [B2055_C2_PWRDET_LGBUF] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, - [B2055_C2_PWRDET_RXTX] = { .ghz5 = 0x00C0, .ghz2 = 0x00C0, NOUPLOAD, }, - [B2055_RRCCAL_CS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_RRCCAL_NOPTSEL] = { .ghz5 = 0x002C, .ghz2 = 0x002C, NOUPLOAD, }, - [B2055_CAL_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_COUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_COUT2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_CVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_RVARCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_LPOCTL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_TS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_RCCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_CAL_RCALRTS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_PADDRV] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, - [B2055_XOCTL1] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2055_XOCTL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_XOREGUL] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2055_XOMISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_PLL_LFC1] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, - [B2055_PLL_CALVTH] = { .ghz5 = 0x0087, .ghz2 = 0x0087, NOUPLOAD, }, - [B2055_PLL_LFC2] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, }, - [B2055_PLL_REF] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2055_PLL_LFR1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2055_PLL_PFDCP] = { .ghz5 = 0x0018, .ghz2 = 0x0018, UPLOAD, }, - [B2055_PLL_IDAC_CPOPAMP] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_PLL_CPREG] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2055_PLL_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_RF_PLLMOD0] = { .ghz5 = 0x009E, .ghz2 = 0x009E, NOUPLOAD, }, - [B2055_RF_PLLMOD1] = { .ghz5 = 0x0009, .ghz2 = 0x0009, NOUPLOAD, }, - [B2055_RF_MMDIDAC1] = { .ghz5 = 0x00C8, .ghz2 = 0x00C8, UPLOAD, }, - [B2055_RF_MMDIDAC0] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_RF_MMDSP] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL3] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2055_VCO_CAL4] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2055_VCO_CAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2055_VCO_CAL6] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, }, - [B2055_VCO_CAL7] = { .ghz5 = 0x003E, .ghz2 = 0x003E, NOUPLOAD, }, - [B2055_VCO_CAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2055_VCO_CAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2055_VCO_CAL10] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2055_VCO_CAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2055_VCO_CAL12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_CAL16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_VCO_KVCO] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_VCO_CAPTAIL] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_VCO_IDACVCO] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_VCO_REG] = { .ghz5 = 0x0084, .ghz2 = 0x0084, UPLOAD, }, - [B2055_PLL_RFVTH] = { .ghz5 = 0x00C3, .ghz2 = 0x00C3, NOUPLOAD, }, - [B2055_LGBUF_CENBUF] = { .ghz5 = 0x008F, .ghz2 = 0x008F, NOUPLOAD, }, - [B2055_LGEN_TUNE1] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, - [B2055_LGEN_TUNE2] = { .ghz5 = 0x00FF, .ghz2 = 0x00FF, NOUPLOAD, }, - [B2055_LGEN_IDAC1] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_LGEN_IDAC2] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_LGEN_BIASC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_LGEN_BIASIDAC] = { .ghz5 = 0x00CC, .ghz2 = 0x00CC, NOUPLOAD, }, - [B2055_LGEN_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_LGEN_DIV] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, - [B2055_LGEN_SPARE2] = { .ghz5 = 0x0080, .ghz2 = 0x0080, NOUPLOAD, }, - [B2055_C1_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, }, - [B2055_C1_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C1_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C1_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, }, - [B2055_C1_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C1_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, }, - [B2055_C1_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, }, - [B2055_C1_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_C1_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2055_C1_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C1_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, }, - [B2055_C1_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, - [B2055_C1_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, - [B2055_C1_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C1_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C1_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C1_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C1_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C1_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, }, - [B2055_C1_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, }, - [B2055_C1_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, }, - [B2055_C1_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, }, - [B2055_C1_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, }, - [B2055_C1_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, - [B2055_C1_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C1_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2055_C1_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2055_C1_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2055_C1_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2055_C1_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, }, - [B2055_C1_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_C1_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, }, - [B2055_C1_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, }, - [B2055_C1_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C1_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C1_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, - [B2055_C1_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, - [B2055_C1_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, - [B2055_C1_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C1_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, - [B2055_C1_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C1_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, }, - [B2055_C1_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, }, - [B2055_C1_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_LGBUF_ATUNE] = { .ghz5 = 0x00F8, .ghz2 = 0x00F8, NOUPLOAD, }, - [B2055_C2_LGBUF_GTUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C2_LGBUF_DIV] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C2_LGBUF_AIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0008, UPLOAD, }, - [B2055_C2_LGBUF_GIDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C2_LGBUF_IDACFO] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_LGBUF_SPARE] = { .ghz5 = 0x0001, .ghz2 = 0x0001, UPLOAD, }, - [B2055_C2_RX_RFSPC1] = { .ghz5 = 0x008A, .ghz2 = 0x008A, NOUPLOAD, }, - [B2055_C2_RX_RFR1] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_C2_RX_RFR2] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2055_C2_RX_RFRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C2_RX_BB_BLCMP] = { .ghz5 = 0x00A0, .ghz2 = 0x00A0, NOUPLOAD, }, - [B2055_C2_RX_BB_LPF] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, - [B2055_C2_RX_BB_MIDACHP] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, - [B2055_C2_RX_BB_VGA1IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C2_RX_BB_VGA2IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C2_RX_BB_VGA3IDAC] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C2_RX_BB_BUFOCTL] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C2_RX_BB_RCCALCTL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C2_RX_BB_RSSICTL1] = { .ghz5 = 0x006A, .ghz2 = 0x006A, UPLOAD, }, - [B2055_C2_RX_BB_RSSICTL2] = { .ghz5 = 0x00AB, .ghz2 = 0x00AB, UPLOAD, }, - [B2055_C2_RX_BB_RSSICTL3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, UPLOAD, }, - [B2055_C2_RX_BB_RSSICTL4] = { .ghz5 = 0x00C1, .ghz2 = 0x00C1, UPLOAD, }, - [B2055_C2_RX_BB_RSSICTL5] = { .ghz5 = 0x00AA, .ghz2 = 0x00AA, UPLOAD, }, - [B2055_C2_RX_BB_REG] = { .ghz5 = 0x0087, .ghz2 = 0x0087, UPLOAD, }, - [B2055_C2_RX_BB_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_RX_TXBBRCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C2_TX_RF_SPGA] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2055_C2_TX_RF_SPAD] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2055_C2_TX_RF_CNTPGA1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2055_C2_TX_RF_CNTPAD1] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2055_C2_TX_RF_PGAIDAC] = { .ghz5 = 0x0097, .ghz2 = 0x0097, UPLOAD, }, - [B2055_C2_TX_PGAPADTN] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2055_C2_TX_PADIDAC1] = { .ghz5 = 0x0014, .ghz2 = 0x0014, UPLOAD, }, - [B2055_C2_TX_PADIDAC2] = { .ghz5 = 0x0033, .ghz2 = 0x0033, NOUPLOAD, }, - [B2055_C2_TX_MXBGTRIM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2055_C2_TX_RF_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2055_C2_TX_RF_PADTSSI1] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, - [B2055_C2_TX_RF_PADTSSI2] = { .ghz5 = 0x000A, .ghz2 = 0x000A, NOUPLOAD, }, - [B2055_C2_TX_RF_SPARE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, UPLOAD, }, - [B2055_C2_TX_RF_IQCAL1] = { .ghz5 = 0x002A, .ghz2 = 0x002A, NOUPLOAD, }, - [B2055_C2_TX_RF_IQCAL2] = { .ghz5 = 0x00A4, .ghz2 = 0x00A4, NOUPLOAD, }, - [B2055_C2_TXBB_RCCAL] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C2_TXBB_LPF1] = { .ghz5 = 0x0028, .ghz2 = 0x0028, NOUPLOAD, }, - [B2055_C2_TX_VOSCNCL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_TX_LPF_MXGMIDAC] = { .ghz5 = 0x004A, .ghz2 = 0x004A, NOUPLOAD, }, - [B2055_C2_TX_BB_MXGM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_PRG_GCHP21] = { .ghz5 = 0x0071, .ghz2 = 0x0071, NOUPLOAD, }, - [B2055_PRG_GCHP22] = { .ghz5 = 0x0072, .ghz2 = 0x0072, NOUPLOAD, }, - [B2055_PRG_GCHP23] = { .ghz5 = 0x0073, .ghz2 = 0x0073, NOUPLOAD, }, - [B2055_PRG_GCHP24] = { .ghz5 = 0x0074, .ghz2 = 0x0074, NOUPLOAD, }, - [B2055_PRG_GCHP25] = { .ghz5 = 0x0075, .ghz2 = 0x0075, NOUPLOAD, }, - [B2055_PRG_GCHP26] = { .ghz5 = 0x0076, .ghz2 = 0x0076, NOUPLOAD, }, - [B2055_PRG_GCHP27] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2055_PRG_GCHP28] = { .ghz5 = 0x0078, .ghz2 = 0x0078, NOUPLOAD, }, - [B2055_PRG_GCHP29] = { .ghz5 = 0x0079, .ghz2 = 0x0079, NOUPLOAD, }, - [B2055_PRG_GCHP30] = { .ghz5 = 0x007A, .ghz2 = 0x007A, NOUPLOAD, }, - [0xC7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xC8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xC9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xCA] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xCB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xCC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xCE] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [0xCF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD1] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C1_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [0xD3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C1_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xD8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_LNA_GAINBST] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xDA] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [0xDB] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xDC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xDD] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2055_C2_B0NB_RSSIVCM] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [0xDF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xE0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [0xE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2055_C2_GENSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -#define RADIOREGS(r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, \ - r12, r13, r14, r15, r16, r17, r18, r19, r20, r21) \ - .radio_pll_ref = r0, \ - .radio_rf_pllmod0 = r1, \ - .radio_rf_pllmod1 = r2, \ - .radio_vco_captail = r3, \ - .radio_vco_cal1 = r4, \ - .radio_vco_cal2 = r5, \ - .radio_pll_lfc1 = r6, \ - .radio_pll_lfr1 = r7, \ - .radio_pll_lfc2 = r8, \ - .radio_lgbuf_cenbuf = r9, \ - .radio_lgen_tune1 = r10, \ - .radio_lgen_tune2 = r11, \ - .radio_c1_lgbuf_atune = r12, \ - .radio_c1_lgbuf_gtune = r13, \ - .radio_c1_rx_rfr1 = r14, \ - .radio_c1_tx_pgapadtn = r15, \ - .radio_c1_tx_mxbgtrim = r16, \ - .radio_c2_lgbuf_atune = r17, \ - .radio_c2_lgbuf_gtune = r18, \ - .radio_c2_rx_rfr1 = r19, \ - .radio_c2_tx_pgapadtn = r20, \ - .radio_c2_tx_mxbgtrim = r21 - -#define PHYREGS(r0, r1, r2, r3, r4, r5) \ - .phy_regs.phy_bw1a = r0, \ - .phy_regs.phy_bw2 = r1, \ - .phy_regs.phy_bw3 = r2, \ - .phy_regs.phy_bw4 = r3, \ - .phy_regs.phy_bw5 = r4, \ - .phy_regs.phy_bw6 = r5 - -static const struct b43_nphy_channeltab_entry_rev2 b43_nphy_channeltab_rev2[] = { - { .channel = 184, - .freq = 4920, /* MHz */ - .unk2 = 3280, - RADIOREGS(0x71, 0xEC, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07B4, 0x07B0, 0x07AC, 0x0214, 0x0215, 0x0216), - }, - { .channel = 186, - .freq = 4930, /* MHz */ - .unk2 = 3287, - RADIOREGS(0x71, 0xED, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07B8, 0x07B4, 0x07B0, 0x0213, 0x0214, 0x0215), - }, - { .channel = 188, - .freq = 4940, /* MHz */ - .unk2 = 3293, - RADIOREGS(0x71, 0xEE, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07BC, 0x07B8, 0x07B4, 0x0212, 0x0213, 0x0214), - }, - { .channel = 190, - .freq = 4950, /* MHz */ - .unk2 = 3300, - RADIOREGS(0x71, 0xEF, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07C0, 0x07BC, 0x07B8, 0x0211, 0x0212, 0x0213), - }, - { .channel = 192, - .freq = 4960, /* MHz */ - .unk2 = 3307, - RADIOREGS(0x71, 0xF0, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07C4, 0x07C0, 0x07BC, 0x020F, 0x0211, 0x0212), - }, - { .channel = 194, - .freq = 4970, /* MHz */ - .unk2 = 3313, - RADIOREGS(0x71, 0xF1, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07C8, 0x07C4, 0x07C0, 0x020E, 0x020F, 0x0211), - }, - { .channel = 196, - .freq = 4980, /* MHz */ - .unk2 = 3320, - RADIOREGS(0x71, 0xF2, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07CC, 0x07C8, 0x07C4, 0x020D, 0x020E, 0x020F), - }, - { .channel = 198, - .freq = 4990, /* MHz */ - .unk2 = 3327, - RADIOREGS(0x71, 0xF3, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07D0, 0x07CC, 0x07C8, 0x020C, 0x020D, 0x020E), - }, - { .channel = 200, - .freq = 5000, /* MHz */ - .unk2 = 3333, - RADIOREGS(0x71, 0xF4, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07D4, 0x07D0, 0x07CC, 0x020B, 0x020C, 0x020D), - }, - { .channel = 202, - .freq = 5010, /* MHz */ - .unk2 = 3340, - RADIOREGS(0x71, 0xF5, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07D8, 0x07D4, 0x07D0, 0x020A, 0x020B, 0x020C), - }, - { .channel = 204, - .freq = 5020, /* MHz */ - .unk2 = 3347, - RADIOREGS(0x71, 0xF6, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07DC, 0x07D8, 0x07D4, 0x0209, 0x020A, 0x020B), - }, - { .channel = 206, - .freq = 5030, /* MHz */ - .unk2 = 3353, - RADIOREGS(0x71, 0xF7, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07E0, 0x07DC, 0x07D8, 0x0208, 0x0209, 0x020A), - }, - { .channel = 208, - .freq = 5040, /* MHz */ - .unk2 = 3360, - RADIOREGS(0x71, 0xF8, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07E4, 0x07E0, 0x07DC, 0x0207, 0x0208, 0x0209), - }, - { .channel = 210, - .freq = 5050, /* MHz */ - .unk2 = 3367, - RADIOREGS(0x71, 0xF9, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F, - 0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F), - PHYREGS(0x07E8, 0x07E4, 0x07E0, 0x0206, 0x0207, 0x0208), - }, - { .channel = 212, - .freq = 5060, /* MHz */ - .unk2 = 3373, - RADIOREGS(0x71, 0xFA, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, - 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E), - PHYREGS(0x07EC, 0x07E8, 0x07E4, 0x0205, 0x0206, 0x0207), - }, - { .channel = 214, - .freq = 5070, /* MHz */ - .unk2 = 3380, - RADIOREGS(0x71, 0xFB, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A, - 0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F, - 0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E), - PHYREGS(0x07F0, 0x07EC, 0x07E8, 0x0204, 0x0205, 0x0206), - }, - { .channel = 216, - .freq = 5080, /* MHz */ - .unk2 = 3387, - RADIOREGS(0x71, 0xFC, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A, - 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, - 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D), - PHYREGS(0x07F4, 0x07F0, 0x07EC, 0x0203, 0x0204, 0x0205), - }, - { .channel = 218, - .freq = 5090, /* MHz */ - .unk2 = 3393, - RADIOREGS(0x71, 0xFD, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A, - 0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F, - 0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D), - PHYREGS(0x07F8, 0x07F4, 0x07F0, 0x0202, 0x0203, 0x0204), - }, - { .channel = 220, - .freq = 5100, /* MHz */ - .unk2 = 3400, - RADIOREGS(0x71, 0xFE, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A, - 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, - 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D), - PHYREGS(0x07FC, 0x07F8, 0x07F4, 0x0201, 0x0202, 0x0203), - }, - { .channel = 222, - .freq = 5110, /* MHz */ - .unk2 = 3407, - RADIOREGS(0x71, 0xFF, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A, - 0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F, - 0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D), - PHYREGS(0x0800, 0x07FC, 0x07F8, 0x0200, 0x0201, 0x0202), - }, - { .channel = 224, - .freq = 5120, /* MHz */ - .unk2 = 3413, - RADIOREGS(0x71, 0x00, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A, - 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, - 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C), - PHYREGS(0x0804, 0x0800, 0x07FC, 0x01FF, 0x0200, 0x0201), - }, - { .channel = 226, - .freq = 5130, /* MHz */ - .unk2 = 3420, - RADIOREGS(0x71, 0x01, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A, - 0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F, - 0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01FE, 0x01FF, 0x0200), - }, - { .channel = 228, - .freq = 5140, /* MHz */ - .unk2 = 3427, - RADIOREGS(0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A, - 0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E, - 0x8B, 0xDD, 0x00, 0x0C, 0x0E, 0x8B), - PHYREGS(0x080C, 0x0808, 0x0804, 0x01FD, 0x01FE, 0x01FF), - }, - { .channel = 32, - .freq = 5160, /* MHz */ - .unk2 = 3440, - RADIOREGS(0x71, 0x04, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A, - 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, - 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A), - PHYREGS(0x0814, 0x0810, 0x080C, 0x01FB, 0x01FC, 0x01FD), - }, - { .channel = 34, - .freq = 5170, /* MHz */ - .unk2 = 3447, - RADIOREGS(0x71, 0x05, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A, - 0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D, - 0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01FA, 0x01FB, 0x01FC), - }, - { .channel = 36, - .freq = 5180, /* MHz */ - .unk2 = 3453, - RADIOREGS(0x71, 0x06, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A, - 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, - 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89), - PHYREGS(0x081C, 0x0818, 0x0814, 0x01F9, 0x01FA, 0x01FB), - }, - { .channel = 38, - .freq = 5190, /* MHz */ - .unk2 = 3460, - RADIOREGS(0x71, 0x07, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A, - 0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C, - 0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89), - PHYREGS(0x0820, 0x081C, 0x0818, 0x01F8, 0x01F9, 0x01FA), - }, - { .channel = 40, - .freq = 5200, /* MHz */ - .unk2 = 3467, - RADIOREGS(0x71, 0x08, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A, - 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, - 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89), - PHYREGS(0x0824, 0x0820, 0x081C, 0x01F7, 0x01F8, 0x01F9), - }, - { .channel = 42, - .freq = 5210, /* MHz */ - .unk2 = 3473, - RADIOREGS(0x71, 0x09, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A, - 0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B, - 0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01F6, 0x01F7, 0x01F8), - }, - { .channel = 44, - .freq = 5220, /* MHz */ - .unk2 = 3480, - RADIOREGS(0x71, 0x0A, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A, - 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, - 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88), - PHYREGS(0x082C, 0x0828, 0x0824, 0x01F5, 0x01F6, 0x01F7), - }, - { .channel = 46, - .freq = 5230, /* MHz */ - .unk2 = 3487, - RADIOREGS(0x71, 0x0B, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A, - 0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A, - 0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88), - PHYREGS(0x0830, 0x082C, 0x0828, 0x01F4, 0x01F5, 0x01F6), - }, - { .channel = 48, - .freq = 5240, /* MHz */ - .unk2 = 3493, - RADIOREGS(0x71, 0x0C, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A, - 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, - 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87), - PHYREGS(0x0834, 0x0830, 0x082C, 0x01F3, 0x01F4, 0x01F5), - }, - { .channel = 50, - .freq = 5250, /* MHz */ - .unk2 = 3500, - RADIOREGS(0x71, 0x0D, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A, - 0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A, - 0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01F2, 0x01F3, 0x01F4), - }, - { .channel = 52, - .freq = 5260, /* MHz */ - .unk2 = 3507, - RADIOREGS(0x71, 0x0E, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A, - 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, - 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87), - PHYREGS(0x083C, 0x0838, 0x0834, 0x01F1, 0x01F2, 0x01F3), - }, - { .channel = 54, - .freq = 5270, /* MHz */ - .unk2 = 3513, - RADIOREGS(0x71, 0x0F, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A, - 0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09, - 0x87, 0xAA, 0x00, 0x08, 0x09, 0x87), - PHYREGS(0x0840, 0x083C, 0x0838, 0x01F0, 0x01F1, 0x01F2), - }, - { .channel = 56, - .freq = 5280, /* MHz */ - .unk2 = 3520, - RADIOREGS(0x71, 0x10, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A, - 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, - 0x86, 0x99, 0x00, 0x08, 0x08, 0x86), - PHYREGS(0x0844, 0x0840, 0x083C, 0x01F0, 0x01F0, 0x01F1), - }, - { .channel = 58, - .freq = 5290, /* MHz */ - .unk2 = 3527, - RADIOREGS(0x71, 0x11, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A, - 0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08, - 0x86, 0x99, 0x00, 0x08, 0x08, 0x86), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01EF, 0x01F0, 0x01F0), - }, - { .channel = 60, - .freq = 5300, /* MHz */ - .unk2 = 3533, - RADIOREGS(0x71, 0x12, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A, - 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, - 0x85, 0x99, 0x00, 0x08, 0x07, 0x85), - PHYREGS(0x084C, 0x0848, 0x0844, 0x01EE, 0x01EF, 0x01F0), - }, - { .channel = 62, - .freq = 5310, /* MHz */ - .unk2 = 3540, - RADIOREGS(0x71, 0x13, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A, - 0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07, - 0x85, 0x99, 0x00, 0x08, 0x07, 0x85), - PHYREGS(0x0850, 0x084C, 0x0848, 0x01ED, 0x01EE, 0x01EF), - }, - { .channel = 64, - .freq = 5320, /* MHz */ - .unk2 = 3547, - RADIOREGS(0x71, 0x14, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A, - 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, - 0x84, 0x88, 0x00, 0x07, 0x07, 0x84), - PHYREGS(0x0854, 0x0850, 0x084C, 0x01EC, 0x01ED, 0x01EE), - }, - { .channel = 66, - .freq = 5330, /* MHz */ - .unk2 = 3553, - RADIOREGS(0x71, 0x15, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A, - 0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07, - 0x84, 0x88, 0x00, 0x07, 0x07, 0x84), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01EB, 0x01EC, 0x01ED), - }, - { .channel = 68, - .freq = 5340, /* MHz */ - .unk2 = 3560, - RADIOREGS(0x71, 0x16, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A, - 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, - 0x84, 0x88, 0x00, 0x07, 0x06, 0x84), - PHYREGS(0x085C, 0x0858, 0x0854, 0x01EA, 0x01EB, 0x01EC), - }, - { .channel = 70, - .freq = 5350, /* MHz */ - .unk2 = 3567, - RADIOREGS(0x71, 0x17, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A, - 0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06, - 0x84, 0x88, 0x00, 0x07, 0x06, 0x84), - PHYREGS(0x0860, 0x085C, 0x0858, 0x01E9, 0x01EA, 0x01EB), - }, - { .channel = 72, - .freq = 5360, /* MHz */ - .unk2 = 3573, - RADIOREGS(0x71, 0x18, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A, - 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, - 0x83, 0x77, 0x00, 0x06, 0x05, 0x83), - PHYREGS(0x0864, 0x0860, 0x085C, 0x01E8, 0x01E9, 0x01EA), - }, - { .channel = 74, - .freq = 5370, /* MHz */ - .unk2 = 3580, - RADIOREGS(0x71, 0x19, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A, - 0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05, - 0x83, 0x77, 0x00, 0x06, 0x05, 0x83), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01E7, 0x01E8, 0x01E9), - }, - { .channel = 76, - .freq = 5380, /* MHz */ - .unk2 = 3587, - RADIOREGS(0x71, 0x1A, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A, - 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04, - 0x82, 0x77, 0x00, 0x06, 0x04, 0x82), - PHYREGS(0x086C, 0x0868, 0x0864, 0x01E6, 0x01E7, 0x01E8), - }, - { .channel = 78, - .freq = 5390, /* MHz */ - .unk2 = 3593, - RADIOREGS(0x71, 0x1B, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A, - 0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04, - 0x82, 0x77, 0x00, 0x06, 0x04, 0x82), - PHYREGS(0x0870, 0x086C, 0x0868, 0x01E5, 0x01E6, 0x01E7), - }, - { .channel = 80, - .freq = 5400, /* MHz */ - .unk2 = 3600, - RADIOREGS(0x71, 0x1C, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A, - 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04, - 0x81, 0x66, 0x00, 0x05, 0x04, 0x81), - PHYREGS(0x0874, 0x0870, 0x086C, 0x01E5, 0x01E5, 0x01E6), - }, - { .channel = 82, - .freq = 5410, /* MHz */ - .unk2 = 3607, - RADIOREGS(0x71, 0x1D, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A, - 0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04, - 0x81, 0x66, 0x00, 0x05, 0x04, 0x81), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01E4, 0x01E5, 0x01E5), - }, - { .channel = 84, - .freq = 5420, /* MHz */ - .unk2 = 3613, - RADIOREGS(0x71, 0x1E, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A, - 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03, - 0x80, 0x66, 0x00, 0x05, 0x03, 0x80), - PHYREGS(0x087C, 0x0878, 0x0874, 0x01E3, 0x01E4, 0x01E5), - }, - { .channel = 86, - .freq = 5430, /* MHz */ - .unk2 = 3620, - RADIOREGS(0x71, 0x1F, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A, - 0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03, - 0x80, 0x66, 0x00, 0x05, 0x03, 0x80), - PHYREGS(0x0880, 0x087C, 0x0878, 0x01E2, 0x01E3, 0x01E4), - }, - { .channel = 88, - .freq = 5440, /* MHz */ - .unk2 = 3627, - RADIOREGS(0x71, 0x20, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A, - 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02, - 0x80, 0x55, 0x00, 0x04, 0x02, 0x80), - PHYREGS(0x0884, 0x0880, 0x087C, 0x01E1, 0x01E2, 0x01E3), - }, - { .channel = 90, - .freq = 5450, /* MHz */ - .unk2 = 3633, - RADIOREGS(0x71, 0x21, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A, - 0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02, - 0x80, 0x55, 0x00, 0x04, 0x02, 0x80), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01E0, 0x01E1, 0x01E2), - }, - { .channel = 92, - .freq = 5460, /* MHz */ - .unk2 = 3640, - RADIOREGS(0x71, 0x22, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A, - 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01, - 0x80, 0x55, 0x00, 0x04, 0x01, 0x80), - PHYREGS(0x088C, 0x0888, 0x0884, 0x01DF, 0x01E0, 0x01E1), - }, - { .channel = 94, - .freq = 5470, /* MHz */ - .unk2 = 3647, - RADIOREGS(0x71, 0x23, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A, - 0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01, - 0x80, 0x55, 0x00, 0x04, 0x01, 0x80), - PHYREGS(0x0890, 0x088C, 0x0888, 0x01DE, 0x01DF, 0x01E0), - }, - { .channel = 96, - .freq = 5480, /* MHz */ - .unk2 = 3653, - RADIOREGS(0x71, 0x24, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A, - 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00, - 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), - PHYREGS(0x0894, 0x0890, 0x088C, 0x01DD, 0x01DE, 0x01DF), - }, - { .channel = 98, - .freq = 5490, /* MHz */ - .unk2 = 3660, - RADIOREGS(0x71, 0x25, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A, - 0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00, - 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01DD, 0x01DD, 0x01DE), - }, - { .channel = 100, - .freq = 5500, /* MHz */ - .unk2 = 3667, - RADIOREGS(0x71, 0x26, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A, - 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00, - 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), - PHYREGS(0x089C, 0x0898, 0x0894, 0x01DC, 0x01DD, 0x01DD), - }, - { .channel = 102, - .freq = 5510, /* MHz */ - .unk2 = 3673, - RADIOREGS(0x71, 0x27, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A, - 0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00, - 0x80, 0x44, 0x00, 0x03, 0x00, 0x80), - PHYREGS(0x08A0, 0x089C, 0x0898, 0x01DB, 0x01DC, 0x01DD), - }, - { .channel = 104, - .freq = 5520, /* MHz */ - .unk2 = 3680, - RADIOREGS(0x71, 0x28, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A, - 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), - PHYREGS(0x08A4, 0x08A0, 0x089C, 0x01DA, 0x01DB, 0x01DC), - }, - { .channel = 106, - .freq = 5530, /* MHz */ - .unk2 = 3687, - RADIOREGS(0x71, 0x29, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A, - 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), - PHYREGS(0x08A8, 0x08A4, 0x08A0, 0x01D9, 0x01DA, 0x01DB), - }, - { .channel = 108, - .freq = 5540, /* MHz */ - .unk2 = 3693, - RADIOREGS(0x71, 0x2A, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A, - 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), - PHYREGS(0x08AC, 0x08A8, 0x08A4, 0x01D8, 0x01D9, 0x01DA), - }, - { .channel = 110, - .freq = 5550, /* MHz */ - .unk2 = 3700, - RADIOREGS(0x71, 0x2B, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A, - 0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x80, 0x33, 0x00, 0x02, 0x00, 0x80), - PHYREGS(0x08B0, 0x08AC, 0x08A8, 0x01D7, 0x01D8, 0x01D9), - }, - { .channel = 112, - .freq = 5560, /* MHz */ - .unk2 = 3707, - RADIOREGS(0x71, 0x2C, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A, - 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, - 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08B4, 0x08B0, 0x08AC, 0x01D7, 0x01D7, 0x01D8), - }, - { .channel = 114, - .freq = 5570, /* MHz */ - .unk2 = 3713, - RADIOREGS(0x71, 0x2D, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A, - 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, - 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08B8, 0x08B4, 0x08B0, 0x01D6, 0x01D7, 0x01D7), - }, - { .channel = 116, - .freq = 5580, /* MHz */ - .unk2 = 3720, - RADIOREGS(0x71, 0x2E, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A, - 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, - 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08BC, 0x08B8, 0x08B4, 0x01D5, 0x01D6, 0x01D7), - }, - { .channel = 118, - .freq = 5590, /* MHz */ - .unk2 = 3727, - RADIOREGS(0x71, 0x2F, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A, - 0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00, - 0x80, 0x22, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08C0, 0x08BC, 0x08B8, 0x01D4, 0x01D5, 0x01D6), - }, - { .channel = 120, - .freq = 5600, /* MHz */ - .unk2 = 3733, - RADIOREGS(0x71, 0x30, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A, - 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00, - 0x80, 0x11, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08C4, 0x08C0, 0x08BC, 0x01D3, 0x01D4, 0x01D5), - }, - { .channel = 122, - .freq = 5610, /* MHz */ - .unk2 = 3740, - RADIOREGS(0x71, 0x31, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A, - 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00, - 0x80, 0x11, 0x00, 0x01, 0x00, 0x80), - PHYREGS(0x08C8, 0x08C4, 0x08C0, 0x01D2, 0x01D3, 0x01D4), - }, - { .channel = 124, - .freq = 5620, /* MHz */ - .unk2 = 3747, - RADIOREGS(0x71, 0x32, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A, - 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, - 0x80, 0x11, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08CC, 0x08C8, 0x08C4, 0x01D2, 0x01D2, 0x01D3), - }, - { .channel = 126, - .freq = 5630, /* MHz */ - .unk2 = 3753, - RADIOREGS(0x71, 0x33, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A, - 0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, - 0x80, 0x11, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08D0, 0x08CC, 0x08C8, 0x01D1, 0x01D2, 0x01D2), - }, - { .channel = 128, - .freq = 5640, /* MHz */ - .unk2 = 3760, - RADIOREGS(0x71, 0x34, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08D4, 0x08D0, 0x08CC, 0x01D0, 0x01D1, 0x01D2), - }, - { .channel = 130, - .freq = 5650, /* MHz */ - .unk2 = 3767, - RADIOREGS(0x71, 0x35, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08D8, 0x08D4, 0x08D0, 0x01CF, 0x01D0, 0x01D1), - }, - { .channel = 132, - .freq = 5660, /* MHz */ - .unk2 = 3773, - RADIOREGS(0x71, 0x36, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08DC, 0x08D8, 0x08D4, 0x01CE, 0x01CF, 0x01D0), - }, - { .channel = 134, - .freq = 5670, /* MHz */ - .unk2 = 3780, - RADIOREGS(0x71, 0x37, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08E0, 0x08DC, 0x08D8, 0x01CE, 0x01CE, 0x01CF), - }, - { .channel = 136, - .freq = 5680, /* MHz */ - .unk2 = 3787, - RADIOREGS(0x71, 0x38, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08E4, 0x08E0, 0x08DC, 0x01CD, 0x01CE, 0x01CE), - }, - { .channel = 138, - .freq = 5690, /* MHz */ - .unk2 = 3793, - RADIOREGS(0x71, 0x39, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08E8, 0x08E4, 0x08E0, 0x01CC, 0x01CD, 0x01CE), - }, - { .channel = 140, - .freq = 5700, /* MHz */ - .unk2 = 3800, - RADIOREGS(0x71, 0x3A, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08EC, 0x08E8, 0x08E4, 0x01CB, 0x01CC, 0x01CD), - }, - { .channel = 142, - .freq = 5710, /* MHz */ - .unk2 = 3807, - RADIOREGS(0x71, 0x3B, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08F0, 0x08EC, 0x08E8, 0x01CA, 0x01CB, 0x01CC), - }, - { .channel = 144, - .freq = 5720, /* MHz */ - .unk2 = 3813, - RADIOREGS(0x71, 0x3C, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08F4, 0x08F0, 0x08EC, 0x01C9, 0x01CA, 0x01CB), - }, - { .channel = 145, - .freq = 5725, /* MHz */ - .unk2 = 3817, - RADIOREGS(0x72, 0x79, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08F6, 0x08F2, 0x08EE, 0x01C9, 0x01CA, 0x01CB), - }, - { .channel = 146, - .freq = 5730, /* MHz */ - .unk2 = 3820, - RADIOREGS(0x71, 0x3D, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08F8, 0x08F4, 0x08F0, 0x01C9, 0x01C9, 0x01CA), - }, - { .channel = 147, - .freq = 5735, /* MHz */ - .unk2 = 3823, - RADIOREGS(0x72, 0x7B, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08FA, 0x08F6, 0x08F2, 0x01C8, 0x01C9, 0x01CA), - }, - { .channel = 148, - .freq = 5740, /* MHz */ - .unk2 = 3827, - RADIOREGS(0x71, 0x3E, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08FC, 0x08F8, 0x08F4, 0x01C8, 0x01C9, 0x01C9), - }, - { .channel = 149, - .freq = 5745, /* MHz */ - .unk2 = 3830, - RADIOREGS(0x72, 0x7D, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x08FE, 0x08FA, 0x08F6, 0x01C8, 0x01C8, 0x01C9), - }, - { .channel = 150, - .freq = 5750, /* MHz */ - .unk2 = 3833, - RADIOREGS(0x71, 0x3F, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0900, 0x08FC, 0x08F8, 0x01C7, 0x01C8, 0x01C9), - }, - { .channel = 151, - .freq = 5755, /* MHz */ - .unk2 = 3837, - RADIOREGS(0x72, 0x7F, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0902, 0x08FE, 0x08FA, 0x01C7, 0x01C8, 0x01C8), - }, - { .channel = 152, - .freq = 5760, /* MHz */ - .unk2 = 3840, - RADIOREGS(0x71, 0x40, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0904, 0x0900, 0x08FC, 0x01C6, 0x01C7, 0x01C8), - }, - { .channel = 153, - .freq = 5765, /* MHz */ - .unk2 = 3843, - RADIOREGS(0x72, 0x81, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0906, 0x0902, 0x08FE, 0x01C6, 0x01C7, 0x01C8), - }, - { .channel = 154, - .freq = 5770, /* MHz */ - .unk2 = 3847, - RADIOREGS(0x71, 0x41, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01C6, 0x01C6, 0x01C7), - }, - { .channel = 155, - .freq = 5775, /* MHz */ - .unk2 = 3850, - RADIOREGS(0x72, 0x83, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x090A, 0x0906, 0x0902, 0x01C5, 0x01C6, 0x01C7), - }, - { .channel = 156, - .freq = 5780, /* MHz */ - .unk2 = 3853, - RADIOREGS(0x71, 0x42, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x090C, 0x0908, 0x0904, 0x01C5, 0x01C6, 0x01C6), - }, - { .channel = 157, - .freq = 5785, /* MHz */ - .unk2 = 3857, - RADIOREGS(0x72, 0x85, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x090E, 0x090A, 0x0906, 0x01C4, 0x01C5, 0x01C6), - }, - { .channel = 158, - .freq = 5790, /* MHz */ - .unk2 = 3860, - RADIOREGS(0x71, 0x43, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0910, 0x090C, 0x0908, 0x01C4, 0x01C5, 0x01C6), - }, - { .channel = 159, - .freq = 5795, /* MHz */ - .unk2 = 3863, - RADIOREGS(0x72, 0x87, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0912, 0x090E, 0x090A, 0x01C4, 0x01C4, 0x01C5), - }, - { .channel = 160, - .freq = 5800, /* MHz */ - .unk2 = 3867, - RADIOREGS(0x71, 0x44, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0914, 0x0910, 0x090C, 0x01C3, 0x01C4, 0x01C5), - }, - { .channel = 161, - .freq = 5805, /* MHz */ - .unk2 = 3870, - RADIOREGS(0x72, 0x89, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0916, 0x0912, 0x090E, 0x01C3, 0x01C4, 0x01C4), - }, - { .channel = 162, - .freq = 5810, /* MHz */ - .unk2 = 3873, - RADIOREGS(0x71, 0x45, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01C2, 0x01C3, 0x01C4), - }, - { .channel = 163, - .freq = 5815, /* MHz */ - .unk2 = 3877, - RADIOREGS(0x72, 0x8B, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x091A, 0x0916, 0x0912, 0x01C2, 0x01C3, 0x01C4), - }, - { .channel = 164, - .freq = 5820, /* MHz */ - .unk2 = 3880, - RADIOREGS(0x71, 0x46, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x091C, 0x0918, 0x0914, 0x01C2, 0x01C2, 0x01C3), - }, - { .channel = 165, - .freq = 5825, /* MHz */ - .unk2 = 3883, - RADIOREGS(0x72, 0x8D, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x091E, 0x091A, 0x0916, 0x01C1, 0x01C2, 0x01C3), - }, - { .channel = 166, - .freq = 5830, /* MHz */ - .unk2 = 3887, - RADIOREGS(0x71, 0x47, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0920, 0x091C, 0x0918, 0x01C1, 0x01C2, 0x01C2), - }, - { .channel = 168, - .freq = 5840, /* MHz */ - .unk2 = 3893, - RADIOREGS(0x71, 0x48, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0924, 0x0920, 0x091C, 0x01C0, 0x01C1, 0x01C2), - }, - { .channel = 170, - .freq = 5850, /* MHz */ - .unk2 = 3900, - RADIOREGS(0x71, 0x49, 0x02, 0x01, 0xE0, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01BF, 0x01C0, 0x01C1), - }, - { .channel = 172, - .freq = 5860, /* MHz */ - .unk2 = 3907, - RADIOREGS(0x71, 0x4A, 0x02, 0x01, 0xDE, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x092C, 0x0928, 0x0924, 0x01BF, 0x01BF, 0x01C0), - }, - { .channel = 174, - .freq = 5870, /* MHz */ - .unk2 = 3913, - RADIOREGS(0x71, 0x4B, 0x02, 0x00, 0xDB, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0930, 0x092C, 0x0928, 0x01BE, 0x01BF, 0x01BF), - }, - { .channel = 176, - .freq = 5880, /* MHz */ - .unk2 = 3920, - RADIOREGS(0x71, 0x4C, 0x02, 0x00, 0xD8, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0934, 0x0930, 0x092C, 0x01BD, 0x01BE, 0x01BF), - }, - { .channel = 178, - .freq = 5890, /* MHz */ - .unk2 = 3927, - RADIOREGS(0x71, 0x4D, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01BC, 0x01BD, 0x01BE), - }, - { .channel = 180, - .freq = 5900, /* MHz */ - .unk2 = 3933, - RADIOREGS(0x71, 0x4E, 0x02, 0x00, 0xD3, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x093C, 0x0938, 0x0934, 0x01BC, 0x01BC, 0x01BD), - }, - { .channel = 182, - .freq = 5910, /* MHz */ - .unk2 = 3940, - RADIOREGS(0x71, 0x4F, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x00, 0x00, 0x80), - PHYREGS(0x0940, 0x093C, 0x0938, 0x01BB, 0x01BC, 0x01BC), - }, - { .channel = 1, - .freq = 2412, /* MHz */ - .unk2 = 3216, - RADIOREGS(0x73, 0x6C, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C, - 0x80, 0xFF, 0x88, 0x0D, 0x0C, 0x80), - PHYREGS(0x03C9, 0x03C5, 0x03C1, 0x043A, 0x043F, 0x0443), - }, - { .channel = 2, - .freq = 2417, /* MHz */ - .unk2 = 3223, - RADIOREGS(0x73, 0x71, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B, - 0x80, 0xFF, 0x88, 0x0C, 0x0B, 0x80), - PHYREGS(0x03CB, 0x03C7, 0x03C3, 0x0438, 0x043D, 0x0441), - }, - { .channel = 3, - .freq = 2422, /* MHz */ - .unk2 = 3229, - RADIOREGS(0x73, 0x76, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, - 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80), - PHYREGS(0x03CD, 0x03C9, 0x03C5, 0x0436, 0x043A, 0x043F), - }, - { .channel = 4, - .freq = 2427, /* MHz */ - .unk2 = 3236, - RADIOREGS(0x73, 0x7B, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A, - 0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80), - PHYREGS(0x03CF, 0x03CB, 0x03C7, 0x0434, 0x0438, 0x043D), - }, - { .channel = 5, - .freq = 2432, /* MHz */ - .unk2 = 3243, - RADIOREGS(0x73, 0x80, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09, - 0x80, 0xFF, 0x88, 0x0C, 0x09, 0x80), - PHYREGS(0x03D1, 0x03CD, 0x03C9, 0x0431, 0x0436, 0x043A), - }, - { .channel = 6, - .freq = 2437, /* MHz */ - .unk2 = 3249, - RADIOREGS(0x73, 0x85, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08, - 0x80, 0xFF, 0x88, 0x0B, 0x08, 0x80), - PHYREGS(0x03D3, 0x03CF, 0x03CB, 0x042F, 0x0434, 0x0438), - }, - { .channel = 7, - .freq = 2442, /* MHz */ - .unk2 = 3256, - RADIOREGS(0x73, 0x8A, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07, - 0x80, 0xFF, 0x88, 0x0A, 0x07, 0x80), - PHYREGS(0x03D5, 0x03D1, 0x03CD, 0x042D, 0x0431, 0x0436), - }, - { .channel = 8, - .freq = 2447, /* MHz */ - .unk2 = 3263, - RADIOREGS(0x73, 0x8F, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06, - 0x80, 0xFF, 0x88, 0x0A, 0x06, 0x80), - PHYREGS(0x03D7, 0x03D3, 0x03CF, 0x042B, 0x042F, 0x0434), - }, - { .channel = 9, - .freq = 2452, /* MHz */ - .unk2 = 3269, - RADIOREGS(0x73, 0x94, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06, - 0x80, 0xFF, 0x88, 0x09, 0x06, 0x80), - PHYREGS(0x03D9, 0x03D5, 0x03D1, 0x0429, 0x042D, 0x0431), - }, - { .channel = 10, - .freq = 2457, /* MHz */ - .unk2 = 3276, - RADIOREGS(0x73, 0x99, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05, - 0x80, 0xFF, 0x88, 0x08, 0x05, 0x80), - PHYREGS(0x03DB, 0x03D7, 0x03D3, 0x0427, 0x042B, 0x042F), - }, - { .channel = 11, - .freq = 2462, /* MHz */ - .unk2 = 3283, - RADIOREGS(0x73, 0x9E, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04, - 0x80, 0xFF, 0x88, 0x08, 0x04, 0x80), - PHYREGS(0x03DD, 0x03D9, 0x03D5, 0x0424, 0x0429, 0x042D), - }, - { .channel = 12, - .freq = 2467, /* MHz */ - .unk2 = 3289, - RADIOREGS(0x73, 0xA3, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03, - 0x80, 0xFF, 0x88, 0x08, 0x03, 0x80), - PHYREGS(0x03DF, 0x03DB, 0x03D7, 0x0422, 0x0427, 0x042B), - }, - { .channel = 13, - .freq = 2472, /* MHz */ - .unk2 = 3296, - RADIOREGS(0x73, 0xA8, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03, - 0x80, 0xFF, 0x88, 0x07, 0x03, 0x80), - PHYREGS(0x03E1, 0x03DD, 0x03D9, 0x0420, 0x0424, 0x0429), - }, - { .channel = 14, - .freq = 2484, /* MHz */ - .unk2 = 3312, - RADIOREGS(0x73, 0xB4, 0x09, 0x0F, 0xFF, 0x01, 0x07, 0x15, - 0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01, - 0x80, 0xFF, 0x88, 0x07, 0x01, 0x80), - PHYREGS(0x03E6, 0x03E2, 0x03DE, 0x041B, 0x041F, 0x0424), - }, -}; - -void b2055_upload_inittab(struct b43_wldev *dev, - bool ghz5, bool ignore_uploadflag) -{ - const struct b2055_inittab_entry *e; - unsigned int i, writes = 0; - u16 value; - - for (i = 0; i < ARRAY_SIZE(b2055_inittab); i++) { - e = &(b2055_inittab[i]); - if (!(e->flags & B2055_INITTAB_ENTRY_OK)) - continue; - if ((e->flags & B2055_INITTAB_UPLOAD) || ignore_uploadflag) { - if (ghz5) - value = e->ghz5; - else - value = e->ghz2; - b43_radio_write16(dev, i, value); - if (++writes % 4 == 0) - b43_read32(dev, B43_MMIO_MACCTL); /* flush */ - } - } -} - -const struct b43_nphy_channeltab_entry_rev2 * -b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel) -{ - const struct b43_nphy_channeltab_entry_rev2 *e; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(b43_nphy_channeltab_rev2); i++) { - e = &(b43_nphy_channeltab_rev2[i]); - if (e->channel == channel) - return e; - } - - return NULL; -} diff --git a/drivers/net/wireless/b43/radio_2055.h b/drivers/net/wireless/b43/radio_2055.h deleted file mode 100644 index 67f96122f..000000000 --- a/drivers/net/wireless/b43/radio_2055.h +++ /dev/null @@ -1,259 +0,0 @@ -#ifndef B43_RADIO_2055_H_ -#define B43_RADIO_2055_H_ - -#include <linux/types.h> - -#include "tables_nphy.h" - -#define B2055_GEN_SPARE 0x00 /* GEN spare */ -#define B2055_SP_PINPD 0x02 /* SP PIN PD */ -#define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */ -#define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */ -#define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */ -#define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */ -#define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */ -#define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */ -#define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */ -#define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */ -#define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */ -#define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */ -#define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */ -#define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */ -#define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */ -#define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */ -#define B2055_MASTER1 0x11 /* Master control 1 */ -#define B2055_MASTER2 0x12 /* Master control 2 */ -#define B2055_PD_LGEN 0x13 /* PD LGEN */ -#define B2055_PD_PLLTS 0x14 /* PD PLL TS */ -#define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */ -#define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */ -#define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */ -#define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */ -#define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */ -#define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */ -#define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */ -#define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */ -#define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */ -#define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */ -#define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */ -#define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */ -#define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */ -#define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */ -#define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */ -#define B2055_CAL_MISC 0x24 /* CAL MISC */ -#define B2055_CAL_COUT 0x25 /* CAL Counter out */ -#define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */ -#define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */ -#define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */ -#define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */ -#define B2055_CAL_TS 0x2A /* CAL TS */ -#define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */ -#define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */ -#define B2055_PADDRV 0x2D /* PAD driver */ -#define B2055_XOCTL1 0x2E /* XO Control 1 */ -#define B2055_XOCTL2 0x2F /* XO Control 2 */ -#define B2055_XOREGUL 0x30 /* XO Regulator */ -#define B2055_XOMISC 0x31 /* XO misc */ -#define B2055_PLL_LFC1 0x32 /* PLL LF C1 */ -#define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */ -#define B2055_PLL_LFC2 0x34 /* PLL LF C2 */ -#define B2055_PLL_REF 0x35 /* PLL reference */ -#define B2055_PLL_LFR1 0x36 /* PLL LF R1 */ -#define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */ -#define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */ -#define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */ -#define B2055_PLL_RCAL 0x3A /* PLL RCAL */ -#define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */ -#define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */ -#define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */ -#define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */ -#define B2055_RF_MMDSP 0x3F /* RF MMD spare */ -#define B2055_VCO_CAL1 0x40 /* VCO cal 1 */ -#define B2055_VCO_CAL2 0x41 /* VCO cal 2 */ -#define B2055_VCO_CAL3 0x42 /* VCO cal 3 */ -#define B2055_VCO_CAL4 0x43 /* VCO cal 4 */ -#define B2055_VCO_CAL5 0x44 /* VCO cal 5 */ -#define B2055_VCO_CAL6 0x45 /* VCO cal 6 */ -#define B2055_VCO_CAL7 0x46 /* VCO cal 7 */ -#define B2055_VCO_CAL8 0x47 /* VCO cal 8 */ -#define B2055_VCO_CAL9 0x48 /* VCO cal 9 */ -#define B2055_VCO_CAL10 0x49 /* VCO cal 10 */ -#define B2055_VCO_CAL11 0x4A /* VCO cal 11 */ -#define B2055_VCO_CAL12 0x4B /* VCO cal 12 */ -#define B2055_VCO_CAL13 0x4C /* VCO cal 13 */ -#define B2055_VCO_CAL14 0x4D /* VCO cal 14 */ -#define B2055_VCO_CAL15 0x4E /* VCO cal 15 */ -#define B2055_VCO_CAL16 0x4F /* VCO cal 16 */ -#define B2055_VCO_KVCO 0x50 /* VCO KVCO */ -#define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */ -#define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */ -#define B2055_VCO_REG 0x53 /* VCO Regulator */ -#define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */ -#define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */ -#define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */ -#define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */ -#define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */ -#define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */ -#define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */ -#define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */ -#define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */ -#define B2055_LGEN_DIV 0x5D /* LGEN div */ -#define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */ -#define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */ -#define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */ -#define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */ -#define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */ -#define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */ -#define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */ -#define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */ -#define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */ -#define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */ -#define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */ -#define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */ -#define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */ -#define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */ -#define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */ -#define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */ -#define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */ -#define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */ -#define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */ -#define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */ -#define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */ -#define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */ -#define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */ -#define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */ -#define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */ -#define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */ -#define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */ -#define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */ -#define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */ -#define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */ -#define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */ -#define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */ -#define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */ -#define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */ -#define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */ -#define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */ -#define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */ -#define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */ -#define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */ -#define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */ -#define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */ -#define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */ -#define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */ -#define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */ -#define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */ -#define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */ -#define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */ -#define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */ -#define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */ -#define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */ -#define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */ -#define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */ -#define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */ -#define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */ -#define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */ -#define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */ -#define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */ -#define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */ -#define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */ -#define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */ -#define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */ -#define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */ -#define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */ -#define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */ -#define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */ -#define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */ -#define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */ -#define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */ -#define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */ -#define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */ -#define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */ -#define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */ -#define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */ -#define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */ -#define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */ -#define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */ -#define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */ -#define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */ -#define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */ -#define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */ -#define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */ -#define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */ -#define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */ -#define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */ -#define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */ -#define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */ -#define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */ -#define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */ -#define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */ -#define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */ -#define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */ -#define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */ -#define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */ -#define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */ -#define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */ -#define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */ -#define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */ -#define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */ -#define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */ -#define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */ -#define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */ -#define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */ -#define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */ -#define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */ -#define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */ -#define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */ -#define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */ -#define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */ -#define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */ -#define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */ -#define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */ - -struct b43_nphy_channeltab_entry_rev2 { - /* The channel number */ - u8 channel; - /* The channel frequency in MHz */ - u16 freq; - /* An unknown value */ - u16 unk2; - /* Radio register values on channelswitch */ - u8 radio_pll_ref; - u8 radio_rf_pllmod0; - u8 radio_rf_pllmod1; - u8 radio_vco_captail; - u8 radio_vco_cal1; - u8 radio_vco_cal2; - u8 radio_pll_lfc1; - u8 radio_pll_lfr1; - u8 radio_pll_lfc2; - u8 radio_lgbuf_cenbuf; - u8 radio_lgen_tune1; - u8 radio_lgen_tune2; - u8 radio_c1_lgbuf_atune; - u8 radio_c1_lgbuf_gtune; - u8 radio_c1_rx_rfr1; - u8 radio_c1_tx_pgapadtn; - u8 radio_c1_tx_mxbgtrim; - u8 radio_c2_lgbuf_atune; - u8 radio_c2_lgbuf_gtune; - u8 radio_c2_rx_rfr1; - u8 radio_c2_tx_pgapadtn; - u8 radio_c2_tx_mxbgtrim; - /* PHY register values on channelswitch */ - struct b43_phy_n_sfo_cfg phy_regs; -}; - -/* Upload the default register value table. - * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz - * table is uploaded. If "ignore_uploadflag" is true, we upload any value - * and ignore the "UPLOAD" flag. */ -void b2055_upload_inittab(struct b43_wldev *dev, - bool ghz5, bool ignore_uploadflag); - -/* Get the NPHY Channel Switch Table entry for a channel. - * Returns NULL on failure to find an entry. */ -const struct b43_nphy_channeltab_entry_rev2 * -b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel); - -#endif /* B43_RADIO_2055_H_ */ diff --git a/drivers/net/wireless/b43/radio_2056.c b/drivers/net/wireless/b43/radio_2056.c deleted file mode 100644 index 2ce25607c..000000000 --- a/drivers/net/wireless/b43/radio_2056.c +++ /dev/null @@ -1,10318 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n 2056 radio device data tables - - Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "radio_2056.h" -#include "phy_common.h" - -struct b2056_inittab_entry { - /* Value to write if we use the 5GHz band. */ - u16 ghz5; - /* Value to write if we use the 2.4GHz band. */ - u16 ghz2; - /* Flags */ - u8 flags; -}; -#define B2056_INITTAB_ENTRY_OK 0x01 -#define B2056_INITTAB_UPLOAD 0x02 -#define UPLOAD .flags = B2056_INITTAB_ENTRY_OK | B2056_INITTAB_UPLOAD -#define NOUPLOAD .flags = B2056_INITTAB_ENTRY_OK - -struct b2056_inittabs_pts { - const struct b2056_inittab_entry *syn; - unsigned int syn_length; - const struct b2056_inittab_entry *tx; - unsigned int tx_length; - const struct b2056_inittab_entry *rx; - unsigned int rx_length; -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev3_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev3_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev3_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev4_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev4_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_phy_rev4_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x002f, .ghz2 = 0x002f, UPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev5_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev5_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, - [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, - [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, - [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, }, - [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, - [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev5_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev6_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x003f, .ghz2 = 0x003f, UPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x002b, .ghz2 = 0x002b, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev6_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev6_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, - [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, }, - [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, }, - [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, }, - [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, }, - [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev7_9_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev8_syn[] = { - [B2056_SYN_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_PU] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_GPIO_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_MASTER] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_TOPBIAS_RCAL] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_AFEREG] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSE] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSEIDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_TEMPPROCSENSERCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LPO] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_VDDCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_VDDCAL_STATUS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCAL_CODE_OUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL1] = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL2] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL3] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_RCCAL_CTRL11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_ZCAL_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_MAST1] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_MAST2] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_MAST3] = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, }, - [B2056_SYN_PLL_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL1] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL3] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL5] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_SYN_PLL_XTAL6] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_REFDIV] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_CP1] = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_SYN_PLL_CP3] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER3] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER5] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_PLL_MMD1] = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, }, - [B2056_SYN_PLL_MMD2] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO1] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_MONITOR1] = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, }, - [B2056_SYN_PLL_MONITOR2] = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL4] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL5] = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL6] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL7] = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL8] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL9] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL11] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL13] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_SYN_PLL_VREG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_PLL_STATUS3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU2] = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PU8] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_BIAS_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RCCR1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF1] = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER2] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF1] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, - [B2056_SYN_LOGEN_BUF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF4] = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV1] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV2] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_DIV3] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLOUT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACLCAL3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_CALEN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_PEAKDET1] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF5_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_BUF6_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, }, - [B2056_SYN_LOGEN_ACL_WAITCNT] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_RX_CMOS_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev8_tx[] = { - [B2056_TX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_GAIN_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_FINE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_I] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_LOFT_COARSE_Q] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER1] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_TX_COM_MASTER2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_RXIQCAL_TXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_SSI_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_IQCAL_VCM_HG] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_IQCAL_IDAC] = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, }, - [B2056_TX_TSSI_VCM] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_TX_AMP_DET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TX_SSI_MUX] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSIA] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSIG] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_TSSI_MISC1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TSSI_MISC3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PA_SPARE1] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, - [B2056_TX_INTPAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAA_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAA_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_BOOST_TUNE] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_STAT] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_TX_INTPAG_IAUX_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_STAT] = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, }, - [B2056_TX_INTPAG_IMAIN_DYN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_INTPAG_CASCBIAS] = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADA_BOOST_TUNE] = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PADG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PADG_CASCBIAS] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_TX_PADG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PADG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAA_BOOST_TUNE] = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAA_MISC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_MASTER] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_PGAG_IDAC] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_TX_PGAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_PGAG_BOOST_TUNE] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_MISC] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_TX_MIXA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXA_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_MIXG] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_MIXG_BOOST_TUNE] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_TX_BB_GM_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_GM] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_TX_TXLPF_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_RCCAL_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_BW] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_TX_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_0] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_1] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_2] = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_3] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_4] = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_5] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_IDAC_6] = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, }, - [B2056_TX_TXLPF_OPAMP_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_TX_TXLPF_MISC] = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, - [B2056_TX_TXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_TXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_INTPA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PAD_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_PGA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_STATUS_TXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC0] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC1] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC2] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC3] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC4] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC5] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC6] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, - [B2056_TX_GMBB_IDAC7] = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev8_rx[] = { - [B2056_RX_RESERVED_ADDR2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_CTRL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_OVR] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RESET] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RCAL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_TXLPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_COM_RC_RXHPF] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR17] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR18] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR19] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR20] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR21] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR22] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR23] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR24] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR25] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR26] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR27] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR28] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR29] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR30] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RESERVED_ADDR31] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXIQCAL_RXMUX] = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, }, - [B2056_RX_RSSI_PU] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_SEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RSSI_GAIN] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_RSSI_NB_IDAC] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2I_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_1] = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, }, - [B2056_RX_RSSI_WB2Q_IDAC_2] = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, }, - [B2056_RX_RSSI_POLE] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_RSSI_WB1_IDAC] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_RSSI_MISC] = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, }, - [B2056_RX_LNAA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAA_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAA_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_A_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_LNA1A_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_LNAG_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_LNAG_TUNE] = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, }, - [B2056_RX_LNAG_GAIN] = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, }, - [B2056_RX_LNA_G_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_LNA1G_MISC] = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, }, - [B2056_RX_MIXA_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, - [B2056_RX_MIXA_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXA_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_RX_MIXA_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXA_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXA_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXG_CTRLPTAT] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_LOB_BIAS] = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, }, - [B2056_RX_MIXG_CORE_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_MIXG_CMFB_IDAC] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MAIN] = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, }, - [B2056_RX_MIXG_BIAS_MISC] = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, }, - [B2056_RX_MIXG_MAST_BIAS] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_MASTER] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_GAIN] = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, }, - [B2056_RX_TIA_SPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TIA_SPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_BB_LPF_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_AACI_MASTER] = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, }, - [B2056_RX_RXLPF_IDAC] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_RXLPF_BIAS_DCCANCEL] = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2056_RX_RXLPF_INVCM_BODY] = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, }, - [B2056_RX_RXLPF_CC_OP] = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, }, - [B2056_RX_RXLPF_GAIN] = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, }, - [B2056_RX_RXLPF_Q_BW] = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, }, - [B2056_RX_RXLPF_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_HPC] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXHPF_OFF7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_RCCAL_LPC] = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_0] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_3] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXLPF_OFF_4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_UNUSED] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_VGA_MASTER] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_VGA_GAIN] = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, }, - [B2056_RX_VGA_HP_CORNER_BW] = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, }, - [B2056_RX_VGABUF_BIAS] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, }, - [B2056_RX_VGABUF_GAIN_BW] = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, }, - [B2056_RX_TXFBMIX_A] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_TXFBMIX_G] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE1] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE2] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, - [B2056_RX_RXSPARE4] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE5] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE6] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE7] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE8] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE9] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE10] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE11] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE12] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE13] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE14] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE15] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_RXSPARE16] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_LNAG_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_MIXTIA_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_VGA_BUF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_Q] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_BUF_BW] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_RXLPF_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, - [B2056_RX_STATUS_HPC_RC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev11_syn[] = { - [B2056_SYN_PLL_PFD] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_CP2] = { .ghz5 = 0x003f, .ghz2 = 0x003f, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER1] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER2] = { .ghz5 = 0x0006, .ghz2 = 0x0006, UPLOAD, }, - [B2056_SYN_PLL_LOOPFILTER4] = { .ghz5 = 0x002b, .ghz2 = 0x002b, UPLOAD, }, - [B2056_SYN_PLL_VCO2] = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, }, - [B2056_SYN_PLL_VCOCAL12] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_SYN_LOGENBUF2] = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev11_tx[] = { - [B2056_TX_PA_SPARE2] = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, }, - [B2056_TX_INTPAA_IAUX_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_IMAIN_STAT] = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, }, - [B2056_TX_INTPAA_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_INTPAG_PASLOPE] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_TX_PADA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PADA_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PADG_SLOPE] = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, }, - [B2056_TX_PGAA_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_TX_PGAA_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_PGAG_SLOPE] = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, }, - [B2056_TX_GMBB_IDAC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_TX_TXSPARE1] = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, }, -}; - -static const struct b2056_inittab_entry b2056_inittab_radio_rev11_rx[] = { - [B2056_RX_BIASPOLE_LNAA1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAA2_IDAC] = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, }, - [B2056_RX_BIASPOLE_LNAG1_IDAC] = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, }, - [B2056_RX_LNAG2_IDAC] = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, }, - [B2056_RX_MIXA_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_MIXA_LOB_BIAS] = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, }, - [B2056_RX_MIXA_BIAS_AUX] = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, }, - [B2056_RX_MIXG_VCM] = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, }, - [B2056_RX_TIA_IOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_QOPAMP] = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, }, - [B2056_RX_TIA_IMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_TIA_QMISC] = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, }, - [B2056_RX_RXLPF_OUTVCM] = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, }, - [B2056_RX_VGA_BIAS_DCCANCEL] = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, }, - [B2056_RX_RXSPARE3] = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, }, -}; - -#define INITTABSPTS(prefix) \ - static const struct b2056_inittabs_pts prefix = { \ - .syn = prefix##_syn, \ - .syn_length = ARRAY_SIZE(prefix##_syn), \ - .tx = prefix##_tx, \ - .tx_length = ARRAY_SIZE(prefix##_tx), \ - .rx = prefix##_rx, \ - .rx_length = ARRAY_SIZE(prefix##_rx), \ - } - -INITTABSPTS(b2056_inittab_phy_rev3); -INITTABSPTS(b2056_inittab_phy_rev4); -INITTABSPTS(b2056_inittab_radio_rev5); -INITTABSPTS(b2056_inittab_radio_rev6); -INITTABSPTS(b2056_inittab_radio_rev7_9); -INITTABSPTS(b2056_inittab_radio_rev8); -INITTABSPTS(b2056_inittab_radio_rev11); - -#define RADIOREGS3(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ - r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ - r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \ - r30, r31, r32, r33, r34, r35, r36) \ - .radio_syn_pll_vcocal1 = r00, \ - .radio_syn_pll_vcocal2 = r01, \ - .radio_syn_pll_refdiv = r02, \ - .radio_syn_pll_mmd2 = r03, \ - .radio_syn_pll_mmd1 = r04, \ - .radio_syn_pll_loopfilter1 = r05, \ - .radio_syn_pll_loopfilter2 = r06, \ - .radio_syn_pll_loopfilter3 = r07, \ - .radio_syn_pll_loopfilter4 = r08, \ - .radio_syn_pll_loopfilter5 = r09, \ - .radio_syn_reserved_addr27 = r10, \ - .radio_syn_reserved_addr28 = r11, \ - .radio_syn_reserved_addr29 = r12, \ - .radio_syn_logen_vcobuf1 = r13, \ - .radio_syn_logen_mixer2 = r14, \ - .radio_syn_logen_buf3 = r15, \ - .radio_syn_logen_buf4 = r16, \ - .radio_rx0_lnaa_tune = r17, \ - .radio_rx0_lnag_tune = r18, \ - .radio_tx0_intpaa_boost_tune = r19, \ - .radio_tx0_intpag_boost_tune = r20, \ - .radio_tx0_pada_boost_tune = r21, \ - .radio_tx0_padg_boost_tune = r22, \ - .radio_tx0_pgaa_boost_tune = r23, \ - .radio_tx0_pgag_boost_tune = r24, \ - .radio_tx0_mixa_boost_tune = r25, \ - .radio_tx0_mixg_boost_tune = r26, \ - .radio_rx1_lnaa_tune = r27, \ - .radio_rx1_lnag_tune = r28, \ - .radio_tx1_intpaa_boost_tune = r29, \ - .radio_tx1_intpag_boost_tune = r30, \ - .radio_tx1_pada_boost_tune = r31, \ - .radio_tx1_padg_boost_tune = r32, \ - .radio_tx1_pgaa_boost_tune = r33, \ - .radio_tx1_pgag_boost_tune = r34, \ - .radio_tx1_mixa_boost_tune = r35, \ - .radio_tx1_mixg_boost_tune = r36 - -#define PHYREGS(r0, r1, r2, r3, r4, r5) \ - .phy_regs.phy_bw1a = r0, \ - .phy_regs.phy_bw2 = r1, \ - .phy_regs.phy_bw3 = r2, \ - .phy_regs.phy_bw4 = r3, \ - .phy_regs.phy_bw5 = r4, \ - .phy_regs.phy_bw6 = r5 - -/* http://bcm-v4.sipsolutions.net/802.11/Radio/2056/ChannelTable */ -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_phy_rev3[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xff, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xfc, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xef, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xfc, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfc, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x8f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x05, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xfa, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x7e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x7e, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x7d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xfa, 0x00, 0x7d, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xfa, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xf8, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xf8, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x5d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xf8, 0x00, 0x5d, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xf8, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x5c, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08, - 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x08, 0x00, 0xf8, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x5c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x2b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x2b, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x2a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x2a, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf8, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf8, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf6, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf6, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf6, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf6, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf6, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf6, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf6, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf4, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf2, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf2, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf2, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06, - 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x06, 0x00, 0xf2, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05, - 0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x05, 0x00, 0xf2, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05, - 0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x05, 0x00, 0xf2, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0f), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0d), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0d), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0d), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0d), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0d), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_phy_rev4[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xff, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfe, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xef, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xef, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfc, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x8f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xfa, 0x00, 0x8f, 0x00, 0x08, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xfa, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x7e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x7e, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x7d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x7d, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x5d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x5d, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x5c, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f, - 0x00, 0xf8, 0x00, 0x5c, 0x00, 0x07, 0x00, 0x7f, - 0x00, 0x0f, 0x00, 0xf8, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x5c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x5c, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x2b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x2b, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x2a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x2a, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d, - 0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f, - 0x00, 0x0d, 0x00, 0xf6, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x1a, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x1a, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x07, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b, - 0x00, 0xf4, 0x00, 0x07, 0x00, 0x04, 0x00, 0x7f, - 0x00, 0x0b, 0x00, 0xf4, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a, - 0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f, - 0x00, 0x0a, 0x00, 0xf2, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09, - 0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f, - 0x00, 0x09, 0x00, 0xf0, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf0, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07, - 0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, - 0x00, 0x07, 0x00, 0xf0, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0e), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_radio_rev5[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a, - 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a, - 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6e, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00, - 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6b, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6b, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x6b, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x6b, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x5b, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x5a, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00, - 0xff, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x5a, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x5a, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x5a, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x5a, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xc8, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x59, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x59, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x59, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00, - 0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x78, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00, - 0x84, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x75, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x75, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x75, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00, - 0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x74, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x84, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x83, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00, - 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00, - 0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x82, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x72, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x72, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x72, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x72, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x71, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x71, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x71, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x71, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x71, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0b, 0x00, 0x1f, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0b), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0a, 0x00, 0x1f, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0a), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x0e, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0a, 0x00, 0x0e, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0a), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x0d, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x0b, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x08, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x09, 0x00, 0x08, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x09), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x09, 0x00, 0x07, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x09), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x06, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x09, 0x00, 0x06, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x09), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x05, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x09, 0x00, 0x05, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x09), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_radio_rev6[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6d, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x67, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x57, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x56, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x46, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x45, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x23, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x12, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x02, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_radio_rev7_9[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c, - 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b, - 0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a, - 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a, - 0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xfe, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09, - 0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x09, 0x00, 0x6e, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6e, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xed, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, - 0xed, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08, - 0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70, - 0x00, 0x08, 0x00, 0x6d, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, - 0xed, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdb, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6c, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xcb, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6b, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xca, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07, - 0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x07, 0x00, 0x6b, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xca, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x6b, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x6b, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x7b, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x7a, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x7a, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x06, 0x00, 0x7a, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x7a, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xa7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x7a, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, - 0xa6, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x79, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x79, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x05, 0x00, 0x79, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x79, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x94, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x79, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x83, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x72, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04, - 0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x04, 0x00, 0x78, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x72, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x78, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x71, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03, - 0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x03, 0x00, 0x77, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x76, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x60, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x86, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02, - 0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x02, 0x00, 0x85, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x85, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x85, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x84, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x84, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01, - 0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x01, 0x00, 0x94, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x10, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x93, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x92, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x91, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x91, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x91, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x91, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, - 0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, - 0x00, 0x00, 0x00, 0x91, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0b, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0b), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0a), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0f, 0x00, 0x0a), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x0a), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x09), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0e, 0x00, 0x09), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x09), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x09), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0d, 0x00, 0x08), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_radio_rev8[] = { - { .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6d, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04, - 0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04, - 0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_radio_rev11[] = { - { - .freq = 4920, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216), - }, - { - .freq = 4930, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215), - }, - { - .freq = 4940, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214), - }, - { - .freq = 4950, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213), - }, - { - .freq = 4960, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212), - }, - { - .freq = 4970, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211), - }, - { - .freq = 4980, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f), - }, - { - .freq = 4990, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e), - }, - { - .freq = 5000, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d), - }, - { - .freq = 5010, - RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c), - }, - { - .freq = 5020, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b), - }, - { - .freq = 5030, - RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a), - }, - { - .freq = 5040, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209), - }, - { - .freq = 5050, - RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208), - }, - { - .freq = 5060, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207), - }, - { - .freq = 5070, - RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206), - }, - { - .freq = 5080, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205), - }, - { - .freq = 5090, - RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204), - }, - { - .freq = 5100, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203), - }, - { - .freq = 5110, - RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202), - }, - { - .freq = 5120, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201), - }, - { - .freq = 5130, - RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200), - }, - { - .freq = 5140, - RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f, - 0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77, - 0x00, 0x0f, 0x00, 0x6f, 0x00), - PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff), - }, - { - .freq = 5160, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd), - }, - { - .freq = 5170, - RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc), - }, - { - .freq = 5180, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0e, 0x00, 0x6f, 0x00), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { - .freq = 5190, - RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa), - }, - { - .freq = 5200, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { - .freq = 5210, - RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00, - 0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8), - }, - { - .freq = 5220, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { - .freq = 5230, - RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6), - }, - { - .freq = 5240, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { - .freq = 5250, - RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00, - 0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4), - }, - { - .freq = 5260, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0d, 0x00, 0x6f, 0x00), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { - .freq = 5270, - RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00, - 0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2), - }, - { - .freq = 5280, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { - .freq = 5290, - RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0), - }, - { - .freq = 5300, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { - .freq = 5310, - RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef), - }, - { - .freq = 5320, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00, - 0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c, - 0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0c, 0x00, 0x6f, 0x00), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { - .freq = 5330, - RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed), - }, - { - .freq = 5340, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec), - }, - { - .freq = 5350, - RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b, - 0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0b, 0x00, 0x6f, 0x00), - PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb), - }, - { - .freq = 5360, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea), - }, - { - .freq = 5370, - RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00, - 0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9), - }, - { - .freq = 5380, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8), - }, - { - .freq = 5390, - RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7), - }, - { - .freq = 5400, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6), - }, - { - .freq = 5410, - RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5), - }, - { - .freq = 5420, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00, - 0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5), - }, - { - .freq = 5430, - RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x0a, 0x00, 0x6f, 0x00), - PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4), - }, - { - .freq = 5440, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3), - }, - { - .freq = 5450, - RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2), - }, - { - .freq = 5460, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1), - }, - { - .freq = 5470, - RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00, - 0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0), - }, - { - .freq = 5480, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df), - }, - { - .freq = 5490, - RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de), - }, - { - .freq = 5500, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { - .freq = 5510, - RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd), - }, - { - .freq = 5520, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { - .freq = 5530, - RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db), - }, - { - .freq = 5540, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00, - 0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { - .freq = 5550, - RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9), - }, - { - .freq = 5560, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { - .freq = 5570, - RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00, - 0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x09, 0x00, 0x6f, 0x00), - PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7), - }, - { - .freq = 5580, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { - .freq = 5590, - RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00, - 0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6), - }, - { - .freq = 5600, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { - .freq = 5610, - RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08, - 0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x08, 0x00, 0x6f, 0x00), - PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4), - }, - { - .freq = 5620, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { - .freq = 5630, - RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2), - }, - { - .freq = 5640, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { - .freq = 5650, - RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x07, 0x00, 0x6f, 0x00), - PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1), - }, - { - .freq = 5660, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { - .freq = 5670, - RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00, - 0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf), - }, - { - .freq = 5680, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { - .freq = 5690, - RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6f, 0x00), - PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce), - }, - { - .freq = 5700, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { - .freq = 5710, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc), - }, - { - .freq = 5720, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb), - }, - { - .freq = 5725, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00, - 0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb), - }, - { - .freq = 5730, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6e, 0x00), - PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca), - }, - { - .freq = 5735, - RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca), - }, - { - .freq = 5740, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9), - }, - { - .freq = 5745, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06, - 0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x06, 0x00, 0x6d, 0x00), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { - .freq = 5750, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6d, 0x00), - PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9), - }, - { - .freq = 5755, - RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8), - }, - { - .freq = 5760, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8), - }, - { - .freq = 5765, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6c, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { - .freq = 5770, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7), - }, - { - .freq = 5775, - RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7), - }, - { - .freq = 5780, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00, - 0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6), - }, - { - .freq = 5785, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { - .freq = 5790, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6), - }, - { - .freq = 5795, - RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5), - }, - { - .freq = 5800, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6b, 0x00), - PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5), - }, - { - .freq = 5805, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { - .freq = 5810, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4), - }, - { - .freq = 5815, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4), - }, - { - .freq = 5820, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x6a, 0x00), - PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3), - }, - { - .freq = 5825, - RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x05, 0x05, 0x02, - 0x15, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, - { - .freq = 5830, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x05, 0x00, 0x69, 0x00), - PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2), - }, - { - .freq = 5840, - RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2), - }, - { - .freq = 5850, - RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1), - }, - { - .freq = 5860, - RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x69, 0x00), - PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0), - }, - { - .freq = 5870, - RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf), - }, - { - .freq = 5880, - RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf), - }, - { - .freq = 5890, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be), - }, - { - .freq = 5900, - RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd), - }, - { - .freq = 5910, - RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x02, - 0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04, - 0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x04, 0x00, 0x68, 0x00), - PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc), - }, - { - .freq = 2412, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { - .freq = 2417, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { - .freq = 2422, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0b, 0x00, 0x0a), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { - .freq = 2427, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { - .freq = 2432, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { - .freq = 2437, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { - .freq = 2442, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x0a), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { - .freq = 2447, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { - .freq = 2452, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { - .freq = 2457, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x0a, 0x00, 0x09), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { - .freq = 2462, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { - .freq = 2467, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { - .freq = 2472, - RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { - .freq = 2484, - RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x06, 0x06, 0x04, - 0x2b, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00, - 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00, - 0x70, 0x00, 0x09, 0x00, 0x09), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - }, -}; - -static const struct b2056_inittabs_pts -*b43_nphy_get_inittabs_rev3(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - switch (dev->phy.rev) { - case 3: - return &b2056_inittab_phy_rev3; - case 4: - return &b2056_inittab_phy_rev4; - default: - switch (phy->radio_rev) { - case 5: - return &b2056_inittab_radio_rev5; - case 6: - return &b2056_inittab_radio_rev6; - case 7: - case 9: - return &b2056_inittab_radio_rev7_9; - case 8: - return &b2056_inittab_radio_rev8; - case 11: - return &b2056_inittab_radio_rev11; - } - } - - return NULL; -} - -static void b2056_upload_inittab(struct b43_wldev *dev, bool ghz5, - bool ignore_uploadflag, u16 routing, - const struct b2056_inittab_entry *e, - unsigned int length) -{ - unsigned int i; - u16 value; - - for (i = 0; i < length; i++, e++) { - if (!(e->flags & B2056_INITTAB_ENTRY_OK)) - continue; - if ((e->flags & B2056_INITTAB_UPLOAD) || ignore_uploadflag) { - if (ghz5) - value = e->ghz5; - else - value = e->ghz2; - b43_radio_write(dev, routing | i, value); - } - } -} - -void b2056_upload_inittabs(struct b43_wldev *dev, - bool ghz5, bool ignore_uploadflag) -{ - const struct b2056_inittabs_pts *pts; - - pts = b43_nphy_get_inittabs_rev3(dev); - if (!pts) { - B43_WARN_ON(1); - return; - } - - b2056_upload_inittab(dev, ghz5, ignore_uploadflag, - B2056_SYN, pts->syn, pts->syn_length); - b2056_upload_inittab(dev, ghz5, ignore_uploadflag, - B2056_TX0, pts->tx, pts->tx_length); - b2056_upload_inittab(dev, ghz5, ignore_uploadflag, - B2056_TX1, pts->tx, pts->tx_length); - b2056_upload_inittab(dev, ghz5, ignore_uploadflag, - B2056_RX0, pts->rx, pts->rx_length); - b2056_upload_inittab(dev, ghz5, ignore_uploadflag, - B2056_RX1, pts->rx, pts->rx_length); -} - -void b2056_upload_syn_pll_cp2(struct b43_wldev *dev, bool ghz5) -{ - const struct b2056_inittabs_pts *pts; - const struct b2056_inittab_entry *e; - - pts = b43_nphy_get_inittabs_rev3(dev); - if (!pts) { - B43_WARN_ON(1); - return; - } - - e = &pts->syn[B2056_SYN_PLL_CP2]; - - b43_radio_write(dev, B2056_SYN_PLL_CP2, ghz5 ? e->ghz5 : e->ghz2); -} - -const struct b43_nphy_channeltab_entry_rev3 * -b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq) -{ - struct b43_phy *phy = &dev->phy; - const struct b43_nphy_channeltab_entry_rev3 *e; - unsigned int length, i; - - switch (phy->rev) { - case 3: - e = b43_nphy_channeltab_phy_rev3; - length = ARRAY_SIZE(b43_nphy_channeltab_phy_rev3); - break; - case 4: - e = b43_nphy_channeltab_phy_rev4; - length = ARRAY_SIZE(b43_nphy_channeltab_phy_rev4); - break; - default: - switch (phy->radio_rev) { - case 5: - e = b43_nphy_channeltab_radio_rev5; - length = ARRAY_SIZE(b43_nphy_channeltab_radio_rev5); - break; - case 6: - e = b43_nphy_channeltab_radio_rev6; - length = ARRAY_SIZE(b43_nphy_channeltab_radio_rev6); - break; - case 7: - case 9: - e = b43_nphy_channeltab_radio_rev7_9; - length = ARRAY_SIZE(b43_nphy_channeltab_radio_rev7_9); - break; - case 8: - e = b43_nphy_channeltab_radio_rev8; - length = ARRAY_SIZE(b43_nphy_channeltab_radio_rev8); - break; - case 11: - e = b43_nphy_channeltab_radio_rev11; - length = ARRAY_SIZE(b43_nphy_channeltab_radio_rev11); - break; - default: - B43_WARN_ON(1); - return NULL; - } - } - - for (i = 0; i < length; i++, e++) { - if (e->freq == freq) - return e; - } - - return NULL; -} diff --git a/drivers/net/wireless/b43/radio_2056.h b/drivers/net/wireless/b43/radio_2056.h deleted file mode 100644 index 5b8667345..000000000 --- a/drivers/net/wireless/b43/radio_2056.h +++ /dev/null @@ -1,1100 +0,0 @@ -#ifndef B43_RADIO_2056_H_ -#define B43_RADIO_2056_H_ - -#include <linux/types.h> - -#include "tables_nphy.h" - -#define B2056_SYN (0x0 << 12) -#define B2056_TX0 (0x2 << 12) -#define B2056_TX1 (0x3 << 12) -#define B2056_RX0 (0x6 << 12) -#define B2056_RX1 (0x7 << 12) -#define B2056_ALLTX (0xE << 12) -#define B2056_ALLRX (0xF << 12) - -#define B2056_SYN_RESERVED_ADDR0 0x00 -#define B2056_SYN_IDCODE 0x01 -#define B2056_SYN_RESERVED_ADDR2 0x02 -#define B2056_SYN_RESERVED_ADDR3 0x03 -#define B2056_SYN_RESERVED_ADDR4 0x04 -#define B2056_SYN_RESERVED_ADDR5 0x05 -#define B2056_SYN_RESERVED_ADDR6 0x06 -#define B2056_SYN_RESERVED_ADDR7 0x07 -#define B2056_SYN_COM_CTRL 0x08 -#define B2056_SYN_COM_PU 0x09 -#define B2056_SYN_COM_OVR 0x0A -#define B2056_SYN_COM_RESET 0x0B -#define B2056_SYN_COM_RCAL 0x0C -#define B2056_SYN_COM_RC_RXLPF 0x0D -#define B2056_SYN_COM_RC_TXLPF 0x0E -#define B2056_SYN_COM_RC_RXHPF 0x0F -#define B2056_SYN_RESERVED_ADDR16 0x10 -#define B2056_SYN_RESERVED_ADDR17 0x11 -#define B2056_SYN_RESERVED_ADDR18 0x12 -#define B2056_SYN_RESERVED_ADDR19 0x13 -#define B2056_SYN_RESERVED_ADDR20 0x14 -#define B2056_SYN_RESERVED_ADDR21 0x15 -#define B2056_SYN_RESERVED_ADDR22 0x16 -#define B2056_SYN_RESERVED_ADDR23 0x17 -#define B2056_SYN_RESERVED_ADDR24 0x18 -#define B2056_SYN_RESERVED_ADDR25 0x19 -#define B2056_SYN_RESERVED_ADDR26 0x1A -#define B2056_SYN_RESERVED_ADDR27 0x1B -#define B2056_SYN_RESERVED_ADDR28 0x1C -#define B2056_SYN_RESERVED_ADDR29 0x1D -#define B2056_SYN_RESERVED_ADDR30 0x1E -#define B2056_SYN_RESERVED_ADDR31 0x1F -#define B2056_SYN_GPIO_MASTER1 0x20 -#define B2056_SYN_GPIO_MASTER2 0x21 -#define B2056_SYN_TOPBIAS_MASTER 0x22 -#define B2056_SYN_TOPBIAS_RCAL 0x23 -#define B2056_SYN_AFEREG 0x24 -#define B2056_SYN_TEMPPROCSENSE 0x25 -#define B2056_SYN_TEMPPROCSENSEIDAC 0x26 -#define B2056_SYN_TEMPPROCSENSERCAL 0x27 -#define B2056_SYN_LPO 0x28 -#define B2056_SYN_VDDCAL_MASTER 0x29 -#define B2056_SYN_VDDCAL_IDAC 0x2A -#define B2056_SYN_VDDCAL_STATUS 0x2B -#define B2056_SYN_RCAL_MASTER 0x2C -#define B2056_SYN_RCAL_CODE_OUT 0x2D -#define B2056_SYN_RCCAL_CTRL0 0x2E -#define B2056_SYN_RCCAL_CTRL1 0x2F -#define B2056_SYN_RCCAL_CTRL2 0x30 -#define B2056_SYN_RCCAL_CTRL3 0x31 -#define B2056_SYN_RCCAL_CTRL4 0x32 -#define B2056_SYN_RCCAL_CTRL5 0x33 -#define B2056_SYN_RCCAL_CTRL6 0x34 -#define B2056_SYN_RCCAL_CTRL7 0x35 -#define B2056_SYN_RCCAL_CTRL8 0x36 -#define B2056_SYN_RCCAL_CTRL9 0x37 -#define B2056_SYN_RCCAL_CTRL10 0x38 -#define B2056_SYN_RCCAL_CTRL11 0x39 -#define B2056_SYN_ZCAL_SPARE1 0x3A -#define B2056_SYN_ZCAL_SPARE2 0x3B -#define B2056_SYN_PLL_MAST1 0x3C -#define B2056_SYN_PLL_MAST2 0x3D -#define B2056_SYN_PLL_MAST3 0x3E -#define B2056_SYN_PLL_BIAS_RESET 0x3F -#define B2056_SYN_PLL_XTAL0 0x40 -#define B2056_SYN_PLL_XTAL1 0x41 -#define B2056_SYN_PLL_XTAL3 0x42 -#define B2056_SYN_PLL_XTAL4 0x43 -#define B2056_SYN_PLL_XTAL5 0x44 -#define B2056_SYN_PLL_XTAL6 0x45 -#define B2056_SYN_PLL_REFDIV 0x46 -#define B2056_SYN_PLL_PFD 0x47 -#define B2056_SYN_PLL_CP1 0x48 -#define B2056_SYN_PLL_CP2 0x49 -#define B2056_SYN_PLL_CP3 0x4A -#define B2056_SYN_PLL_LOOPFILTER1 0x4B -#define B2056_SYN_PLL_LOOPFILTER2 0x4C -#define B2056_SYN_PLL_LOOPFILTER3 0x4D -#define B2056_SYN_PLL_LOOPFILTER4 0x4E -#define B2056_SYN_PLL_LOOPFILTER5 0x4F -#define B2056_SYN_PLL_MMD1 0x50 -#define B2056_SYN_PLL_MMD2 0x51 -#define B2056_SYN_PLL_VCO1 0x52 -#define B2056_SYN_PLL_VCO2 0x53 -#define B2056_SYN_PLL_MONITOR1 0x54 -#define B2056_SYN_PLL_MONITOR2 0x55 -#define B2056_SYN_PLL_VCOCAL1 0x56 -#define B2056_SYN_PLL_VCOCAL2 0x57 -#define B2056_SYN_PLL_VCOCAL4 0x58 -#define B2056_SYN_PLL_VCOCAL5 0x59 -#define B2056_SYN_PLL_VCOCAL6 0x5A -#define B2056_SYN_PLL_VCOCAL7 0x5B -#define B2056_SYN_PLL_VCOCAL8 0x5C -#define B2056_SYN_PLL_VCOCAL9 0x5D -#define B2056_SYN_PLL_VCOCAL10 0x5E -#define B2056_SYN_PLL_VCOCAL11 0x5F -#define B2056_SYN_PLL_VCOCAL12 0x60 -#define B2056_SYN_PLL_VCOCAL13 0x61 -#define B2056_SYN_PLL_VREG 0x62 -#define B2056_SYN_PLL_STATUS1 0x63 -#define B2056_SYN_PLL_STATUS2 0x64 -#define B2056_SYN_PLL_STATUS3 0x65 -#define B2056_SYN_LOGEN_PU0 0x66 -#define B2056_SYN_LOGEN_PU1 0x67 -#define B2056_SYN_LOGEN_PU2 0x68 -#define B2056_SYN_LOGEN_PU3 0x69 -#define B2056_SYN_LOGEN_PU5 0x6A -#define B2056_SYN_LOGEN_PU6 0x6B -#define B2056_SYN_LOGEN_PU7 0x6C -#define B2056_SYN_LOGEN_PU8 0x6D -#define B2056_SYN_LOGEN_BIAS_RESET 0x6E -#define B2056_SYN_LOGEN_RCCR1 0x6F -#define B2056_SYN_LOGEN_VCOBUF1 0x70 -#define B2056_SYN_LOGEN_MIXER1 0x71 -#define B2056_SYN_LOGEN_MIXER2 0x72 -#define B2056_SYN_LOGEN_BUF1 0x73 -#define B2056_SYN_LOGENBUF2 0x74 -#define B2056_SYN_LOGEN_BUF3 0x75 -#define B2056_SYN_LOGEN_BUF4 0x76 -#define B2056_SYN_LOGEN_DIV1 0x77 -#define B2056_SYN_LOGEN_DIV2 0x78 -#define B2056_SYN_LOGEN_DIV3 0x79 -#define B2056_SYN_LOGEN_ACL1 0x7A -#define B2056_SYN_LOGEN_ACL2 0x7B -#define B2056_SYN_LOGEN_ACL3 0x7C -#define B2056_SYN_LOGEN_ACL4 0x7D -#define B2056_SYN_LOGEN_ACL5 0x7E -#define B2056_SYN_LOGEN_ACL6 0x7F -#define B2056_SYN_LOGEN_ACLOUT 0x80 -#define B2056_SYN_LOGEN_ACLCAL1 0x81 -#define B2056_SYN_LOGEN_ACLCAL2 0x82 -#define B2056_SYN_LOGEN_ACLCAL3 0x83 -#define B2056_SYN_CALEN 0x84 -#define B2056_SYN_LOGEN_PEAKDET1 0x85 -#define B2056_SYN_LOGEN_CORE_ACL_OVR 0x86 -#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87 -#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88 -#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89 -#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A -#define B2056_SYN_LOGEN_VCOBUF2 0x8B -#define B2056_SYN_LOGEN_MIXER3 0x8C -#define B2056_SYN_LOGEN_BUF5 0x8D -#define B2056_SYN_LOGEN_BUF6 0x8E -#define B2056_SYN_LOGEN_CBUFRX1 0x8F -#define B2056_SYN_LOGEN_CBUFRX2 0x90 -#define B2056_SYN_LOGEN_CBUFRX3 0x91 -#define B2056_SYN_LOGEN_CBUFRX4 0x92 -#define B2056_SYN_LOGEN_CBUFTX1 0x93 -#define B2056_SYN_LOGEN_CBUFTX2 0x94 -#define B2056_SYN_LOGEN_CBUFTX3 0x95 -#define B2056_SYN_LOGEN_CBUFTX4 0x96 -#define B2056_SYN_LOGEN_CMOSRX1 0x97 -#define B2056_SYN_LOGEN_CMOSRX2 0x98 -#define B2056_SYN_LOGEN_CMOSRX3 0x99 -#define B2056_SYN_LOGEN_CMOSRX4 0x9A -#define B2056_SYN_LOGEN_CMOSTX1 0x9B -#define B2056_SYN_LOGEN_CMOSTX2 0x9C -#define B2056_SYN_LOGEN_CMOSTX3 0x9D -#define B2056_SYN_LOGEN_CMOSTX4 0x9E -#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9F -#define B2056_SYN_LOGEN_MIXER3_OVRVAL 0xA0 -#define B2056_SYN_LOGEN_BUF5_OVRVAL 0xA1 -#define B2056_SYN_LOGEN_BUF6_OVRVAL 0xA2 -#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xA3 -#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xA4 -#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xA5 -#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xA6 -#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xA7 -#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xA8 -#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xA9 -#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xAA -#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xAB -#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xAC -#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xAD -#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xAE -#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xAF -#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xB0 -#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xB1 -#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xB2 -#define B2056_SYN_LOGEN_ACL_WAITCNT 0xB3 -#define B2056_SYN_LOGEN_CORE_CALVALID 0xB4 -#define B2056_SYN_LOGEN_RX_CMOS_CALVALID 0xB5 -#define B2056_SYN_LOGEN_TX_CMOS_VALID 0xB6 - -#define B2056_TX_RESERVED_ADDR0 0x00 -#define B2056_TX_IDCODE 0x01 -#define B2056_TX_RESERVED_ADDR2 0x02 -#define B2056_TX_RESERVED_ADDR3 0x03 -#define B2056_TX_RESERVED_ADDR4 0x04 -#define B2056_TX_RESERVED_ADDR5 0x05 -#define B2056_TX_RESERVED_ADDR6 0x06 -#define B2056_TX_RESERVED_ADDR7 0x07 -#define B2056_TX_COM_CTRL 0x08 -#define B2056_TX_COM_PU 0x09 -#define B2056_TX_COM_OVR 0x0A -#define B2056_TX_COM_RESET 0x0B -#define B2056_TX_COM_RCAL 0x0C -#define B2056_TX_COM_RC_RXLPF 0x0D -#define B2056_TX_COM_RC_TXLPF 0x0E -#define B2056_TX_COM_RC_RXHPF 0x0F -#define B2056_TX_RESERVED_ADDR16 0x10 -#define B2056_TX_RESERVED_ADDR17 0x11 -#define B2056_TX_RESERVED_ADDR18 0x12 -#define B2056_TX_RESERVED_ADDR19 0x13 -#define B2056_TX_RESERVED_ADDR20 0x14 -#define B2056_TX_RESERVED_ADDR21 0x15 -#define B2056_TX_RESERVED_ADDR22 0x16 -#define B2056_TX_RESERVED_ADDR23 0x17 -#define B2056_TX_RESERVED_ADDR24 0x18 -#define B2056_TX_RESERVED_ADDR25 0x19 -#define B2056_TX_RESERVED_ADDR26 0x1A -#define B2056_TX_RESERVED_ADDR27 0x1B -#define B2056_TX_RESERVED_ADDR28 0x1C -#define B2056_TX_RESERVED_ADDR29 0x1D -#define B2056_TX_RESERVED_ADDR30 0x1E -#define B2056_TX_RESERVED_ADDR31 0x1F -#define B2056_TX_IQCAL_GAIN_BW 0x20 -#define B2056_TX_LOFT_FINE_I 0x21 -#define B2056_TX_LOFT_FINE_Q 0x22 -#define B2056_TX_LOFT_COARSE_I 0x23 -#define B2056_TX_LOFT_COARSE_Q 0x24 -#define B2056_TX_TX_COM_MASTER1 0x25 -#define B2056_TX_TX_COM_MASTER2 0x26 -#define B2056_TX_RXIQCAL_TXMUX 0x27 -#define B2056_TX_TX_SSI_MASTER 0x28 -#define B2056_TX_IQCAL_VCM_HG 0x29 -#define B2056_TX_IQCAL_IDAC 0x2A -#define B2056_TX_TSSI_VCM 0x2B -#define B2056_TX_TX_AMP_DET 0x2C -#define B2056_TX_TX_SSI_MUX 0x2D -#define B2056_TX_TSSIA 0x2E -#define B2056_TX_TSSIG 0x2F -#define B2056_TX_TSSI_MISC1 0x30 -#define B2056_TX_TSSI_MISC2 0x31 -#define B2056_TX_TSSI_MISC3 0x32 -#define B2056_TX_PA_SPARE1 0x33 -#define B2056_TX_PA_SPARE2 0x34 -#define B2056_TX_INTPAA_MASTER 0x35 -#define B2056_TX_INTPAA_GAIN 0x36 -#define B2056_TX_INTPAA_BOOST_TUNE 0x37 -#define B2056_TX_INTPAA_IAUX_STAT 0x38 -#define B2056_TX_INTPAA_IAUX_DYN 0x39 -#define B2056_TX_INTPAA_IMAIN_STAT 0x3A -#define B2056_TX_INTPAA_IMAIN_DYN 0x3B -#define B2056_TX_INTPAA_CASCBIAS 0x3C -#define B2056_TX_INTPAA_PASLOPE 0x3D -#define B2056_TX_INTPAA_PA_MISC 0x3E -#define B2056_TX_INTPAG_MASTER 0x3F -#define B2056_TX_INTPAG_GAIN 0x40 -#define B2056_TX_INTPAG_BOOST_TUNE 0x41 -#define B2056_TX_INTPAG_IAUX_STAT 0x42 -#define B2056_TX_INTPAG_IAUX_DYN 0x43 -#define B2056_TX_INTPAG_IMAIN_STAT 0x44 -#define B2056_TX_INTPAG_IMAIN_DYN 0x45 -#define B2056_TX_INTPAG_CASCBIAS 0x46 -#define B2056_TX_INTPAG_PASLOPE 0x47 -#define B2056_TX_INTPAG_PA_MISC 0x48 -#define B2056_TX_PADA_MASTER 0x49 -#define B2056_TX_PADA_IDAC 0x4A -#define B2056_TX_PADA_CASCBIAS 0x4B -#define B2056_TX_PADA_GAIN 0x4C -#define B2056_TX_PADA_BOOST_TUNE 0x4D -#define B2056_TX_PADA_SLOPE 0x4E -#define B2056_TX_PADG_MASTER 0x4F -#define B2056_TX_PADG_IDAC 0x50 -#define B2056_TX_PADG_CASCBIAS 0x51 -#define B2056_TX_PADG_GAIN 0x52 -#define B2056_TX_PADG_BOOST_TUNE 0x53 -#define B2056_TX_PADG_SLOPE 0x54 -#define B2056_TX_PGAA_MASTER 0x55 -#define B2056_TX_PGAA_IDAC 0x56 -#define B2056_TX_PGAA_GAIN 0x57 -#define B2056_TX_PGAA_BOOST_TUNE 0x58 -#define B2056_TX_PGAA_SLOPE 0x59 -#define B2056_TX_PGAA_MISC 0x5A -#define B2056_TX_PGAG_MASTER 0x5B -#define B2056_TX_PGAG_IDAC 0x5C -#define B2056_TX_PGAG_GAIN 0x5D -#define B2056_TX_PGAG_BOOST_TUNE 0x5E -#define B2056_TX_PGAG_SLOPE 0x5F -#define B2056_TX_PGAG_MISC 0x60 -#define B2056_TX_MIXA_MASTER 0x61 -#define B2056_TX_MIXA_BOOST_TUNE 0x62 -#define B2056_TX_MIXG 0x63 -#define B2056_TX_MIXG_BOOST_TUNE 0x64 -#define B2056_TX_BB_GM_MASTER 0x65 -#define B2056_TX_GMBB_GM 0x66 -#define B2056_TX_GMBB_IDAC 0x67 -#define B2056_TX_TXLPF_MASTER 0x68 -#define B2056_TX_TXLPF_RCCAL 0x69 -#define B2056_TX_TXLPF_RCCAL_OFF0 0x6A -#define B2056_TX_TXLPF_RCCAL_OFF1 0x6B -#define B2056_TX_TXLPF_RCCAL_OFF2 0x6C -#define B2056_TX_TXLPF_RCCAL_OFF3 0x6D -#define B2056_TX_TXLPF_RCCAL_OFF4 0x6E -#define B2056_TX_TXLPF_RCCAL_OFF5 0x6F -#define B2056_TX_TXLPF_RCCAL_OFF6 0x70 -#define B2056_TX_TXLPF_BW 0x71 -#define B2056_TX_TXLPF_GAIN 0x72 -#define B2056_TX_TXLPF_IDAC 0x73 -#define B2056_TX_TXLPF_IDAC_0 0x74 -#define B2056_TX_TXLPF_IDAC_1 0x75 -#define B2056_TX_TXLPF_IDAC_2 0x76 -#define B2056_TX_TXLPF_IDAC_3 0x77 -#define B2056_TX_TXLPF_IDAC_4 0x78 -#define B2056_TX_TXLPF_IDAC_5 0x79 -#define B2056_TX_TXLPF_IDAC_6 0x7A -#define B2056_TX_TXLPF_OPAMP_IDAC 0x7B -#define B2056_TX_TXLPF_MISC 0x7C -#define B2056_TX_TXSPARE1 0x7D -#define B2056_TX_TXSPARE2 0x7E -#define B2056_TX_TXSPARE3 0x7F -#define B2056_TX_TXSPARE4 0x80 -#define B2056_TX_TXSPARE5 0x81 -#define B2056_TX_TXSPARE6 0x82 -#define B2056_TX_TXSPARE7 0x83 -#define B2056_TX_TXSPARE8 0x84 -#define B2056_TX_TXSPARE9 0x85 -#define B2056_TX_TXSPARE10 0x86 -#define B2056_TX_TXSPARE11 0x87 -#define B2056_TX_TXSPARE12 0x88 -#define B2056_TX_TXSPARE13 0x89 -#define B2056_TX_TXSPARE14 0x8A -#define B2056_TX_TXSPARE15 0x8B -#define B2056_TX_TXSPARE16 0x8C -#define B2056_TX_STATUS_INTPA_GAIN 0x8D -#define B2056_TX_STATUS_PAD_GAIN 0x8E -#define B2056_TX_STATUS_PGA_GAIN 0x8F -#define B2056_TX_STATUS_GM_TXLPF_GAIN 0x90 -#define B2056_TX_STATUS_TXLPF_BW 0x91 -#define B2056_TX_STATUS_TXLPF_RC 0x92 -#define B2056_TX_GMBB_IDAC0 0x93 -#define B2056_TX_GMBB_IDAC1 0x94 -#define B2056_TX_GMBB_IDAC2 0x95 -#define B2056_TX_GMBB_IDAC3 0x96 -#define B2056_TX_GMBB_IDAC4 0x97 -#define B2056_TX_GMBB_IDAC5 0x98 -#define B2056_TX_GMBB_IDAC6 0x99 -#define B2056_TX_GMBB_IDAC7 0x9A - -#define B2056_RX_RESERVED_ADDR0 0x00 -#define B2056_RX_IDCODE 0x01 -#define B2056_RX_RESERVED_ADDR2 0x02 -#define B2056_RX_RESERVED_ADDR3 0x03 -#define B2056_RX_RESERVED_ADDR4 0x04 -#define B2056_RX_RESERVED_ADDR5 0x05 -#define B2056_RX_RESERVED_ADDR6 0x06 -#define B2056_RX_RESERVED_ADDR7 0x07 -#define B2056_RX_COM_CTRL 0x08 -#define B2056_RX_COM_PU 0x09 -#define B2056_RX_COM_OVR 0x0A -#define B2056_RX_COM_RESET 0x0B -#define B2056_RX_COM_RCAL 0x0C -#define B2056_RX_COM_RC_RXLPF 0x0D -#define B2056_RX_COM_RC_TXLPF 0x0E -#define B2056_RX_COM_RC_RXHPF 0x0F -#define B2056_RX_RESERVED_ADDR16 0x10 -#define B2056_RX_RESERVED_ADDR17 0x11 -#define B2056_RX_RESERVED_ADDR18 0x12 -#define B2056_RX_RESERVED_ADDR19 0x13 -#define B2056_RX_RESERVED_ADDR20 0x14 -#define B2056_RX_RESERVED_ADDR21 0x15 -#define B2056_RX_RESERVED_ADDR22 0x16 -#define B2056_RX_RESERVED_ADDR23 0x17 -#define B2056_RX_RESERVED_ADDR24 0x18 -#define B2056_RX_RESERVED_ADDR25 0x19 -#define B2056_RX_RESERVED_ADDR26 0x1A -#define B2056_RX_RESERVED_ADDR27 0x1B -#define B2056_RX_RESERVED_ADDR28 0x1C -#define B2056_RX_RESERVED_ADDR29 0x1D -#define B2056_RX_RESERVED_ADDR30 0x1E -#define B2056_RX_RESERVED_ADDR31 0x1F -#define B2056_RX_RXIQCAL_RXMUX 0x20 -#define B2056_RX_RSSI_PU 0x21 -#define B2056_RX_RSSI_SEL 0x22 -#define B2056_RX_RSSI_GAIN 0x23 -#define B2056_RX_RSSI_NB_IDAC 0x24 -#define B2056_RX_RSSI_WB2I_IDAC_1 0x25 -#define B2056_RX_RSSI_WB2I_IDAC_2 0x26 -#define B2056_RX_RSSI_WB2Q_IDAC_1 0x27 -#define B2056_RX_RSSI_WB2Q_IDAC_2 0x28 -#define B2056_RX_RSSI_POLE 0x29 -#define B2056_RX_RSSI_WB1_IDAC 0x2A -#define B2056_RX_RSSI_MISC 0x2B -#define B2056_RX_LNAA_MASTER 0x2C -#define B2056_RX_LNAA_TUNE 0x2D -#define B2056_RX_LNAA_GAIN 0x2E -#define B2056_RX_LNA_A_SLOPE 0x2F -#define B2056_RX_BIASPOLE_LNAA1_IDAC 0x30 -#define B2056_RX_LNAA2_IDAC 0x31 -#define B2056_RX_LNA1A_MISC 0x32 -#define B2056_RX_LNAG_MASTER 0x33 -#define B2056_RX_LNAG_TUNE 0x34 -#define B2056_RX_LNAG_GAIN 0x35 -#define B2056_RX_LNA_G_SLOPE 0x36 -#define B2056_RX_BIASPOLE_LNAG1_IDAC 0x37 -#define B2056_RX_LNAG2_IDAC 0x38 -#define B2056_RX_LNA1G_MISC 0x39 -#define B2056_RX_MIXA_MASTER 0x3A -#define B2056_RX_MIXA_VCM 0x3B -#define B2056_RX_MIXA_CTRLPTAT 0x3C -#define B2056_RX_MIXA_LOB_BIAS 0x3D -#define B2056_RX_MIXA_CORE_IDAC 0x3E -#define B2056_RX_MIXA_CMFB_IDAC 0x3F -#define B2056_RX_MIXA_BIAS_AUX 0x40 -#define B2056_RX_MIXA_BIAS_MAIN 0x41 -#define B2056_RX_MIXA_BIAS_MISC 0x42 -#define B2056_RX_MIXA_MAST_BIAS 0x43 -#define B2056_RX_MIXG_MASTER 0x44 -#define B2056_RX_MIXG_VCM 0x45 -#define B2056_RX_MIXG_CTRLPTAT 0x46 -#define B2056_RX_MIXG_LOB_BIAS 0x47 -#define B2056_RX_MIXG_CORE_IDAC 0x48 -#define B2056_RX_MIXG_CMFB_IDAC 0x49 -#define B2056_RX_MIXG_BIAS_AUX 0x4A -#define B2056_RX_MIXG_BIAS_MAIN 0x4B -#define B2056_RX_MIXG_BIAS_MISC 0x4C -#define B2056_RX_MIXG_MAST_BIAS 0x4D -#define B2056_RX_TIA_MASTER 0x4E -#define B2056_RX_TIA_IOPAMP 0x4F -#define B2056_RX_TIA_QOPAMP 0x50 -#define B2056_RX_TIA_IMISC 0x51 -#define B2056_RX_TIA_QMISC 0x52 -#define B2056_RX_TIA_GAIN 0x53 -#define B2056_RX_TIA_SPARE1 0x54 -#define B2056_RX_TIA_SPARE2 0x55 -#define B2056_RX_BB_LPF_MASTER 0x56 -#define B2056_RX_AACI_MASTER 0x57 -#define B2056_RX_RXLPF_IDAC 0x58 -#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59 -#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5A -#define B2056_RX_RXLPF_BIAS_DCCANCEL 0x5B -#define B2056_RX_RXLPF_OUTVCM 0x5C -#define B2056_RX_RXLPF_INVCM_BODY 0x5D -#define B2056_RX_RXLPF_CC_OP 0x5E -#define B2056_RX_RXLPF_GAIN 0x5F -#define B2056_RX_RXLPF_Q_BW 0x60 -#define B2056_RX_RXLPF_HP_CORNER_BW 0x61 -#define B2056_RX_RXLPF_RCCAL_HPC 0x62 -#define B2056_RX_RXHPF_OFF0 0x63 -#define B2056_RX_RXHPF_OFF1 0x64 -#define B2056_RX_RXHPF_OFF2 0x65 -#define B2056_RX_RXHPF_OFF3 0x66 -#define B2056_RX_RXHPF_OFF4 0x67 -#define B2056_RX_RXHPF_OFF5 0x68 -#define B2056_RX_RXHPF_OFF6 0x69 -#define B2056_RX_RXHPF_OFF7 0x6A -#define B2056_RX_RXLPF_RCCAL_LPC 0x6B -#define B2056_RX_RXLPF_OFF_0 0x6C -#define B2056_RX_RXLPF_OFF_1 0x6D -#define B2056_RX_RXLPF_OFF_2 0x6E -#define B2056_RX_RXLPF_OFF_3 0x6F -#define B2056_RX_RXLPF_OFF_4 0x70 -#define B2056_RX_UNUSED 0x71 -#define B2056_RX_VGA_MASTER 0x72 -#define B2056_RX_VGA_BIAS 0x73 -#define B2056_RX_VGA_BIAS_DCCANCEL 0x74 -#define B2056_RX_VGA_GAIN 0x75 -#define B2056_RX_VGA_HP_CORNER_BW 0x76 -#define B2056_RX_VGABUF_BIAS 0x77 -#define B2056_RX_VGABUF_GAIN_BW 0x78 -#define B2056_RX_TXFBMIX_A 0x79 -#define B2056_RX_TXFBMIX_G 0x7A -#define B2056_RX_RXSPARE1 0x7B -#define B2056_RX_RXSPARE2 0x7C -#define B2056_RX_RXSPARE3 0x7D -#define B2056_RX_RXSPARE4 0x7E -#define B2056_RX_RXSPARE5 0x7F -#define B2056_RX_RXSPARE6 0x80 -#define B2056_RX_RXSPARE7 0x81 -#define B2056_RX_RXSPARE8 0x82 -#define B2056_RX_RXSPARE9 0x83 -#define B2056_RX_RXSPARE10 0x84 -#define B2056_RX_RXSPARE11 0x85 -#define B2056_RX_RXSPARE12 0x86 -#define B2056_RX_RXSPARE13 0x87 -#define B2056_RX_RXSPARE14 0x88 -#define B2056_RX_RXSPARE15 0x89 -#define B2056_RX_RXSPARE16 0x8A -#define B2056_RX_STATUS_LNAA_GAIN 0x8B -#define B2056_RX_STATUS_LNAG_GAIN 0x8C -#define B2056_RX_STATUS_MIXTIA_GAIN 0x8D -#define B2056_RX_STATUS_RXLPF_GAIN 0x8E -#define B2056_RX_STATUS_VGA_BUF_GAIN 0x8F -#define B2056_RX_STATUS_RXLPF_Q 0x90 -#define B2056_RX_STATUS_RXLPF_BUF_BW 0x91 -#define B2056_RX_STATUS_RXLPF_VGA_HPC 0x92 -#define B2056_RX_STATUS_RXLPF_RC 0x93 -#define B2056_RX_STATUS_HPC_RC 0x94 - -#define B2056_LNA1_A_PU 0x01 -#define B2056_LNA2_A_PU 0x02 -#define B2056_LNA1_G_PU 0x01 -#define B2056_LNA2_G_PU 0x02 -#define B2056_MIXA_PU_I 0x01 -#define B2056_MIXA_PU_Q 0x02 -#define B2056_MIXA_PU_GM 0x10 -#define B2056_MIXG_PU_I 0x01 -#define B2056_MIXG_PU_Q 0x02 -#define B2056_MIXG_PU_GM 0x10 -#define B2056_TIA_PU 0x01 -#define B2056_BB_LPF_PU 0x20 -#define B2056_W1_PU 0x02 -#define B2056_W2_PU 0x04 -#define B2056_NB_PU 0x08 -#define B2056_RSSI_W1_SEL 0x02 -#define B2056_RSSI_W2_SEL 0x04 -#define B2056_RSSI_NB_SEL 0x08 -#define B2056_VCM_MASK 0x1C -#define B2056_RSSI_VCM_SHIFT 0x02 - -#define B2056_SYN (0x0 << 12) -#define B2056_TX0 (0x2 << 12) -#define B2056_TX1 (0x3 << 12) -#define B2056_RX0 (0x6 << 12) -#define B2056_RX1 (0x7 << 12) -#define B2056_ALLTX (0xE << 12) -#define B2056_ALLRX (0xF << 12) - -#define B2056_SYN_RESERVED_ADDR0 0x00 -#define B2056_SYN_IDCODE 0x01 -#define B2056_SYN_RESERVED_ADDR2 0x02 -#define B2056_SYN_RESERVED_ADDR3 0x03 -#define B2056_SYN_RESERVED_ADDR4 0x04 -#define B2056_SYN_RESERVED_ADDR5 0x05 -#define B2056_SYN_RESERVED_ADDR6 0x06 -#define B2056_SYN_RESERVED_ADDR7 0x07 -#define B2056_SYN_COM_CTRL 0x08 -#define B2056_SYN_COM_PU 0x09 -#define B2056_SYN_COM_OVR 0x0A -#define B2056_SYN_COM_RESET 0x0B -#define B2056_SYN_COM_RCAL 0x0C -#define B2056_SYN_COM_RC_RXLPF 0x0D -#define B2056_SYN_COM_RC_TXLPF 0x0E -#define B2056_SYN_COM_RC_RXHPF 0x0F -#define B2056_SYN_RESERVED_ADDR16 0x10 -#define B2056_SYN_RESERVED_ADDR17 0x11 -#define B2056_SYN_RESERVED_ADDR18 0x12 -#define B2056_SYN_RESERVED_ADDR19 0x13 -#define B2056_SYN_RESERVED_ADDR20 0x14 -#define B2056_SYN_RESERVED_ADDR21 0x15 -#define B2056_SYN_RESERVED_ADDR22 0x16 -#define B2056_SYN_RESERVED_ADDR23 0x17 -#define B2056_SYN_RESERVED_ADDR24 0x18 -#define B2056_SYN_RESERVED_ADDR25 0x19 -#define B2056_SYN_RESERVED_ADDR26 0x1A -#define B2056_SYN_RESERVED_ADDR27 0x1B -#define B2056_SYN_RESERVED_ADDR28 0x1C -#define B2056_SYN_RESERVED_ADDR29 0x1D -#define B2056_SYN_RESERVED_ADDR30 0x1E -#define B2056_SYN_RESERVED_ADDR31 0x1F -#define B2056_SYN_GPIO_MASTER1 0x20 -#define B2056_SYN_GPIO_MASTER2 0x21 -#define B2056_SYN_TOPBIAS_MASTER 0x22 -#define B2056_SYN_TOPBIAS_RCAL 0x23 -#define B2056_SYN_AFEREG 0x24 -#define B2056_SYN_TEMPPROCSENSE 0x25 -#define B2056_SYN_TEMPPROCSENSEIDAC 0x26 -#define B2056_SYN_TEMPPROCSENSERCAL 0x27 -#define B2056_SYN_LPO 0x28 -#define B2056_SYN_VDDCAL_MASTER 0x29 -#define B2056_SYN_VDDCAL_IDAC 0x2A -#define B2056_SYN_VDDCAL_STATUS 0x2B -#define B2056_SYN_RCAL_MASTER 0x2C -#define B2056_SYN_RCAL_CODE_OUT 0x2D -#define B2056_SYN_RCCAL_CTRL0 0x2E -#define B2056_SYN_RCCAL_CTRL1 0x2F -#define B2056_SYN_RCCAL_CTRL2 0x30 -#define B2056_SYN_RCCAL_CTRL3 0x31 -#define B2056_SYN_RCCAL_CTRL4 0x32 -#define B2056_SYN_RCCAL_CTRL5 0x33 -#define B2056_SYN_RCCAL_CTRL6 0x34 -#define B2056_SYN_RCCAL_CTRL7 0x35 -#define B2056_SYN_RCCAL_CTRL8 0x36 -#define B2056_SYN_RCCAL_CTRL9 0x37 -#define B2056_SYN_RCCAL_CTRL10 0x38 -#define B2056_SYN_RCCAL_CTRL11 0x39 -#define B2056_SYN_ZCAL_SPARE1 0x3A -#define B2056_SYN_ZCAL_SPARE2 0x3B -#define B2056_SYN_PLL_MAST1 0x3C -#define B2056_SYN_PLL_MAST2 0x3D -#define B2056_SYN_PLL_MAST3 0x3E -#define B2056_SYN_PLL_BIAS_RESET 0x3F -#define B2056_SYN_PLL_XTAL0 0x40 -#define B2056_SYN_PLL_XTAL1 0x41 -#define B2056_SYN_PLL_XTAL3 0x42 -#define B2056_SYN_PLL_XTAL4 0x43 -#define B2056_SYN_PLL_XTAL5 0x44 -#define B2056_SYN_PLL_XTAL6 0x45 -#define B2056_SYN_PLL_REFDIV 0x46 -#define B2056_SYN_PLL_PFD 0x47 -#define B2056_SYN_PLL_CP1 0x48 -#define B2056_SYN_PLL_CP2 0x49 -#define B2056_SYN_PLL_CP3 0x4A -#define B2056_SYN_PLL_LOOPFILTER1 0x4B -#define B2056_SYN_PLL_LOOPFILTER2 0x4C -#define B2056_SYN_PLL_LOOPFILTER3 0x4D -#define B2056_SYN_PLL_LOOPFILTER4 0x4E -#define B2056_SYN_PLL_LOOPFILTER5 0x4F -#define B2056_SYN_PLL_MMD1 0x50 -#define B2056_SYN_PLL_MMD2 0x51 -#define B2056_SYN_PLL_VCO1 0x52 -#define B2056_SYN_PLL_VCO2 0x53 -#define B2056_SYN_PLL_MONITOR1 0x54 -#define B2056_SYN_PLL_MONITOR2 0x55 -#define B2056_SYN_PLL_VCOCAL1 0x56 -#define B2056_SYN_PLL_VCOCAL2 0x57 -#define B2056_SYN_PLL_VCOCAL4 0x58 -#define B2056_SYN_PLL_VCOCAL5 0x59 -#define B2056_SYN_PLL_VCOCAL6 0x5A -#define B2056_SYN_PLL_VCOCAL7 0x5B -#define B2056_SYN_PLL_VCOCAL8 0x5C -#define B2056_SYN_PLL_VCOCAL9 0x5D -#define B2056_SYN_PLL_VCOCAL10 0x5E -#define B2056_SYN_PLL_VCOCAL11 0x5F -#define B2056_SYN_PLL_VCOCAL12 0x60 -#define B2056_SYN_PLL_VCOCAL13 0x61 -#define B2056_SYN_PLL_VREG 0x62 -#define B2056_SYN_PLL_STATUS1 0x63 -#define B2056_SYN_PLL_STATUS2 0x64 -#define B2056_SYN_PLL_STATUS3 0x65 -#define B2056_SYN_LOGEN_PU0 0x66 -#define B2056_SYN_LOGEN_PU1 0x67 -#define B2056_SYN_LOGEN_PU2 0x68 -#define B2056_SYN_LOGEN_PU3 0x69 -#define B2056_SYN_LOGEN_PU5 0x6A -#define B2056_SYN_LOGEN_PU6 0x6B -#define B2056_SYN_LOGEN_PU7 0x6C -#define B2056_SYN_LOGEN_PU8 0x6D -#define B2056_SYN_LOGEN_BIAS_RESET 0x6E -#define B2056_SYN_LOGEN_RCCR1 0x6F -#define B2056_SYN_LOGEN_VCOBUF1 0x70 -#define B2056_SYN_LOGEN_MIXER1 0x71 -#define B2056_SYN_LOGEN_MIXER2 0x72 -#define B2056_SYN_LOGEN_BUF1 0x73 -#define B2056_SYN_LOGENBUF2 0x74 -#define B2056_SYN_LOGEN_BUF3 0x75 -#define B2056_SYN_LOGEN_BUF4 0x76 -#define B2056_SYN_LOGEN_DIV1 0x77 -#define B2056_SYN_LOGEN_DIV2 0x78 -#define B2056_SYN_LOGEN_DIV3 0x79 -#define B2056_SYN_LOGEN_ACL1 0x7A -#define B2056_SYN_LOGEN_ACL2 0x7B -#define B2056_SYN_LOGEN_ACL3 0x7C -#define B2056_SYN_LOGEN_ACL4 0x7D -#define B2056_SYN_LOGEN_ACL5 0x7E -#define B2056_SYN_LOGEN_ACL6 0x7F -#define B2056_SYN_LOGEN_ACLOUT 0x80 -#define B2056_SYN_LOGEN_ACLCAL1 0x81 -#define B2056_SYN_LOGEN_ACLCAL2 0x82 -#define B2056_SYN_LOGEN_ACLCAL3 0x83 -#define B2056_SYN_CALEN 0x84 -#define B2056_SYN_LOGEN_PEAKDET1 0x85 -#define B2056_SYN_LOGEN_CORE_ACL_OVR 0x86 -#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87 -#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88 -#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89 -#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A -#define B2056_SYN_LOGEN_VCOBUF2 0x8B -#define B2056_SYN_LOGEN_MIXER3 0x8C -#define B2056_SYN_LOGEN_BUF5 0x8D -#define B2056_SYN_LOGEN_BUF6 0x8E -#define B2056_SYN_LOGEN_CBUFRX1 0x8F -#define B2056_SYN_LOGEN_CBUFRX2 0x90 -#define B2056_SYN_LOGEN_CBUFRX3 0x91 -#define B2056_SYN_LOGEN_CBUFRX4 0x92 -#define B2056_SYN_LOGEN_CBUFTX1 0x93 -#define B2056_SYN_LOGEN_CBUFTX2 0x94 -#define B2056_SYN_LOGEN_CBUFTX3 0x95 -#define B2056_SYN_LOGEN_CBUFTX4 0x96 -#define B2056_SYN_LOGEN_CMOSRX1 0x97 -#define B2056_SYN_LOGEN_CMOSRX2 0x98 -#define B2056_SYN_LOGEN_CMOSRX3 0x99 -#define B2056_SYN_LOGEN_CMOSRX4 0x9A -#define B2056_SYN_LOGEN_CMOSTX1 0x9B -#define B2056_SYN_LOGEN_CMOSTX2 0x9C -#define B2056_SYN_LOGEN_CMOSTX3 0x9D -#define B2056_SYN_LOGEN_CMOSTX4 0x9E -#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL 0x9F -#define B2056_SYN_LOGEN_MIXER3_OVRVAL 0xA0 -#define B2056_SYN_LOGEN_BUF5_OVRVAL 0xA1 -#define B2056_SYN_LOGEN_BUF6_OVRVAL 0xA2 -#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL 0xA3 -#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL 0xA4 -#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL 0xA5 -#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL 0xA6 -#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL 0xA7 -#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL 0xA8 -#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL 0xA9 -#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL 0xAA -#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL 0xAB -#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL 0xAC -#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL 0xAD -#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL 0xAE -#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL 0xAF -#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL 0xB0 -#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL 0xB1 -#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL 0xB2 -#define B2056_SYN_LOGEN_ACL_WAITCNT 0xB3 -#define B2056_SYN_LOGEN_CORE_CALVALID 0xB4 -#define B2056_SYN_LOGEN_RX_CMOS_CALVALID 0xB5 -#define B2056_SYN_LOGEN_TX_CMOS_VALID 0xB6 - -#define B2056_TX_RESERVED_ADDR0 0x00 -#define B2056_TX_IDCODE 0x01 -#define B2056_TX_RESERVED_ADDR2 0x02 -#define B2056_TX_RESERVED_ADDR3 0x03 -#define B2056_TX_RESERVED_ADDR4 0x04 -#define B2056_TX_RESERVED_ADDR5 0x05 -#define B2056_TX_RESERVED_ADDR6 0x06 -#define B2056_TX_RESERVED_ADDR7 0x07 -#define B2056_TX_COM_CTRL 0x08 -#define B2056_TX_COM_PU 0x09 -#define B2056_TX_COM_OVR 0x0A -#define B2056_TX_COM_RESET 0x0B -#define B2056_TX_COM_RCAL 0x0C -#define B2056_TX_COM_RC_RXLPF 0x0D -#define B2056_TX_COM_RC_TXLPF 0x0E -#define B2056_TX_COM_RC_RXHPF 0x0F -#define B2056_TX_RESERVED_ADDR16 0x10 -#define B2056_TX_RESERVED_ADDR17 0x11 -#define B2056_TX_RESERVED_ADDR18 0x12 -#define B2056_TX_RESERVED_ADDR19 0x13 -#define B2056_TX_RESERVED_ADDR20 0x14 -#define B2056_TX_RESERVED_ADDR21 0x15 -#define B2056_TX_RESERVED_ADDR22 0x16 -#define B2056_TX_RESERVED_ADDR23 0x17 -#define B2056_TX_RESERVED_ADDR24 0x18 -#define B2056_TX_RESERVED_ADDR25 0x19 -#define B2056_TX_RESERVED_ADDR26 0x1A -#define B2056_TX_RESERVED_ADDR27 0x1B -#define B2056_TX_RESERVED_ADDR28 0x1C -#define B2056_TX_RESERVED_ADDR29 0x1D -#define B2056_TX_RESERVED_ADDR30 0x1E -#define B2056_TX_RESERVED_ADDR31 0x1F -#define B2056_TX_IQCAL_GAIN_BW 0x20 -#define B2056_TX_LOFT_FINE_I 0x21 -#define B2056_TX_LOFT_FINE_Q 0x22 -#define B2056_TX_LOFT_COARSE_I 0x23 -#define B2056_TX_LOFT_COARSE_Q 0x24 -#define B2056_TX_TX_COM_MASTER1 0x25 -#define B2056_TX_TX_COM_MASTER2 0x26 -#define B2056_TX_RXIQCAL_TXMUX 0x27 -#define B2056_TX_TX_SSI_MASTER 0x28 -#define B2056_TX_IQCAL_VCM_HG 0x29 -#define B2056_TX_IQCAL_IDAC 0x2A -#define B2056_TX_TSSI_VCM 0x2B -#define B2056_TX_TX_AMP_DET 0x2C -#define B2056_TX_TX_SSI_MUX 0x2D -#define B2056_TX_TSSIA 0x2E -#define B2056_TX_TSSIG 0x2F -#define B2056_TX_TSSI_MISC1 0x30 -#define B2056_TX_TSSI_MISC2 0x31 -#define B2056_TX_TSSI_MISC3 0x32 -#define B2056_TX_PA_SPARE1 0x33 -#define B2056_TX_PA_SPARE2 0x34 -#define B2056_TX_INTPAA_MASTER 0x35 -#define B2056_TX_INTPAA_GAIN 0x36 -#define B2056_TX_INTPAA_BOOST_TUNE 0x37 -#define B2056_TX_INTPAA_IAUX_STAT 0x38 -#define B2056_TX_INTPAA_IAUX_DYN 0x39 -#define B2056_TX_INTPAA_IMAIN_STAT 0x3A -#define B2056_TX_INTPAA_IMAIN_DYN 0x3B -#define B2056_TX_INTPAA_CASCBIAS 0x3C -#define B2056_TX_INTPAA_PASLOPE 0x3D -#define B2056_TX_INTPAA_PA_MISC 0x3E -#define B2056_TX_INTPAG_MASTER 0x3F -#define B2056_TX_INTPAG_GAIN 0x40 -#define B2056_TX_INTPAG_BOOST_TUNE 0x41 -#define B2056_TX_INTPAG_IAUX_STAT 0x42 -#define B2056_TX_INTPAG_IAUX_DYN 0x43 -#define B2056_TX_INTPAG_IMAIN_STAT 0x44 -#define B2056_TX_INTPAG_IMAIN_DYN 0x45 -#define B2056_TX_INTPAG_CASCBIAS 0x46 -#define B2056_TX_INTPAG_PASLOPE 0x47 -#define B2056_TX_INTPAG_PA_MISC 0x48 -#define B2056_TX_PADA_MASTER 0x49 -#define B2056_TX_PADA_IDAC 0x4A -#define B2056_TX_PADA_CASCBIAS 0x4B -#define B2056_TX_PADA_GAIN 0x4C -#define B2056_TX_PADA_BOOST_TUNE 0x4D -#define B2056_TX_PADA_SLOPE 0x4E -#define B2056_TX_PADG_MASTER 0x4F -#define B2056_TX_PADG_IDAC 0x50 -#define B2056_TX_PADG_CASCBIAS 0x51 -#define B2056_TX_PADG_GAIN 0x52 -#define B2056_TX_PADG_BOOST_TUNE 0x53 -#define B2056_TX_PADG_SLOPE 0x54 -#define B2056_TX_PGAA_MASTER 0x55 -#define B2056_TX_PGAA_IDAC 0x56 -#define B2056_TX_PGAA_GAIN 0x57 -#define B2056_TX_PGAA_BOOST_TUNE 0x58 -#define B2056_TX_PGAA_SLOPE 0x59 -#define B2056_TX_PGAA_MISC 0x5A -#define B2056_TX_PGAG_MASTER 0x5B -#define B2056_TX_PGAG_IDAC 0x5C -#define B2056_TX_PGAG_GAIN 0x5D -#define B2056_TX_PGAG_BOOST_TUNE 0x5E -#define B2056_TX_PGAG_SLOPE 0x5F -#define B2056_TX_PGAG_MISC 0x60 -#define B2056_TX_MIXA_MASTER 0x61 -#define B2056_TX_MIXA_BOOST_TUNE 0x62 -#define B2056_TX_MIXG 0x63 -#define B2056_TX_MIXG_BOOST_TUNE 0x64 -#define B2056_TX_BB_GM_MASTER 0x65 -#define B2056_TX_GMBB_GM 0x66 -#define B2056_TX_GMBB_IDAC 0x67 -#define B2056_TX_TXLPF_MASTER 0x68 -#define B2056_TX_TXLPF_RCCAL 0x69 -#define B2056_TX_TXLPF_RCCAL_OFF0 0x6A -#define B2056_TX_TXLPF_RCCAL_OFF1 0x6B -#define B2056_TX_TXLPF_RCCAL_OFF2 0x6C -#define B2056_TX_TXLPF_RCCAL_OFF3 0x6D -#define B2056_TX_TXLPF_RCCAL_OFF4 0x6E -#define B2056_TX_TXLPF_RCCAL_OFF5 0x6F -#define B2056_TX_TXLPF_RCCAL_OFF6 0x70 -#define B2056_TX_TXLPF_BW 0x71 -#define B2056_TX_TXLPF_GAIN 0x72 -#define B2056_TX_TXLPF_IDAC 0x73 -#define B2056_TX_TXLPF_IDAC_0 0x74 -#define B2056_TX_TXLPF_IDAC_1 0x75 -#define B2056_TX_TXLPF_IDAC_2 0x76 -#define B2056_TX_TXLPF_IDAC_3 0x77 -#define B2056_TX_TXLPF_IDAC_4 0x78 -#define B2056_TX_TXLPF_IDAC_5 0x79 -#define B2056_TX_TXLPF_IDAC_6 0x7A -#define B2056_TX_TXLPF_OPAMP_IDAC 0x7B -#define B2056_TX_TXLPF_MISC 0x7C -#define B2056_TX_TXSPARE1 0x7D -#define B2056_TX_TXSPARE2 0x7E -#define B2056_TX_TXSPARE3 0x7F -#define B2056_TX_TXSPARE4 0x80 -#define B2056_TX_TXSPARE5 0x81 -#define B2056_TX_TXSPARE6 0x82 -#define B2056_TX_TXSPARE7 0x83 -#define B2056_TX_TXSPARE8 0x84 -#define B2056_TX_TXSPARE9 0x85 -#define B2056_TX_TXSPARE10 0x86 -#define B2056_TX_TXSPARE11 0x87 -#define B2056_TX_TXSPARE12 0x88 -#define B2056_TX_TXSPARE13 0x89 -#define B2056_TX_TXSPARE14 0x8A -#define B2056_TX_TXSPARE15 0x8B -#define B2056_TX_TXSPARE16 0x8C -#define B2056_TX_STATUS_INTPA_GAIN 0x8D -#define B2056_TX_STATUS_PAD_GAIN 0x8E -#define B2056_TX_STATUS_PGA_GAIN 0x8F -#define B2056_TX_STATUS_GM_TXLPF_GAIN 0x90 -#define B2056_TX_STATUS_TXLPF_BW 0x91 -#define B2056_TX_STATUS_TXLPF_RC 0x92 -#define B2056_TX_GMBB_IDAC0 0x93 -#define B2056_TX_GMBB_IDAC1 0x94 -#define B2056_TX_GMBB_IDAC2 0x95 -#define B2056_TX_GMBB_IDAC3 0x96 -#define B2056_TX_GMBB_IDAC4 0x97 -#define B2056_TX_GMBB_IDAC5 0x98 -#define B2056_TX_GMBB_IDAC6 0x99 -#define B2056_TX_GMBB_IDAC7 0x9A - -#define B2056_RX_RESERVED_ADDR0 0x00 -#define B2056_RX_IDCODE 0x01 -#define B2056_RX_RESERVED_ADDR2 0x02 -#define B2056_RX_RESERVED_ADDR3 0x03 -#define B2056_RX_RESERVED_ADDR4 0x04 -#define B2056_RX_RESERVED_ADDR5 0x05 -#define B2056_RX_RESERVED_ADDR6 0x06 -#define B2056_RX_RESERVED_ADDR7 0x07 -#define B2056_RX_COM_CTRL 0x08 -#define B2056_RX_COM_PU 0x09 -#define B2056_RX_COM_OVR 0x0A -#define B2056_RX_COM_RESET 0x0B -#define B2056_RX_COM_RCAL 0x0C -#define B2056_RX_COM_RC_RXLPF 0x0D -#define B2056_RX_COM_RC_TXLPF 0x0E -#define B2056_RX_COM_RC_RXHPF 0x0F -#define B2056_RX_RESERVED_ADDR16 0x10 -#define B2056_RX_RESERVED_ADDR17 0x11 -#define B2056_RX_RESERVED_ADDR18 0x12 -#define B2056_RX_RESERVED_ADDR19 0x13 -#define B2056_RX_RESERVED_ADDR20 0x14 -#define B2056_RX_RESERVED_ADDR21 0x15 -#define B2056_RX_RESERVED_ADDR22 0x16 -#define B2056_RX_RESERVED_ADDR23 0x17 -#define B2056_RX_RESERVED_ADDR24 0x18 -#define B2056_RX_RESERVED_ADDR25 0x19 -#define B2056_RX_RESERVED_ADDR26 0x1A -#define B2056_RX_RESERVED_ADDR27 0x1B -#define B2056_RX_RESERVED_ADDR28 0x1C -#define B2056_RX_RESERVED_ADDR29 0x1D -#define B2056_RX_RESERVED_ADDR30 0x1E -#define B2056_RX_RESERVED_ADDR31 0x1F -#define B2056_RX_RXIQCAL_RXMUX 0x20 -#define B2056_RX_RSSI_PU 0x21 -#define B2056_RX_RSSI_SEL 0x22 -#define B2056_RX_RSSI_GAIN 0x23 -#define B2056_RX_RSSI_NB_IDAC 0x24 -#define B2056_RX_RSSI_WB2I_IDAC_1 0x25 -#define B2056_RX_RSSI_WB2I_IDAC_2 0x26 -#define B2056_RX_RSSI_WB2Q_IDAC_1 0x27 -#define B2056_RX_RSSI_WB2Q_IDAC_2 0x28 -#define B2056_RX_RSSI_POLE 0x29 -#define B2056_RX_RSSI_WB1_IDAC 0x2A -#define B2056_RX_RSSI_MISC 0x2B -#define B2056_RX_LNAA_MASTER 0x2C -#define B2056_RX_LNAA_TUNE 0x2D -#define B2056_RX_LNAA_GAIN 0x2E -#define B2056_RX_LNA_A_SLOPE 0x2F -#define B2056_RX_BIASPOLE_LNAA1_IDAC 0x30 -#define B2056_RX_LNAA2_IDAC 0x31 -#define B2056_RX_LNA1A_MISC 0x32 -#define B2056_RX_LNAG_MASTER 0x33 -#define B2056_RX_LNAG_TUNE 0x34 -#define B2056_RX_LNAG_GAIN 0x35 -#define B2056_RX_LNA_G_SLOPE 0x36 -#define B2056_RX_BIASPOLE_LNAG1_IDAC 0x37 -#define B2056_RX_LNAG2_IDAC 0x38 -#define B2056_RX_LNA1G_MISC 0x39 -#define B2056_RX_MIXA_MASTER 0x3A -#define B2056_RX_MIXA_VCM 0x3B -#define B2056_RX_MIXA_CTRLPTAT 0x3C -#define B2056_RX_MIXA_LOB_BIAS 0x3D -#define B2056_RX_MIXA_CORE_IDAC 0x3E -#define B2056_RX_MIXA_CMFB_IDAC 0x3F -#define B2056_RX_MIXA_BIAS_AUX 0x40 -#define B2056_RX_MIXA_BIAS_MAIN 0x41 -#define B2056_RX_MIXA_BIAS_MISC 0x42 -#define B2056_RX_MIXA_MAST_BIAS 0x43 -#define B2056_RX_MIXG_MASTER 0x44 -#define B2056_RX_MIXG_VCM 0x45 -#define B2056_RX_MIXG_CTRLPTAT 0x46 -#define B2056_RX_MIXG_LOB_BIAS 0x47 -#define B2056_RX_MIXG_CORE_IDAC 0x48 -#define B2056_RX_MIXG_CMFB_IDAC 0x49 -#define B2056_RX_MIXG_BIAS_AUX 0x4A -#define B2056_RX_MIXG_BIAS_MAIN 0x4B -#define B2056_RX_MIXG_BIAS_MISC 0x4C -#define B2056_RX_MIXG_MAST_BIAS 0x4D -#define B2056_RX_TIA_MASTER 0x4E -#define B2056_RX_TIA_IOPAMP 0x4F -#define B2056_RX_TIA_QOPAMP 0x50 -#define B2056_RX_TIA_IMISC 0x51 -#define B2056_RX_TIA_QMISC 0x52 -#define B2056_RX_TIA_GAIN 0x53 -#define B2056_RX_TIA_SPARE1 0x54 -#define B2056_RX_TIA_SPARE2 0x55 -#define B2056_RX_BB_LPF_MASTER 0x56 -#define B2056_RX_AACI_MASTER 0x57 -#define B2056_RX_RXLPF_IDAC 0x58 -#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ 0x59 -#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ 0x5A -#define B2056_RX_RXLPF_BIAS_DCCANCEL 0x5B -#define B2056_RX_RXLPF_OUTVCM 0x5C -#define B2056_RX_RXLPF_INVCM_BODY 0x5D -#define B2056_RX_RXLPF_CC_OP 0x5E -#define B2056_RX_RXLPF_GAIN 0x5F -#define B2056_RX_RXLPF_Q_BW 0x60 -#define B2056_RX_RXLPF_HP_CORNER_BW 0x61 -#define B2056_RX_RXLPF_RCCAL_HPC 0x62 -#define B2056_RX_RXHPF_OFF0 0x63 -#define B2056_RX_RXHPF_OFF1 0x64 -#define B2056_RX_RXHPF_OFF2 0x65 -#define B2056_RX_RXHPF_OFF3 0x66 -#define B2056_RX_RXHPF_OFF4 0x67 -#define B2056_RX_RXHPF_OFF5 0x68 -#define B2056_RX_RXHPF_OFF6 0x69 -#define B2056_RX_RXHPF_OFF7 0x6A -#define B2056_RX_RXLPF_RCCAL_LPC 0x6B -#define B2056_RX_RXLPF_OFF_0 0x6C -#define B2056_RX_RXLPF_OFF_1 0x6D -#define B2056_RX_RXLPF_OFF_2 0x6E -#define B2056_RX_RXLPF_OFF_3 0x6F -#define B2056_RX_RXLPF_OFF_4 0x70 -#define B2056_RX_UNUSED 0x71 -#define B2056_RX_VGA_MASTER 0x72 -#define B2056_RX_VGA_BIAS 0x73 -#define B2056_RX_VGA_BIAS_DCCANCEL 0x74 -#define B2056_RX_VGA_GAIN 0x75 -#define B2056_RX_VGA_HP_CORNER_BW 0x76 -#define B2056_RX_VGABUF_BIAS 0x77 -#define B2056_RX_VGABUF_GAIN_BW 0x78 -#define B2056_RX_TXFBMIX_A 0x79 -#define B2056_RX_TXFBMIX_G 0x7A -#define B2056_RX_RXSPARE1 0x7B -#define B2056_RX_RXSPARE2 0x7C -#define B2056_RX_RXSPARE3 0x7D -#define B2056_RX_RXSPARE4 0x7E -#define B2056_RX_RXSPARE5 0x7F -#define B2056_RX_RXSPARE6 0x80 -#define B2056_RX_RXSPARE7 0x81 -#define B2056_RX_RXSPARE8 0x82 -#define B2056_RX_RXSPARE9 0x83 -#define B2056_RX_RXSPARE10 0x84 -#define B2056_RX_RXSPARE11 0x85 -#define B2056_RX_RXSPARE12 0x86 -#define B2056_RX_RXSPARE13 0x87 -#define B2056_RX_RXSPARE14 0x88 -#define B2056_RX_RXSPARE15 0x89 -#define B2056_RX_RXSPARE16 0x8A -#define B2056_RX_STATUS_LNAA_GAIN 0x8B -#define B2056_RX_STATUS_LNAG_GAIN 0x8C -#define B2056_RX_STATUS_MIXTIA_GAIN 0x8D -#define B2056_RX_STATUS_RXLPF_GAIN 0x8E -#define B2056_RX_STATUS_VGA_BUF_GAIN 0x8F -#define B2056_RX_STATUS_RXLPF_Q 0x90 -#define B2056_RX_STATUS_RXLPF_BUF_BW 0x91 -#define B2056_RX_STATUS_RXLPF_VGA_HPC 0x92 -#define B2056_RX_STATUS_RXLPF_RC 0x93 -#define B2056_RX_STATUS_HPC_RC 0x94 - -#define B2056_LNA1_A_PU 0x01 -#define B2056_LNA2_A_PU 0x02 -#define B2056_LNA1_G_PU 0x01 -#define B2056_LNA2_G_PU 0x02 -#define B2056_MIXA_PU_I 0x01 -#define B2056_MIXA_PU_Q 0x02 -#define B2056_MIXA_PU_GM 0x10 -#define B2056_MIXG_PU_I 0x01 -#define B2056_MIXG_PU_Q 0x02 -#define B2056_MIXG_PU_GM 0x10 -#define B2056_TIA_PU 0x01 -#define B2056_BB_LPF_PU 0x20 -#define B2056_W1_PU 0x02 -#define B2056_W2_PU 0x04 -#define B2056_NB_PU 0x08 -#define B2056_RSSI_W1_SEL 0x02 -#define B2056_RSSI_W2_SEL 0x04 -#define B2056_RSSI_NB_SEL 0x08 -#define B2056_VCM_MASK 0x1C -#define B2056_RSSI_VCM_SHIFT 0x02 - -struct b43_nphy_channeltab_entry_rev3 { - /* The channel frequency in MHz */ - u16 freq; - /* Radio register values on channelswitch */ - u8 radio_syn_pll_vcocal1; - u8 radio_syn_pll_vcocal2; - u8 radio_syn_pll_refdiv; - u8 radio_syn_pll_mmd2; - u8 radio_syn_pll_mmd1; - u8 radio_syn_pll_loopfilter1; - u8 radio_syn_pll_loopfilter2; - u8 radio_syn_pll_loopfilter3; - u8 radio_syn_pll_loopfilter4; - u8 radio_syn_pll_loopfilter5; - u8 radio_syn_reserved_addr27; - u8 radio_syn_reserved_addr28; - u8 radio_syn_reserved_addr29; - u8 radio_syn_logen_vcobuf1; - u8 radio_syn_logen_mixer2; - u8 radio_syn_logen_buf3; - u8 radio_syn_logen_buf4; - u8 radio_rx0_lnaa_tune; - u8 radio_rx0_lnag_tune; - u8 radio_tx0_intpaa_boost_tune; - u8 radio_tx0_intpag_boost_tune; - u8 radio_tx0_pada_boost_tune; - u8 radio_tx0_padg_boost_tune; - u8 radio_tx0_pgaa_boost_tune; - u8 radio_tx0_pgag_boost_tune; - u8 radio_tx0_mixa_boost_tune; - u8 radio_tx0_mixg_boost_tune; - u8 radio_rx1_lnaa_tune; - u8 radio_rx1_lnag_tune; - u8 radio_tx1_intpaa_boost_tune; - u8 radio_tx1_intpag_boost_tune; - u8 radio_tx1_pada_boost_tune; - u8 radio_tx1_padg_boost_tune; - u8 radio_tx1_pgaa_boost_tune; - u8 radio_tx1_pgag_boost_tune; - u8 radio_tx1_mixa_boost_tune; - u8 radio_tx1_mixg_boost_tune; - /* PHY register values on channelswitch */ - struct b43_phy_n_sfo_cfg phy_regs; -}; - -void b2056_upload_inittabs(struct b43_wldev *dev, - bool ghz5, bool ignore_uploadflag); -void b2056_upload_syn_pll_cp2(struct b43_wldev *dev, bool ghz5); - -/* Get the NPHY Channel Switch Table entry for a channel. - * Returns NULL on failure to find an entry. */ -const struct b43_nphy_channeltab_entry_rev3 * -b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq); - -#endif /* B43_RADIO_2056_H_ */ diff --git a/drivers/net/wireless/b43/radio_2057.c b/drivers/net/wireless/b43/radio_2057.c deleted file mode 100644 index ff1e026a6..000000000 --- a/drivers/net/wireless/b43/radio_2057.c +++ /dev/null @@ -1,637 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n 2057 radio device data tables - - Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "radio_2057.h" -#include "phy_common.h" - -static u16 r2057_rev4_init[][2] = { - { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, - { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff }, - { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 }, - { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c }, - { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 }, - { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c }, - { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, - { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, - { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, - { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, - { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, -}; - -static u16 r2057_rev5_init[][2] = { - { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 }, - { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, - { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, - { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, - { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 }, - { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f }, - { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, - { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, - { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, - { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, - { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, { 0x1C2, 0x80 }, -}; - -static u16 r2057_rev5a_init[][2] = { - { 0x00, 0x15 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x23, 0x6 }, - { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, - { 0x59, 0x88 }, { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, - { 0x64, 0x0f }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, - { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, { 0xE1, 0x20 }, - { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0x106, 0x01 }, { 0x116, 0x3f }, - { 0x117, 0x36 }, { 0x126, 0x20 }, { 0x14E, 0x01 }, { 0x15E, 0x00 }, - { 0x15F, 0x00 }, { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, - { 0x163, 0x00 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, - { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, - { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, { 0x1B7, 0x0c }, { 0x1C1, 0x01 }, - { 0x1C2, 0x80 }, -}; - -static u16 r2057_rev7_init[][2] = { - { 0x00, 0x00 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 }, - { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 }, - { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x13 }, - { 0x66, 0xee }, { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, - { 0x7C, 0x14 }, { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, - { 0x92, 0x36 }, { 0xA1, 0x20 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, - { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x13 }, { 0xEB, 0xee }, - { 0xF3, 0x58 }, { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x14 }, - { 0x102, 0xee }, { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, - { 0x126, 0x20 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 }, - { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 }, - { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, - { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, - { 0x1B7, 0x05 }, { 0x1C2, 0xa0 }, -}; - -/* TODO: Which devices should use it? -static u16 r2057_rev8_init[][2] = { - { 0x00, 0x08 }, { 0x01, 0x57 }, { 0x02, 0x20 }, { 0x31, 0x00 }, - { 0x32, 0x00 }, { 0x33, 0x00 }, { 0x51, 0x70 }, { 0x59, 0x88 }, - { 0x5C, 0x20 }, { 0x62, 0x33 }, { 0x63, 0x0f }, { 0x64, 0x0f }, - { 0x6E, 0x58 }, { 0x75, 0x13 }, { 0x7B, 0x13 }, { 0x7C, 0x0f }, - { 0x7D, 0xee }, { 0x81, 0x01 }, { 0x91, 0x3f }, { 0x92, 0x36 }, - { 0xA1, 0x20 }, { 0xC9, 0x01 }, { 0xD6, 0x70 }, { 0xDE, 0x88 }, - { 0xE1, 0x20 }, { 0xE8, 0x0f }, { 0xE9, 0x0f }, { 0xF3, 0x58 }, - { 0xFA, 0x13 }, { 0x100, 0x13 }, { 0x101, 0x0f }, { 0x102, 0xee }, - { 0x106, 0x01 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x126, 0x20 }, - { 0x14E, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, { 0x160, 0x00 }, - { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, { 0x16A, 0x00 }, - { 0x16B, 0x00 }, { 0x16C, 0x00 }, { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, - { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, { 0x1AB, 0x00 }, { 0x1AC, 0x00 }, - { 0x1B7, 0x05 }, { 0x1C2, 0xa0 }, -}; -*/ - -/* Extracted from MMIO dump of 6.30.223.141 */ -static u16 r2057_rev9_init[][2] = { - { 0x27, 0x1f }, { 0x28, 0x0a }, { 0x29, 0x2f }, { 0x42, 0x1f }, - { 0x48, 0x3f }, { 0x5c, 0x41 }, { 0x63, 0x14 }, { 0x64, 0x12 }, - { 0x66, 0xff }, { 0x74, 0xa3 }, { 0x7b, 0x14 }, { 0x7c, 0x14 }, - { 0x7d, 0xee }, { 0x86, 0xc0 }, { 0xc4, 0x10 }, { 0xc9, 0x01 }, - { 0xe1, 0x41 }, { 0xe8, 0x14 }, { 0xe9, 0x12 }, { 0xeb, 0xff }, - { 0xf5, 0x0a }, { 0xf8, 0x09 }, { 0xf9, 0xa3 }, { 0x100, 0x14 }, - { 0x101, 0x10 }, { 0x102, 0xee }, { 0x10b, 0xc0 }, { 0x149, 0x10 }, - { 0x14e, 0x01 }, { 0x1b7, 0x05 }, { 0x1c2, 0xa0 }, -}; - -/* Extracted from MMIO dump of 6.30.223.248 */ -static u16 r2057_rev14_init[][2] = { - { 0x011, 0xfc }, { 0x030, 0x24 }, { 0x040, 0x1c }, { 0x082, 0x08 }, - { 0x0b4, 0x44 }, { 0x0c8, 0x01 }, { 0x0c9, 0x01 }, { 0x107, 0x08 }, - { 0x14d, 0x01 }, { 0x14e, 0x01 }, { 0x1af, 0x40 }, { 0x1b0, 0x40 }, - { 0x1cc, 0x01 }, { 0x1cf, 0x10 }, { 0x1d0, 0x0f }, { 0x1d3, 0x10 }, - { 0x1d4, 0x0f }, -}; - -#define RADIOREGS7(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ - r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ - r20, r21, r22, r23, r24, r25, r26, r27) \ - .radio_vcocal_countval0 = r00, \ - .radio_vcocal_countval1 = r01, \ - .radio_rfpll_refmaster_sparextalsize = r02, \ - .radio_rfpll_loopfilter_r1 = r03, \ - .radio_rfpll_loopfilter_c2 = r04, \ - .radio_rfpll_loopfilter_c1 = r05, \ - .radio_cp_kpd_idac = r06, \ - .radio_rfpll_mmd0 = r07, \ - .radio_rfpll_mmd1 = r08, \ - .radio_vcobuf_tune = r09, \ - .radio_logen_mx2g_tune = r10, \ - .radio_logen_mx5g_tune = r11, \ - .radio_logen_indbuf2g_tune = r12, \ - .radio_logen_indbuf5g_tune = r13, \ - .radio_txmix2g_tune_boost_pu_core0 = r14, \ - .radio_pad2g_tune_pus_core0 = r15, \ - .radio_pga_boost_tune_core0 = r16, \ - .radio_txmix5g_boost_tune_core0 = r17, \ - .radio_pad5g_tune_misc_pus_core0 = r18, \ - .radio_lna2g_tune_core0 = r19, \ - .radio_lna5g_tune_core0 = r20, \ - .radio_txmix2g_tune_boost_pu_core1 = r21, \ - .radio_pad2g_tune_pus_core1 = r22, \ - .radio_pga_boost_tune_core1 = r23, \ - .radio_txmix5g_boost_tune_core1 = r24, \ - .radio_pad5g_tune_misc_pus_core1 = r25, \ - .radio_lna2g_tune_core1 = r26, \ - .radio_lna5g_tune_core1 = r27 - -#define RADIOREGS7_2G(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ - r10, r11, r12, r13, r14, r15, r16, r17) \ - .radio_vcocal_countval0 = r00, \ - .radio_vcocal_countval1 = r01, \ - .radio_rfpll_refmaster_sparextalsize = r02, \ - .radio_rfpll_loopfilter_r1 = r03, \ - .radio_rfpll_loopfilter_c2 = r04, \ - .radio_rfpll_loopfilter_c1 = r05, \ - .radio_cp_kpd_idac = r06, \ - .radio_rfpll_mmd0 = r07, \ - .radio_rfpll_mmd1 = r08, \ - .radio_vcobuf_tune = r09, \ - .radio_logen_mx2g_tune = r10, \ - .radio_logen_indbuf2g_tune = r11, \ - .radio_txmix2g_tune_boost_pu_core0 = r12, \ - .radio_pad2g_tune_pus_core0 = r13, \ - .radio_lna2g_tune_core0 = r14, \ - .radio_txmix2g_tune_boost_pu_core1 = r15, \ - .radio_pad2g_tune_pus_core1 = r16, \ - .radio_lna2g_tune_core1 = r17 - -#define PHYREGS(r0, r1, r2, r3, r4, r5) \ - .phy_regs.phy_bw1a = r0, \ - .phy_regs.phy_bw2 = r1, \ - .phy_regs.phy_bw3 = r2, \ - .phy_regs.phy_bw4 = r3, \ - .phy_regs.phy_bw5 = r4, \ - .phy_regs.phy_bw6 = r5 - -/* Copied from brcmsmac (5.75.11): chan_info_nphyrev8_2057_rev5 */ -static const struct b43_nphy_chantabent_rev7_2g b43_nphy_chantab_phy_rev8_radio_rev5[] = { - { - .freq = 2412, - RADIOREGS7_2G(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, - 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, - 0x03, 0xff), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { - .freq = 2417, - RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, - 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xff, 0x61, - 0x03, 0xff), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { - .freq = 2422, - RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, - 0x09, 0x0d, 0x08, 0x0e, 0x61, 0x03, 0xef, 0x61, - 0x03, 0xef), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { - .freq = 2427, - RADIOREGS7_2G(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, - 0x09, 0x0c, 0x08, 0x0e, 0x61, 0x03, 0xdf, 0x61, - 0x03, 0xdf), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { - .freq = 2432, - RADIOREGS7_2G(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, - 0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xcf, 0x61, - 0x03, 0xcf), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { - .freq = 2437, - RADIOREGS7_2G(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, - 0x09, 0x0c, 0x07, 0x0d, 0x61, 0x03, 0xbf, 0x61, - 0x03, 0xbf), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { - .freq = 2442, - RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, - 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0xaf, 0x61, - 0x03, 0xaf), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { - .freq = 2447, - RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, - 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x9f, 0x61, - 0x03, 0x9f), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { - .freq = 2452, - RADIOREGS7_2G(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, - 0x09, 0x0b, 0x07, 0x0d, 0x61, 0x03, 0x8f, 0x61, - 0x03, 0x8f), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { - .freq = 2457, - RADIOREGS7_2G(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, - 0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x7f, 0x61, - 0x03, 0x7f), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { - .freq = 2462, - RADIOREGS7_2G(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, - 0x09, 0x0b, 0x07, 0x0c, 0x61, 0x03, 0x6f, 0x61, - 0x03, 0x6f), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { - .freq = 2467, - RADIOREGS7_2G(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, - 0x09, 0x0b, 0x06, 0x0c, 0x61, 0x03, 0x5f, 0x61, - 0x03, 0x5f), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { - .freq = 2472, - RADIOREGS7_2G(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, - 0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x4f, 0x61, - 0x03, 0x4f), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { - .freq = 2484, - RADIOREGS7_2G(0x78, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xb4, - 0x09, 0x0a, 0x06, 0x0b, 0x61, 0x03, 0x3f, 0x61, - 0x03, 0x3f), - PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424), - } -}; - -/* Extracted from MMIO dump of 6.30.223.248 */ -static const struct b43_nphy_chantabent_rev7_2g b43_nphy_chantab_phy_rev17_radio_rev14[] = { - { - .freq = 2412, - RADIOREGS7_2G(0x48, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x6c, - 0x09, 0x0d, 0x09, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { - .freq = 2417, - RADIOREGS7_2G(0x4b, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x71, - 0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { - .freq = 2422, - RADIOREGS7_2G(0x4e, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x76, - 0x09, 0x0d, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { - .freq = 2427, - RADIOREGS7_2G(0x52, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x7b, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { - .freq = 2432, - RADIOREGS7_2G(0x55, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x80, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { - .freq = 2437, - RADIOREGS7_2G(0x58, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x85, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x53, 0xff, 0x21, - 0x53, 0xff), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { - .freq = 2442, - RADIOREGS7_2G(0x5c, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8a, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, - 0x43, 0xff), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { - .freq = 2447, - RADIOREGS7_2G(0x5f, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x8f, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, - 0x43, 0xff), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { - .freq = 2452, - RADIOREGS7_2G(0x62, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x94, - 0x09, 0x0c, 0x08, 0x03, 0x21, 0x43, 0xff, 0x21, - 0x43, 0xff), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { - .freq = 2457, - RADIOREGS7_2G(0x66, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x99, - 0x09, 0x0b, 0x07, 0x03, 0x21, 0x43, 0xff, 0x21, - 0x43, 0xff), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { - .freq = 2462, - RADIOREGS7_2G(0x69, 0x16, 0x30, 0x2b, 0x1f, 0x1f, 0x30, 0x9e, - 0x09, 0x0b, 0x07, 0x03, 0x01, 0x43, 0xff, 0x01, - 0x43, 0xff), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, -}; - -/* Extracted from MMIO dump of 6.30.223.141 */ -static const struct b43_nphy_chantabent_rev7 b43_nphy_chantab_phy_rev16_radio_rev9[] = { - { - .freq = 2412, - RADIOREGS7(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, - 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { - .freq = 2417, - RADIOREGS7(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, - 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { - .freq = 2422, - RADIOREGS7(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, - 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { - .freq = 2427, - RADIOREGS7(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, - 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { - .freq = 2432, - RADIOREGS7(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, - 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { - .freq = 2437, - RADIOREGS7(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, - 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { - .freq = 2442, - RADIOREGS7(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { - .freq = 2447, - RADIOREGS7(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { - .freq = 2452, - RADIOREGS7(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { - .freq = 2457, - RADIOREGS7(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, - 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { - .freq = 2462, - RADIOREGS7(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, - 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x41, 0x63, - 0x00, 0x00, 0x00, 0xf0, 0x00, 0x41, 0x63, 0x00, - 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { - .freq = 5180, - RADIOREGS7(0xbe, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x06, - 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, - 0x9f, 0x2f, 0xa3, 0x00, 0xfc, 0x00, 0x00, 0x4f, - 0x3a, 0x83, 0x00, 0xfc), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { - .freq = 5200, - RADIOREGS7(0xc5, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x08, - 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, - 0x7f, 0x2f, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x4c, - 0x4a, 0x83, 0x00, 0xf8), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { - .freq = 5220, - RADIOREGS7(0xcc, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0a, - 0x02, 0x0e, 0x00, 0x0e, 0x00, 0x9e, 0x00, 0x00, - 0x6d, 0x3d, 0x83, 0x00, 0xf8, 0x00, 0x00, 0x2d, - 0x2a, 0x73, 0x00, 0xf8), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { - .freq = 5240, - RADIOREGS7(0xd2, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0c, - 0x02, 0x0d, 0x00, 0x0d, 0x00, 0x8d, 0x00, 0x00, - 0x4d, 0x1c, 0x73, 0x00, 0xf8, 0x00, 0x00, 0x4d, - 0x2b, 0x73, 0x00, 0xf8), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { - .freq = 5745, - RADIOREGS7(0x7b, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x7d, - 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, - 0x08, 0x03, 0x03, 0x00, 0x30, 0x00, 0x00, 0x06, - 0x02, 0x03, 0x00, 0x30), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { - .freq = 5765, - RADIOREGS7(0x81, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x81, - 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, - 0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, - 0x02, 0x03, 0x00, 0x00), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { - .freq = 5785, - RADIOREGS7(0x88, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x85, - 0x04, 0x08, 0x00, 0x06, 0x00, 0x15, 0x00, 0x00, - 0x08, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x05, - 0x21, 0x03, 0x00, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { - .freq = 5805, - RADIOREGS7(0x8f, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x89, - 0x04, 0x07, 0x00, 0x06, 0x00, 0x04, 0x00, 0x00, - 0x06, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x03, 0x00, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { - .freq = 5825, - RADIOREGS7(0x95, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x8d, - 0x04, 0x07, 0x00, 0x05, 0x00, 0x03, 0x00, 0x00, - 0x05, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x03, 0x00, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, -}; - -void r2057_upload_inittabs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 *table = NULL; - u16 size, i; - - switch (phy->rev) { - case 7: - table = r2057_rev4_init[0]; - size = ARRAY_SIZE(r2057_rev4_init); - break; - case 8: - if (phy->radio_rev == 5) { - table = r2057_rev5_init[0]; - size = ARRAY_SIZE(r2057_rev5_init); - } else if (phy->radio_rev == 7) { - table = r2057_rev7_init[0]; - size = ARRAY_SIZE(r2057_rev7_init); - } - break; - case 9: - if (phy->radio_rev == 5) { - table = r2057_rev5a_init[0]; - size = ARRAY_SIZE(r2057_rev5a_init); - } - break; - case 16: - if (phy->radio_rev == 9) { - table = r2057_rev9_init[0]; - size = ARRAY_SIZE(r2057_rev9_init); - } - break; - case 17: - if (phy->radio_rev == 14) { - table = r2057_rev14_init[0]; - size = ARRAY_SIZE(r2057_rev14_init); - } - break; - } - - B43_WARN_ON(!table); - - if (table) { - for (i = 0; i < size; i++, table += 2) - b43_radio_write(dev, table[0], table[1]); - } -} - -void r2057_get_chantabent_rev7(struct b43_wldev *dev, u16 freq, - const struct b43_nphy_chantabent_rev7 **tabent_r7, - const struct b43_nphy_chantabent_rev7_2g **tabent_r7_2g) -{ - struct b43_phy *phy = &dev->phy; - const struct b43_nphy_chantabent_rev7 *e_r7 = NULL; - const struct b43_nphy_chantabent_rev7_2g *e_r7_2g = NULL; - unsigned int len, i; - - *tabent_r7 = NULL; - *tabent_r7_2g = NULL; - - switch (phy->rev) { - case 8: - if (phy->radio_rev == 5) { - e_r7_2g = b43_nphy_chantab_phy_rev8_radio_rev5; - len = ARRAY_SIZE(b43_nphy_chantab_phy_rev8_radio_rev5); - } - break; - case 16: - if (phy->radio_rev == 9) { - e_r7 = b43_nphy_chantab_phy_rev16_radio_rev9; - len = ARRAY_SIZE(b43_nphy_chantab_phy_rev16_radio_rev9); - } - break; - case 17: - if (phy->radio_rev == 14) { - e_r7_2g = b43_nphy_chantab_phy_rev17_radio_rev14; - len = ARRAY_SIZE(b43_nphy_chantab_phy_rev17_radio_rev14); - } - break; - default: - break; - } - - if (e_r7) { - for (i = 0; i < len; i++, e_r7++) { - if (e_r7->freq == freq) { - *tabent_r7 = e_r7; - return; - } - } - } else if (e_r7_2g) { - for (i = 0; i < len; i++, e_r7_2g++) { - if (e_r7_2g->freq == freq) { - *tabent_r7_2g = e_r7_2g; - return; - } - } - } else { - B43_WARN_ON(1); - } -} diff --git a/drivers/net/wireless/b43/radio_2057.h b/drivers/net/wireless/b43/radio_2057.h deleted file mode 100644 index 220d08023..000000000 --- a/drivers/net/wireless/b43/radio_2057.h +++ /dev/null @@ -1,506 +0,0 @@ -#ifndef B43_RADIO_2057_H_ -#define B43_RADIO_2057_H_ - -#include <linux/types.h> - -#include "tables_nphy.h" - -#define R2057_DACBUF_VINCM_CORE0 0x000 -#define R2057_IDCODE 0x001 -#define R2057_RCCAL_MASTER 0x002 -#define R2057_RCCAL_CAP_SIZE 0x003 -#define R2057_RCAL_CONFIG 0x004 -#define R2057_GPAIO_CONFIG 0x005 -#define R2057_GPAIO_SEL1 0x006 -#define R2057_GPAIO_SEL0 0x007 -#define R2057_CLPO_CONFIG 0x008 -#define R2057_BANDGAP_CONFIG 0x009 -#define R2057_BANDGAP_RCAL_TRIM 0x00a -#define R2057_AFEREG_CONFIG 0x00b -#define R2057_TEMPSENSE_CONFIG 0x00c -#define R2057_XTAL_CONFIG1 0x00d -#define R2057_XTAL_ICORE_SIZE 0x00e -#define R2057_XTAL_BUF_SIZE 0x00f -#define R2057_XTAL_PULLCAP_SIZE 0x010 -#define R2057_RFPLL_MASTER 0x011 -#define R2057_VCOMONITOR_VTH_L 0x012 -#define R2057_VCOMONITOR_VTH_H 0x013 -#define R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT 0x014 -#define R2057_VCO_VARCSIZE_IDAC 0x015 -#define R2057_VCOCAL_COUNTVAL0 0x016 -#define R2057_VCOCAL_COUNTVAL1 0x017 -#define R2057_VCOCAL_INTCLK_COUNT 0x018 -#define R2057_VCOCAL_MASTER 0x019 -#define R2057_VCOCAL_NUMCAPCHANGE 0x01a -#define R2057_VCOCAL_WINSIZE 0x01b -#define R2057_VCOCAL_DELAY_AFTER_REFRESH 0x01c -#define R2057_VCOCAL_DELAY_AFTER_CLOSELOOP 0x01d -#define R2057_VCOCAL_DELAY_AFTER_OPENLOOP 0x01e -#define R2057_VCOCAL_DELAY_BEFORE_OPENLOOP 0x01f -#define R2057_VCO_FORCECAPEN_FORCECAP1 0x020 -#define R2057_VCO_FORCECAP0 0x021 -#define R2057_RFPLL_REFMASTER_SPAREXTALSIZE 0x022 -#define R2057_RFPLL_PFD_RESET_PW 0x023 -#define R2057_RFPLL_LOOPFILTER_R2 0x024 -#define R2057_RFPLL_LOOPFILTER_R1 0x025 -#define R2057_RFPLL_LOOPFILTER_C3 0x026 -#define R2057_RFPLL_LOOPFILTER_C2 0x027 -#define R2057_RFPLL_LOOPFILTER_C1 0x028 -#define R2057_CP_KPD_IDAC 0x029 -#define R2057_RFPLL_IDACS 0x02a -#define R2057_RFPLL_MISC_EN 0x02b -#define R2057_RFPLL_MMD0 0x02c -#define R2057_RFPLL_MMD1 0x02d -#define R2057_RFPLL_MISC_CAL_RESETN 0x02e -#define R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES 0x02f -#define R2057_VCO_ALCREF_BBPLLXTAL_SIZE 0x030 -#define R2057_VCOCAL_READCAP0 0x031 -#define R2057_VCOCAL_READCAP1 0x032 -#define R2057_VCOCAL_STATUS 0x033 -#define R2057_LOGEN_PUS 0x034 -#define R2057_LOGEN_PTAT_RESETS 0x035 -#define R2057_VCOBUF_IDACS 0x036 -#define R2057_VCOBUF_TUNE 0x037 -#define R2057_CMOSBUF_TX2GQ_IDACS 0x038 -#define R2057_CMOSBUF_TX2GI_IDACS 0x039 -#define R2057_CMOSBUF_TX5GQ_IDACS 0x03a -#define R2057_CMOSBUF_TX5GI_IDACS 0x03b -#define R2057_CMOSBUF_RX2GQ_IDACS 0x03c -#define R2057_CMOSBUF_RX2GI_IDACS 0x03d -#define R2057_CMOSBUF_RX5GQ_IDACS 0x03e -#define R2057_CMOSBUF_RX5GI_IDACS 0x03f -#define R2057_LOGEN_MX2G_IDACS 0x040 -#define R2057_LOGEN_MX2G_TUNE 0x041 -#define R2057_LOGEN_MX5G_IDACS 0x042 -#define R2057_LOGEN_MX5G_TUNE 0x043 -#define R2057_LOGEN_MX5G_RCCR 0x044 -#define R2057_LOGEN_INDBUF2G_IDAC 0x045 -#define R2057_LOGEN_INDBUF2G_IBOOST 0x046 -#define R2057_LOGEN_INDBUF2G_TUNE 0x047 -#define R2057_LOGEN_INDBUF5G_IDAC 0x048 -#define R2057_LOGEN_INDBUF5G_IBOOST 0x049 -#define R2057_LOGEN_INDBUF5G_TUNE 0x04a -#define R2057_CMOSBUF_TX_RCCR 0x04b -#define R2057_CMOSBUF_RX_RCCR 0x04c -#define R2057_LOGEN_SEL_PKDET 0x04d -#define R2057_CMOSBUF_SHAREIQ_PTAT 0x04e - -/* MISC core 0 */ -#define R2057_RXTXBIAS_CONFIG_CORE0 0x04f -#define R2057_TXGM_TXRF_PUS_CORE0 0x050 -#define R2057_TXGM_IDAC_BLEED_CORE0 0x051 -#define R2057_TXGM_GAIN_CORE0 0x056 -#define R2057_TXGM2G_PKDET_PUS_CORE0 0x057 -#define R2057_PAD2G_PTATS_CORE0 0x058 -#define R2057_PAD2G_IDACS_CORE0 0x059 -#define R2057_PAD2G_BOOST_PU_CORE0 0x05a -#define R2057_PAD2G_CASCV_GAIN_CORE0 0x05b -#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE0 0x05c -#define R2057_TXMIX2G_LODC_CORE0 0x05d -#define R2057_PAD2G_TUNE_PUS_CORE0 0x05e -#define R2057_IPA2G_GAIN_CORE0 0x05f -#define R2057_TSSI2G_SPARE1_CORE0 0x060 -#define R2057_TSSI2G_SPARE2_CORE0 0x061 -#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0 0x062 -#define R2057_IPA2G_IMAIN_CORE0 0x063 -#define R2057_IPA2G_CASCONV_CORE0 0x064 -#define R2057_IPA2G_CASCOFFV_CORE0 0x065 -#define R2057_IPA2G_BIAS_FILTER_CORE0 0x066 -#define R2057_TX5G_PKDET_CORE0 0x069 -#define R2057_PGA_PTAT_TXGM5G_PU_CORE0 0x06a -#define R2057_PAD5G_PTATS1_CORE0 0x06b -#define R2057_PAD5G_CLASS_PTATS2_CORE0 0x06c -#define R2057_PGA_BOOSTPTAT_IMAIN_CORE0 0x06d -#define R2057_PAD5G_CASCV_IMAIN_CORE0 0x06e -#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0 0x06f -#define R2057_PGA_BOOST_TUNE_CORE0 0x070 -#define R2057_PGA_GAIN_CORE0 0x071 -#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0 0x072 -#define R2057_TXMIX5G_BOOST_TUNE_CORE0 0x073 -#define R2057_PAD5G_TUNE_MISC_PUS_CORE0 0x074 -#define R2057_IPA5G_IAUX_CORE0 0x075 -#define R2057_IPA5G_GAIN_CORE0 0x076 -#define R2057_TSSI5G_SPARE1_CORE0 0x077 -#define R2057_TSSI5G_SPARE2_CORE0 0x078 -#define R2057_IPA5G_CASCOFFV_PU_CORE0 0x079 -#define R2057_IPA5G_PTAT_CORE0 0x07a -#define R2057_IPA5G_IMAIN_CORE0 0x07b -#define R2057_IPA5G_CASCONV_CORE0 0x07c -#define R2057_IPA5G_BIAS_FILTER_CORE0 0x07d -#define R2057_PAD_BIAS_FILTER_BWS_CORE0 0x080 -#define R2057_TR2G_CONFIG1_CORE0_NU 0x081 -#define R2057_TR2G_CONFIG2_CORE0_NU 0x082 -#define R2057_LNA5G_RFEN_CORE0 0x083 -#define R2057_TR5G_CONFIG2_CORE0_NU 0x084 -#define R2057_RXRFBIAS_IBOOST_PU_CORE0 0x085 -#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0 0x086 -#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0 0x087 -#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE0 0x088 -#define R2057_RXMIX_CMFBITAIL_PU_CORE0 0x089 -#define R2057_LNA2_IMAIN_PTAT_PU_CORE0 0x08a -#define R2057_LNA2_IAUX_PTAT_CORE0 0x08b -#define R2057_LNA1_IMAIN_PTAT_PU_CORE0 0x08c -#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE0 0x08d -#define R2057_RXRFBIAS_BANDSEL_CORE0 0x08e -#define R2057_TIA_CONFIG_CORE0 0x08f -#define R2057_TIA_IQGAIN_CORE0 0x090 -#define R2057_TIA_IBIAS2_CORE0 0x091 -#define R2057_TIA_IBIAS1_CORE0 0x092 -#define R2057_TIA_SPARE_Q_CORE0 0x093 -#define R2057_TIA_SPARE_I_CORE0 0x094 -#define R2057_RXMIX2G_PUS_CORE0 0x095 -#define R2057_RXMIX2G_VCMREFS_CORE0 0x096 -#define R2057_RXMIX2G_LODC_QI_CORE0 0x097 -#define R2057_W12G_BW_LNA2G_PUS_CORE0 0x098 -#define R2057_LNA2G_GAIN_CORE0 0x099 -#define R2057_LNA2G_TUNE_CORE0 0x09a -#define R2057_RXMIX5G_PUS_CORE0 0x09b -#define R2057_RXMIX5G_VCMREFS_CORE0 0x09c -#define R2057_RXMIX5G_LODC_QI_CORE0 0x09d -#define R2057_W15G_BW_LNA5G_PUS_CORE0 0x09e -#define R2057_LNA5G_GAIN_CORE0 0x09f -#define R2057_LNA5G_TUNE_CORE0 0x0a0 -#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE0 0x0a1 -#define R2057_RXBB_BIAS_MASTER_CORE0 0x0a2 -#define R2057_RXBB_VGABUF_IDACS_CORE0 0x0a3 -#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0 0x0a4 -#define R2057_TXBUF_VINCM_CORE0 0x0a5 -#define R2057_TXBUF_IDACS_CORE0 0x0a6 -#define R2057_LPF_RESP_RXBUF_BW_CORE0 0x0a7 -#define R2057_RXBB_CC_CORE0 0x0a8 -#define R2057_RXBB_SPARE3_CORE0 0x0a9 -#define R2057_RXBB_RCCAL_HPC_CORE0 0x0aa -#define R2057_LPF_IDACS_CORE0 0x0ab -#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0 0x0ac -#define R2057_TXBUF_GAIN_CORE0 0x0ad -#define R2057_AFELOOPBACK_AACI_RESP_CORE0 0x0ae -#define R2057_RXBUF_DEGEN_CORE0 0x0af -#define R2057_RXBB_SPARE2_CORE0 0x0b0 -#define R2057_RXBB_SPARE1_CORE0 0x0b1 -#define R2057_RSSI_MASTER_CORE0 0x0b2 -#define R2057_W2_MASTER_CORE0 0x0b3 -#define R2057_NB_MASTER_CORE0 0x0b4 -#define R2057_W2_IDACS0_Q_CORE0 0x0b5 -#define R2057_W2_IDACS1_Q_CORE0 0x0b6 -#define R2057_W2_IDACS0_I_CORE0 0x0b7 -#define R2057_W2_IDACS1_I_CORE0 0x0b8 -#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0 0x0b9 -#define R2057_NB_IDACS_Q_CORE0 0x0ba -#define R2057_NB_IDACS_I_CORE0 0x0bb -#define R2057_BACKUP4_CORE0 0x0c1 -#define R2057_BACKUP3_CORE0 0x0c2 -#define R2057_BACKUP2_CORE0 0x0c3 -#define R2057_BACKUP1_CORE0 0x0c4 -#define R2057_SPARE16_CORE0 0x0c5 -#define R2057_SPARE15_CORE0 0x0c6 -#define R2057_SPARE14_CORE0 0x0c7 -#define R2057_SPARE13_CORE0 0x0c8 -#define R2057_SPARE12_CORE0 0x0c9 -#define R2057_SPARE11_CORE0 0x0ca -#define R2057_TX2G_BIAS_RESETS_CORE0 0x0cb -#define R2057_TX5G_BIAS_RESETS_CORE0 0x0cc -#define R2057_IQTEST_SEL_PU 0x0cd -#define R2057_XTAL_CONFIG2 0x0ce -#define R2057_BUFS_MISC_LPFBW_CORE0 0x0cf -#define R2057_TXLPF_RCCAL_CORE0 0x0d0 -#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0 0x0d1 -#define R2057_LPF_GAIN_CORE0 0x0d2 -#define R2057_DACBUF_IDACS_BW_CORE0 0x0d3 - -/* MISC core 1 */ -#define R2057_RXTXBIAS_CONFIG_CORE1 0x0d4 -#define R2057_TXGM_TXRF_PUS_CORE1 0x0d5 -#define R2057_TXGM_IDAC_BLEED_CORE1 0x0d6 -#define R2057_TXGM_GAIN_CORE1 0x0db -#define R2057_TXGM2G_PKDET_PUS_CORE1 0x0dc -#define R2057_PAD2G_PTATS_CORE1 0x0dd -#define R2057_PAD2G_IDACS_CORE1 0x0de -#define R2057_PAD2G_BOOST_PU_CORE1 0x0df -#define R2057_PAD2G_CASCV_GAIN_CORE1 0x0e0 -#define R2057_TXMIX2G_TUNE_BOOST_PU_CORE1 0x0e1 -#define R2057_TXMIX2G_LODC_CORE1 0x0e2 -#define R2057_PAD2G_TUNE_PUS_CORE1 0x0e3 -#define R2057_IPA2G_GAIN_CORE1 0x0e4 -#define R2057_TSSI2G_SPARE1_CORE1 0x0e5 -#define R2057_TSSI2G_SPARE2_CORE1 0x0e6 -#define R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1 0x0e7 -#define R2057_IPA2G_IMAIN_CORE1 0x0e8 -#define R2057_IPA2G_CASCONV_CORE1 0x0e9 -#define R2057_IPA2G_CASCOFFV_CORE1 0x0ea -#define R2057_IPA2G_BIAS_FILTER_CORE1 0x0eb -#define R2057_TX5G_PKDET_CORE1 0x0ee -#define R2057_PGA_PTAT_TXGM5G_PU_CORE1 0x0ef -#define R2057_PAD5G_PTATS1_CORE1 0x0f0 -#define R2057_PAD5G_CLASS_PTATS2_CORE1 0x0f1 -#define R2057_PGA_BOOSTPTAT_IMAIN_CORE1 0x0f2 -#define R2057_PAD5G_CASCV_IMAIN_CORE1 0x0f3 -#define R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1 0x0f4 -#define R2057_PGA_BOOST_TUNE_CORE1 0x0f5 -#define R2057_PGA_GAIN_CORE1 0x0f6 -#define R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1 0x0f7 -#define R2057_TXMIX5G_BOOST_TUNE_CORE1 0x0f8 -#define R2057_PAD5G_TUNE_MISC_PUS_CORE1 0x0f9 -#define R2057_IPA5G_IAUX_CORE1 0x0fa -#define R2057_IPA5G_GAIN_CORE1 0x0fb -#define R2057_TSSI5G_SPARE1_CORE1 0x0fc -#define R2057_TSSI5G_SPARE2_CORE1 0x0fd -#define R2057_IPA5G_CASCOFFV_PU_CORE1 0x0fe -#define R2057_IPA5G_PTAT_CORE1 0x0ff -#define R2057_IPA5G_IMAIN_CORE1 0x100 -#define R2057_IPA5G_CASCONV_CORE1 0x101 -#define R2057_IPA5G_BIAS_FILTER_CORE1 0x102 -#define R2057_PAD_BIAS_FILTER_BWS_CORE1 0x105 -#define R2057_TR2G_CONFIG1_CORE1_NU 0x106 -#define R2057_TR2G_CONFIG2_CORE1_NU 0x107 -#define R2057_LNA5G_RFEN_CORE1 0x108 -#define R2057_TR5G_CONFIG2_CORE1_NU 0x109 -#define R2057_RXRFBIAS_IBOOST_PU_CORE1 0x10a -#define R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1 0x10b -#define R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1 0x10c -#define R2057_RXMIX_ICORE_RXGM_IAUX_CORE1 0x10d -#define R2057_RXMIX_CMFBITAIL_PU_CORE1 0x10e -#define R2057_LNA2_IMAIN_PTAT_PU_CORE1 0x10f -#define R2057_LNA2_IAUX_PTAT_CORE1 0x110 -#define R2057_LNA1_IMAIN_PTAT_PU_CORE1 0x111 -#define R2057_LNA15G_INPUT_MATCH_TUNE_CORE1 0x112 -#define R2057_RXRFBIAS_BANDSEL_CORE1 0x113 -#define R2057_TIA_CONFIG_CORE1 0x114 -#define R2057_TIA_IQGAIN_CORE1 0x115 -#define R2057_TIA_IBIAS2_CORE1 0x116 -#define R2057_TIA_IBIAS1_CORE1 0x117 -#define R2057_TIA_SPARE_Q_CORE1 0x118 -#define R2057_TIA_SPARE_I_CORE1 0x119 -#define R2057_RXMIX2G_PUS_CORE1 0x11a -#define R2057_RXMIX2G_VCMREFS_CORE1 0x11b -#define R2057_RXMIX2G_LODC_QI_CORE1 0x11c -#define R2057_W12G_BW_LNA2G_PUS_CORE1 0x11d -#define R2057_LNA2G_GAIN_CORE1 0x11e -#define R2057_LNA2G_TUNE_CORE1 0x11f -#define R2057_RXMIX5G_PUS_CORE1 0x120 -#define R2057_RXMIX5G_VCMREFS_CORE1 0x121 -#define R2057_RXMIX5G_LODC_QI_CORE1 0x122 -#define R2057_W15G_BW_LNA5G_PUS_CORE1 0x123 -#define R2057_LNA5G_GAIN_CORE1 0x124 -#define R2057_LNA5G_TUNE_CORE1 0x125 -#define R2057_LPFSEL_TXRX_RXBB_PUS_CORE1 0x126 -#define R2057_RXBB_BIAS_MASTER_CORE1 0x127 -#define R2057_RXBB_VGABUF_IDACS_CORE1 0x128 -#define R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1 0x129 -#define R2057_TXBUF_VINCM_CORE1 0x12a -#define R2057_TXBUF_IDACS_CORE1 0x12b -#define R2057_LPF_RESP_RXBUF_BW_CORE1 0x12c -#define R2057_RXBB_CC_CORE1 0x12d -#define R2057_RXBB_SPARE3_CORE1 0x12e -#define R2057_RXBB_RCCAL_HPC_CORE1 0x12f -#define R2057_LPF_IDACS_CORE1 0x130 -#define R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1 0x131 -#define R2057_TXBUF_GAIN_CORE1 0x132 -#define R2057_AFELOOPBACK_AACI_RESP_CORE1 0x133 -#define R2057_RXBUF_DEGEN_CORE1 0x134 -#define R2057_RXBB_SPARE2_CORE1 0x135 -#define R2057_RXBB_SPARE1_CORE1 0x136 -#define R2057_RSSI_MASTER_CORE1 0x137 -#define R2057_W2_MASTER_CORE1 0x138 -#define R2057_NB_MASTER_CORE1 0x139 -#define R2057_W2_IDACS0_Q_CORE1 0x13a -#define R2057_W2_IDACS1_Q_CORE1 0x13b -#define R2057_W2_IDACS0_I_CORE1 0x13c -#define R2057_W2_IDACS1_I_CORE1 0x13d -#define R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1 0x13e -#define R2057_NB_IDACS_Q_CORE1 0x13f -#define R2057_NB_IDACS_I_CORE1 0x140 -#define R2057_BACKUP4_CORE1 0x146 -#define R2057_BACKUP3_CORE1 0x147 -#define R2057_BACKUP2_CORE1 0x148 -#define R2057_BACKUP1_CORE1 0x149 -#define R2057_SPARE16_CORE1 0x14a -#define R2057_SPARE15_CORE1 0x14b -#define R2057_SPARE14_CORE1 0x14c -#define R2057_SPARE13_CORE1 0x14d -#define R2057_SPARE12_CORE1 0x14e -#define R2057_SPARE11_CORE1 0x14f -#define R2057_TX2G_BIAS_RESETS_CORE1 0x150 -#define R2057_TX5G_BIAS_RESETS_CORE1 0x151 -#define R2057_SPARE8_CORE1 0x152 -#define R2057_SPARE7_CORE1 0x153 -#define R2057_BUFS_MISC_LPFBW_CORE1 0x154 -#define R2057_TXLPF_RCCAL_CORE1 0x155 -#define R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1 0x156 -#define R2057_LPF_GAIN_CORE1 0x157 -#define R2057_DACBUF_IDACS_BW_CORE1 0x158 - -#define R2057_DACBUF_VINCM_CORE1 0x159 -#define R2057_RCCAL_START_R1_Q1_P1 0x15a -#define R2057_RCCAL_X1 0x15b -#define R2057_RCCAL_TRC0 0x15c -#define R2057_RCCAL_TRC1 0x15d -#define R2057_RCCAL_DONE_OSCCAP 0x15e -#define R2057_RCCAL_N0_0 0x15f -#define R2057_RCCAL_N0_1 0x160 -#define R2057_RCCAL_N1_0 0x161 -#define R2057_RCCAL_N1_1 0x162 -#define R2057_RCAL_STATUS 0x163 -#define R2057_XTALPUOVR_PINCTRL 0x164 -#define R2057_OVR_REG0 0x165 -#define R2057_OVR_REG1 0x166 -#define R2057_OVR_REG2 0x167 -#define R2057_OVR_REG3 0x168 -#define R2057_OVR_REG4 0x169 -#define R2057_RCCAL_SCAP_VAL 0x16a -#define R2057_RCCAL_BCAP_VAL 0x16b -#define R2057_RCCAL_HPC_VAL 0x16c -#define R2057_RCCAL_OVERRIDES 0x16d - -/* TX core 0 */ -#define R2057_TX0_IQCAL_GAIN_BW 0x170 -#define R2057_TX0_LOFT_FINE_I 0x171 -#define R2057_TX0_LOFT_FINE_Q 0x172 -#define R2057_TX0_LOFT_COARSE_I 0x173 -#define R2057_TX0_LOFT_COARSE_Q 0x174 -#define R2057_TX0_TX_SSI_MASTER 0x175 -#define R2057_TX0_IQCAL_VCM_HG 0x176 -#define R2057_TX0_IQCAL_IDAC 0x177 -#define R2057_TX0_TSSI_VCM 0x178 -#define R2057_TX0_TX_SSI_MUX 0x179 -#define R2057_TX0_TSSIA 0x17a -#define R2057_TX0_TSSIG 0x17b -#define R2057_TX0_TSSI_MISC1 0x17c -#define R2057_TX0_TXRXCOUPLE_2G_ATTEN 0x17d -#define R2057_TX0_TXRXCOUPLE_2G_PWRUP 0x17e -#define R2057_TX0_TXRXCOUPLE_5G_ATTEN 0x17f -#define R2057_TX0_TXRXCOUPLE_5G_PWRUP 0x180 - -/* TX core 1 */ -#define R2057_TX1_IQCAL_GAIN_BW 0x190 -#define R2057_TX1_LOFT_FINE_I 0x191 -#define R2057_TX1_LOFT_FINE_Q 0x192 -#define R2057_TX1_LOFT_COARSE_I 0x193 -#define R2057_TX1_LOFT_COARSE_Q 0x194 -#define R2057_TX1_TX_SSI_MASTER 0x195 -#define R2057_TX1_IQCAL_VCM_HG 0x196 -#define R2057_TX1_IQCAL_IDAC 0x197 -#define R2057_TX1_TSSI_VCM 0x198 -#define R2057_TX1_TX_SSI_MUX 0x199 -#define R2057_TX1_TSSIA 0x19a -#define R2057_TX1_TSSIG 0x19b -#define R2057_TX1_TSSI_MISC1 0x19c -#define R2057_TX1_TXRXCOUPLE_2G_ATTEN 0x19d -#define R2057_TX1_TXRXCOUPLE_2G_PWRUP 0x19e -#define R2057_TX1_TXRXCOUPLE_5G_ATTEN 0x19f -#define R2057_TX1_TXRXCOUPLE_5G_PWRUP 0x1a0 - -#define R2057_AFE_VCM_CAL_MASTER_CORE0 0x1a1 -#define R2057_AFE_SET_VCM_I_CORE0 0x1a2 -#define R2057_AFE_SET_VCM_Q_CORE0 0x1a3 -#define R2057_AFE_STATUS_VCM_IQADC_CORE0 0x1a4 -#define R2057_AFE_STATUS_VCM_I_CORE0 0x1a5 -#define R2057_AFE_STATUS_VCM_Q_CORE0 0x1a6 -#define R2057_AFE_VCM_CAL_MASTER_CORE1 0x1a7 -#define R2057_AFE_SET_VCM_I_CORE1 0x1a8 -#define R2057_AFE_SET_VCM_Q_CORE1 0x1a9 -#define R2057_AFE_STATUS_VCM_IQADC_CORE1 0x1aa -#define R2057_AFE_STATUS_VCM_I_CORE1 0x1ab -#define R2057_AFE_STATUS_VCM_Q_CORE1 0x1ac - -#define R2057v7_DACBUF_VINCM_CORE0 0x1ad -#define R2057v7_RCCAL_MASTER 0x1ae -#define R2057v7_TR2G_CONFIG3_CORE0_NU 0x1af -#define R2057v7_TR2G_CONFIG3_CORE1_NU 0x1b0 -#define R2057v7_LOGEN_PUS1 0x1b1 -#define R2057v7_OVR_REG5 0x1b2 -#define R2057v7_OVR_REG6 0x1b3 -#define R2057v7_OVR_REG7 0x1b4 -#define R2057v7_OVR_REG8 0x1b5 -#define R2057v7_OVR_REG9 0x1b6 -#define R2057v7_OVR_REG10 0x1b7 -#define R2057v7_OVR_REG11 0x1b8 -#define R2057v7_OVR_REG12 0x1b9 -#define R2057v7_OVR_REG13 0x1ba -#define R2057v7_OVR_REG14 0x1bb -#define R2057v7_OVR_REG15 0x1bc -#define R2057v7_OVR_REG16 0x1bd -#define R2057v7_OVR_REG1 0x1be -#define R2057v7_OVR_REG18 0x1bf -#define R2057v7_OVR_REG19 0x1c0 -#define R2057v7_OVR_REG20 0x1c1 -#define R2057v7_OVR_REG21 0x1c2 -#define R2057v7_OVR_REG2 0x1c3 -#define R2057v7_OVR_REG23 0x1c4 -#define R2057v7_OVR_REG24 0x1c5 -#define R2057v7_OVR_REG25 0x1c6 -#define R2057v7_OVR_REG26 0x1c7 -#define R2057v7_OVR_REG27 0x1c8 -#define R2057v7_OVR_REG28 0x1c9 -#define R2057v7_IQTEST_SEL_PU2 0x1ca - -#define R2057_VCM_MASK 0x7 - -struct b43_nphy_chantabent_rev7 { - /* The channel frequency in MHz */ - u16 freq; - /* Radio regs values on channelswitch */ - u8 radio_vcocal_countval0; - u8 radio_vcocal_countval1; - u8 radio_rfpll_refmaster_sparextalsize; - u8 radio_rfpll_loopfilter_r1; - u8 radio_rfpll_loopfilter_c2; - u8 radio_rfpll_loopfilter_c1; - u8 radio_cp_kpd_idac; - u8 radio_rfpll_mmd0; - u8 radio_rfpll_mmd1; - u8 radio_vcobuf_tune; - u8 radio_logen_mx2g_tune; - u8 radio_logen_mx5g_tune; - u8 radio_logen_indbuf2g_tune; - u8 radio_logen_indbuf5g_tune; - u8 radio_txmix2g_tune_boost_pu_core0; - u8 radio_pad2g_tune_pus_core0; - u8 radio_pga_boost_tune_core0; - u8 radio_txmix5g_boost_tune_core0; - u8 radio_pad5g_tune_misc_pus_core0; - u8 radio_lna2g_tune_core0; - u8 radio_lna5g_tune_core0; - u8 radio_txmix2g_tune_boost_pu_core1; - u8 radio_pad2g_tune_pus_core1; - u8 radio_pga_boost_tune_core1; - u8 radio_txmix5g_boost_tune_core1; - u8 radio_pad5g_tune_misc_pus_core1; - u8 radio_lna2g_tune_core1; - u8 radio_lna5g_tune_core1; - /* PHY res values on channelswitch */ - struct b43_phy_n_sfo_cfg phy_regs; -}; - -struct b43_nphy_chantabent_rev7_2g { - /* The channel frequency in MHz */ - u16 freq; - /* Radio regs values on channelswitch */ - u8 radio_vcocal_countval0; - u8 radio_vcocal_countval1; - u8 radio_rfpll_refmaster_sparextalsize; - u8 radio_rfpll_loopfilter_r1; - u8 radio_rfpll_loopfilter_c2; - u8 radio_rfpll_loopfilter_c1; - u8 radio_cp_kpd_idac; - u8 radio_rfpll_mmd0; - u8 radio_rfpll_mmd1; - u8 radio_vcobuf_tune; - u8 radio_logen_mx2g_tune; - u8 radio_logen_indbuf2g_tune; - u8 radio_txmix2g_tune_boost_pu_core0; - u8 radio_pad2g_tune_pus_core0; - u8 radio_lna2g_tune_core0; - u8 radio_txmix2g_tune_boost_pu_core1; - u8 radio_pad2g_tune_pus_core1; - u8 radio_lna2g_tune_core1; - /* PHY regs values on channelswitch */ - struct b43_phy_n_sfo_cfg phy_regs; -}; - -void r2057_upload_inittabs(struct b43_wldev *dev); - -void r2057_get_chantabent_rev7(struct b43_wldev *dev, u16 freq, - const struct b43_nphy_chantabent_rev7 **tabent_r7, - const struct b43_nphy_chantabent_rev7_2g **tabent_r7_2g); - -#endif /* B43_RADIO_2057_H_ */ diff --git a/drivers/net/wireless/b43/radio_2059.c b/drivers/net/wireless/b43/radio_2059.c deleted file mode 100644 index a3cf9efd7..000000000 --- a/drivers/net/wireless/b43/radio_2059.c +++ /dev/null @@ -1,364 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n 2059 radio device data tables - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "radio_2059.h" - -/* Extracted from MMIO dump of 6.30.223.141 */ -static u16 r2059_phy_rev1_init[][2] = { - { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 }, - { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 }, - { 0x188, 0x05 }, -}; - -#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ - r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ - r20) \ - .radio_syn16 = r00, \ - .radio_syn17 = r01, \ - .radio_syn22 = r02, \ - .radio_syn25 = r03, \ - .radio_syn27 = r04, \ - .radio_syn28 = r05, \ - .radio_syn29 = r06, \ - .radio_syn2c = r07, \ - .radio_syn2d = r08, \ - .radio_syn37 = r09, \ - .radio_syn41 = r10, \ - .radio_syn43 = r11, \ - .radio_syn47 = r12, \ - .radio_rxtx4a = r13, \ - .radio_rxtx58 = r14, \ - .radio_rxtx5a = r15, \ - .radio_rxtx6a = r16, \ - .radio_rxtx6d = r17, \ - .radio_rxtx6e = r18, \ - .radio_rxtx92 = r19, \ - .radio_rxtx98 = r20 - -#define PHYREGS(r0, r1, r2, r3, r4, r5) \ - .phy_regs.bw1 = r0, \ - .phy_regs.bw2 = r1, \ - .phy_regs.bw3 = r2, \ - .phy_regs.bw4 = r3, \ - .phy_regs.bw5 = r4, \ - .phy_regs.bw6 = r5 - -/* Extracted from MMIO dump of 6.30.223.141 - * TODO: Values for channels 12 & 13 are outdated (from some old 5.x driver)! - */ -static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radio2059[] = { - { - .freq = 2412, - RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, - 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xd0, 0x00), - PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), - }, - { - .freq = 2417, - RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, - 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xd0, 0x00), - PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), - }, - { - .freq = 2422, - RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, - 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xd0, 0x00), - PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), - }, - { - .freq = 2427, - RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, - 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xa0, 0x00), - PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), - }, - { - .freq = 2432, - RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, - 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xa0, 0x00), - PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), - }, - { - .freq = 2437, - RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, - 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0xa0, 0x00), - PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), - }, - { - .freq = 2442, - RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0x80, 0x00), - PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), - }, - { - .freq = 2447, - RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0x80, 0x00), - PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), - }, - { - .freq = 2452, - RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, - 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0x80, 0x00), - PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), - }, - { - .freq = 2457, - RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, - 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0x60, 0x00), - PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), - }, - { - .freq = 2462, - RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, - 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x73, - 0x00, 0x00, 0x00, 0x60, 0x00), - PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), - }, - { .freq = 2467, - RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, - 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, - 0x00, 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), - }, - { .freq = 2472, - RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, - 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, - 0x00, 0x00, 0x00, 0xf0, 0x00), - PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), - }, - { - .freq = 5180, - RADIOREGS(0xbe, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x06, - 0x02, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, - 0x0f, 0x4f, 0xa3, 0x00, 0xfc), - PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb), - }, - { - .freq = 5200, - RADIOREGS(0xc5, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x08, - 0x02, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, - 0x0f, 0x4f, 0x93, 0x00, 0xfb), - PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9), - }, - { - .freq = 5220, - RADIOREGS(0xcc, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0a, - 0x02, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, - 0x0f, 0x4f, 0x93, 0x00, 0xea), - PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7), - }, - { - .freq = 5240, - RADIOREGS(0xd2, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0c, - 0x02, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, - 0x0f, 0x4f, 0x93, 0x00, 0xda), - PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5), - }, - { - .freq = 5260, - RADIOREGS(0xd9, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x0e, - 0x02, 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x00, - 0x0f, 0x4f, 0x93, 0x00, 0xca), - PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3), - }, - { - .freq = 5280, - RADIOREGS(0xe0, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x10, - 0x02, 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x00, - 0x0f, 0x4f, 0x93, 0x00, 0xb9), - PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1), - }, - { - .freq = 5300, - RADIOREGS(0xe6, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x12, - 0x02, 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x00, - 0x0f, 0x4c, 0x83, 0x00, 0xb8), - PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0), - }, - { - .freq = 5320, - RADIOREGS(0xed, 0x16, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x14, - 0x02, 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x00, - 0x0f, 0x4c, 0x83, 0x00, 0xa8), - PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee), - }, - { - .freq = 5500, - RADIOREGS(0x29, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x26, - 0x02, 0x09, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, - 0x0a, 0x46, 0x43, 0x00, 0x75), - PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd), - }, - { - .freq = 5520, - RADIOREGS(0x30, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x28, - 0x02, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, - 0x0a, 0x46, 0x43, 0x00, 0x75), - PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc), - }, - { - .freq = 5540, - RADIOREGS(0x36, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x2a, - 0x02, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, - 0x0a, 0x46, 0x43, 0x00, 0x75), - PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da), - }, - { - .freq = 5560, - RADIOREGS(0x3d, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x2c, - 0x02, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, - 0x0a, 0x46, 0x43, 0x00, 0x75), - PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8), - }, - { - .freq = 5580, - RADIOREGS(0x44, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x2e, - 0x02, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, - 0x0a, 0x46, 0x43, 0x00, 0x74), - PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7), - }, - { - .freq = 5600, - RADIOREGS(0x4a, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x30, - 0x02, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, - 0x09, 0x44, 0x23, 0x00, 0x54), - PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5), - }, - { - .freq = 5620, - RADIOREGS(0x51, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x32, - 0x02, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, - 0x09, 0x44, 0x23, 0x00, 0x54), - PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3), - }, - { - .freq = 5640, - RADIOREGS(0x58, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x34, - 0x02, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, - 0x09, 0x44, 0x23, 0x00, 0x43), - PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2), - }, - { - .freq = 5660, - RADIOREGS(0x5e, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x36, - 0x02, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, - 0x09, 0x43, 0x23, 0x00, 0x43), - PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0), - }, - { - .freq = 5680, - RADIOREGS(0x65, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x38, - 0x02, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, - 0x09, 0x42, 0x23, 0x00, 0x43), - PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce), - }, - { - .freq = 5700, - RADIOREGS(0x6c, 0x17, 0x10, 0x1f, 0x08, 0x08, 0x3f, 0x3a, - 0x02, 0x07, 0x00, 0x07, 0x00, 0x07, 0x00, 0x00, - 0x08, 0x42, 0x13, 0x00, 0x32), - PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd), - }, - { - .freq = 5745, - RADIOREGS(0x7b, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x7d, - 0x04, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, - 0x08, 0x42, 0x13, 0x00, 0x21), - PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9), - }, - { - .freq = 5765, - RADIOREGS(0x81, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x81, - 0x04, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, - 0x08, 0x42, 0x13, 0x00, 0x11), - PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8), - }, - { - .freq = 5785, - RADIOREGS(0x88, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x85, - 0x04, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x00, - 0x08, 0x42, 0x13, 0x00, 0x00), - PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6), - }, - { - .freq = 5805, - RADIOREGS(0x8f, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x89, - 0x04, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x00, - 0x06, 0x41, 0x03, 0x00, 0x00), - PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4), - }, - { - .freq = 5825, - RADIOREGS(0x95, 0x17, 0x20, 0x1f, 0x08, 0x08, 0x3f, 0x8d, - 0x04, 0x05, 0x00, 0x05, 0x00, 0x05, 0x00, 0x00, - 0x06, 0x41, 0x03, 0x00, 0x00), - PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3), - }, -}; - -void r2059_upload_inittabs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 *table = NULL; - u16 size, i; - - switch (phy->rev) { - case 1: - table = r2059_phy_rev1_init[0]; - size = ARRAY_SIZE(r2059_phy_rev1_init); - break; - default: - B43_WARN_ON(1); - return; - } - - for (i = 0; i < size; i++, table += 2) - b43_radio_write(dev, R2059_ALL | table[0], table[1]); -} - -const struct b43_phy_ht_channeltab_e_radio2059 -*b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq) -{ - const struct b43_phy_ht_channeltab_e_radio2059 *e; - unsigned int i; - - e = b43_phy_ht_channeltab_radio2059; - for (i = 0; i < ARRAY_SIZE(b43_phy_ht_channeltab_radio2059); i++, e++) { - if (e->freq == freq) - return e; - } - - return NULL; -} diff --git a/drivers/net/wireless/b43/radio_2059.h b/drivers/net/wireless/b43/radio_2059.h deleted file mode 100644 index 9e22fb605..000000000 --- a/drivers/net/wireless/b43/radio_2059.h +++ /dev/null @@ -1,60 +0,0 @@ -#ifndef B43_RADIO_2059_H_ -#define B43_RADIO_2059_H_ - -#include <linux/types.h> - -#include "phy_ht.h" - -#define R2059_C1 0x000 -#define R2059_C2 0x400 -#define R2059_C3 0x800 -#define R2059_ALL 0xC00 - -#define R2059_RCAL_CONFIG 0x004 -#define R2059_RFPLL_MASTER 0x011 -#define R2059_RFPLL_MISC_EN 0x02b -#define R2059_RFPLL_MISC_CAL_RESETN 0x02e -#define R2059_XTAL_CONFIG2 0x0c0 -#define R2059_RCCAL_START_R1_Q1_P1 0x13c -#define R2059_RCCAL_X1 0x13d -#define R2059_RCCAL_TRC0 0x13e -#define R2059_RCCAL_DONE_OSCCAP 0x140 -#define R2059_RCAL_STATUS 0x145 -#define R2059_RCCAL_MASTER 0x17f - -/* Values for various registers uploaded on channel switching */ -struct b43_phy_ht_channeltab_e_radio2059 { - /* The channel frequency in MHz */ - u16 freq; - /* Values for radio registers */ - u8 radio_syn16; - u8 radio_syn17; - u8 radio_syn22; - u8 radio_syn25; - u8 radio_syn27; - u8 radio_syn28; - u8 radio_syn29; - u8 radio_syn2c; - u8 radio_syn2d; - u8 radio_syn37; - u8 radio_syn41; - u8 radio_syn43; - u8 radio_syn47; - u8 radio_rxtx4a; - u8 radio_rxtx58; - u8 radio_rxtx5a; - u8 radio_rxtx6a; - u8 radio_rxtx6d; - u8 radio_rxtx6e; - u8 radio_rxtx92; - u8 radio_rxtx98; - /* Values for PHY registers */ - struct b43_phy_ht_channeltab_e_phy phy_regs; -}; - -void r2059_upload_inittabs(struct b43_wldev *dev); - -const struct b43_phy_ht_channeltab_e_radio2059 -*b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq); - -#endif /* B43_RADIO_2059_H_ */ diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c deleted file mode 100644 index 70c2fcedd..000000000 --- a/drivers/net/wireless/b43/rfkill.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - - Broadcom B43 wireless driver - RFKILL support - - Copyright (c) 2007 Michael Buesch <m@bues.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" - - -/* Returns TRUE, if the radio is enabled in hardware. */ -bool b43_is_hw_radio_enabled(struct b43_wldev *dev) -{ - return !(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI) - & B43_MMIO_RADIO_HWENABLED_HI_MASK); -} - -/* The poll callback for the hardware button. */ -void b43_rfkill_poll(struct ieee80211_hw *hw) -{ - struct b43_wl *wl = hw_to_b43_wl(hw); - struct b43_wldev *dev = wl->current_dev; - bool enabled; - bool brought_up = false; - - mutex_lock(&wl->mutex); - if (unlikely(b43_status(dev) < B43_STAT_INITIALIZED)) { - if (b43_bus_powerup(dev, 0)) { - mutex_unlock(&wl->mutex); - return; - } - b43_device_enable(dev, 0); - brought_up = true; - } - - enabled = b43_is_hw_radio_enabled(dev); - - if (unlikely(enabled != dev->radio_hw_enable)) { - dev->radio_hw_enable = enabled; - b43info(wl, "Radio hardware status changed to %s\n", - enabled ? "ENABLED" : "DISABLED"); - wiphy_rfkill_set_hw_state(hw->wiphy, !enabled); - if (enabled != dev->phy.radio_on) - b43_software_rfkill(dev, !enabled); - } - - if (brought_up) { - b43_device_disable(dev, 0); - b43_bus_may_powerdown(dev); - } - - mutex_unlock(&wl->mutex); -} diff --git a/drivers/net/wireless/b43/rfkill.h b/drivers/net/wireless/b43/rfkill.h deleted file mode 100644 index f046c3ca0..000000000 --- a/drivers/net/wireless/b43/rfkill.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef B43_RFKILL_H_ -#define B43_RFKILL_H_ - -struct ieee80211_hw; -struct b43_wldev; - -void b43_rfkill_poll(struct ieee80211_hw *hw); - -bool b43_is_hw_radio_enabled(struct b43_wldev *dev); - -#endif /* B43_RFKILL_H_ */ diff --git a/drivers/net/wireless/b43/sdio.c b/drivers/net/wireless/b43/sdio.c deleted file mode 100644 index 59a521800..000000000 --- a/drivers/net/wireless/b43/sdio.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Broadcom B43 wireless driver - * - * SDIO over Sonics Silicon Backplane bus glue for b43. - * - * Copyright (C) 2009 Albert Herranz - * Copyright (C) 2009 Michael Buesch <m@bues.ch> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -#include <linux/kernel.h> -#include <linux/mmc/card.h> -#include <linux/mmc/sdio_func.h> -#include <linux/mmc/sdio_ids.h> -#include <linux/slab.h> -#include <linux/ssb/ssb.h> - -#include "sdio.h" -#include "b43.h" - - -#define HNBU_CHIPID 0x01 /* vendor & device id */ - -#define B43_SDIO_BLOCK_SIZE 64 /* rx fifo max size in bytes */ - - -static const struct b43_sdio_quirk { - u16 vendor; - u16 device; - unsigned int quirks; -} b43_sdio_quirks[] = { - { 0x14E4, 0x4318, SSB_QUIRK_SDIO_READ_AFTER_WRITE32, }, - { }, -}; - - -static unsigned int b43_sdio_get_quirks(u16 vendor, u16 device) -{ - const struct b43_sdio_quirk *q; - - for (q = b43_sdio_quirks; q->quirks; q++) { - if (vendor == q->vendor && device == q->device) - return q->quirks; - } - - return 0; -} - -static void b43_sdio_interrupt_dispatcher(struct sdio_func *func) -{ - struct b43_sdio *sdio = sdio_get_drvdata(func); - struct b43_wldev *dev = sdio->irq_handler_opaque; - - if (unlikely(b43_status(dev) < B43_STAT_STARTED)) - return; - - sdio_release_host(func); - sdio->irq_handler(dev); - sdio_claim_host(func); -} - -int b43_sdio_request_irq(struct b43_wldev *dev, - void (*handler)(struct b43_wldev *dev)) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - struct sdio_func *func = bus->host_sdio; - struct b43_sdio *sdio = sdio_get_drvdata(func); - int err; - - sdio->irq_handler_opaque = dev; - sdio->irq_handler = handler; - sdio_claim_host(func); - err = sdio_claim_irq(func, b43_sdio_interrupt_dispatcher); - sdio_release_host(func); - - return err; -} - -void b43_sdio_free_irq(struct b43_wldev *dev) -{ - struct ssb_bus *bus = dev->dev->sdev->bus; - struct sdio_func *func = bus->host_sdio; - struct b43_sdio *sdio = sdio_get_drvdata(func); - - sdio_claim_host(func); - sdio_release_irq(func); - sdio_release_host(func); - sdio->irq_handler_opaque = NULL; - sdio->irq_handler = NULL; -} - -static int b43_sdio_probe(struct sdio_func *func, - const struct sdio_device_id *id) -{ - struct b43_sdio *sdio; - struct sdio_func_tuple *tuple; - u16 vendor = 0, device = 0; - int error; - - /* Look for the card chip identifier. */ - tuple = func->tuples; - while (tuple) { - switch (tuple->code) { - case 0x80: - switch (tuple->data[0]) { - case HNBU_CHIPID: - if (tuple->size != 5) - break; - vendor = tuple->data[1] | (tuple->data[2]<<8); - device = tuple->data[3] | (tuple->data[4]<<8); - dev_info(&func->dev, "Chip ID %04x:%04x\n", - vendor, device); - break; - default: - break; - } - break; - default: - break; - } - tuple = tuple->next; - } - if (!vendor || !device) { - error = -ENODEV; - goto out; - } - - sdio_claim_host(func); - error = sdio_set_block_size(func, B43_SDIO_BLOCK_SIZE); - if (error) { - dev_err(&func->dev, "failed to set block size to %u bytes," - " error %d\n", B43_SDIO_BLOCK_SIZE, error); - goto err_release_host; - } - error = sdio_enable_func(func); - if (error) { - dev_err(&func->dev, "failed to enable func, error %d\n", error); - goto err_release_host; - } - sdio_release_host(func); - - sdio = kzalloc(sizeof(*sdio), GFP_KERNEL); - if (!sdio) { - error = -ENOMEM; - dev_err(&func->dev, "failed to allocate ssb bus\n"); - goto err_disable_func; - } - error = ssb_bus_sdiobus_register(&sdio->ssb, func, - b43_sdio_get_quirks(vendor, device)); - if (error) { - dev_err(&func->dev, "failed to register ssb sdio bus," - " error %d\n", error); - goto err_free_ssb; - } - sdio_set_drvdata(func, sdio); - - return 0; - -err_free_ssb: - kfree(sdio); -err_disable_func: - sdio_claim_host(func); - sdio_disable_func(func); -err_release_host: - sdio_release_host(func); -out: - return error; -} - -static void b43_sdio_remove(struct sdio_func *func) -{ - struct b43_sdio *sdio = sdio_get_drvdata(func); - - ssb_bus_unregister(&sdio->ssb); - sdio_claim_host(func); - sdio_disable_func(func); - sdio_release_host(func); - kfree(sdio); - sdio_set_drvdata(func, NULL); -} - -static const struct sdio_device_id b43_sdio_ids[] = { - { SDIO_DEVICE(0x02d0, 0x044b) }, /* Nintendo Wii WLAN daughter card */ - { SDIO_DEVICE(0x0092, 0x0004) }, /* C-guys, Inc. EW-CG1102GC */ - { }, -}; - -static struct sdio_driver b43_sdio_driver = { - .name = "b43-sdio", - .id_table = b43_sdio_ids, - .probe = b43_sdio_probe, - .remove = b43_sdio_remove, -}; - -int b43_sdio_init(void) -{ - return sdio_register_driver(&b43_sdio_driver); -} - -void b43_sdio_exit(void) -{ - sdio_unregister_driver(&b43_sdio_driver); -} diff --git a/drivers/net/wireless/b43/sdio.h b/drivers/net/wireless/b43/sdio.h deleted file mode 100644 index 1e93926f3..000000000 --- a/drivers/net/wireless/b43/sdio.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef B43_SDIO_H_ -#define B43_SDIO_H_ - -#include <linux/ssb/ssb.h> - -struct b43_wldev; - - -#ifdef CONFIG_B43_SDIO - -struct b43_sdio { - struct ssb_bus ssb; - void *irq_handler_opaque; - void (*irq_handler)(struct b43_wldev *dev); -}; - -int b43_sdio_request_irq(struct b43_wldev *dev, - void (*handler)(struct b43_wldev *dev)); -void b43_sdio_free_irq(struct b43_wldev *dev); - -int b43_sdio_init(void); -void b43_sdio_exit(void); - - -#else /* CONFIG_B43_SDIO */ - - -static inline int b43_sdio_request_irq(struct b43_wldev *dev, - void (*handler)(struct b43_wldev *dev)) -{ - return -ENODEV; -} -static inline void b43_sdio_free_irq(struct b43_wldev *dev) -{ -} -static inline int b43_sdio_init(void) -{ - return 0; -} -static inline void b43_sdio_exit(void) -{ -} - -#endif /* CONFIG_B43_SDIO */ -#endif /* B43_SDIO_H_ */ diff --git a/drivers/net/wireless/b43/sysfs.c b/drivers/net/wireless/b43/sysfs.c deleted file mode 100644 index 3190493bd..000000000 --- a/drivers/net/wireless/b43/sysfs.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - - Broadcom B43 wireless driver - - SYSFS support routines - - Copyright (c) 2006 Michael Buesch <m@bues.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/capability.h> -#include <linux/io.h> - -#include "b43.h" -#include "sysfs.h" -#include "main.h" -#include "phy_common.h" - -#define GENERIC_FILESIZE 64 - -static int get_integer(const char *buf, size_t count) -{ - char tmp[10 + 1] = { 0 }; - int ret = -EINVAL; - - if (count == 0) - goto out; - count = min_t(size_t, count, 10); - memcpy(tmp, buf, count); - ret = simple_strtol(tmp, NULL, 10); - out: - return ret; -} - -static ssize_t b43_attr_interfmode_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct b43_wldev *wldev = dev_to_b43_wldev(dev); - ssize_t count = 0; - - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - - mutex_lock(&wldev->wl->mutex); - - if (wldev->phy.type != B43_PHYTYPE_G) { - mutex_unlock(&wldev->wl->mutex); - return -ENOSYS; - } - - switch (wldev->phy.g->interfmode) { - case B43_INTERFMODE_NONE: - count = - snprintf(buf, PAGE_SIZE, - "0 (No Interference Mitigation)\n"); - break; - case B43_INTERFMODE_NONWLAN: - count = - snprintf(buf, PAGE_SIZE, - "1 (Non-WLAN Interference Mitigation)\n"); - break; - case B43_INTERFMODE_MANUALWLAN: - count = - snprintf(buf, PAGE_SIZE, - "2 (WLAN Interference Mitigation)\n"); - break; - default: - B43_WARN_ON(1); - } - - mutex_unlock(&wldev->wl->mutex); - - return count; -} - -static ssize_t b43_attr_interfmode_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct b43_wldev *wldev = dev_to_b43_wldev(dev); - int err; - int mode; - - if (!capable(CAP_NET_ADMIN)) - return -EPERM; - - mode = get_integer(buf, count); - switch (mode) { - case 0: - mode = B43_INTERFMODE_NONE; - break; - case 1: - mode = B43_INTERFMODE_NONWLAN; - break; - case 2: - mode = B43_INTERFMODE_MANUALWLAN; - break; - case 3: - mode = B43_INTERFMODE_AUTOWLAN; - break; - default: - return -EINVAL; - } - - mutex_lock(&wldev->wl->mutex); - - if (wldev->phy.ops->interf_mitigation) { - err = wldev->phy.ops->interf_mitigation(wldev, mode); - if (err) { - b43err(wldev->wl, "Interference Mitigation not " - "supported by device\n"); - } - } else - err = -ENOSYS; - - mmiowb(); - mutex_unlock(&wldev->wl->mutex); - - return err ? err : count; -} - -static DEVICE_ATTR(interference, 0644, - b43_attr_interfmode_show, b43_attr_interfmode_store); - -int b43_sysfs_register(struct b43_wldev *wldev) -{ - struct device *dev = wldev->dev->dev; - - B43_WARN_ON(b43_status(wldev) != B43_STAT_INITIALIZED); - - return device_create_file(dev, &dev_attr_interference); -} - -void b43_sysfs_unregister(struct b43_wldev *wldev) -{ - struct device *dev = wldev->dev->dev; - - device_remove_file(dev, &dev_attr_interference); -} diff --git a/drivers/net/wireless/b43/sysfs.h b/drivers/net/wireless/b43/sysfs.h deleted file mode 100644 index 12bda9ef1..000000000 --- a/drivers/net/wireless/b43/sysfs.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef B43_SYSFS_H_ -#define B43_SYSFS_H_ - -struct b43_wldev; - -int b43_sysfs_register(struct b43_wldev *dev); -void b43_sysfs_unregister(struct b43_wldev *dev); - -#endif /* B43_SYSFS_H_ */ diff --git a/drivers/net/wireless/b43/tables.c b/drivers/net/wireless/b43/tables.c deleted file mode 100644 index ea288df8a..000000000 --- a/drivers/net/wireless/b43/tables.c +++ /dev/null @@ -1,466 +0,0 @@ -/* - - Broadcom B43 wireless driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2006, 2006 Michael Buesch <m@bues.ch> - Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "tables.h" -#include "phy_g.h" - - -const u32 b43_tab_rotor[] = { - 0xFEB93FFD, 0xFEC63FFD, /* 0 */ - 0xFED23FFD, 0xFEDF3FFD, - 0xFEEC3FFE, 0xFEF83FFE, - 0xFF053FFE, 0xFF113FFE, - 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */ - 0xFF373FFF, 0xFF443FFF, - 0xFF503FFF, 0xFF5D3FFF, - 0xFF693FFF, 0xFF763FFF, - 0xFF824000, 0xFF8F4000, /* 16 */ - 0xFF9B4000, 0xFFA84000, - 0xFFB54000, 0xFFC14000, - 0xFFCE4000, 0xFFDA4000, - 0xFFE74000, 0xFFF34000, /* 24 */ - 0x00004000, 0x000D4000, - 0x00194000, 0x00264000, - 0x00324000, 0x003F4000, - 0x004B4000, 0x00584000, /* 32 */ - 0x00654000, 0x00714000, - 0x007E4000, 0x008A3FFF, - 0x00973FFF, 0x00A33FFF, - 0x00B03FFF, 0x00BC3FFF, /* 40 */ - 0x00C93FFF, 0x00D63FFF, - 0x00E23FFE, 0x00EF3FFE, - 0x00FB3FFE, 0x01083FFE, - 0x01143FFE, 0x01213FFD, /* 48 */ - 0x012E3FFD, 0x013A3FFD, - 0x01473FFD, -}; - -const u32 b43_tab_retard[] = { - 0xDB93CB87, 0xD666CF64, /* 0 */ - 0xD1FDD358, 0xCDA6D826, - 0xCA38DD9F, 0xC729E2B4, - 0xC469E88E, 0xC26AEE2B, - 0xC0DEF46C, 0xC073FA62, /* 8 */ - 0xC01D00D5, 0xC0760743, - 0xC1560D1E, 0xC2E51369, - 0xC4ED18FF, 0xC7AC1ED7, - 0xCB2823B2, 0xCEFA28D9, /* 16 */ - 0xD2F62D3F, 0xD7BB3197, - 0xDCE53568, 0xE1FE3875, - 0xE7D13B35, 0xED663D35, - 0xF39B3EC4, 0xF98E3FA7, /* 24 */ - 0x00004000, 0x06723FA7, - 0x0C653EC4, 0x129A3D35, - 0x182F3B35, 0x1E023875, - 0x231B3568, 0x28453197, /* 32 */ - 0x2D0A2D3F, 0x310628D9, - 0x34D823B2, 0x38541ED7, - 0x3B1318FF, 0x3D1B1369, - 0x3EAA0D1E, 0x3F8A0743, /* 40 */ - 0x3FE300D5, 0x3F8DFA62, - 0x3F22F46C, 0x3D96EE2B, - 0x3B97E88E, 0x38D7E2B4, - 0x35C8DD9F, 0x325AD826, /* 48 */ - 0x2E03D358, 0x299ACF64, - 0x246DCB87, -}; - -const u16 b43_tab_finefreqa[] = { - 0x0082, 0x0082, 0x0102, 0x0182, /* 0 */ - 0x0202, 0x0282, 0x0302, 0x0382, - 0x0402, 0x0482, 0x0502, 0x0582, - 0x05E2, 0x0662, 0x06E2, 0x0762, - 0x07E2, 0x0842, 0x08C2, 0x0942, /* 16 */ - 0x09C2, 0x0A22, 0x0AA2, 0x0B02, - 0x0B82, 0x0BE2, 0x0C62, 0x0CC2, - 0x0D42, 0x0DA2, 0x0E02, 0x0E62, - 0x0EE2, 0x0F42, 0x0FA2, 0x1002, /* 32 */ - 0x1062, 0x10C2, 0x1122, 0x1182, - 0x11E2, 0x1242, 0x12A2, 0x12E2, - 0x1342, 0x13A2, 0x1402, 0x1442, - 0x14A2, 0x14E2, 0x1542, 0x1582, /* 48 */ - 0x15E2, 0x1622, 0x1662, 0x16C1, - 0x1701, 0x1741, 0x1781, 0x17E1, - 0x1821, 0x1861, 0x18A1, 0x18E1, - 0x1921, 0x1961, 0x19A1, 0x19E1, /* 64 */ - 0x1A21, 0x1A61, 0x1AA1, 0x1AC1, - 0x1B01, 0x1B41, 0x1B81, 0x1BA1, - 0x1BE1, 0x1C21, 0x1C41, 0x1C81, - 0x1CA1, 0x1CE1, 0x1D01, 0x1D41, /* 80 */ - 0x1D61, 0x1DA1, 0x1DC1, 0x1E01, - 0x1E21, 0x1E61, 0x1E81, 0x1EA1, - 0x1EE1, 0x1F01, 0x1F21, 0x1F41, - 0x1F81, 0x1FA1, 0x1FC1, 0x1FE1, /* 96 */ - 0x2001, 0x2041, 0x2061, 0x2081, - 0x20A1, 0x20C1, 0x20E1, 0x2101, - 0x2121, 0x2141, 0x2161, 0x2181, - 0x21A1, 0x21C1, 0x21E1, 0x2201, /* 112 */ - 0x2221, 0x2241, 0x2261, 0x2281, - 0x22A1, 0x22C1, 0x22C1, 0x22E1, - 0x2301, 0x2321, 0x2341, 0x2361, - 0x2361, 0x2381, 0x23A1, 0x23C1, /* 128 */ - 0x23E1, 0x23E1, 0x2401, 0x2421, - 0x2441, 0x2441, 0x2461, 0x2481, - 0x2481, 0x24A1, 0x24C1, 0x24C1, - 0x24E1, 0x2501, 0x2501, 0x2521, /* 144 */ - 0x2541, 0x2541, 0x2561, 0x2561, - 0x2581, 0x25A1, 0x25A1, 0x25C1, - 0x25C1, 0x25E1, 0x2601, 0x2601, - 0x2621, 0x2621, 0x2641, 0x2641, /* 160 */ - 0x2661, 0x2661, 0x2681, 0x2681, - 0x26A1, 0x26A1, 0x26C1, 0x26C1, - 0x26E1, 0x26E1, 0x2701, 0x2701, - 0x2721, 0x2721, 0x2740, 0x2740, /* 176 */ - 0x2760, 0x2760, 0x2780, 0x2780, - 0x2780, 0x27A0, 0x27A0, 0x27C0, - 0x27C0, 0x27E0, 0x27E0, 0x27E0, - 0x2800, 0x2800, 0x2820, 0x2820, /* 192 */ - 0x2820, 0x2840, 0x2840, 0x2840, - 0x2860, 0x2860, 0x2880, 0x2880, - 0x2880, 0x28A0, 0x28A0, 0x28A0, - 0x28C0, 0x28C0, 0x28C0, 0x28E0, /* 208 */ - 0x28E0, 0x28E0, 0x2900, 0x2900, - 0x2900, 0x2920, 0x2920, 0x2920, - 0x2940, 0x2940, 0x2940, 0x2960, - 0x2960, 0x2960, 0x2960, 0x2980, /* 224 */ - 0x2980, 0x2980, 0x29A0, 0x29A0, - 0x29A0, 0x29A0, 0x29C0, 0x29C0, - 0x29C0, 0x29E0, 0x29E0, 0x29E0, - 0x29E0, 0x2A00, 0x2A00, 0x2A00, /* 240 */ - 0x2A00, 0x2A20, 0x2A20, 0x2A20, - 0x2A20, 0x2A40, 0x2A40, 0x2A40, - 0x2A40, 0x2A60, 0x2A60, 0x2A60, -}; - -const u16 b43_tab_finefreqg[] = { - 0x0089, 0x02E9, 0x0409, 0x04E9, /* 0 */ - 0x05A9, 0x0669, 0x0709, 0x0789, - 0x0829, 0x08A9, 0x0929, 0x0989, - 0x0A09, 0x0A69, 0x0AC9, 0x0B29, - 0x0BA9, 0x0BE9, 0x0C49, 0x0CA9, /* 16 */ - 0x0D09, 0x0D69, 0x0DA9, 0x0E09, - 0x0E69, 0x0EA9, 0x0F09, 0x0F49, - 0x0FA9, 0x0FE9, 0x1029, 0x1089, - 0x10C9, 0x1109, 0x1169, 0x11A9, /* 32 */ - 0x11E9, 0x1229, 0x1289, 0x12C9, - 0x1309, 0x1349, 0x1389, 0x13C9, - 0x1409, 0x1449, 0x14A9, 0x14E9, - 0x1529, 0x1569, 0x15A9, 0x15E9, /* 48 */ - 0x1629, 0x1669, 0x16A9, 0x16E8, - 0x1728, 0x1768, 0x17A8, 0x17E8, - 0x1828, 0x1868, 0x18A8, 0x18E8, - 0x1928, 0x1968, 0x19A8, 0x19E8, /* 64 */ - 0x1A28, 0x1A68, 0x1AA8, 0x1AE8, - 0x1B28, 0x1B68, 0x1BA8, 0x1BE8, - 0x1C28, 0x1C68, 0x1CA8, 0x1CE8, - 0x1D28, 0x1D68, 0x1DC8, 0x1E08, /* 80 */ - 0x1E48, 0x1E88, 0x1EC8, 0x1F08, - 0x1F48, 0x1F88, 0x1FE8, 0x2028, - 0x2068, 0x20A8, 0x2108, 0x2148, - 0x2188, 0x21C8, 0x2228, 0x2268, /* 96 */ - 0x22C8, 0x2308, 0x2348, 0x23A8, - 0x23E8, 0x2448, 0x24A8, 0x24E8, - 0x2548, 0x25A8, 0x2608, 0x2668, - 0x26C8, 0x2728, 0x2787, 0x27E7, /* 112 */ - 0x2847, 0x28C7, 0x2947, 0x29A7, - 0x2A27, 0x2AC7, 0x2B47, 0x2BE7, - 0x2CA7, 0x2D67, 0x2E47, 0x2F67, - 0x3247, 0x3526, 0x3646, 0x3726, /* 128 */ - 0x3806, 0x38A6, 0x3946, 0x39E6, - 0x3A66, 0x3AE6, 0x3B66, 0x3BC6, - 0x3C45, 0x3CA5, 0x3D05, 0x3D85, - 0x3DE5, 0x3E45, 0x3EA5, 0x3EE5, /* 144 */ - 0x3F45, 0x3FA5, 0x4005, 0x4045, - 0x40A5, 0x40E5, 0x4145, 0x4185, - 0x41E5, 0x4225, 0x4265, 0x42C5, - 0x4305, 0x4345, 0x43A5, 0x43E5, /* 160 */ - 0x4424, 0x4464, 0x44C4, 0x4504, - 0x4544, 0x4584, 0x45C4, 0x4604, - 0x4644, 0x46A4, 0x46E4, 0x4724, - 0x4764, 0x47A4, 0x47E4, 0x4824, /* 176 */ - 0x4864, 0x48A4, 0x48E4, 0x4924, - 0x4964, 0x49A4, 0x49E4, 0x4A24, - 0x4A64, 0x4AA4, 0x4AE4, 0x4B23, - 0x4B63, 0x4BA3, 0x4BE3, 0x4C23, /* 192 */ - 0x4C63, 0x4CA3, 0x4CE3, 0x4D23, - 0x4D63, 0x4DA3, 0x4DE3, 0x4E23, - 0x4E63, 0x4EA3, 0x4EE3, 0x4F23, - 0x4F63, 0x4FC3, 0x5003, 0x5043, /* 208 */ - 0x5083, 0x50C3, 0x5103, 0x5143, - 0x5183, 0x51E2, 0x5222, 0x5262, - 0x52A2, 0x52E2, 0x5342, 0x5382, - 0x53C2, 0x5402, 0x5462, 0x54A2, /* 224 */ - 0x5502, 0x5542, 0x55A2, 0x55E2, - 0x5642, 0x5682, 0x56E2, 0x5722, - 0x5782, 0x57E1, 0x5841, 0x58A1, - 0x5901, 0x5961, 0x59C1, 0x5A21, /* 240 */ - 0x5AA1, 0x5B01, 0x5B81, 0x5BE1, - 0x5C61, 0x5D01, 0x5D80, 0x5E20, - 0x5EE0, 0x5FA0, 0x6080, 0x61C0, -}; - -const u16 b43_tab_noisea2[] = { - 0x0001, 0x0001, 0x0001, 0xFFFE, - 0xFFFE, 0x3FFF, 0x1000, 0x0393, -}; - -const u16 b43_tab_noisea3[] = { - 0x5E5E, 0x5E5E, 0x5E5E, 0x3F48, - 0x4C4C, 0x4C4C, 0x4C4C, 0x2D36, -}; - -const u16 b43_tab_noiseg1[] = { - 0x013C, 0x01F5, 0x031A, 0x0631, - 0x0001, 0x0001, 0x0001, 0x0001, -}; - -const u16 b43_tab_noiseg2[] = { - 0x5484, 0x3C40, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, -}; - -const u16 b43_tab_noisescalea2[] = { - 0x6767, 0x6767, 0x6767, 0x6767, /* 0 */ - 0x6767, 0x6767, 0x6767, 0x6767, - 0x6767, 0x6767, 0x6767, 0x6767, - 0x6767, 0x6700, 0x6767, 0x6767, - 0x6767, 0x6767, 0x6767, 0x6767, /* 16 */ - 0x6767, 0x6767, 0x6767, 0x6767, - 0x6767, 0x6767, 0x0067, -}; - -const u16 b43_tab_noisescalea3[] = { - 0x2323, 0x2323, 0x2323, 0x2323, /* 0 */ - 0x2323, 0x2323, 0x2323, 0x2323, - 0x2323, 0x2323, 0x2323, 0x2323, - 0x2323, 0x2300, 0x2323, 0x2323, - 0x2323, 0x2323, 0x2323, 0x2323, /* 16 */ - 0x2323, 0x2323, 0x2323, 0x2323, - 0x2323, 0x2323, 0x0023, -}; - -const u16 b43_tab_noisescaleg1[] = { - 0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */ - 0x2F2D, 0x2A2A, 0x2527, 0x1F21, - 0x1A1D, 0x1719, 0x1616, 0x1414, - 0x1414, 0x1400, 0x1414, 0x1614, - 0x1716, 0x1A19, 0x1F1D, 0x2521, /* 16 */ - 0x2A27, 0x2F2A, 0x332D, 0x3B35, - 0x5140, 0x6C62, 0x0077, -}; - -const u16 b43_tab_noisescaleg2[] = { - 0xD8DD, 0xCBD4, 0xBCC0, 0xB6B7, /* 0 */ - 0xB2B0, 0xADAD, 0xA7A9, 0x9FA1, - 0x969B, 0x9195, 0x8F8F, 0x8A8A, - 0x8A8A, 0x8A00, 0x8A8A, 0x8F8A, - 0x918F, 0x9695, 0x9F9B, 0xA7A1, /* 16 */ - 0xADA9, 0xB2AD, 0xB6B0, 0xBCB7, - 0xCBC0, 0xD8D4, 0x00DD, -}; - -const u16 b43_tab_noisescaleg3[] = { - 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 0 */ - 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, - 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, - 0xA4A4, 0xA400, 0xA4A4, 0xA4A4, - 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 16 */ - 0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, - 0xA4A4, 0xA4A4, 0x00A4, -}; - -const u16 b43_tab_sigmasqr1[] = { - 0x007A, 0x0075, 0x0071, 0x006C, /* 0 */ - 0x0067, 0x0063, 0x005E, 0x0059, - 0x0054, 0x0050, 0x004B, 0x0046, - 0x0042, 0x003D, 0x003D, 0x003D, - 0x003D, 0x003D, 0x003D, 0x003D, /* 16 */ - 0x003D, 0x003D, 0x003D, 0x003D, - 0x003D, 0x003D, 0x0000, 0x003D, - 0x003D, 0x003D, 0x003D, 0x003D, - 0x003D, 0x003D, 0x003D, 0x003D, /* 32 */ - 0x003D, 0x003D, 0x003D, 0x003D, - 0x0042, 0x0046, 0x004B, 0x0050, - 0x0054, 0x0059, 0x005E, 0x0063, - 0x0067, 0x006C, 0x0071, 0x0075, /* 48 */ - 0x007A, -}; - -const u16 b43_tab_sigmasqr2[] = { - 0x00DE, 0x00DC, 0x00DA, 0x00D8, /* 0 */ - 0x00D6, 0x00D4, 0x00D2, 0x00CF, - 0x00CD, 0x00CA, 0x00C7, 0x00C4, - 0x00C1, 0x00BE, 0x00BE, 0x00BE, - 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 16 */ - 0x00BE, 0x00BE, 0x00BE, 0x00BE, - 0x00BE, 0x00BE, 0x0000, 0x00BE, - 0x00BE, 0x00BE, 0x00BE, 0x00BE, - 0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 32 */ - 0x00BE, 0x00BE, 0x00BE, 0x00BE, - 0x00C1, 0x00C4, 0x00C7, 0x00CA, - 0x00CD, 0x00CF, 0x00D2, 0x00D4, - 0x00D6, 0x00D8, 0x00DA, 0x00DC, /* 48 */ - 0x00DE, -}; - -const u16 b43_tab_rssiagc1[] = { - 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8, /* 0 */ - 0xFFF8, 0xFFF9, 0xFFFC, 0xFFFE, - 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8, - 0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8, -}; - -const u16 b43_tab_rssiagc2[] = { - 0x0820, 0x0820, 0x0920, 0x0C38, /* 0 */ - 0x0820, 0x0820, 0x0820, 0x0820, - 0x0820, 0x0820, 0x0920, 0x0A38, - 0x0820, 0x0820, 0x0820, 0x0820, - 0x0820, 0x0820, 0x0920, 0x0A38, /* 16 */ - 0x0820, 0x0820, 0x0820, 0x0820, - 0x0820, 0x0820, 0x0920, 0x0A38, - 0x0820, 0x0820, 0x0820, 0x0820, - 0x0820, 0x0820, 0x0920, 0x0A38, /* 32 */ - 0x0820, 0x0820, 0x0820, 0x0820, - 0x0820, 0x0820, 0x0920, 0x0A38, - 0x0820, 0x0820, 0x0820, 0x0820, -}; - -static inline void assert_sizes(void) -{ - BUILD_BUG_ON(B43_TAB_ROTOR_SIZE != ARRAY_SIZE(b43_tab_rotor)); - BUILD_BUG_ON(B43_TAB_RETARD_SIZE != ARRAY_SIZE(b43_tab_retard)); - BUILD_BUG_ON(B43_TAB_FINEFREQA_SIZE != ARRAY_SIZE(b43_tab_finefreqa)); - BUILD_BUG_ON(B43_TAB_FINEFREQG_SIZE != ARRAY_SIZE(b43_tab_finefreqg)); - BUILD_BUG_ON(B43_TAB_NOISEA2_SIZE != ARRAY_SIZE(b43_tab_noisea2)); - BUILD_BUG_ON(B43_TAB_NOISEA3_SIZE != ARRAY_SIZE(b43_tab_noisea3)); - BUILD_BUG_ON(B43_TAB_NOISEG1_SIZE != ARRAY_SIZE(b43_tab_noiseg1)); - BUILD_BUG_ON(B43_TAB_NOISEG2_SIZE != ARRAY_SIZE(b43_tab_noiseg2)); - BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE != - ARRAY_SIZE(b43_tab_noisescalea2)); - BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE != - ARRAY_SIZE(b43_tab_noisescalea3)); - BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE != - ARRAY_SIZE(b43_tab_noisescaleg1)); - BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE != - ARRAY_SIZE(b43_tab_noisescaleg2)); - BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE != - ARRAY_SIZE(b43_tab_noisescaleg3)); - BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr1)); - BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr2)); - BUILD_BUG_ON(B43_TAB_RSSIAGC1_SIZE != ARRAY_SIZE(b43_tab_rssiagc1)); - BUILD_BUG_ON(B43_TAB_RSSIAGC2_SIZE != ARRAY_SIZE(b43_tab_rssiagc2)); -} - -u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset) -{ - struct b43_phy_g *gphy = dev->phy.g; - u16 addr; - - addr = table + offset; - if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) || - (addr - 1 != gphy->ofdmtab_addr)) { - /* The hardware has a different address in memory. Update it. */ - b43_phy_write(dev, B43_PHY_OTABLECTL, addr); - gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ; - } - gphy->ofdmtab_addr = addr; - - return b43_phy_read(dev, B43_PHY_OTABLEI); - - /* Some compiletime assertions... */ - assert_sizes(); -} - -void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table, - u16 offset, u16 value) -{ - struct b43_phy_g *gphy = dev->phy.g; - u16 addr; - - addr = table + offset; - if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) || - (addr - 1 != gphy->ofdmtab_addr)) { - /* The hardware has a different address in memory. Update it. */ - b43_phy_write(dev, B43_PHY_OTABLECTL, addr); - gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE; - } - gphy->ofdmtab_addr = addr; - b43_phy_write(dev, B43_PHY_OTABLEI, value); -} - -u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset) -{ - struct b43_phy_g *gphy = dev->phy.g; - u32 ret; - u16 addr; - - addr = table + offset; - if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) || - (addr - 1 != gphy->ofdmtab_addr)) { - /* The hardware has a different address in memory. Update it. */ - b43_phy_write(dev, B43_PHY_OTABLECTL, addr); - gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ; - } - gphy->ofdmtab_addr = addr; - ret = b43_phy_read(dev, B43_PHY_OTABLEQ); - ret <<= 16; - ret |= b43_phy_read(dev, B43_PHY_OTABLEI); - - return ret; -} - -void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table, - u16 offset, u32 value) -{ - struct b43_phy_g *gphy = dev->phy.g; - u16 addr; - - addr = table + offset; - if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) || - (addr - 1 != gphy->ofdmtab_addr)) { - /* The hardware has a different address in memory. Update it. */ - b43_phy_write(dev, B43_PHY_OTABLECTL, addr); - gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE; - } - gphy->ofdmtab_addr = addr; - - b43_phy_write(dev, B43_PHY_OTABLEI, value); - b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16)); -} - -u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset) -{ - b43_phy_write(dev, B43_PHY_GTABCTL, table + offset); - return b43_phy_read(dev, B43_PHY_GTABDATA); -} - -void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value) -{ - b43_phy_write(dev, B43_PHY_GTABCTL, table + offset); - b43_phy_write(dev, B43_PHY_GTABDATA, value); -} diff --git a/drivers/net/wireless/b43/tables.h b/drivers/net/wireless/b43/tables.h deleted file mode 100644 index 80e73c7cb..000000000 --- a/drivers/net/wireless/b43/tables.h +++ /dev/null @@ -1,34 +0,0 @@ -#ifndef B43_TABLES_H_ -#define B43_TABLES_H_ - -#define B43_TAB_ROTOR_SIZE 53 -extern const u32 b43_tab_rotor[]; -#define B43_TAB_RETARD_SIZE 53 -extern const u32 b43_tab_retard[]; -#define B43_TAB_FINEFREQA_SIZE 256 -extern const u16 b43_tab_finefreqa[]; -#define B43_TAB_FINEFREQG_SIZE 256 -extern const u16 b43_tab_finefreqg[]; -#define B43_TAB_NOISEA2_SIZE 8 -extern const u16 b43_tab_noisea2[]; -#define B43_TAB_NOISEA3_SIZE 8 -extern const u16 b43_tab_noisea3[]; -#define B43_TAB_NOISEG1_SIZE 8 -extern const u16 b43_tab_noiseg1[]; -#define B43_TAB_NOISEG2_SIZE 8 -extern const u16 b43_tab_noiseg2[]; -#define B43_TAB_NOISESCALE_SIZE 27 -extern const u16 b43_tab_noisescalea2[]; -extern const u16 b43_tab_noisescalea3[]; -extern const u16 b43_tab_noisescaleg1[]; -extern const u16 b43_tab_noisescaleg2[]; -extern const u16 b43_tab_noisescaleg3[]; -#define B43_TAB_SIGMASQR_SIZE 53 -extern const u16 b43_tab_sigmasqr1[]; -extern const u16 b43_tab_sigmasqr2[]; -#define B43_TAB_RSSIAGC1_SIZE 16 -extern const u16 b43_tab_rssiagc1[]; -#define B43_TAB_RSSIAGC2_SIZE 48 -extern const u16 b43_tab_rssiagc2[]; - -#endif /* B43_TABLES_H_ */ diff --git a/drivers/net/wireless/b43/tables_lpphy.c b/drivers/net/wireless/b43/tables_lpphy.c deleted file mode 100644 index cff187c56..000000000 --- a/drivers/net/wireless/b43/tables_lpphy.c +++ /dev/null @@ -1,2456 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11a/g LP-PHY and radio device data tables - - Copyright (c) 2009 Michael Buesch <m@bues.ch> - Copyright (c) 2009 Gábor Stefanik <netrolller.3d@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "tables_lpphy.h" -#include "phy_common.h" -#include "phy_lp.h" - - -/* Entry of the 2062/2063 radio init table */ -struct b206x_init_tab_entry { - u16 offset; - u16 value_a; - u16 value_g; - u8 flags; -}; -#define B206X_FLAG_A 0x01 /* Flag: Init in A mode */ -#define B206X_FLAG_G 0x02 /* Flag: Init in G mode */ - -static const struct b206x_init_tab_entry b2062_init_tab[] = { - /* { .offset = B2062_N_COMM1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = 0x0001, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_COMM4, .value_a = 0x0001, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_COMM5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM10, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM11, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM12, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM13, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM14, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_COMM15, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_PDN_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_PDN_CTL1, .value_a = 0x0000, .value_g = 0x00CA, .flags = B206X_FLAG_G, }, - /* { .offset = B2062_N_PDN_CTL2, .value_a = 0x0018, .value_g = 0x0018, .flags = 0, }, */ - { .offset = B2062_N_PDN_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_N_PDN_CTL4, .value_a = 0x0015, .value_g = 0x002A, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_GEN_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_IQ_CALIB, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - { .offset = B2062_N_LGENC, .value_a = 0x00DB, .value_g = 0x00FF, .flags = B206X_FLAG_A, }, - /* { .offset = B2062_N_LGENA_LPF, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_BIAS0, .value_a = 0x0041, .value_g = 0x0041, .flags = 0, }, */ - /* { .offset = B2062_N_LGNEA_BIAS1, .value_a = 0x0002, .value_g = 0x0002, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_CTL0, .value_a = 0x0032, .value_g = 0x0032, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_LGENA_TUNE0, .value_a = 0x00DD, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_LGENA_TUNE1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_LGENA_TUNE2, .value_a = 0x00DD, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_N_LGENA_TUNE3, .value_a = 0x0077, .value_g = 0x00B5, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_N_LGENA_CTL3, .value_a = 0x0000, .value_g = 0x00FF, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_LGENA_CTL4, .value_a = 0x001F, .value_g = 0x001F, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_CTL5, .value_a = 0x0032, .value_g = 0x0032, .flags = 0, }, */ - /* { .offset = B2062_N_LGENA_CTL6, .value_a = 0x0032, .value_g = 0x0032, .flags = 0, }, */ - { .offset = B2062_N_LGENA_CTL7, .value_a = 0x0033, .value_g = 0x0033, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_RXA_CTL0, .value_a = 0x0009, .value_g = 0x0009, .flags = 0, }, */ - { .offset = B2062_N_RXA_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - /* { .offset = B2062_N_RXA_CTL2, .value_a = 0x0018, .value_g = 0x0018, .flags = 0, }, */ - /* { .offset = B2062_N_RXA_CTL3, .value_a = 0x0027, .value_g = 0x0027, .flags = 0, }, */ - /* { .offset = B2062_N_RXA_CTL4, .value_a = 0x0028, .value_g = 0x0028, .flags = 0, }, */ - /* { .offset = B2062_N_RXA_CTL5, .value_a = 0x0007, .value_g = 0x0007, .flags = 0, }, */ - /* { .offset = B2062_N_RXA_CTL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_RXA_CTL7, .value_a = 0x0008, .value_g = 0x0008, .flags = 0, }, */ - { .offset = B2062_N_RXBB_CTL0, .value_a = 0x0082, .value_g = 0x0080, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_RXBB_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_GAIN0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_RXBB_GAIN1, .value_a = 0x0004, .value_g = 0x0004, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_N_RXBB_GAIN2, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_RXBB_GAIN3, .value_a = 0x0011, .value_g = 0x0011, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI0, .value_a = 0x0043, .value_g = 0x0043, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI1, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_CALIB0, .value_a = 0x0010, .value_g = 0x0010, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_CALIB1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_CALIB2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS0, .value_a = 0x0006, .value_g = 0x0006, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS1, .value_a = 0x002A, .value_g = 0x002A, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS2, .value_a = 0x00AA, .value_g = 0x00AA, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS3, .value_a = 0x0021, .value_g = 0x0021, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS4, .value_a = 0x00AA, .value_g = 0x00AA, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_BIAS5, .value_a = 0x0022, .value_g = 0x0022, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI2, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI3, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI4, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2062_N_RXBB_RSSI5, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL0, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL2, .value_a = 0x0084, .value_g = 0x0084, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_N_TX_CTL4, .value_a = 0x0003, .value_g = 0x0003, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_N_TX_CTL5, .value_a = 0x0002, .value_g = 0x0002, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_TX_CTL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL7, .value_a = 0x0058, .value_g = 0x0058, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL8, .value_a = 0x0082, .value_g = 0x0082, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TX_CTL_A, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TX_GC2G, .value_a = 0x00FF, .value_g = 0x00FF, .flags = 0, }, */ - /* { .offset = B2062_N_TX_GC5G, .value_a = 0x00FF, .value_g = 0x00FF, .flags = 0, }, */ - { .offset = B2062_N_TX_TUNE, .value_a = 0x0088, .value_g = 0x001B, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_N_TX_PAD, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2062_N_TX_PGA, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2062_N_TX_PADAUX, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2062_N_TX_PGAAUX, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2062_N_TSSI_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TSSI_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TSSI_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_IQ_CALIB_CTL0, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2062_N_IQ_CALIB_CTL1, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_N_IQ_CALIB_CTL2, .value_a = 0x0032, .value_g = 0x0032, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_TS, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_CTL1, .value_a = 0x0015, .value_g = 0x0015, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_CTL2, .value_a = 0x000F, .value_g = 0x000F, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_CTL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_DBG0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_DBG1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_DBG2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_CALIB_DBG3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_PSENSE_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_PSENSE_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_PSENSE_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_N_TEST_BUF0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RADIO_ID_CODE, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_COMM4, .value_a = 0x0001, .value_g = 0x0000, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_COMM5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM10, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM11, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM12, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM13, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM14, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_COMM15, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_PDS_CTL0, .value_a = 0x00FF, .value_g = 0x00FF, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_PDS_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_PDS_CTL2, .value_a = 0x008E, .value_g = 0x008E, .flags = 0, }, */ - /* { .offset = B2062_S_PDS_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_BG_CTL0, .value_a = 0x0006, .value_g = 0x0006, .flags = 0, }, */ - /* { .offset = B2062_S_BG_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_BG_CTL2, .value_a = 0x0011, .value_g = 0x0011, .flags = 0, }, */ - { .offset = B2062_S_LGENG_CTL0, .value_a = 0x00F8, .value_g = 0x00D8, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_LGENG_CTL1, .value_a = 0x003C, .value_g = 0x0024, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_LGENG_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_LGENG_CTL3, .value_a = 0x0041, .value_g = 0x0041, .flags = 0, }, */ - /* { .offset = B2062_S_LGENG_CTL4, .value_a = 0x0002, .value_g = 0x0002, .flags = 0, }, */ - /* { .offset = B2062_S_LGENG_CTL5, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2062_S_LGENG_CTL6, .value_a = 0x0022, .value_g = 0x0022, .flags = 0, }, */ - /* { .offset = B2062_S_LGENG_CTL7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_LGENG_CTL8, .value_a = 0x0088, .value_g = 0x0080, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_LGENG_CTL9, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - { .offset = B2062_S_LGENG_CTL10, .value_a = 0x0088, .value_g = 0x0080, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_LGENG_CTL11, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL0, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL1, .value_a = 0x0007, .value_g = 0x0007, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL2, .value_a = 0x00AF, .value_g = 0x00AF, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL3, .value_a = 0x0012, .value_g = 0x0012, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL4, .value_a = 0x000B, .value_g = 0x000B, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL5, .value_a = 0x005F, .value_g = 0x005F, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL7, .value_a = 0x0040, .value_g = 0x0040, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL8, .value_a = 0x0052, .value_g = 0x0052, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL9, .value_a = 0x0026, .value_g = 0x0026, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL10, .value_a = 0x0003, .value_g = 0x0003, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL11, .value_a = 0x0036, .value_g = 0x0036, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL12, .value_a = 0x0057, .value_g = 0x0057, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL13, .value_a = 0x0011, .value_g = 0x0011, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL14, .value_a = 0x0075, .value_g = 0x0075, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL15, .value_a = 0x00B4, .value_g = 0x00B4, .flags = 0, }, */ - /* { .offset = B2062_S_REFPLL_CTL16, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL0, .value_a = 0x0098, .value_g = 0x0098, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL1, .value_a = 0x0010, .value_g = 0x0010, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RFPLL_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL5, .value_a = 0x0043, .value_g = 0x0043, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL6, .value_a = 0x0047, .value_g = 0x0047, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL7, .value_a = 0x000C, .value_g = 0x000C, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL8, .value_a = 0x0011, .value_g = 0x0011, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL9, .value_a = 0x0011, .value_g = 0x0011, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL10, .value_a = 0x000E, .value_g = 0x000E, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL11, .value_a = 0x0008, .value_g = 0x0008, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL12, .value_a = 0x0033, .value_g = 0x0033, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL13, .value_a = 0x000A, .value_g = 0x000A, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL14, .value_a = 0x0006, .value_g = 0x0006, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RFPLL_CTL15, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL16, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL17, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL18, .value_a = 0x003E, .value_g = 0x003E, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL19, .value_a = 0x0013, .value_g = 0x0013, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RFPLL_CTL20, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL21, .value_a = 0x0062, .value_g = 0x0062, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL22, .value_a = 0x0007, .value_g = 0x0007, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL23, .value_a = 0x0016, .value_g = 0x0016, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL24, .value_a = 0x005C, .value_g = 0x005C, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL25, .value_a = 0x0095, .value_g = 0x0095, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RFPLL_CTL26, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL27, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL28, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RFPLL_CTL29, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL30, .value_a = 0x00A0, .value_g = 0x00A0, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL31, .value_a = 0x0004, .value_g = 0x0004, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RFPLL_CTL32, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2062_S_RFPLL_CTL33, .value_a = 0x00CC, .value_g = 0x00CC, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2062_S_RFPLL_CTL34, .value_a = 0x0007, .value_g = 0x0007, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2062_S_RXG_CNT0, .value_a = 0x0010, .value_g = 0x0010, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT5, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT6, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT7, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - { .offset = B2062_S_RXG_CNT8, .value_a = 0x000F, .value_g = 0x000F, .flags = B206X_FLAG_A, }, - /* { .offset = B2062_S_RXG_CNT9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT10, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT11, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT12, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT13, .value_a = 0x0044, .value_g = 0x0044, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT14, .value_a = 0x00A0, .value_g = 0x00A0, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT15, .value_a = 0x0004, .value_g = 0x0004, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT16, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2062_S_RXG_CNT17, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ -}; - -static const struct b206x_init_tab_entry b2063_init_tab[] = { - { .offset = B2063_COMM1, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - /* { .offset = B2063_COMM2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_COMM10, .value_a = 0x0001, .value_g = 0x0000, .flags = B206X_FLAG_A, }, - /* { .offset = B2063_COMM11, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM12, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM13, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_COMM14, .value_a = 0x0006, .value_g = 0x0006, .flags = 0, }, */ - /* { .offset = B2063_COMM15, .value_a = 0x000f, .value_g = 0x000f, .flags = 0, }, */ - { .offset = B2063_COMM16, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM17, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM18, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM19, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM20, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM21, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM22, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM23, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - { .offset = B2063_COMM24, .value_a = 0x0000, .value_g = 0x0000, .flags = B206X_FLAG_G, }, - /* { .offset = B2063_PWR_SWITCH_CTL, .value_a = 0x007f, .value_g = 0x007f, .flags = 0, }, */ - /* { .offset = B2063_PLL_SP1, .value_a = 0x003f, .value_g = 0x003f, .flags = 0, }, */ - /* { .offset = B2063_PLL_SP2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_LOGEN_SP1, .value_a = 0x00e8, .value_g = 0x00d4, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2063_LOGEN_SP2, .value_a = 0x00a7, .value_g = 0x0053, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_LOGEN_SP3, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - { .offset = B2063_LOGEN_SP4, .value_a = 0x00f0, .value_g = 0x000f, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_LOGEN_SP5, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - { .offset = B2063_G_RX_SP1, .value_a = 0x001f, .value_g = 0x005e, .flags = B206X_FLAG_G, }, - { .offset = B2063_G_RX_SP2, .value_a = 0x007f, .value_g = 0x007e, .flags = B206X_FLAG_G, }, - { .offset = B2063_G_RX_SP3, .value_a = 0x0030, .value_g = 0x00f0, .flags = B206X_FLAG_G, }, - /* { .offset = B2063_G_RX_SP4, .value_a = 0x0035, .value_g = 0x0035, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SP5, .value_a = 0x003f, .value_g = 0x003f, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SP6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_G_RX_SP7, .value_a = 0x007f, .value_g = 0x007f, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_G_RX_SP8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SP9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_G_RX_SP10, .value_a = 0x000c, .value_g = 0x000c, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_G_RX_SP11, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_A_RX_SP1, .value_a = 0x003c, .value_g = 0x003f, .flags = B206X_FLAG_A, }, - { .offset = B2063_A_RX_SP2, .value_a = 0x00fc, .value_g = 0x00fe, .flags = B206X_FLAG_A, }, - /* { .offset = B2063_A_RX_SP3, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SP4, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SP5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SP6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_A_RX_SP7, .value_a = 0x0008, .value_g = 0x0008, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_RX_BB_SP1, .value_a = 0x000f, .value_g = 0x000f, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_SP2, .value_a = 0x0022, .value_g = 0x0022, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_SP3, .value_a = 0x00a8, .value_g = 0x00a8, .flags = 0, }, */ - { .offset = B2063_RX_BB_SP4, .value_a = 0x0060, .value_g = 0x0060, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_RX_BB_SP5, .value_a = 0x0011, .value_g = 0x0011, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_SP6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_SP7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_RX_BB_SP8, .value_a = 0x0030, .value_g = 0x0030, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_TX_RF_SP1, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP2, .value_a = 0x0003, .value_g = 0x0003, .flags = 0, }, */ - { .offset = B2063_TX_RF_SP3, .value_a = 0x000c, .value_g = 0x000b, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2063_TX_RF_SP4, .value_a = 0x0010, .value_g = 0x000f, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_TX_RF_SP5, .value_a = 0x000f, .value_g = 0x000f, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP6, .value_a = 0x0080, .value_g = 0x0080, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP7, .value_a = 0x0068, .value_g = 0x0068, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP8, .value_a = 0x0068, .value_g = 0x0068, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP9, .value_a = 0x0080, .value_g = 0x0080, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP10, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP11, .value_a = 0x0003, .value_g = 0x0003, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP12, .value_a = 0x0038, .value_g = 0x0038, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP13, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP14, .value_a = 0x0038, .value_g = 0x0038, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP15, .value_a = 0x00c0, .value_g = 0x00c0, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP16, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_SP17, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - { .offset = B2063_PA_SP1, .value_a = 0x003d, .value_g = 0x00fd, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_PA_SP2, .value_a = 0x000c, .value_g = 0x000c, .flags = 0, }, */ - /* { .offset = B2063_PA_SP3, .value_a = 0x0096, .value_g = 0x0096, .flags = 0, }, */ - /* { .offset = B2063_PA_SP4, .value_a = 0x005a, .value_g = 0x005a, .flags = 0, }, */ - /* { .offset = B2063_PA_SP5, .value_a = 0x007f, .value_g = 0x007f, .flags = 0, }, */ - /* { .offset = B2063_PA_SP6, .value_a = 0x007f, .value_g = 0x007f, .flags = 0, }, */ - /* { .offset = B2063_PA_SP7, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - { .offset = B2063_TX_BB_SP1, .value_a = 0x0002, .value_g = 0x0002, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_TX_BB_SP2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_BB_SP3, .value_a = 0x0030, .value_g = 0x0030, .flags = 0, }, */ - /* { .offset = B2063_REG_SP1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_BANDGAP_CTL1, .value_a = 0x0056, .value_g = 0x0056, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_BANDGAP_CTL2, .value_a = 0x0006, .value_g = 0x0006, .flags = 0, }, */ - /* { .offset = B2063_LPO_CTL1, .value_a = 0x000e, .value_g = 0x000e, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL1, .value_a = 0x007e, .value_g = 0x007e, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL2, .value_a = 0x0015, .value_g = 0x0015, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL3, .value_a = 0x000f, .value_g = 0x000f, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RC_CALIB_CTL10, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_CALNRST, .value_a = 0x0004, .value_g = 0x0004, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_IN_PLL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_IN_PLL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_CP1, .value_a = 0x00cf, .value_g = 0x00cf, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_CP2, .value_a = 0x0059, .value_g = 0x0059, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_CP3, .value_a = 0x0007, .value_g = 0x0007, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_CP4, .value_a = 0x0042, .value_g = 0x0042, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_LF1, .value_a = 0x00db, .value_g = 0x00db, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_LF2, .value_a = 0x0094, .value_g = 0x0094, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_LF3, .value_a = 0x0028, .value_g = 0x0028, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_LF4, .value_a = 0x0063, .value_g = 0x0063, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_SG1, .value_a = 0x0007, .value_g = 0x0007, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_SG2, .value_a = 0x00d3, .value_g = 0x00d3, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_SG3, .value_a = 0x00b1, .value_g = 0x00b1, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_SG4, .value_a = 0x003b, .value_g = 0x003b, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_SG5, .value_a = 0x0006, .value_g = 0x0006, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO1, .value_a = 0x0058, .value_g = 0x0058, .flags = 0, }, */ - { .offset = B2063_PLL_JTAG_PLL_VCO2, .value_a = 0x00f7, .value_g = 0x00f7, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB3, .value_a = 0x0002, .value_g = 0x0002, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB5, .value_a = 0x0009, .value_g = 0x0009, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB6, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB7, .value_a = 0x0016, .value_g = 0x0016, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB8, .value_a = 0x006b, .value_g = 0x006b, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_VCO_CALIB10, .value_a = 0x00b3, .value_g = 0x00b3, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_XTAL_12, .value_a = 0x0004, .value_g = 0x0004, .flags = 0, }, */ - /* { .offset = B2063_PLL_JTAG_PLL_XTAL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_ACL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_ACL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_ACL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_ACL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_ACL5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_INPUTS, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_WAITCNT, .value_a = 0x0002, .value_g = 0x0002, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVR1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVR2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL1, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL2, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL3, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL4, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL5, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL6, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_OVAL7, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CALVLD1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CALVLD2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LO_CALIB_CVAL7, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_CALIB_EN, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_PEAKDET1, .value_a = 0x00ff, .value_g = 0x00ff, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_RCCR1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_VCOBUF1, .value_a = 0x0060, .value_g = 0x0060, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_MIXER1, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_MIXER2, .value_a = 0x000c, .value_g = 0x000c, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_BUF1, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_BUF2, .value_a = 0x000c, .value_g = 0x000c, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_DIV1, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_DIV2, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_DIV3, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_CBUFRX1, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_CBUFRX2, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_CBUFTX1, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_CBUFTX2, .value_a = 0x0066, .value_g = 0x0066, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_IDAC1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_SPARE1, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_SPARE2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_LOGEN_SPARE3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_1ST1, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_G_RX_1ST2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_1ST3, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND1, .value_a = 0x0030, .value_g = 0x0030, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND2, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND3, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND5, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND7, .value_a = 0x0035, .value_g = 0x0035, .flags = 0, }, */ - /* { .offset = B2063_G_RX_2ND8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PS1, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PS2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PS3, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PS4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PS5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_MIX1, .value_a = 0x0044, .value_g = 0x0044, .flags = 0, }, */ - /* { .offset = B2063_G_RX_MIX2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_G_RX_MIX3, .value_a = 0x0071, .value_g = 0x0071, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2063_G_RX_MIX4, .value_a = 0x0071, .value_g = 0x0071, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_G_RX_MIX5, .value_a = 0x0003, .value_g = 0x0003, .flags = 0, }, */ - /* { .offset = B2063_G_RX_MIX6, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_G_RX_MIX7, .value_a = 0x0044, .value_g = 0x0044, .flags = 0, }, */ - /* { .offset = B2063_G_RX_MIX8, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2063_G_RX_PDET1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SPARES1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SPARES2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_G_RX_SPARES3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_1ST1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_A_RX_1ST2, .value_a = 0x00f0, .value_g = 0x0030, .flags = B206X_FLAG_A, }, - /* { .offset = B2063_A_RX_1ST3, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_A_RX_1ST4, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_A_RX_1ST5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND1, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND4, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_2ND7, .value_a = 0x0005, .value_g = 0x0005, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PS1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PS2, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PS3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PS4, .value_a = 0x0033, .value_g = 0x0033, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PS5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_A_RX_PS6, .value_a = 0x0077, .value_g = 0x0077, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_A_RX_MIX1, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_A_RX_MIX2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_MIX3, .value_a = 0x0044, .value_g = 0x0044, .flags = 0, }, */ - { .offset = B2063_A_RX_MIX4, .value_a = 0x0003, .value_g = 0x0003, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2063_A_RX_MIX5, .value_a = 0x000f, .value_g = 0x000f, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - { .offset = B2063_A_RX_MIX6, .value_a = 0x000f, .value_g = 0x000f, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_A_RX_MIX7, .value_a = 0x0044, .value_g = 0x0044, .flags = 0, }, */ - /* { .offset = B2063_A_RX_MIX8, .value_a = 0x0001, .value_g = 0x0001, .flags = 0, }, */ - /* { .offset = B2063_A_RX_PWRDET1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SPARE1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SPARE2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_A_RX_SPARE3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_RX_TIA_CTL1, .value_a = 0x0077, .value_g = 0x0077, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_RX_TIA_CTL2, .value_a = 0x0058, .value_g = 0x0058, .flags = 0, }, */ - { .offset = B2063_RX_TIA_CTL3, .value_a = 0x0077, .value_g = 0x0077, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_RX_TIA_CTL4, .value_a = 0x0058, .value_g = 0x0058, .flags = 0, }, */ - /* { .offset = B2063_RX_TIA_CTL5, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RX_TIA_CTL6, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL1, .value_a = 0x0074, .value_g = 0x0074, .flags = 0, }, */ - { .offset = B2063_RX_BB_CTL2, .value_a = 0x0004, .value_g = 0x0004, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_RX_BB_CTL3, .value_a = 0x00a2, .value_g = 0x00a2, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL4, .value_a = 0x00aa, .value_g = 0x00aa, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL5, .value_a = 0x0024, .value_g = 0x0024, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL6, .value_a = 0x00a9, .value_g = 0x00a9, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL7, .value_a = 0x0028, .value_g = 0x0028, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL8, .value_a = 0x0010, .value_g = 0x0010, .flags = 0, }, */ - /* { .offset = B2063_RX_BB_CTL9, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL1, .value_a = 0x0080, .value_g = 0x0080, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_IDAC_LO_RF_I, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_IDAC_LO_RF_Q, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_IDAC_LO_BB_I, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_IDAC_LO_BB_Q, .value_a = 0x0088, .value_g = 0x0088, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL2, .value_a = 0x0080, .value_g = 0x0080, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL3, .value_a = 0x0038, .value_g = 0x0038, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL4, .value_a = 0x00b8, .value_g = 0x00b8, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL5, .value_a = 0x0080, .value_g = 0x0080, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL6, .value_a = 0x0038, .value_g = 0x0038, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL7, .value_a = 0x0078, .value_g = 0x0078, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL8, .value_a = 0x00c0, .value_g = 0x00c0, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL9, .value_a = 0x0003, .value_g = 0x0003, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL10, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL14, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_RF_CTL15, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_PA_CTL1, .value_a = 0x0000, .value_g = 0x0004, .flags = B206X_FLAG_A, }, - /* { .offset = B2063_PA_CTL2, .value_a = 0x000c, .value_g = 0x000c, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL3, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL4, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL5, .value_a = 0x0096, .value_g = 0x0096, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL6, .value_a = 0x0077, .value_g = 0x0077, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL7, .value_a = 0x005a, .value_g = 0x005a, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL8, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL9, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL10, .value_a = 0x0021, .value_g = 0x0021, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL11, .value_a = 0x0070, .value_g = 0x0070, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL12, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_PA_CTL13, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_BB_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_BB_CTL2, .value_a = 0x00b3, .value_g = 0x00b3, .flags = 0, }, */ - /* { .offset = B2063_TX_BB_CTL3, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2063_TX_BB_CTL4, .value_a = 0x000b, .value_g = 0x000b, .flags = 0, }, */ - /* { .offset = B2063_GPIO_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - { .offset = B2063_VREG_CTL1, .value_a = 0x0003, .value_g = 0x0003, .flags = B206X_FLAG_A | B206X_FLAG_G, }, - /* { .offset = B2063_AMUX_CTL1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_IQ_CALIB_GVAR, .value_a = 0x00b3, .value_g = 0x00b3, .flags = 0, }, */ - /* { .offset = B2063_IQ_CALIB_CTL1, .value_a = 0x0055, .value_g = 0x0055, .flags = 0, }, */ - /* { .offset = B2063_IQ_CALIB_CTL2, .value_a = 0x0030, .value_g = 0x0030, .flags = 0, }, */ - /* { .offset = B2063_TEMPSENSE_CTL1, .value_a = 0x0046, .value_g = 0x0046, .flags = 0, }, */ - /* { .offset = B2063_TEMPSENSE_CTL2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_RX_LOOPBACK1, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_TX_RX_LOOPBACK2, .value_a = 0x0000, .value_g = 0x0000, .flags = 0, }, */ - /* { .offset = B2063_EXT_TSSI_CTL1, .value_a = 0x0021, .value_g = 0x0021, .flags = 0, }, */ - /* { .offset = B2063_EXT_TSSI_CTL2, .value_a = 0x0023, .value_g = 0x0023, .flags = 0, }, */ - /* { .offset = B2063_AFE_CTL , .value_a = 0x0002, .value_g = 0x0002, .flags = 0, }, */ -}; - -void b2062_upload_init_table(struct b43_wldev *dev) -{ - const struct b206x_init_tab_entry *e; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(b2062_init_tab); i++) { - e = &b2062_init_tab[i]; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (!(e->flags & B206X_FLAG_G)) - continue; - b43_radio_write(dev, e->offset, e->value_g); - } else { - if (!(e->flags & B206X_FLAG_A)) - continue; - b43_radio_write(dev, e->offset, e->value_a); - } - } -} - -void b2063_upload_init_table(struct b43_wldev *dev) -{ - const struct b206x_init_tab_entry *e; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(b2063_init_tab); i++) { - e = &b2063_init_tab[i]; - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (!(e->flags & B206X_FLAG_G)) - continue; - b43_radio_write(dev, e->offset, e->value_g); - } else { - if (!(e->flags & B206X_FLAG_A)) - continue; - b43_radio_write(dev, e->offset, e->value_a); - } - } -} - -u32 b43_lptab_read(struct b43_wldev *dev, u32 offset) -{ - u32 type, value; - - type = offset & B43_LPTAB_TYPEMASK; - offset &= ~B43_LPTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - switch (type) { - case B43_LPTAB_8BIT: - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_LPPHY_TABLEDATALO) & 0xFF; - break; - case B43_LPTAB_16BIT: - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_LPPHY_TABLEDATALO); - break; - case B43_LPTAB_32BIT: - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_LPPHY_TABLEDATAHI); - value <<= 16; - value |= b43_phy_read(dev, B43_LPPHY_TABLEDATALO); - break; - default: - B43_WARN_ON(1); - value = 0; - } - - return value; -} - -void b43_lptab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data) -{ - u32 type; - u8 *data = _data; - unsigned int i; - - type = offset & B43_LPTAB_TYPEMASK; - offset &= ~B43_LPTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_LPTAB_8BIT: - *data = b43_phy_read(dev, B43_LPPHY_TABLEDATALO) & 0xFF; - data++; - break; - case B43_LPTAB_16BIT: - *((u16 *)data) = b43_phy_read(dev, B43_LPPHY_TABLEDATALO); - data += 2; - break; - case B43_LPTAB_32BIT: - *((u32 *)data) = b43_phy_read(dev, B43_LPPHY_TABLEDATAHI); - *((u32 *)data) <<= 16; - *((u32 *)data) |= b43_phy_read(dev, B43_LPPHY_TABLEDATALO); - data += 4; - break; - default: - B43_WARN_ON(1); - } - } -} - -void b43_lptab_write(struct b43_wldev *dev, u32 offset, u32 value) -{ - u32 type; - - type = offset & B43_LPTAB_TYPEMASK; - offset &= ~B43_LPTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - switch (type) { - case B43_LPTAB_8BIT: - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - case B43_LPTAB_16BIT: - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - case B43_LPTAB_32BIT: - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_LPPHY_TABLEDATAHI, value >> 16); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - default: - B43_WARN_ON(1); - } -} - -void b43_lptab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data) -{ - u32 type, value; - const u8 *data = _data; - unsigned int i; - - type = offset & B43_LPTAB_TYPEMASK; - offset &= ~B43_LPTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_LPPHY_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_LPTAB_8BIT: - value = *data; - data++; - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - case B43_LPTAB_16BIT: - value = *((u16 *)data); - data += 2; - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - case B43_LPTAB_32BIT: - value = *((u32 *)data); - data += 4; - b43_phy_write(dev, B43_LPPHY_TABLEDATAHI, value >> 16); - b43_phy_write(dev, B43_LPPHY_TABLEDATALO, value); - break; - default: - B43_WARN_ON(1); - } - } -} - -static const u8 lpphy_min_sig_sq_table[] = { - 0xde, 0xdc, 0xda, 0xd8, 0xd6, 0xd4, 0xd2, 0xcf, 0xcd, - 0xca, 0xc7, 0xc4, 0xc1, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, - 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0x00, - 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, - 0xbe, 0xbe, 0xbe, 0xbe, 0xc1, 0xc4, 0xc7, 0xca, 0xcd, - 0xcf, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde, -}; - -static const u16 lpphy_rev01_noise_scale_table[] = { - 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, - 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa400, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, - 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0x00a4, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4c00, 0x2d36, - 0x0000, 0x0000, 0x4c00, 0x2d36, -}; - -static const u16 lpphy_rev2plus_noise_scale_table[] = { - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x0000, - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, - 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, - 0x00a4, -}; - -static const u16 lpphy_crs_gain_nft_table[] = { - 0x0366, 0x036a, 0x036f, 0x0364, 0x0367, 0x036d, 0x0374, 0x037f, 0x036f, - 0x037b, 0x038a, 0x0378, 0x0367, 0x036d, 0x0375, 0x0381, 0x0374, 0x0381, - 0x0392, 0x03a9, 0x03c4, 0x03e1, 0x0001, 0x001f, 0x0040, 0x005e, 0x007f, - 0x009e, 0x00bd, 0x00dd, 0x00fd, 0x011d, 0x013d, -}; - -static const u16 lpphy_rev01_filter_control_table[] = { - 0xa0fc, 0x10fc, 0x10db, 0x20b7, 0xff93, 0x10bf, 0x109b, 0x2077, 0xff53, - 0x0127, -}; - -static const u32 lpphy_rev2plus_filter_control_table[] = { - 0x000141fc, 0x000021fc, 0x000021b7, 0x0000416f, 0x0001ff27, 0x0000217f, - 0x00002137, 0x000040ef, 0x0001fea7, 0x0000024f, -}; - -static const u32 lpphy_rev01_ps_control_table[] = { - 0x00010000, 0x000000a0, 0x00040000, 0x00000048, 0x08080101, 0x00000080, - 0x08080101, 0x00000040, 0x08080101, 0x000000c0, 0x08a81501, 0x000000c0, - 0x0fe8fd01, 0x000000c0, 0x08300105, 0x000000c0, 0x08080201, 0x000000c0, - 0x08280205, 0x000000c0, 0xe80802fe, 0x000000c7, 0x28080206, 0x000000c0, - 0x08080202, 0x000000c0, 0x0ba87602, 0x000000c0, 0x1068013d, 0x000000c0, - 0x10280105, 0x000000c0, 0x08880102, 0x000000c0, 0x08280106, 0x000000c0, - 0xe80801fd, 0x000000c7, 0xa8080115, 0x000000c0, -}; - -static const u32 lpphy_rev2plus_ps_control_table[] = { - 0x00e38e08, 0x00e08e38, 0x00000000, 0x00000000, 0x00000000, 0x00002080, - 0x00006180, 0x00003002, 0x00000040, 0x00002042, 0x00180047, 0x00080043, - 0x00000041, 0x000020c1, 0x00046006, 0x00042002, 0x00040000, 0x00002003, - 0x00180006, 0x00080002, -}; - -static const u8 lpphy_pll_fraction_table[] = { - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x80, - 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, -}; - -static const u16 lpphy_iqlo_cal_table[] = { - 0x0200, 0x0300, 0x0400, 0x0600, 0x0800, 0x0b00, 0x1000, 0x1001, 0x1002, - 0x1003, 0x1004, 0x1005, 0x1006, 0x1007, 0x1707, 0x2007, 0x2d07, 0x4007, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0200, 0x0300, 0x0400, 0x0600, - 0x0800, 0x0b00, 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, - 0x1007, 0x1707, 0x2007, 0x2d07, 0x4007, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u16 lpphy_rev0_ofdm_cck_gain_table[] = { - 0x0001, 0x0001, 0x0001, 0x0001, 0x1001, 0x2001, 0x3001, 0x4001, 0x5001, - 0x6001, 0x7001, 0x7011, 0x7021, 0x2035, 0x2045, 0x2055, 0x2065, 0x2075, - 0x006d, 0x007d, 0x014d, 0x015d, 0x115d, 0x035d, 0x135d, 0x055d, 0x155d, - 0x0d5d, 0x1d5d, 0x2d5d, 0x555d, 0x655d, 0x755d, -}; - -static const u16 lpphy_rev1_ofdm_cck_gain_table[] = { - 0x5000, 0x6000, 0x7000, 0x0001, 0x1001, 0x2001, 0x3001, 0x4001, 0x5001, - 0x6001, 0x7001, 0x7011, 0x7021, 0x2035, 0x2045, 0x2055, 0x2065, 0x2075, - 0x006d, 0x007d, 0x014d, 0x015d, 0x115d, 0x035d, 0x135d, 0x055d, 0x155d, - 0x0d5d, 0x1d5d, 0x2d5d, 0x555d, 0x655d, 0x755d, -}; - -static const u16 lpphy_gain_delta_table[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u32 lpphy_tx_power_control_table[] = { - 0x00000050, 0x0000004f, 0x0000004e, 0x0000004d, 0x0000004c, 0x0000004b, - 0x0000004a, 0x00000049, 0x00000048, 0x00000047, 0x00000046, 0x00000045, - 0x00000044, 0x00000043, 0x00000042, 0x00000041, 0x00000040, 0x0000003f, - 0x0000003e, 0x0000003d, 0x0000003c, 0x0000003b, 0x0000003a, 0x00000039, - 0x00000038, 0x00000037, 0x00000036, 0x00000035, 0x00000034, 0x00000033, - 0x00000032, 0x00000031, 0x00000030, 0x0000002f, 0x0000002e, 0x0000002d, - 0x0000002c, 0x0000002b, 0x0000002a, 0x00000029, 0x00000028, 0x00000027, - 0x00000026, 0x00000025, 0x00000024, 0x00000023, 0x00000022, 0x00000021, - 0x00000020, 0x0000001f, 0x0000001e, 0x0000001d, 0x0000001c, 0x0000001b, - 0x0000001a, 0x00000019, 0x00000018, 0x00000017, 0x00000016, 0x00000015, - 0x00000014, 0x00000013, 0x00000012, 0x00000011, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x000075a0, 0x000075a0, 0x000075a1, 0x000075a1, 0x000075a2, 0x000075a2, - 0x000075a3, 0x000075a3, 0x000074b0, 0x000074b0, 0x000074b1, 0x000074b1, - 0x000074b2, 0x000074b2, 0x000074b3, 0x000074b3, 0x00006d20, 0x00006d20, - 0x00006d21, 0x00006d21, 0x00006d22, 0x00006d22, 0x00006d23, 0x00006d23, - 0x00004660, 0x00004660, 0x00004661, 0x00004661, 0x00004662, 0x00004662, - 0x00004663, 0x00004663, 0x00003e60, 0x00003e60, 0x00003e61, 0x00003e61, - 0x00003e62, 0x00003e62, 0x00003e63, 0x00003e63, 0x00003660, 0x00003660, - 0x00003661, 0x00003661, 0x00003662, 0x00003662, 0x00003663, 0x00003663, - 0x00002e60, 0x00002e60, 0x00002e61, 0x00002e61, 0x00002e62, 0x00002e62, - 0x00002e63, 0x00002e63, 0x00002660, 0x00002660, 0x00002661, 0x00002661, - 0x00002662, 0x00002662, 0x00002663, 0x00002663, 0x000025e0, 0x000025e0, - 0x000025e1, 0x000025e1, 0x000025e2, 0x000025e2, 0x000025e3, 0x000025e3, - 0x00001de0, 0x00001de0, 0x00001de1, 0x00001de1, 0x00001de2, 0x00001de2, - 0x00001de3, 0x00001de3, 0x00001d60, 0x00001d60, 0x00001d61, 0x00001d61, - 0x00001d62, 0x00001d62, 0x00001d63, 0x00001d63, 0x00001560, 0x00001560, - 0x00001561, 0x00001561, 0x00001562, 0x00001562, 0x00001563, 0x00001563, - 0x00000d60, 0x00000d60, 0x00000d61, 0x00000d61, 0x00000d62, 0x00000d62, - 0x00000d63, 0x00000d63, 0x00000ce0, 0x00000ce0, 0x00000ce1, 0x00000ce1, - 0x00000ce2, 0x00000ce2, 0x00000ce3, 0x00000ce3, 0x00000e10, 0x00000e10, - 0x00000e11, 0x00000e11, 0x00000e12, 0x00000e12, 0x00000e13, 0x00000e13, - 0x00000bf0, 0x00000bf0, 0x00000bf1, 0x00000bf1, 0x00000bf2, 0x00000bf2, - 0x00000bf3, 0x00000bf3, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, - 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x000000ff, 0x000002fc, - 0x0000fa08, 0x00000305, 0x00000206, 0x00000304, 0x0000fb04, 0x0000fcff, - 0x000005fb, 0x0000fd01, 0x00000401, 0x00000006, 0x0000ff03, 0x000007fc, - 0x0000fc08, 0x00000203, 0x0000fffb, 0x00000600, 0x0000fa01, 0x0000fc03, - 0x0000fe06, 0x0000fe00, 0x00000102, 0x000007fd, 0x000004fb, 0x000006ff, - 0x000004fd, 0x0000fdfa, 0x000007fb, 0x0000fdfa, 0x0000fa06, 0x00000500, - 0x0000f902, 0x000007fa, 0x0000fafa, 0x00000500, 0x000007fa, 0x00000700, - 0x00000305, 0x000004ff, 0x00000801, 0x00000503, 0x000005f9, 0x00000404, - 0x0000fb08, 0x000005fd, 0x00000501, 0x00000405, 0x0000fb03, 0x000007fc, - 0x00000403, 0x00000303, 0x00000402, 0x0000faff, 0x0000fe05, 0x000005fd, - 0x0000fe01, 0x000007fa, 0x00000202, 0x00000504, 0x00000102, 0x000008fe, - 0x0000fa04, 0x0000fafc, 0x0000fe08, 0x000000f9, 0x000002fa, 0x000003fe, - 0x00000304, 0x000004f9, 0x00000100, 0x0000fd06, 0x000008fc, 0x00000701, - 0x00000504, 0x0000fdfe, 0x0000fdfc, 0x000003fe, 0x00000704, 0x000002fc, - 0x000004f9, 0x0000fdfd, 0x0000fa07, 0x00000205, 0x000003fd, 0x000005fb, - 0x000004f9, 0x00000804, 0x0000fc06, 0x0000fcf9, 0x00000100, 0x0000fe05, - 0x00000408, 0x0000fb02, 0x00000304, 0x000006fe, 0x000004fa, 0x00000305, - 0x000008fc, 0x00000102, 0x000001fd, 0x000004fc, 0x0000fe03, 0x00000701, - 0x000001fb, 0x000001f9, 0x00000206, 0x000006fd, 0x00000508, 0x00000700, - 0x00000304, 0x000005fe, 0x000005ff, 0x0000fa04, 0x00000303, 0x0000fefb, - 0x000007f9, 0x0000fefc, 0x000004fd, 0x000005fc, 0x0000fffd, 0x0000fc08, - 0x0000fbf9, 0x0000fd07, 0x000008fb, 0x0000fe02, 0x000006fb, 0x00000702, -}; - -static const u32 lpphy_gain_idx_table[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x10000001, 0x00000000, 0x20000082, 0x00000000, 0x40000104, 0x00000000, - 0x60004207, 0x00000001, 0x7000838a, 0x00000001, 0xd021050d, 0x00000001, - 0xe041c683, 0x00000001, 0x50828805, 0x00000000, 0x80e34288, 0x00000000, - 0xb144040b, 0x00000000, 0xe1a6058e, 0x00000000, 0x12064711, 0x00000001, - 0xb0a18612, 0x00000010, 0xe1024794, 0x00000010, 0x11630915, 0x00000011, - 0x31c3ca1b, 0x00000011, 0xc1848a9c, 0x00000018, 0xf1e50da0, 0x00000018, - 0x22468e21, 0x00000019, 0x4286d023, 0x00000019, 0xa347d0a4, 0x00000019, - 0xb36811a6, 0x00000019, 0xf3e89227, 0x00000019, 0x0408d329, 0x0000001a, - 0x244953aa, 0x0000001a, 0x346994ab, 0x0000001a, 0x54aa152c, 0x0000001a, - 0x64ca55ad, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x10000001, 0x00000000, 0x20000082, 0x00000000, - 0x40000104, 0x00000000, 0x60004207, 0x00000001, 0x7000838a, 0x00000001, - 0xd021050d, 0x00000001, 0xe041c683, 0x00000001, 0x50828805, 0x00000000, - 0x80e34288, 0x00000000, 0xb144040b, 0x00000000, 0xe1a6058e, 0x00000000, - 0x12064711, 0x00000001, 0xb0a18612, 0x00000010, 0xe1024794, 0x00000010, - 0x11630915, 0x00000011, 0x31c3ca1b, 0x00000011, 0xc1848a9c, 0x00000018, - 0xf1e50da0, 0x00000018, 0x22468e21, 0x00000019, 0x4286d023, 0x00000019, - 0xa347d0a4, 0x00000019, 0xb36811a6, 0x00000019, 0xf3e89227, 0x00000019, - 0x0408d329, 0x0000001a, 0x244953aa, 0x0000001a, 0x346994ab, 0x0000001a, - 0x54aa152c, 0x0000001a, 0x64ca55ad, 0x0000001a, -}; - -static const u16 lpphy_aux_gain_idx_table[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0001, 0x0002, 0x0004, 0x0016, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0016, -}; - -static const u32 lpphy_gain_value_table[] = { - 0x00000008, 0x0000000e, 0x00000014, 0x0000001a, 0x000000fb, 0x00000004, - 0x00000008, 0x0000000d, 0x00000001, 0x00000004, 0x00000007, 0x0000000a, - 0x0000000d, 0x00000010, 0x00000012, 0x00000015, 0x00000000, 0x00000006, - 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000012, 0x00000000, - 0x00000000, 0x00000000, 0x00000018, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000003, 0x00000006, 0x00000009, 0x0000000c, 0x0000000f, - 0x00000012, 0x00000015, 0x00000018, 0x0000001b, 0x0000001e, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000009, 0x000000f1, - 0x00000000, 0x00000000, -}; - -static const u16 lpphy_gain_table[] = { - 0x0000, 0x0400, 0x0800, 0x0802, 0x0804, 0x0806, 0x0807, 0x0808, 0x080a, - 0x080b, 0x080c, 0x080e, 0x080f, 0x0810, 0x0812, 0x0813, 0x0814, 0x0816, - 0x0817, 0x081a, 0x081b, 0x081f, 0x0820, 0x0824, 0x0830, 0x0834, 0x0837, - 0x083b, 0x083f, 0x0840, 0x0844, 0x0857, 0x085b, 0x085f, 0x08d7, 0x08db, - 0x08df, 0x0957, 0x095b, 0x095f, 0x0b57, 0x0b5b, 0x0b5f, 0x0f5f, 0x135f, - 0x175f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u32 lpphy_a0_gain_idx_table[] = { - 0x001111e0, 0x00652051, 0x00606055, 0x005b005a, 0x00555060, 0x00511065, - 0x004c806b, 0x0047d072, 0x00444078, 0x00400080, 0x003ca087, 0x0039408f, - 0x0035e098, 0x0032e0a1, 0x003030aa, 0x002d80b4, 0x002ae0bf, 0x002880ca, - 0x002640d6, 0x002410e3, 0x002220f0, 0x002020ff, 0x001e510e, 0x001ca11e, - 0x001b012f, 0x00199140, 0x00182153, 0x0016c168, 0x0015817d, 0x00145193, - 0x001321ab, 0x001211c5, 0x001111e0, 0x001021fc, 0x000f321a, 0x000e523a, - 0x000d925c, 0x000cd27f, 0x000c12a5, 0x000b62cd, 0x000ac2f8, 0x000a2325, - 0x00099355, 0x00091387, 0x000883bd, 0x000813f5, 0x0007a432, 0x00073471, - 0x0006c4b5, 0x000664fc, 0x00061547, 0x0005b598, 0x000565ec, 0x00051646, - 0x0004d6a5, 0x0004870a, 0x00044775, 0x000407e6, 0x0003d85e, 0x000398dd, - 0x00036963, 0x000339f2, 0x00030a89, 0x0002db28, -}; - -static const u16 lpphy_a0_aux_gain_idx_table[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0002, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0002, 0x0014, -}; - -static const u32 lpphy_a0_gain_value_table[] = { - 0x00000008, 0x0000000e, 0x00000014, 0x0000001a, 0x000000fb, 0x00000004, - 0x00000008, 0x0000000d, 0x00000001, 0x00000004, 0x00000007, 0x0000000a, - 0x0000000d, 0x00000010, 0x00000012, 0x00000015, 0x00000000, 0x00000006, - 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000012, 0x00000000, - 0x00000000, 0x00000000, 0x00000018, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000003, 0x00000006, 0x00000009, 0x0000000c, 0x0000000f, - 0x00000012, 0x00000015, 0x00000018, 0x0000001b, 0x0000001e, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x000000f7, - 0x00000000, 0x00000000, -}; - -static const u16 lpphy_a0_gain_table[] = { - 0x0000, 0x0002, 0x0004, 0x0006, 0x0007, 0x0008, 0x000a, 0x000b, 0x000c, - 0x000e, 0x000f, 0x0010, 0x0012, 0x0013, 0x0014, 0x0016, 0x0017, 0x001a, - 0x001b, 0x001f, 0x0020, 0x0024, 0x0030, 0x0034, 0x0037, 0x003b, 0x003f, - 0x0040, 0x0044, 0x0057, 0x005b, 0x005f, 0x00d7, 0x00db, 0x00df, 0x0157, - 0x015b, 0x015f, 0x0357, 0x035b, 0x035f, 0x075f, 0x0b5f, 0x0f5f, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u16 lpphy_sw_control_table[] = { - 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0128, - 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0009, 0x0009, - 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0018, 0x0018, 0x0018, - 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0128, 0x0128, 0x0009, 0x0009, - 0x0028, 0x0028, 0x0028, 0x0028, 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, - 0x0028, 0x0028, 0x0028, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, - 0x0009, 0x0009, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, - 0x0018, -}; - -static const u8 lpphy_hf_table[] = { - 0x4b, 0x36, 0x24, 0x18, 0x49, 0x34, 0x23, 0x17, 0x48, - 0x33, 0x23, 0x17, 0x48, 0x33, 0x23, 0x17, -}; - -static const u32 lpphy_papd_eps_table[] = { - 0x00000000, 0x00013ffc, 0x0001dff3, 0x0001bff0, 0x00023fe9, 0x00021fdf, - 0x00028fdf, 0x00033fd2, 0x00039fcb, 0x00043fc7, 0x0004efc2, 0x00055fb5, - 0x0005cfb0, 0x00063fa8, 0x00068fa3, 0x00071f98, 0x0007ef92, 0x00084f8b, - 0x0008df82, 0x00097f77, 0x0009df69, 0x000a3f62, 0x000adf57, 0x000b6f4c, - 0x000bff41, 0x000c9f39, 0x000cff30, 0x000dbf27, 0x000e4f1e, 0x000edf16, - 0x000f7f13, 0x00102f11, 0x00110f10, 0x0011df11, 0x0012ef15, 0x00143f1c, - 0x00158f27, 0x00172f35, 0x00193f47, 0x001baf5f, 0x001e6f7e, 0x0021cfa4, - 0x0025bfd2, 0x002a2008, 0x002fb047, 0x00360090, 0x003d40e0, 0x0045c135, - 0x004fb189, 0x005ae1d7, 0x0067221d, 0x0075025a, 0x007ff291, 0x007ff2bf, - 0x007ff2e3, 0x007ff2ff, 0x007ff315, 0x007ff329, 0x007ff33f, 0x007ff356, - 0x007ff36e, 0x007ff39c, 0x007ff441, 0x007ff506, -}; - -static const u32 lpphy_papd_mult_table[] = { - 0x001111e0, 0x00652051, 0x00606055, 0x005b005a, 0x00555060, 0x00511065, - 0x004c806b, 0x0047d072, 0x00444078, 0x00400080, 0x003ca087, 0x0039408f, - 0x0035e098, 0x0032e0a1, 0x003030aa, 0x002d80b4, 0x002ae0bf, 0x002880ca, - 0x002640d6, 0x002410e3, 0x002220f0, 0x002020ff, 0x001e510e, 0x001ca11e, - 0x001b012f, 0x00199140, 0x00182153, 0x0016c168, 0x0015817d, 0x00145193, - 0x001321ab, 0x001211c5, 0x001111e0, 0x001021fc, 0x000f321a, 0x000e523a, - 0x000d925c, 0x000cd27f, 0x000c12a5, 0x000b62cd, 0x000ac2f8, 0x000a2325, - 0x00099355, 0x00091387, 0x000883bd, 0x000813f5, 0x0007a432, 0x00073471, - 0x0006c4b5, 0x000664fc, 0x00061547, 0x0005b598, 0x000565ec, 0x00051646, - 0x0004d6a5, 0x0004870a, 0x00044775, 0x000407e6, 0x0003d85e, 0x000398dd, - 0x00036963, 0x000339f2, 0x00030a89, 0x0002db28, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev0_nopa_tx_gain_table[] = { - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 152, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 147, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 143, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 139, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 135, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 131, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 128, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 124, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 121, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 117, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 114, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 111, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 107, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 104, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 101, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 99, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 96, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 93, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 90, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 88, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 85, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 83, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 81, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 78, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 76, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 74, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 71, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev0_2ghz_tx_gain_table[] = { - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 73, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 71, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 69, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 73, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 71, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 69, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 10, .pad = 5, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 9, .pad = 5, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 71, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 69, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 9, .pad = 4, .dac = 0, .bb_mult = 58, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 8, .pad = 4, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 7, .pad = 4, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 7, .pad = 3, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 7, .pad = 3, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 7, .pad = 3, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 7, .pad = 3, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 7, .pad = 3, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 6, .pad = 3, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 6, .pad = 3, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 6, .pad = 3, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 6, .pad = 3, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 6, .pad = 3, .dac = 0, .bb_mult = 58, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 5, .pad = 3, .dac = 0, .bb_mult = 57, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 83, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 81, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 78, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 76, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 74, }, - { .gm = 4, .pga = 4, .pad = 2, .dac = 0, .bb_mult = 72, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev0_5ghz_tx_gain_table[] = { - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 99, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 96, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 93, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 90, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 88, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 85, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 83, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 81, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 78, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 76, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 74, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 55, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 55, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 60, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev1_nopa_tx_gain_table[] = { - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 152, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 147, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 143, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 139, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 135, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 131, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 128, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 124, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 121, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 117, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 114, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 111, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 107, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 104, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 101, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 99, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 96, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 93, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 90, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 88, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 85, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 83, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 81, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 78, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 76, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 74, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 71, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev1_2ghz_tx_gain_table[] = { - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 90, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 88, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 85, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 83, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 81, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 78, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 76, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 74, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 73, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 71, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 69, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 73, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 71, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 69, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 67, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 65, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 63, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 61, }, - { .gm = 4, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 60, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 72, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 70, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 68, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 66, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 64, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 62, }, - { .gm = 4, .pga = 10, .pad = 6, .dac = 0, .bb_mult = 60, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev1_5ghz_tx_gain_table[] = { - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 99, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 96, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 93, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 90, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 88, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 85, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 83, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 81, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 78, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 76, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 74, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 15, .dac = 0, .bb_mult = 55, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 14, .dac = 0, .bb_mult = 55, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 13, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 72, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 12, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 73, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 11, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 71, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 15, .pad = 10, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 15, .pad = 9, .dac = 0, .bb_mult = 56, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 14, .pad = 9, .dac = 0, .bb_mult = 58, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 9, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 60, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 13, .pad = 8, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 8, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 12, .pad = 7, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 70, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 68, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 66, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 61, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 59, }, - { .gm = 7, .pga = 11, .pad = 7, .dac = 0, .bb_mult = 57, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 69, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 67, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 65, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 63, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 62, }, - { .gm = 7, .pga = 11, .pad = 6, .dac = 0, .bb_mult = 60, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev2_nopa_tx_gain_table[] = { - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 152, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 147, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 143, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 139, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 135, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 131, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 128, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 124, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 121, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 117, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 114, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 111, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 107, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 104, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 101, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 99, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 96, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 93, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 90, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 88, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 85, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 83, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 81, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 78, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 76, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 74, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 72, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 70, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 68, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 66, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 197, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 192, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 186, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 181, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 176, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 171, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 166, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 161, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 157, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 152, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 148, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 144, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 140, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 136, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 132, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 128, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 124, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 121, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 117, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 114, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 111, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 108, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 105, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 102, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 99, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 96, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 93, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 91, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 88, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 86, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 83, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 81, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 79, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 76, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 74, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 72, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 70, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 68, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 66, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 248, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 248, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 241, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 241, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 234, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 234, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 227, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 227, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 221, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 221, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 215, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 215, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 208, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 208, .pad = 52, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 203, .pad = 52, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 203, .pad = 51, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 197, .pad = 51, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 197, .pad = 49, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 191, .pad = 49, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 191, .pad = 48, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 186, .pad = 48, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 186, .pad = 47, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 181, .pad = 47, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 181, .pad = 45, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 175, .pad = 45, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 175, .pad = 44, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 170, .pad = 44, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 170, .pad = 43, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 166, .pad = 43, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 166, .pad = 42, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 161, .pad = 42, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 161, .pad = 40, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 156, .pad = 40, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 156, .pad = 39, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 152, .pad = 39, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 152, .pad = 38, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 148, .pad = 38, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 148, .pad = 37, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 143, .pad = 37, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 143, .pad = 36, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 139, .pad = 36, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 139, .pad = 35, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 135, .pad = 35, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 135, .pad = 34, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 132, .pad = 34, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 132, .pad = 33, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 128, .pad = 33, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 128, .pad = 32, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 124, .pad = 32, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 124, .pad = 31, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 121, .pad = 31, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 121, .pad = 30, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 117, .pad = 30, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 117, .pad = 29, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 114, .pad = 29, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 114, .pad = 29, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 111, .pad = 29, .dac = 0, .bb_mult = 64, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev2_2ghz_tx_gain_table[] = { - { .gm = 7, .pga = 99, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 96, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 93, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 90, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 88, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 85, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 83, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 81, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 78, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 76, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 74, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 72, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 70, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 68, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 66, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 64, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 64, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 62, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 62, .pad = 248, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 60, .pad = 248, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 60, .pad = 241, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 59, .pad = 241, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 59, .pad = 234, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 57, .pad = 234, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 57, .pad = 227, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 55, .pad = 227, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 55, .pad = 221, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 54, .pad = 221, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 54, .pad = 215, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 52, .pad = 215, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 52, .pad = 208, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 51, .pad = 208, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 51, .pad = 203, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 49, .pad = 203, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 49, .pad = 197, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 48, .pad = 197, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 48, .pad = 191, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 47, .pad = 191, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 47, .pad = 186, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 45, .pad = 186, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 45, .pad = 181, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 44, .pad = 181, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 44, .pad = 175, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 43, .pad = 175, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 43, .pad = 170, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 42, .pad = 170, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 42, .pad = 166, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 40, .pad = 166, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 40, .pad = 161, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 39, .pad = 161, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 39, .pad = 156, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 38, .pad = 156, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 38, .pad = 152, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 37, .pad = 152, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 37, .pad = 148, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 36, .pad = 148, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 36, .pad = 143, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 35, .pad = 143, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 35, .pad = 139, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 34, .pad = 139, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 34, .pad = 135, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 33, .pad = 135, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 33, .pad = 132, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 32, .pad = 132, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 32, .pad = 128, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 31, .pad = 128, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 31, .pad = 124, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 30, .pad = 124, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 30, .pad = 121, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 29, .pad = 121, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 29, .pad = 117, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 29, .pad = 117, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 29, .pad = 114, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 28, .pad = 114, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 28, .pad = 111, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 27, .pad = 111, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 27, .pad = 108, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 26, .pad = 108, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 26, .pad = 104, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 25, .pad = 104, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 25, .pad = 102, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 25, .pad = 102, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 25, .pad = 99, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 24, .pad = 99, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 24, .pad = 96, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 23, .pad = 96, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 23, .pad = 93, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 23, .pad = 93, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 23, .pad = 90, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 22, .pad = 90, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 22, .pad = 88, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 21, .pad = 88, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 21, .pad = 85, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 21, .pad = 85, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 21, .pad = 83, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 20, .pad = 83, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 20, .pad = 81, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 20, .pad = 81, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 20, .pad = 78, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 19, .pad = 78, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 19, .pad = 76, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 19, .pad = 76, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 19, .pad = 74, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 18, .pad = 74, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 18, .pad = 72, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 18, .pad = 72, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 18, .pad = 70, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 17, .pad = 70, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 17, .pad = 68, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 17, .pad = 68, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 17, .pad = 66, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 16, .pad = 66, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 16, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 16, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 16, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 15, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 14, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 52, .dac = 0, .bb_mult = 64, }, - { .gm = 7, .pga = 13, .pad = 52, .dac = 0, .bb_mult = 64, }, -}; - -static struct lpphy_tx_gain_table_entry lpphy_rev2_5ghz_tx_gain_table[] = { - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 152, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 147, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 143, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 139, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 135, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 131, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 128, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 124, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 121, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 117, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 114, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 111, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 107, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 104, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 101, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 99, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 96, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 93, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 90, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 88, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 85, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 83, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 81, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 78, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 76, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 74, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 72, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 70, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 68, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 66, }, - { .gm = 255, .pga = 255, .pad = 255, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 248, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 241, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 234, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 227, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 221, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 215, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 208, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 203, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 197, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 191, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 186, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 181, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 175, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 170, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 166, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 161, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 156, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 152, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 148, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 143, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 139, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 135, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 132, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 128, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 124, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 121, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 117, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 114, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 111, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 108, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 104, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 102, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 99, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 96, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 93, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 90, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 88, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 85, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 83, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 81, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 78, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 76, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 74, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 72, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 70, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 68, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 66, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 64, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 255, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 248, .pad = 62, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 248, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 241, .pad = 60, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 241, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 234, .pad = 59, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 234, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 227, .pad = 57, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 227, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 221, .pad = 55, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 221, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 215, .pad = 54, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 215, .pad = 52, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 208, .pad = 52, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 208, .pad = 51, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 203, .pad = 51, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 203, .pad = 49, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 197, .pad = 49, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 197, .pad = 48, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 191, .pad = 48, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 191, .pad = 47, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 186, .pad = 47, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 186, .pad = 45, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 181, .pad = 45, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 181, .pad = 44, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 175, .pad = 44, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 175, .pad = 43, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 170, .pad = 43, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 170, .pad = 42, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 166, .pad = 42, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 166, .pad = 40, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 161, .pad = 40, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 161, .pad = 39, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 156, .pad = 39, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 156, .pad = 38, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 152, .pad = 38, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 152, .pad = 37, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 148, .pad = 37, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 148, .pad = 36, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 143, .pad = 36, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 143, .pad = 35, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 139, .pad = 35, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 139, .pad = 34, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 135, .pad = 34, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 135, .pad = 33, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 132, .pad = 33, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 132, .pad = 32, .dac = 0, .bb_mult = 64, }, - { .gm = 255, .pga = 128, .pad = 32, .dac = 0, .bb_mult = 64, }, -}; - -void lpphy_rev0_1_table_init(struct b43_wldev *dev) -{ - B43_WARN_ON(dev->phy.rev >= 2); - - b43_lptab_write_bulk(dev, B43_LPTAB8(2, 0), - ARRAY_SIZE(lpphy_min_sig_sq_table), lpphy_min_sig_sq_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(1, 0), - ARRAY_SIZE(lpphy_rev01_noise_scale_table), lpphy_rev01_noise_scale_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(14, 0), - ARRAY_SIZE(lpphy_crs_gain_nft_table), lpphy_crs_gain_nft_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(8, 0), - ARRAY_SIZE(lpphy_rev01_filter_control_table), lpphy_rev01_filter_control_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(9, 0), - ARRAY_SIZE(lpphy_rev01_ps_control_table), lpphy_rev01_ps_control_table); - b43_lptab_write_bulk(dev, B43_LPTAB8(6, 0), - ARRAY_SIZE(lpphy_pll_fraction_table), lpphy_pll_fraction_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(0, 0), - ARRAY_SIZE(lpphy_iqlo_cal_table), lpphy_iqlo_cal_table); - if (dev->phy.rev == 0) { - b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), - ARRAY_SIZE(lpphy_rev0_ofdm_cck_gain_table), lpphy_rev0_ofdm_cck_gain_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), - ARRAY_SIZE(lpphy_rev0_ofdm_cck_gain_table), lpphy_rev0_ofdm_cck_gain_table); - } else { - b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), - ARRAY_SIZE(lpphy_rev1_ofdm_cck_gain_table), lpphy_rev1_ofdm_cck_gain_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), - ARRAY_SIZE(lpphy_rev1_ofdm_cck_gain_table), lpphy_rev1_ofdm_cck_gain_table); -} - b43_lptab_write_bulk(dev, B43_LPTAB16(15, 0), - ARRAY_SIZE(lpphy_gain_delta_table), lpphy_gain_delta_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0), - ARRAY_SIZE(lpphy_tx_power_control_table), lpphy_tx_power_control_table); -} - -void lpphy_rev2plus_table_init(struct b43_wldev *dev) -{ - int i; - - B43_WARN_ON(dev->phy.rev < 2); - - for (i = 0; i < 704; i++) - b43_lptab_write(dev, B43_LPTAB32(7, i), 0); - - b43_lptab_write_bulk(dev, B43_LPTAB8(2, 0), - ARRAY_SIZE(lpphy_min_sig_sq_table), lpphy_min_sig_sq_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(1, 0), - ARRAY_SIZE(lpphy_rev2plus_noise_scale_table), lpphy_rev2plus_noise_scale_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(11, 0), - ARRAY_SIZE(lpphy_rev2plus_filter_control_table), lpphy_rev2plus_filter_control_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(12, 0), - ARRAY_SIZE(lpphy_rev2plus_ps_control_table), lpphy_rev2plus_ps_control_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(13, 0), - ARRAY_SIZE(lpphy_gain_idx_table), lpphy_gain_idx_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(14, 0), - ARRAY_SIZE(lpphy_aux_gain_idx_table), lpphy_aux_gain_idx_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(15, 0), - ARRAY_SIZE(lpphy_sw_control_table), lpphy_sw_control_table); - b43_lptab_write_bulk(dev, B43_LPTAB8(16, 0), - ARRAY_SIZE(lpphy_hf_table), lpphy_hf_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(17, 0), - ARRAY_SIZE(lpphy_gain_value_table), lpphy_gain_value_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(18, 0), - ARRAY_SIZE(lpphy_gain_table), lpphy_gain_table); - b43_lptab_write_bulk(dev, B43_LPTAB8(6, 0), - ARRAY_SIZE(lpphy_pll_fraction_table), lpphy_pll_fraction_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(0, 0), - ARRAY_SIZE(lpphy_iqlo_cal_table), lpphy_iqlo_cal_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(9, 0), - ARRAY_SIZE(lpphy_papd_eps_table), lpphy_papd_eps_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0), - ARRAY_SIZE(lpphy_papd_mult_table), lpphy_papd_mult_table); - - if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) { - b43_lptab_write_bulk(dev, B43_LPTAB32(13, 0), - ARRAY_SIZE(lpphy_a0_gain_idx_table), lpphy_a0_gain_idx_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(14, 0), - ARRAY_SIZE(lpphy_a0_aux_gain_idx_table), lpphy_a0_aux_gain_idx_table); - b43_lptab_write_bulk(dev, B43_LPTAB32(17, 0), - ARRAY_SIZE(lpphy_a0_gain_value_table), lpphy_a0_gain_value_table); - b43_lptab_write_bulk(dev, B43_LPTAB16(18, 0), - ARRAY_SIZE(lpphy_a0_gain_table), lpphy_a0_gain_table); - } -} - -static void lpphy_rev0_1_write_gain_table(struct b43_wldev *dev, int offset, - struct lpphy_tx_gain_table_entry data) -{ - u32 tmp; - - B43_WARN_ON(dev->phy.rev >= 2); - - tmp = data.pad << 11; - tmp |= data.pga << 7; - tmp |= data.gm << 4; - tmp |= data.dac; - b43_lptab_write(dev, B43_LPTAB32(10, 0xC0 + offset), tmp); - tmp = data.bb_mult << 20; - b43_lptab_write(dev, B43_LPTAB32(10, 0x140 + offset), tmp); -} - -static void lpphy_rev2plus_write_gain_table(struct b43_wldev *dev, int offset, - struct lpphy_tx_gain_table_entry data) -{ - u32 tmp; - - B43_WARN_ON(dev->phy.rev < 2); - - tmp = data.pad << 16; - tmp |= data.pga << 8; - tmp |= data.gm; - if (dev->phy.rev >= 3) { - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - tmp |= 0x10 << 24; - else - tmp |= 0x70 << 24; - } else { - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - tmp |= 0x14 << 24; - else - tmp |= 0x7F << 24; - } - b43_lptab_write(dev, B43_LPTAB32(7, 0xC0 + offset), tmp); - tmp = data.bb_mult << 20; - tmp |= data.dac << 28; - b43_lptab_write(dev, B43_LPTAB32(7, 0x140 + offset), tmp); -} - -void lpphy_write_gain_table(struct b43_wldev *dev, int offset, - struct lpphy_tx_gain_table_entry data) -{ - if (dev->phy.rev >= 2) - lpphy_rev2plus_write_gain_table(dev, offset, data); - else - lpphy_rev0_1_write_gain_table(dev, offset, data); -} - -void lpphy_write_gain_table_bulk(struct b43_wldev *dev, int offset, int count, - struct lpphy_tx_gain_table_entry *table) -{ - int i; - - for (i = offset; i < count; i++) - lpphy_write_gain_table(dev, i, table[i]); -} - -void lpphy_init_tx_gain_table(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - switch (dev->phy.rev) { - case 0: - if ((sprom->boardflags_hi & B43_BFH_NOPA) || - (sprom->boardflags_lo & B43_BFL_HGPA)) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev0_nopa_tx_gain_table); - else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev0_2ghz_tx_gain_table); - else - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev0_5ghz_tx_gain_table); - break; - case 1: - if ((sprom->boardflags_hi & B43_BFH_NOPA) || - (sprom->boardflags_lo & B43_BFL_HGPA)) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev1_nopa_tx_gain_table); - else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev1_2ghz_tx_gain_table); - else - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev1_5ghz_tx_gain_table); - break; - default: - if (sprom->boardflags_hi & B43_BFH_NOPA) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev2_nopa_tx_gain_table); - else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev2_2ghz_tx_gain_table); - else - lpphy_write_gain_table_bulk(dev, 0, 128, - lpphy_rev2_5ghz_tx_gain_table); - } -} diff --git a/drivers/net/wireless/b43/tables_lpphy.h b/drivers/net/wireless/b43/tables_lpphy.h deleted file mode 100644 index 84f1d265f..000000000 --- a/drivers/net/wireless/b43/tables_lpphy.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef B43_TABLES_LPPHY_H_ -#define B43_TABLES_LPPHY_H_ - - -#define B43_LPTAB_TYPEMASK 0xF0000000 -#define B43_LPTAB_8BIT 0x10000000 -#define B43_LPTAB_16BIT 0x20000000 -#define B43_LPTAB_32BIT 0x30000000 -#define B43_LPTAB8(table, offset) (((table) << 10) | (offset) | B43_LPTAB_8BIT) -#define B43_LPTAB16(table, offset) (((table) << 10) | (offset) | B43_LPTAB_16BIT) -#define B43_LPTAB32(table, offset) (((table) << 10) | (offset) | B43_LPTAB_32BIT) - -/* Table definitions */ -#define B43_LPTAB_TXPWR_R2PLUS B43_LPTAB32(0x07, 0) /* TX power lookup table (rev >= 2) */ -#define B43_LPTAB_TXPWR_R0_1 B43_LPTAB32(0xA0, 0) /* TX power lookup table (rev < 2) */ - -u32 b43_lptab_read(struct b43_wldev *dev, u32 offset); -void b43_lptab_write(struct b43_wldev *dev, u32 offset, u32 value); - -/* Bulk table access. Note that these functions return the bulk data in - * host endianness! The returned data is _not_ a bytearray, but an array - * consisting of nr_elements of the data type. */ -void b43_lptab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *data); -void b43_lptab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *data); - -void b2062_upload_init_table(struct b43_wldev *dev); -void b2063_upload_init_table(struct b43_wldev *dev); - -struct lpphy_tx_gain_table_entry { - u8 gm, pga, pad, dac, bb_mult; -}; - -void lpphy_write_gain_table(struct b43_wldev *dev, int offset, - struct lpphy_tx_gain_table_entry data); -void lpphy_write_gain_table_bulk(struct b43_wldev *dev, int offset, int count, - struct lpphy_tx_gain_table_entry *table); - -void lpphy_rev0_1_table_init(struct b43_wldev *dev); -void lpphy_rev2plus_table_init(struct b43_wldev *dev); -void lpphy_init_tx_gain_table(struct b43_wldev *dev); - -#endif /* B43_TABLES_LPPHY_H_ */ diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c deleted file mode 100644 index b2f0d245b..000000000 --- a/drivers/net/wireless/b43/tables_nphy.c +++ /dev/null @@ -1,3878 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n PHY data tables - - Copyright (c) 2008 Michael Buesch <m@bues.ch> - Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "tables_nphy.h" -#include "phy_common.h" -#include "phy_n.h" - -static const u8 b43_ntab_adjustpower0[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static const u8 b43_ntab_adjustpower1[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static const u16 b43_ntab_bdi[] = { - 0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2, -}; - -static const u32 b43_ntab_channelest[] = { - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, -}; - -static const u8 b43_ntab_estimatepowerlt0[] = { - 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, - 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, - 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, - 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, - 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, - 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, - 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, - 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, -}; - -static const u8 b43_ntab_estimatepowerlt1[] = { - 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, - 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, - 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, - 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, - 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, - 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, - 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, - 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, -}; - -static const u8 b43_ntab_framelookup[] = { - 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, - 0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E, - 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A, - 0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A, -}; - -static const u32 b43_ntab_framestruct[] = { - 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, - 0x09804506, 0x00100030, 0x09804507, 0x00100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024, - 0x0980450E, 0x00100034, 0x0980450F, 0x00100034, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, - 0x1980C506, 0x00100030, 0x21810506, 0x00100030, - 0x21810506, 0x00100030, 0x01800504, 0x00100030, - 0x11808505, 0x00100030, 0x29814507, 0x01100030, - 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, - 0x21810506, 0x00100030, 0x21810506, 0x00100030, - 0x29814507, 0x01100030, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, - 0x1980C50E, 0x00100038, 0x2181050E, 0x00100038, - 0x2181050E, 0x00100038, 0x0180050C, 0x00100038, - 0x1180850D, 0x00100038, 0x2981450F, 0x01100038, - 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, - 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, - 0x2981450F, 0x01100038, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, - 0x1980C506, 0x00100030, 0x1980C506, 0x00100030, - 0x11808504, 0x00100030, 0x3981CA05, 0x00100030, - 0x29814507, 0x01100030, 0x00000000, 0x00000000, - 0x10008A04, 0x00100000, 0x3981CA05, 0x00100030, - 0x1980C506, 0x00100030, 0x29814507, 0x01100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028, - 0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038, - 0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038, - 0x2981450F, 0x01100038, 0x00000000, 0x00000000, - 0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038, - 0x1980C50E, 0x00100038, 0x2981450F, 0x01100038, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x02001405, 0x00100040, - 0x0B004A06, 0x01900060, 0x13008A06, 0x01900060, - 0x13008A06, 0x01900060, 0x43020A04, 0x00100060, - 0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060, - 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, - 0x13008A06, 0x01900060, 0x13008A06, 0x01900060, - 0x23010A07, 0x01500060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x00100010, 0x0200140D, 0x00100050, - 0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070, - 0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070, - 0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070, - 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, - 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, - 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x50029404, 0x00100000, 0x32019405, 0x00100040, - 0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060, - 0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060, - 0x23010A07, 0x01500060, 0x00000000, 0x00000000, - 0x5802D404, 0x00100000, 0x3B01D405, 0x00100060, - 0x0B004A06, 0x01900060, 0x23010A07, 0x01500060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x5002940C, 0x00100010, 0x3201940D, 0x00100050, - 0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070, - 0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070, - 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, - 0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070, - 0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x000F4800, 0x62031405, 0x00100040, - 0x53028A06, 0x01900060, 0x53028A07, 0x01900060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x000F4808, 0x6203140D, 0x00100048, - 0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024, - 0x1980C50E, 0x00100034, 0x2181050E, 0x00100034, - 0x2181050E, 0x00100034, 0x0180050C, 0x00100038, - 0x1180850D, 0x00100038, 0x1181850D, 0x00100038, - 0x2981450F, 0x01100038, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, - 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, - 0x1181850D, 0x00100038, 0x2981450F, 0x01100038, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, - 0x0180C506, 0x00100030, 0x0180C506, 0x00100030, - 0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130, - 0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130, - 0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130, - 0x2981450F, 0x01100030, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x00100008, 0x0200140D, 0x00100048, - 0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068, - 0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070, - 0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070, - 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, - 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, - 0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x50029404, 0x00100000, 0x32019405, 0x00100040, - 0x03004A06, 0x01900060, 0x03004A06, 0x01900060, - 0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160, - 0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160, - 0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160, - 0x23010A0F, 0x01500060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, - 0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060, - 0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060, - 0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, - 0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070, - 0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070, - 0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, - 0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060, - 0x53028A07, 0x0190C060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, - 0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070, - 0x53028A0F, 0x0190C070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_gainctl0[] = { - 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, - 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, - 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, - 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, - 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, - 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, - 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, - 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, - 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, - 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, - 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, - 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, - 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, - 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, - 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, - 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, - 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, - 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, - 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, - 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, - 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, - 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, - 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, - 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, - 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, - 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, - 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, - 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, - 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, -}; - -static const u32 b43_ntab_gainctl1[] = { - 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, - 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, - 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, - 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, - 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, - 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, - 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, - 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, - 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, - 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, - 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, - 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, - 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, - 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, - 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, - 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, - 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, - 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, - 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, - 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, - 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, - 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, - 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, - 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, - 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, - 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, - 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, - 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, - 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, - 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, -}; - -static const u32 b43_ntab_intlevel[] = { - 0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46, - 0x00C1188D, 0x080024D2, 0x00000070, -}; - -static const u32 b43_ntab_iqlt0[] = { - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, -}; - -static const u32 b43_ntab_iqlt1[] = { - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, - 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, -}; - -static const u16 b43_ntab_loftlt0[] = { - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, -}; - -static const u16 b43_ntab_loftlt1[] = { - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, - 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, - 0x0002, 0x0103, -}; - -static const u8 b43_ntab_mcs[] = { - 0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C, - 0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C, - 0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C, - 0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C, - 0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C, - 0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44, - 0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54, - 0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static const u32 b43_ntab_noisevar10[] = { - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, -}; - -static const u32 b43_ntab_noisevar11[] = { - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, - 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, -}; - -static const u16 b43_ntab_pilot[] = { - 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, - 0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5, - 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82, - 0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, - 0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF, - 0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5, - 0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815, - 0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF, - 0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02, - 0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295, - 0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A, - 0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF, - 0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008, - 0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280, - 0xF0A0, 0xF028, 0xFFFF, 0xFFFF, -}; - -static const u32 b43_ntab_pilotlt[] = { - 0x76540123, 0x62407351, 0x76543201, 0x76540213, - 0x76540123, 0x76430521, -}; - -static const u32 b43_ntab_tdi20a0[] = { - 0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0, - 0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D, - 0x00020301, 0x00030504, 0x00040708, 0x0005090B, - 0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718, - 0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31, - 0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE, - 0x00058982, 0x00068C05, 0x00099309, 0x000A950C, - 0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99, - 0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632, - 0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF, - 0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D, - 0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A, - 0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00, - 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi20a1[] = { - 0x00014B26, 0x00028D29, 0x000393AD, 0x00049630, - 0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D, - 0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B, - 0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418, - 0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1, - 0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E, - 0x000F4702, 0x00008905, 0x00020C09, 0x0003128C, - 0x0004148F, 0x00051712, 0x00065916, 0x00091B19, - 0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2, - 0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF, - 0x00035303, 0x00045506, 0x0005978A, 0x0006998D, - 0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A, - 0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00, - 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi40a0[] = { - 0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2, - 0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C, - 0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2, - 0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3, - 0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D, - 0x00153717, 0x00168320, 0x00180CA9, 0x00199633, - 0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4, - 0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F, - 0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734, - 0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5, - 0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010, - 0x001EF999, 0x00010522, 0x00028EAC, 0x00045835, - 0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6, - 0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111, - 0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936, - 0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7, - 0x00031070, 0x000499FA, 0x00062888, 0x0007F212, - 0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37, - 0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868, - 0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313, - 0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38, - 0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969, - 0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414, - 0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39, - 0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A, - 0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515, - 0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A, - 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi40a1[] = { - 0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD, - 0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07, - 0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D, - 0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE, - 0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88, - 0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E, - 0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF, - 0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89, - 0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F, - 0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260, - 0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A, - 0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0, - 0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361, - 0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B, - 0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1, - 0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462, - 0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C, - 0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2, - 0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563, - 0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D, - 0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3, - 0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664, - 0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F, - 0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4, - 0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5, - 0x001390EE, 0x00151A78, 0x0016A906, 0x00183290, - 0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5, - 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdtrn[] = { - 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, - 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, - 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, - 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, - 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, - 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, - 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, - 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, - 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, - 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, - 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, - 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, - 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, - 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, - 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, - 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, - 0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8, - 0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6, - 0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7, - 0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD, - 0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9, - 0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7, - 0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798, - 0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895, - 0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94, - 0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8, - 0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87, - 0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8, - 0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8, - 0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A, - 0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4, - 0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE, - 0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A, - 0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014, - 0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991, - 0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498, - 0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960, - 0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C, - 0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D, - 0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, - 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, - 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, - 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, - 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, - 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, - 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, - 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, - 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, - 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, - 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, - 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, - 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, - 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, - 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, - 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, - 0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54, - 0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6, - 0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2, - 0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3, - 0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA, - 0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6, - 0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12, - 0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0, - 0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC, - 0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A, - 0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E, - 0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D, - 0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826, - 0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A, - 0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE, - 0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30, - 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, - 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, - 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, - 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, - 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, - 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, - 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, - 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, - 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, - 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, - 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, - 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, - 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, - 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, - 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, - 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, - 0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46, - 0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0, - 0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1, - 0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693, - 0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341, - 0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0, - 0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D, - 0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6, - 0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90, - 0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A, - 0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039, - 0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433, - 0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94, - 0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A, - 0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D, - 0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0, - 0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157, - 0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277, - 0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C, - 0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8, - 0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9, - 0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157, - 0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52, - 0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B, - 0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69, - 0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374, - 0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328, - 0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9, - 0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457, - 0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022, - 0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A, - 0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0, - 0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68, - 0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D, - 0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44, - 0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D, - 0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125, - 0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25, - 0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C, - 0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31, - 0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5, - 0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438, - 0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B, - 0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2, - 0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313, - 0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927, - 0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21, - 0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500, - 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, - 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, - 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, - 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, - 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, - 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, - 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, - 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, - 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, - 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, - 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, - 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, - 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, - 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, - 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, - 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, -}; - -static const u32 b43_ntab_tmap[] = { - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, - 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888, - 0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, - 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, - 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, - 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, - 0xF1111110, 0x11111111, 0x11F11111, 0x00011111, - 0x11110000, 0x1111F111, 0x11111111, 0x111111F1, - 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA, - 0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, - 0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88, - 0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888, - 0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808, - 0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08, - 0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080, - 0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, - 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, - 0x22000000, 0x2222B222, 0x22222222, 0x222222B2, - 0xB2222220, 0x22222222, 0x22D22222, 0x00000222, - 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, - 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, - 0x33000000, 0x3333B333, 0x33333333, 0x333333B3, - 0xB3333330, 0x33333333, 0x33D33333, 0x00000333, - 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, - 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, - 0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, - 0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, - 0x22222200, 0x2222F222, 0x22222222, 0x222222F2, - 0x22222222, 0x22222222, 0x22F22222, 0x00000222, - 0x11000000, 0x1111F111, 0x11111111, 0x11111111, - 0xF1111111, 0x11111111, 0x11F11111, 0x01111111, - 0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B, - 0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB, - 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, - 0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA, - 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, - 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB, - 0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999, - 0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88, - 0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A, - 0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B, - 0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909, - 0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08, - 0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A, - 0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090, - 0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090, - 0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080, - 0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0, - 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, - 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, - 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, - 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, - 0x33000000, 0x3333F333, 0x33333333, 0x333333F3, - 0xF3333330, 0x33333333, 0x33F33333, 0x00000333, - 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, - 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, - 0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, - 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, - 0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, - 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, - 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, - 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, - 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, - 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -/* static tables, PHY revision >= 3 */ -static const u32 b43_ntab_framestruct_r3[] = { - 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, - 0x09804506, 0x00100030, 0x09804507, 0x00100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004a0c, 0x00100004, 0x01000a0d, 0x00100024, - 0x0980450e, 0x00100034, 0x0980450f, 0x00100034, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, - 0x1980c506, 0x00100030, 0x21810506, 0x00100030, - 0x21810506, 0x00100030, 0x01800504, 0x00100030, - 0x11808505, 0x00100030, 0x29814507, 0x01100030, - 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, - 0x21810506, 0x00100030, 0x21810506, 0x00100030, - 0x29814507, 0x01100030, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, - 0x1980c50e, 0x00100038, 0x2181050e, 0x00100038, - 0x2181050e, 0x00100038, 0x0180050c, 0x00100038, - 0x1180850d, 0x00100038, 0x2981450f, 0x01100038, - 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, - 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, - 0x2981450f, 0x01100038, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, - 0x1980c506, 0x00100030, 0x1980c506, 0x00100030, - 0x11808504, 0x00100030, 0x3981ca05, 0x00100030, - 0x29814507, 0x01100030, 0x00000000, 0x00000000, - 0x10008a04, 0x00100000, 0x3981ca05, 0x00100030, - 0x1980c506, 0x00100030, 0x29814507, 0x01100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004a0c, 0x00100008, 0x01000a0d, 0x00100028, - 0x1980c50e, 0x00100038, 0x1980c50e, 0x00100038, - 0x1180850c, 0x00100038, 0x3981ca0d, 0x00100038, - 0x2981450f, 0x01100038, 0x00000000, 0x00000000, - 0x10008a0c, 0x00100008, 0x3981ca0d, 0x00100038, - 0x1980c50e, 0x00100038, 0x2981450f, 0x01100038, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x02001405, 0x00100040, - 0x0b004a06, 0x01900060, 0x13008a06, 0x01900060, - 0x13008a06, 0x01900060, 0x43020a04, 0x00100060, - 0x1b00ca05, 0x00100060, 0x23010a07, 0x01500060, - 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, - 0x13008a06, 0x01900060, 0x13008a06, 0x01900060, - 0x23010a07, 0x01500060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x00100010, 0x0200140d, 0x00100050, - 0x0b004a0e, 0x01900070, 0x13008a0e, 0x01900070, - 0x13008a0e, 0x01900070, 0x43020a0c, 0x00100070, - 0x1b00ca0d, 0x00100070, 0x23010a0f, 0x01500070, - 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, - 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, - 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x50029404, 0x00100000, 0x32019405, 0x00100040, - 0x0b004a06, 0x01900060, 0x0b004a06, 0x01900060, - 0x5b02ca04, 0x00100060, 0x3b01d405, 0x00100060, - 0x23010a07, 0x01500060, 0x00000000, 0x00000000, - 0x5802d404, 0x00100000, 0x3b01d405, 0x00100060, - 0x0b004a06, 0x01900060, 0x23010a07, 0x01500060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x5002940c, 0x00100010, 0x3201940d, 0x00100050, - 0x0b004a0e, 0x01900070, 0x0b004a0e, 0x01900070, - 0x5b02ca0c, 0x00100070, 0x3b01d40d, 0x00100070, - 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, - 0x5802d40c, 0x00100010, 0x3b01d40d, 0x00100070, - 0x0b004a0e, 0x01900070, 0x23010a0f, 0x01500070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x000f4800, 0x62031405, 0x00100040, - 0x53028a06, 0x01900060, 0x53028a07, 0x01900060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x000f4808, 0x6203140d, 0x00100048, - 0x53028a0e, 0x01900068, 0x53028a0f, 0x01900068, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000a0c, 0x00100004, 0x11008a0d, 0x00100024, - 0x1980c50e, 0x00100034, 0x2181050e, 0x00100034, - 0x2181050e, 0x00100034, 0x0180050c, 0x00100038, - 0x1180850d, 0x00100038, 0x1181850d, 0x00100038, - 0x2981450f, 0x01100038, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, - 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, - 0x1181850d, 0x00100038, 0x2981450f, 0x01100038, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, - 0x0180c506, 0x00100030, 0x0180c506, 0x00100030, - 0x2180c50c, 0x00100030, 0x49820a0d, 0x0016a130, - 0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x2000ca0c, 0x00100000, 0x49820a0d, 0x0016a130, - 0x1980c50e, 0x00100030, 0x41824a0d, 0x0016a130, - 0x2981450f, 0x01100030, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x00100008, 0x0200140d, 0x00100048, - 0x0b004a0e, 0x01900068, 0x13008a0e, 0x01900068, - 0x13008a0e, 0x01900068, 0x43020a0c, 0x00100070, - 0x1b00ca0d, 0x00100070, 0x1b014a0d, 0x00100070, - 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, - 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, - 0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x50029404, 0x00100000, 0x32019405, 0x00100040, - 0x03004a06, 0x01900060, 0x03004a06, 0x01900060, - 0x6b030a0c, 0x00100060, 0x4b02140d, 0x0016a160, - 0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x6b03140c, 0x00100060, 0x4b02140d, 0x0016a160, - 0x0b004a0e, 0x01900060, 0x4302540d, 0x0016a160, - 0x23010a0f, 0x01500060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, - 0x53028a06, 0x01900060, 0x5b02ca06, 0x01900060, - 0x5b02ca06, 0x01900060, 0x43020a04, 0x00100060, - 0x1b00ca05, 0x00100060, 0x53028a07, 0x0190c060, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, - 0x53028a0e, 0x01900070, 0x5b02ca0e, 0x01900070, - 0x5b02ca0e, 0x01900070, 0x43020a0c, 0x00100070, - 0x1b00ca0d, 0x00100070, 0x53028a0f, 0x0190c070, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, - 0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060, - 0x53028a07, 0x0190c060, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, - 0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070, - 0x53028a0f, 0x0190c070, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u16 b43_ntab_pilot_r3[] = { - 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, - 0xff08, 0xff08, 0x80d5, 0x80d5, 0x80d5, 0x80d5, - 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0xff0a, 0xff82, - 0xffa0, 0xff28, 0xffff, 0xffff, 0xffff, 0xffff, - 0xff82, 0xffa0, 0xff28, 0xff0a, 0xffff, 0xffff, - 0xffff, 0xffff, 0xf83f, 0xfa1f, 0xfa97, 0xfab5, - 0xf2bd, 0xf0bf, 0xffff, 0xffff, 0xf017, 0xf815, - 0xf215, 0xf095, 0xf035, 0xf01d, 0xffff, 0xffff, - 0xff08, 0xff02, 0xff80, 0xff20, 0xff08, 0xff02, - 0xff80, 0xff20, 0xf01f, 0xf817, 0xfa15, 0xf295, - 0xf0b5, 0xf03d, 0xffff, 0xffff, 0xf82a, 0xfa0a, - 0xfa82, 0xfaa0, 0xf2a8, 0xf0aa, 0xffff, 0xffff, - 0xf002, 0xf800, 0xf200, 0xf080, 0xf020, 0xf008, - 0xffff, 0xffff, 0xf00a, 0xf802, 0xfa00, 0xf280, - 0xf0a0, 0xf028, 0xffff, 0xffff, -}; - -static const u32 b43_ntab_tmap_r3[] = { - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, - 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, - 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, - 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, - 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, - 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, - 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, - 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, - 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, - 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, - 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, - 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, - 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, - 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, - 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, - 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, - 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, - 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, - 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, - 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, - 0x22222222, 0x22222222, 0x22f22222, 0x00000222, - 0x11000000, 0x1111f111, 0x11111111, 0x11111111, - 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, - 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, - 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, - 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, - 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, - 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, - 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, - 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, - 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, - 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, - 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, - 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, - 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, - 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, - 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, - 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, - 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, - 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, - 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, - 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, - 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, - 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, - 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, - 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, - 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, - 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_intlevel_r3[] = { - 0x00802070, 0x0671188d, 0x0a60192c, 0x0a300e46, - 0x00c1188d, 0x080024d2, 0x00000070, -}; - -static const u32 b43_ntab_tdtrn_r3[] = { - 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, - 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, - 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, - 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, - 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, - 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, - 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, - 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, - 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, - 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, - 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, - 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, - 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, - 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, - 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, - 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, - 0xfa58fa58, 0xf895043b, 0xff4c09c0, 0xfbc6ffa8, - 0xfb84f384, 0x0798f6f9, 0x05760122, 0x058409f6, - 0x0b500000, 0x05b7f542, 0x08860432, 0x06ddfee7, - 0xfb84f384, 0xf9d90664, 0xf7e8025c, 0x00fff7bd, - 0x05a805a8, 0xf7bd00ff, 0x025cf7e8, 0x0664f9d9, - 0xf384fb84, 0xfee706dd, 0x04320886, 0xf54205b7, - 0x00000b50, 0x09f60584, 0x01220576, 0xf6f90798, - 0xf384fb84, 0xffa8fbc6, 0x09c0ff4c, 0x043bf895, - 0x02d402d4, 0x07de0270, 0xfc96079c, 0xf90afe94, - 0xfe00ff2c, 0x02d4065d, 0x092a0096, 0x0014fbb8, - 0xfd2cfd2c, 0x076afb3c, 0x0096f752, 0xf991fd87, - 0xfb2c0200, 0xfeb8f960, 0x08e0fc96, 0x049802a8, - 0xfd2cfd2c, 0x02a80498, 0xfc9608e0, 0xf960feb8, - 0x0200fb2c, 0xfd87f991, 0xf7520096, 0xfb3c076a, - 0xfd2cfd2c, 0xfbb80014, 0x0096092a, 0x065d02d4, - 0xff2cfe00, 0xfe94f90a, 0x079cfc96, 0x027007de, - 0x02d402d4, 0x027007de, 0x079cfc96, 0xfe94f90a, - 0xff2cfe00, 0x065d02d4, 0x0096092a, 0xfbb80014, - 0xfd2cfd2c, 0xfb3c076a, 0xf7520096, 0xfd87f991, - 0x0200fb2c, 0xf960feb8, 0xfc9608e0, 0x02a80498, - 0xfd2cfd2c, 0x049802a8, 0x08e0fc96, 0xfeb8f960, - 0xfb2c0200, 0xf991fd87, 0x0096f752, 0x076afb3c, - 0xfd2cfd2c, 0x0014fbb8, 0x092a0096, 0x02d4065d, - 0xfe00ff2c, 0xf90afe94, 0xfc96079c, 0x07de0270, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, - 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, - 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, - 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, - 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, - 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, - 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, - 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, - 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, - 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, - 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, - 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, - 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, - 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, - 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, - 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, - 0x061c061c, 0xff30009d, 0xffb21141, 0xfd87fb54, - 0xf65dfe59, 0x02eef99e, 0x0166f03c, 0xfff809b6, - 0x000008a4, 0x000af42b, 0x00eff577, 0xfa840bf2, - 0xfc02ff51, 0x08260f67, 0xfff0036f, 0x0842f9c3, - 0x00000000, 0x063df7be, 0xfc910010, 0xf099f7da, - 0x00af03fe, 0xf40e057c, 0x0a89ff11, 0x0bd5fff6, - 0xf75c0000, 0xf64a0008, 0x0fc4fe9a, 0x0662fd12, - 0x01a709a3, 0x04ac0279, 0xeebf004e, 0xff6300d0, - 0xf9e4f9e4, 0x00d0ff63, 0x004eeebf, 0x027904ac, - 0x09a301a7, 0xfd120662, 0xfe9a0fc4, 0x0008f64a, - 0x0000f75c, 0xfff60bd5, 0xff110a89, 0x057cf40e, - 0x03fe00af, 0xf7daf099, 0x0010fc91, 0xf7be063d, - 0x00000000, 0xf9c30842, 0x036ffff0, 0x0f670826, - 0xff51fc02, 0x0bf2fa84, 0xf57700ef, 0xf42b000a, - 0x08a40000, 0x09b6fff8, 0xf03c0166, 0xf99e02ee, - 0xfe59f65d, 0xfb54fd87, 0x1141ffb2, 0x009dff30, - 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, - 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, - 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, - 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, - 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, - 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, - 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, - 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, - 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, - 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, - 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, - 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, - 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, - 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, - 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, - 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, - 0xfa58fa58, 0xf8f0fe00, 0x0448073d, 0xfdc9fe46, - 0xf9910258, 0x089d0407, 0xfd5cf71a, 0x02affde0, - 0x083e0496, 0xff5a0740, 0xff7afd97, 0x00fe01f1, - 0x0009082e, 0xfa94ff75, 0xfecdf8ea, 0xffb0f693, - 0xfd2cfa58, 0x0433ff16, 0xfba405dd, 0xfa610341, - 0x06a606cb, 0x0039fd2d, 0x0677fa97, 0x01fa05e0, - 0xf896003e, 0x075a068b, 0x012cfc3e, 0xfa23f98d, - 0xfc7cfd43, 0xff90fc0d, 0x01c10982, 0x00c601d6, - 0xfd2cfd2c, 0x01d600c6, 0x098201c1, 0xfc0dff90, - 0xfd43fc7c, 0xf98dfa23, 0xfc3e012c, 0x068b075a, - 0x003ef896, 0x05e001fa, 0xfa970677, 0xfd2d0039, - 0x06cb06a6, 0x0341fa61, 0x05ddfba4, 0xff160433, - 0xfa58fd2c, 0xf693ffb0, 0xf8eafecd, 0xff75fa94, - 0x082e0009, 0x01f100fe, 0xfd97ff7a, 0x0740ff5a, - 0x0496083e, 0xfde002af, 0xf71afd5c, 0x0407089d, - 0x0258f991, 0xfe46fdc9, 0x073d0448, 0xfe00f8f0, - 0xfd2cfd2c, 0xfce00500, 0xfc09fddc, 0xfe680157, - 0x04c70571, 0xfc3aff21, 0xfcd70228, 0x056d0277, - 0x0200fe00, 0x0022f927, 0xfe3c032b, 0xfc44ff3c, - 0x03e9fbdb, 0x04570313, 0x04c9ff5c, 0x000d03b8, - 0xfa580000, 0xfbe900d2, 0xf9d0fe0b, 0x0125fdf9, - 0x042501bf, 0x0328fa2b, 0xffa902f0, 0xfa250157, - 0x0200fe00, 0x03740438, 0xff0405fd, 0x030cfe52, - 0x0037fb39, 0xff6904c5, 0x04f8fd23, 0xfd31fc1b, - 0xfd2cfd2c, 0xfc1bfd31, 0xfd2304f8, 0x04c5ff69, - 0xfb390037, 0xfe52030c, 0x05fdff04, 0x04380374, - 0xfe000200, 0x0157fa25, 0x02f0ffa9, 0xfa2b0328, - 0x01bf0425, 0xfdf90125, 0xfe0bf9d0, 0x00d2fbe9, - 0x0000fa58, 0x03b8000d, 0xff5c04c9, 0x03130457, - 0xfbdb03e9, 0xff3cfc44, 0x032bfe3c, 0xf9270022, - 0xfe000200, 0x0277056d, 0x0228fcd7, 0xff21fc3a, - 0x057104c7, 0x0157fe68, 0xfddcfc09, 0x0500fce0, - 0xfd2cfd2c, 0x0500fce0, 0xfddcfc09, 0x0157fe68, - 0x057104c7, 0xff21fc3a, 0x0228fcd7, 0x0277056d, - 0xfe000200, 0xf9270022, 0x032bfe3c, 0xff3cfc44, - 0xfbdb03e9, 0x03130457, 0xff5c04c9, 0x03b8000d, - 0x0000fa58, 0x00d2fbe9, 0xfe0bf9d0, 0xfdf90125, - 0x01bf0425, 0xfa2b0328, 0x02f0ffa9, 0x0157fa25, - 0xfe000200, 0x04380374, 0x05fdff04, 0xfe52030c, - 0xfb390037, 0x04c5ff69, 0xfd2304f8, 0xfc1bfd31, - 0xfd2cfd2c, 0xfd31fc1b, 0x04f8fd23, 0xff6904c5, - 0x0037fb39, 0x030cfe52, 0xff0405fd, 0x03740438, - 0x0200fe00, 0xfa250157, 0xffa902f0, 0x0328fa2b, - 0x042501bf, 0x0125fdf9, 0xf9d0fe0b, 0xfbe900d2, - 0xfa580000, 0x000d03b8, 0x04c9ff5c, 0x04570313, - 0x03e9fbdb, 0xfc44ff3c, 0xfe3c032b, 0x0022f927, - 0x0200fe00, 0x056d0277, 0xfcd70228, 0xfc3aff21, - 0x04c70571, 0xfe680157, 0xfc09fddc, 0xfce00500, - 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, - 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, - 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, - 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, - 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, - 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, - 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, - 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, - 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, - 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, - 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, - 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, - 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, - 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, - 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, - 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, -}; - -static const u32 b43_ntab_noisevar_r3[] = { - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, - 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, -}; - -static const u16 b43_ntab_mcs_r3[] = { - 0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019, - 0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090, - 0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108, - 0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c, - 0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199, - 0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8, - 0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128, - 0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a, - 0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8, - 0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8, - 0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa, - 0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca, - 0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001, - 0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014, - 0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081, - 0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094, - 0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, -}; - -static const u32 b43_ntab_tdi20a0_r3[] = { - 0x00091226, 0x000a1429, 0x000b56ad, 0x000c58b0, - 0x000d5ab3, 0x000e9cb6, 0x000f9eba, 0x0000c13d, - 0x00020301, 0x00030504, 0x00040708, 0x0005090b, - 0x00064b8e, 0x00095291, 0x000a5494, 0x000b9718, - 0x000c9927, 0x000d9b2a, 0x000edd2e, 0x000fdf31, - 0x000101b4, 0x000243b7, 0x000345bb, 0x000447be, - 0x00058982, 0x00068c05, 0x00099309, 0x000a950c, - 0x000bd78f, 0x000cd992, 0x000ddb96, 0x000f1d99, - 0x00005fa8, 0x0001422c, 0x0002842f, 0x00038632, - 0x00048835, 0x0005ca38, 0x0006ccbc, 0x0009d3bf, - 0x000b1603, 0x000c1806, 0x000d1a0a, 0x000e1c0d, - 0x000f5e10, 0x00008093, 0x00018297, 0x0002c49a, - 0x0003c680, 0x0004c880, 0x00060b00, 0x00070d00, - 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi20a1_r3[] = { - 0x00014b26, 0x00028d29, 0x000393ad, 0x00049630, - 0x0005d833, 0x0006da36, 0x00099c3a, 0x000a9e3d, - 0x000bc081, 0x000cc284, 0x000dc488, 0x000f068b, - 0x0000488e, 0x00018b91, 0x0002d214, 0x0003d418, - 0x0004d6a7, 0x000618aa, 0x00071aae, 0x0009dcb1, - 0x000b1eb4, 0x000c0137, 0x000d033b, 0x000e053e, - 0x000f4702, 0x00008905, 0x00020c09, 0x0003128c, - 0x0004148f, 0x00051712, 0x00065916, 0x00091b19, - 0x000a1d28, 0x000b5f2c, 0x000c41af, 0x000d43b2, - 0x000e85b5, 0x000f87b8, 0x0000c9bc, 0x00024cbf, - 0x00035303, 0x00045506, 0x0005978a, 0x0006998d, - 0x00095b90, 0x000a5d93, 0x000b9f97, 0x000c821a, - 0x000d8400, 0x000ec600, 0x000fc800, 0x00010a00, - 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi40a0_r3[] = { - 0x0011a346, 0x00136ccf, 0x0014f5d9, 0x001641e2, - 0x0017cb6b, 0x00195475, 0x001b2383, 0x001cad0c, - 0x001e7616, 0x0000821f, 0x00020ba8, 0x0003d4b2, - 0x00056447, 0x00072dd0, 0x0008b6da, 0x000a02e3, - 0x000b8c6c, 0x000d15f6, 0x0011e484, 0x0013ae0d, - 0x00153717, 0x00168320, 0x00180ca9, 0x00199633, - 0x001b6548, 0x001ceed1, 0x001eb7db, 0x0000c3e4, - 0x00024d6d, 0x000416f7, 0x0005a585, 0x00076f0f, - 0x0008f818, 0x000a4421, 0x000bcdab, 0x000d9734, - 0x00122649, 0x0013efd2, 0x001578dc, 0x0016c4e5, - 0x00184e6e, 0x001a17f8, 0x001ba686, 0x001d3010, - 0x001ef999, 0x00010522, 0x00028eac, 0x00045835, - 0x0005e74a, 0x0007b0d3, 0x00093a5d, 0x000a85e6, - 0x000c0f6f, 0x000dd8f9, 0x00126787, 0x00143111, - 0x0015ba9a, 0x00170623, 0x00188fad, 0x001a5936, - 0x001be84b, 0x001db1d4, 0x001f3b5e, 0x000146e7, - 0x00031070, 0x000499fa, 0x00062888, 0x0007f212, - 0x00097b9b, 0x000ac7a4, 0x000c50ae, 0x000e1a37, - 0x0012a94c, 0x001472d5, 0x0015fc5f, 0x00174868, - 0x0018d171, 0x001a9afb, 0x001c2989, 0x001df313, - 0x001f7c9c, 0x000188a5, 0x000351af, 0x0004db38, - 0x0006aa4d, 0x000833d7, 0x0009bd60, 0x000b0969, - 0x000c9273, 0x000e5bfc, 0x00132a8a, 0x0014b414, - 0x00163d9d, 0x001789a6, 0x001912b0, 0x001adc39, - 0x001c6bce, 0x001e34d8, 0x001fbe61, 0x0001ca6a, - 0x00039374, 0x00051cfd, 0x0006ec0b, 0x00087515, - 0x0009fe9e, 0x000b4aa7, 0x000cd3b1, 0x000e9d3a, - 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_tdi40a1_r3[] = { - 0x001edb36, 0x000129ca, 0x0002b353, 0x00047cdd, - 0x0005c8e6, 0x000791ef, 0x00091bf9, 0x000aaa07, - 0x000c3391, 0x000dfd1a, 0x00120923, 0x0013d22d, - 0x00155c37, 0x0016eacb, 0x00187454, 0x001a3dde, - 0x001b89e7, 0x001d12f0, 0x001f1cfa, 0x00016b88, - 0x00033492, 0x0004be1b, 0x00060a24, 0x0007d32e, - 0x00095d38, 0x000aec4c, 0x000c7555, 0x000e3edf, - 0x00124ae8, 0x001413f1, 0x0015a37b, 0x00172c89, - 0x0018b593, 0x001a419c, 0x001bcb25, 0x001d942f, - 0x001f63b9, 0x0001ad4d, 0x00037657, 0x0004c260, - 0x00068be9, 0x000814f3, 0x0009a47c, 0x000b2d8a, - 0x000cb694, 0x000e429d, 0x00128c26, 0x001455b0, - 0x0015e4ba, 0x00176e4e, 0x0018f758, 0x001a8361, - 0x001c0cea, 0x001dd674, 0x001fa57d, 0x0001ee8b, - 0x0003b795, 0x0005039e, 0x0006cd27, 0x000856b1, - 0x0009e5c6, 0x000b6f4f, 0x000cf859, 0x000e8462, - 0x00130deb, 0x00149775, 0x00162603, 0x0017af8c, - 0x00193896, 0x001ac49f, 0x001c4e28, 0x001e17b2, - 0x0000a6c7, 0x00023050, 0x0003f9da, 0x00054563, - 0x00070eec, 0x00089876, 0x000a2704, 0x000bb08d, - 0x000d3a17, 0x001185a0, 0x00134f29, 0x0014d8b3, - 0x001667c8, 0x0017f151, 0x00197adb, 0x001b0664, - 0x001c8fed, 0x001e5977, 0x0000e805, 0x0002718f, - 0x00043b18, 0x000586a1, 0x0007502b, 0x0008d9b4, - 0x000a68c9, 0x000bf252, 0x000dbbdc, 0x0011c7e5, - 0x001390ee, 0x00151a78, 0x0016a906, 0x00183290, - 0x0019bc19, 0x001b4822, 0x001cd12c, 0x001e9ab5, - 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_pilotlt_r3[] = { - 0x76540213, 0x62407351, 0x76543210, 0x76540213, - 0x76540213, 0x76430521, -}; - -static const u32 b43_ntab_channelest_r3[] = { - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x44444444, 0x44444444, 0x44444444, 0x44444444, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, - 0x10101010, 0x10101010, 0x10101010, 0x10101010, -}; - -static const u8 b43_ntab_framelookup_r3[] = { - 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, - 0x0a, 0x0c, 0x1c, 0x1c, 0x0b, 0x0d, 0x1e, 0x1e, - 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1a, 0x1a, - 0x0e, 0x10, 0x20, 0x28, 0x0f, 0x11, 0x22, 0x2a, -}; - -static const u8 b43_ntab_estimatepowerlt0_r3[] = { - 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, - 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, - 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, - 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, - 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, - 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, - 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, - 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, -}; - -static const u8 b43_ntab_estimatepowerlt1_r3[] = { - 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, - 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, - 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, - 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, - 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, - 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, - 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, - 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, -}; - -static const u8 b43_ntab_adjustpower0_r3[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static const u8 b43_ntab_adjustpower1_r3[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; - -static const u32 b43_ntab_gainctl0_r3[] = { - 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, - 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, - 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, - 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, - 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, - 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, - 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, - 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, - 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, - 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, - 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, - 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, - 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, - 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, - 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, - 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, - 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, - 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, - 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, - 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, - 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, - 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, - 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, - 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, - 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, - 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, - 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, - 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, - 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, - 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, - 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, - 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, -}; - -static const u32 b43_ntab_gainctl1_r3[] = { - 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, - 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, - 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, - 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, - 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, - 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, - 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, - 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, - 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, - 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, - 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, - 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, - 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, - 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, - 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, - 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, - 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, - 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, - 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, - 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, - 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, - 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, - 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, - 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, - 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, - 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, - 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, - 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, - 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, - 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, - 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, - 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, -}; - -static const u32 b43_ntab_iqlt0_r3[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_ntab_iqlt1_r3[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u16 b43_ntab_loftlt0_r3[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -static const u16 b43_ntab_loftlt1_r3[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -/* volatile tables, PHY revision >= 3 */ - -/* indexed by antswctl2g */ -static const u16 b43_ntab_antswctl_r3[4][32] = { - { - 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, - 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, - 0x0000, 0x0000, 0x0188, 0x0000, 0x0000, - 0x0000, 0x0082, 0x0082, 0x0211, 0x0222, - 0x0328, 0x0000, 0x0000, 0x0000, 0x0144, - 0x0000, 0x0000, 0x0000, 0x0188, 0x0000, - 0x0000, 0x0000, - }, - { - 0x0022, 0x0022, 0x0011, 0x0022, 0x0022, - 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, - 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, - 0x0000, 0x0022, 0x0022, 0x0011, 0x0022, - 0x0022, 0x0000, 0x0000, 0x0000, 0x0011, - 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, - 0x0000, 0x0000, - }, - { - 0x0088, 0x0088, 0x0044, 0x0088, 0x0088, - 0x0000, 0x0000, 0x0000, 0x0044, 0x0000, - 0x0000, 0x0000, 0x0088, 0x0000, 0x0000, - 0x0000, 0x0088, 0x0088, 0x0044, 0x0088, - 0x0088, 0x0000, 0x0000, 0x0000, 0x0044, - 0x0000, 0x0000, 0x0000, 0x0088, 0x0000, - 0x0000, 0x0000, - }, - { - 0x0022, 0x0022, 0x0011, 0x0022, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, - 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, - 0x03cc, 0x0022, 0x0022, 0x0011, 0x0022, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0011, - 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, - 0x0000, 0x03cc, - } -}; - -/* static tables, PHY revision >= 7 */ - -/* Copied from brcmsmac (5.75.11) */ -static const u32 b43_ntab_tmap_r7[] = { - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, - 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, - 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, - 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, - 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, - 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, - 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, - 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, - 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, - 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, - 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, - 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, - 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, - 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, - 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, - 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, - 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, - 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, - 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, - 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, - 0x22222222, 0x22222222, 0x22f22222, 0x00000222, - 0x11000000, 0x1111f111, 0x11111111, 0x11111111, - 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, - 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, - 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, - 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, - 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, - 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, - 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, - 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, - 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, - 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, - 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, - 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, - 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, - 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, - 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, - 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, - 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, - 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, - 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, - 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, - 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, - 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, - 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, - 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, - 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, - 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, - 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, - 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, - 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, - 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, - 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -/* Extracted from MMIO dump of 6.30.223.141 */ -static const u32 b43_ntab_noisevar_r7[] = { - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, - 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, -}; - -/************************************************** - * TX gain tables - **************************************************/ - -static const u32 b43_ntab_tx_gain_rev0_1_2[] = { - 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42, - 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44, - 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844, - 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44, - 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844, - 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644, - 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444, - 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44, - 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844, - 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44, - 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944, - 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744, - 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544, - 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44, - 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844, - 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44, - 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944, - 0x03902942, 0x03902844, 0x03902842, 0x03902744, - 0x03902742, 0x03902644, 0x03902642, 0x03902544, - 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44, - 0x03802a42, 0x03802944, 0x03802942, 0x03802844, - 0x03802842, 0x03802744, 0x03802742, 0x03802644, - 0x03802642, 0x03802544, 0x03802542, 0x03802444, - 0x03802442, 0x03802344, 0x03802342, 0x03802244, - 0x03802242, 0x03802144, 0x03802142, 0x03802044, - 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44, - 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44, - 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44, - 0x03801a42, 0x03801944, 0x03801942, 0x03801844, - 0x03801842, 0x03801744, 0x03801742, 0x03801644, - 0x03801642, 0x03801544, 0x03801542, 0x03801444, - 0x03801442, 0x03801344, 0x03801342, 0x00002b00, -}; - -/* EPA 2 GHz */ - -static const u32 b43_ntab_tx_gain_epa_rev3_2g[] = { - 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e, - 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037, - 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e, - 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037, - 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e, - 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037, - 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e, - 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037, - 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e, - 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037, - 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e, - 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037, - 0x19410044, 0x19410042, 0x19410040, 0x1941003e, - 0x1941003c, 0x1941003b, 0x19410039, 0x19410037, - 0x18410044, 0x18410042, 0x18410040, 0x1841003e, - 0x1841003c, 0x1841003b, 0x18410039, 0x18410037, - 0x17410044, 0x17410042, 0x17410040, 0x1741003e, - 0x1741003c, 0x1741003b, 0x17410039, 0x17410037, - 0x16410044, 0x16410042, 0x16410040, 0x1641003e, - 0x1641003c, 0x1641003b, 0x16410039, 0x16410037, - 0x15410044, 0x15410042, 0x15410040, 0x1541003e, - 0x1541003c, 0x1541003b, 0x15410039, 0x15410037, - 0x14410044, 0x14410042, 0x14410040, 0x1441003e, - 0x1441003c, 0x1441003b, 0x14410039, 0x14410037, - 0x13410044, 0x13410042, 0x13410040, 0x1341003e, - 0x1341003c, 0x1341003b, 0x13410039, 0x13410037, - 0x12410044, 0x12410042, 0x12410040, 0x1241003e, - 0x1241003c, 0x1241003b, 0x12410039, 0x12410037, - 0x11410044, 0x11410042, 0x11410040, 0x1141003e, - 0x1141003c, 0x1141003b, 0x11410039, 0x11410037, - 0x10410044, 0x10410042, 0x10410040, 0x1041003e, - 0x1041003c, 0x1041003b, 0x10410039, 0x10410037, -}; - -static const u32 b43_ntab_tx_gain_epa_rev3_hi_pwr_2g[] = { - 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e, - 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037, - 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e, - 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037, - 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e, - 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037, - 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e, - 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037, - 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e, - 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037, - 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e, - 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037, - 0x09410044, 0x09410042, 0x09410040, 0x0941003e, - 0x0941003c, 0x0941003b, 0x09410039, 0x09410037, - 0x08410044, 0x08410042, 0x08410040, 0x0841003e, - 0x0841003c, 0x0841003b, 0x08410039, 0x08410037, - 0x07410044, 0x07410042, 0x07410040, 0x0741003e, - 0x0741003c, 0x0741003b, 0x07410039, 0x07410037, - 0x06410044, 0x06410042, 0x06410040, 0x0641003e, - 0x0641003c, 0x0641003b, 0x06410039, 0x06410037, - 0x05410044, 0x05410042, 0x05410040, 0x0541003e, - 0x0541003c, 0x0541003b, 0x05410039, 0x05410037, - 0x04410044, 0x04410042, 0x04410040, 0x0441003e, - 0x0441003c, 0x0441003b, 0x04410039, 0x04410037, - 0x03410044, 0x03410042, 0x03410040, 0x0341003e, - 0x0341003c, 0x0341003b, 0x03410039, 0x03410037, - 0x02410044, 0x02410042, 0x02410040, 0x0241003e, - 0x0241003c, 0x0241003b, 0x02410039, 0x02410037, - 0x01410044, 0x01410042, 0x01410040, 0x0141003e, - 0x0141003c, 0x0141003b, 0x01410039, 0x01410037, - 0x00410044, 0x00410042, 0x00410040, 0x0041003e, - 0x0041003c, 0x0041003b, 0x00410039, 0x00410037 -}; - -/* EPA 5 GHz */ - -static const u32 b43_ntab_tx_gain_epa_rev3_5g[] = { - 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e, - 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037, - 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e, - 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037, - 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e, - 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037, - 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e, - 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037, - 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e, - 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037, - 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e, - 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037, - 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e, - 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037, - 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e, - 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037, - 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e, - 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037, - 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e, - 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037, - 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e, - 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037, - 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e, - 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037, - 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e, - 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037, - 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e, - 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037, - 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e, - 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037, - 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e, - 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037, -}; - -static const u32 b43_ntab_tx_gain_epa_rev4_5g[] = { - 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e, - 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037, - 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e, - 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037, - 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e, - 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037, - 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e, - 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037, - 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e, - 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037, - 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e, - 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037, - 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e, - 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037, - 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e, - 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037, - 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e, - 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037, - 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e, - 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037, - 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e, - 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037, - 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e, - 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038, - 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e, - 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037, - 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e, - 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037, - 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e, - 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037, - 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c, - 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034, -}; - -static const u32 b43_ntab_tx_gain_epa_rev4_hi_pwr_5g[] = { - 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e, - 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037, - 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e, - 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037, - 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e, - 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037, - 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e, - 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037, - 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e, - 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037, - 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e, - 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037, - 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e, - 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037, - 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e, - 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037, - 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e, - 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037, - 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e, - 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037, - 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e, - 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037, - 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e, - 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038, - 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e, - 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037, - 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e, - 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037, - 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e, - 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037, - 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c, - 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034 -}; - -static const u32 b43_ntab_tx_gain_epa_rev5_5g[] = { - 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044, - 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c, - 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e, - 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a, - 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e, - 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a, - 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e, - 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037, - 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040, - 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a, - 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c, - 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038, - 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b, - 0x09620039, 0x09620037, 0x09620035, 0x09620033, - 0x08620044, 0x08620042, 0x08620040, 0x0862003e, - 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039, - 0x07620043, 0x07620042, 0x07620040, 0x0762003f, - 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039, - 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b, - 0x06620039, 0x06620037, 0x06620035, 0x06620033, - 0x05620046, 0x05620044, 0x05620042, 0x05620040, - 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039, - 0x04620044, 0x04620042, 0x04620040, 0x0462003e, - 0x0462003c, 0x0462003b, 0x04620039, 0x04620038, - 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039, - 0x03620038, 0x03620037, 0x03620035, 0x03620033, - 0x0262004c, 0x0262004a, 0x02620048, 0x02620047, - 0x02620046, 0x02620044, 0x02620043, 0x02620042, - 0x0162004a, 0x01620048, 0x01620046, 0x01620044, - 0x01620043, 0x01620042, 0x01620041, 0x01620040, - 0x00620042, 0x00620040, 0x0062003e, 0x0062003c, - 0x0062003b, 0x00620039, 0x00620037, 0x00620035, -}; - -/* IPA 2 GHz */ - -static const u32 b43_ntab_tx_gain_ipa_rev3_2g[] = { - 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029, - 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025, - 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029, - 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025, - 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029, - 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025, - 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029, - 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025, - 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029, - 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025, - 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029, - 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025, - 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029, - 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025, - 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029, - 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025, - 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029, - 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025, - 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029, - 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025, - 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029, - 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025, - 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029, - 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025, - 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029, - 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025, - 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029, - 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025, - 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029, - 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025, - 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029, - 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025, -}; - -static const u32 b43_ntab_tx_gain_ipa_rev5_2g[] = { - 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029, - 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025, - 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029, - 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025, - 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029, - 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025, - 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029, - 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025, - 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029, - 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025, - 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029, - 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025, - 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029, - 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025, - 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029, - 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025, - 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029, - 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025, - 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029, - 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025, - 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029, - 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025, - 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029, - 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025, - 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029, - 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025, - 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029, - 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025, - 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029, - 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025, - 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029, - 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025, -}; - -static const u32 b43_ntab_tx_gain_ipa_rev6_2g[] = { - 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029, - 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025, - 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029, - 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025, - 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029, - 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025, - 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029, - 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025, - 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029, - 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025, - 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029, - 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025, - 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029, - 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025, - 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029, - 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025, - 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029, - 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025, - 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029, - 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025, - 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029, - 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025, - 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029, - 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025, - 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029, - 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025, - 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029, - 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025, - 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029, - 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025, - 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029, - 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025, -}; - -/* Copied from brcmsmac (5.75.11): nphy_tpc_txgain_ipa_2g_2057rev5 */ -static const u32 b43_ntab_tx_gain_ipa_2057_rev5_2g[] = { - 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e, - 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033, - 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e, - 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d, - 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c, - 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d, - 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a, - 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029, - 0x30270027, 0x30270025, 0x30270023, 0x301f002c, - 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024, - 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b, - 0x30170028, 0x30170026, 0x30170024, 0x30170022, - 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b, - 0x3017001a, 0x30170018, 0x30170017, 0x30170015, - 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024, - 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d, - 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017, - 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215, - 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, - 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, -}; - -/* Extracted from MMIO dump of 6.30.223.141 */ -static const u32 b43_ntab_tx_gain_ipa_2057_rev9_2g[] = { - 0x60ff0031, 0x60e7002c, 0x60cf002a, 0x60c70029, - 0x60b70029, 0x60a70029, 0x609f002a, 0x6097002b, - 0x6087002e, 0x60770031, 0x606f0032, 0x60670034, - 0x60670031, 0x605f0033, 0x605f0031, 0x60570033, - 0x60570030, 0x6057002d, 0x6057002b, 0x604f002d, - 0x604f002b, 0x604f0029, 0x604f0026, 0x60470029, - 0x60470027, 0x603f0029, 0x603f0027, 0x603f0025, - 0x60370029, 0x60370027, 0x60370024, 0x602f002a, - 0x602f0028, 0x602f0026, 0x602f0024, 0x6027002a, - 0x60270028, 0x60270026, 0x60270024, 0x60270022, - 0x601f002b, 0x601f0029, 0x601f0027, 0x601f0024, - 0x601f0022, 0x601f0020, 0x601f001f, 0x601f001d, - 0x60170029, 0x60170027, 0x60170025, 0x60170023, - 0x60170021, 0x6017001f, 0x6017001d, 0x6017001c, - 0x6017001a, 0x60170018, 0x60170018, 0x60170016, - 0x60170015, 0x600f0029, 0x600f0027, 0x600f0025, - 0x600f0023, 0x600f0021, 0x600f001f, 0x600f001d, - 0x600f001c, 0x600f001a, 0x600f0019, 0x600f0018, - 0x600f0016, 0x600f0015, 0x600f0115, 0x600f0215, - 0x600f0315, 0x600f0415, 0x600f0515, 0x600f0615, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, - 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, -}; - -/* Extracted from MMIO dump of 6.30.223.248 */ -static const u32 b43_ntab_tx_gain_ipa_2057_rev14_2g[] = { - 0x50df002e, 0x50cf002d, 0x50bf002c, 0x50b7002b, - 0x50af002a, 0x50a70029, 0x509f0029, 0x50970028, - 0x508f0027, 0x50870027, 0x507f0027, 0x50770027, - 0x506f0027, 0x50670027, 0x505f0028, 0x50570029, - 0x504f002b, 0x5047002e, 0x5047002b, 0x50470029, - 0x503f002c, 0x503f0029, 0x5037002c, 0x5037002a, - 0x50370028, 0x502f002d, 0x502f002b, 0x502f0028, - 0x502f0026, 0x5027002d, 0x5027002a, 0x50270028, - 0x50270026, 0x50270024, 0x501f002e, 0x501f002b, - 0x501f0029, 0x501f0027, 0x501f0024, 0x501f0022, - 0x501f0020, 0x501f001f, 0x5017002c, 0x50170029, - 0x50170027, 0x50170024, 0x50170022, 0x50170021, - 0x5017001f, 0x5017001d, 0x5017001b, 0x5017001a, - 0x50170018, 0x50170017, 0x50170015, 0x500f002c, - 0x500f002a, 0x500f0027, 0x500f0025, 0x500f0023, - 0x500f0022, 0x500f001f, 0x500f001e, 0x500f001c, - 0x500f001a, 0x500f0019, 0x500f0018, 0x500f0016, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, - 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, -}; - -/* IPA 2 5Hz */ - -static const u32 b43_ntab_tx_gain_ipa_rev3_5g[] = { - 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031, - 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b, - 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027, - 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022, - 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025, - 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027, - 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023, - 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027, - 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022, - 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025, - 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021, - 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026, - 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022, - 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026, - 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022, - 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026, - 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022, - 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026, - 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022, - 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026, - 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021, - 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026, - 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029, - 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024, - 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027, - 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023, - 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026, - 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022, - 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025, - 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027, - 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022, - 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f, -}; - -/* Extracted from MMIO dump of 6.30.223.141 */ -static const u32 b43_ntab_tx_gain_ipa_2057_rev9_5g[] = { - 0x7f7f0053, 0x7f7f004b, 0x7f7f0044, 0x7f7f003f, - 0x7f7f0039, 0x7f7f0035, 0x7f7f0032, 0x7f7f0030, - 0x7f7f002d, 0x7e7f0030, 0x7e7f002d, 0x7d7f0032, - 0x7d7f002f, 0x7d7f002c, 0x7c7f0032, 0x7c7f0030, - 0x7c7f002d, 0x7b7f0030, 0x7b7f002e, 0x7b7f002b, - 0x7a7f0032, 0x7a7f0030, 0x7a7f002d, 0x7a7f002b, - 0x797f0030, 0x797f002e, 0x797f002b, 0x797f0029, - 0x787f0030, 0x787f002d, 0x787f002b, 0x777f0032, - 0x777f0030, 0x777f002d, 0x777f002b, 0x767f0031, - 0x767f002f, 0x767f002c, 0x767f002a, 0x757f0031, - 0x757f002f, 0x757f002c, 0x757f002a, 0x747f0030, - 0x747f002d, 0x747f002b, 0x737f0032, 0x737f002f, - 0x737f002c, 0x737f002a, 0x727f0030, 0x727f002d, - 0x727f002b, 0x727f0029, 0x717f0030, 0x717f002d, - 0x717f002b, 0x707f0031, 0x707f002f, 0x707f002c, - 0x707f002a, 0x707f0027, 0x707f0025, 0x707f0023, - 0x707f0021, 0x707f001f, 0x707f001d, 0x707f001c, - 0x707f001a, 0x707f0019, 0x707f0017, 0x707f0016, - 0x707f0015, 0x707f0014, 0x707f0012, 0x707f0012, - 0x707f0011, 0x707f0010, 0x707f000f, 0x707f000e, - 0x707f000d, 0x707f000d, 0x707f000c, 0x707f000b, - 0x707f000a, 0x707f000a, 0x707f0009, 0x707f0008, - 0x707f0008, 0x707f0008, 0x707f0008, 0x707f0007, - 0x707f0007, 0x707f0006, 0x707f0006, 0x707f0006, - 0x707f0005, 0x707f0005, 0x707f0005, 0x707f0004, - 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003, - 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, - 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, - 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, - 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, - 0x707f0002, 0x707f0001, 0x707f0001, 0x707f0001, - 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, -}; - -const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[] = { - -114, -108, -98, -91, -84, -78, -70, -62, - -54, -46, -39, -31, -23, -15, -8, 0 -}; - -/* Extracted from MMIO dump of 6.30.223.248 - * Entries: 0, 15, 17, 21, 24, 26, 27, 29, 30 were guessed - */ -static const s16 b43_ntab_rf_pwr_offset_2057_rev9_2g[] = { - -133, -133, -107, -92, -81, - -73, -66, -61, -56, -52, - -48, -44, -41, -37, -34, - -31, -28, -25, -22, -19, - -17, -14, -12, -10, -9, - -7, -5, -4, -3, -2, - -1, 0, -}; - -/* Extracted from MMIO dump of 6.30.223.248 */ -static const s16 b43_ntab_rf_pwr_offset_2057_rev9_5g[] = { - -101, -94, -86, -79, -72, - -65, -57, -50, -42, -35, - -28, -21, -16, -9, -4, - 0, -}; - -/* Extracted from MMIO dump of 6.30.223.248 - * Entries: 0, 26, 28, 29, 30, 31 were guessed - */ -static const s16 b43_ntab_rf_pwr_offset_2057_rev14_2g[] = { - -111, -111, -111, -84, -70, - -59, -52, -45, -40, -36, - -32, -29, -26, -23, -21, - -18, -16, -15, -13, -11, - -10, -8, -7, -6, -5, - -4, -4, -3, -3, -2, - -2, -1, -}; - -const u16 tbl_iqcal_gainparams[2][9][8] = { - { - { 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 }, - { 0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69 }, - { 0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68 }, - { 0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67 }, - { 0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66 }, - { 0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65 }, - { 0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65 }, - { 0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65 }, - { 0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65 } - }, - { - { 0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, - { 0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, - { 0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79 }, - { 0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78 }, - { 0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78 }, - { 0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78 }, - { 0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78 }, - { 0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78 }, - { 0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78 } - } -}; - -const struct nphy_txiqcal_ladder ladder_lo[] = { - { 3, 0 }, - { 4, 0 }, - { 6, 0 }, - { 9, 0 }, - { 13, 0 }, - { 18, 0 }, - { 25, 0 }, - { 25, 1 }, - { 25, 2 }, - { 25, 3 }, - { 25, 4 }, - { 25, 5 }, - { 25, 6 }, - { 25, 7 }, - { 35, 7 }, - { 50, 7 }, - { 71, 7 }, - { 100, 7 } -}; - -const struct nphy_txiqcal_ladder ladder_iq[] = { - { 3, 0 }, - { 4, 0 }, - { 6, 0 }, - { 9, 0 }, - { 13, 0 }, - { 18, 0 }, - { 25, 0 }, - { 35, 0 }, - { 50, 0 }, - { 71, 0 }, - { 100, 0 }, - { 100, 1 }, - { 100, 2 }, - { 100, 3 }, - { 100, 4 }, - { 100, 5 }, - { 100, 6 }, - { 100, 7 } -}; - -const u16 loscale[] = { - 256, 256, 271, 271, - 287, 256, 256, 271, - 271, 287, 287, 304, - 304, 256, 256, 271, - 271, 287, 287, 304, - 304, 322, 322, 341, - 341, 362, 362, 383, - 383, 256, 256, 271, - 271, 287, 287, 304, - 304, 322, 322, 256, - 256, 271, 271, 287, - 287, 304, 304, 322, - 322, 341, 341, 362, - 362, 256, 256, 271, - 271, 287, 287, 304, - 304, 322, 322, 256, - 256, 271, 271, 287, - 287, 304, 304, 322, - 322, 341, 341, 362, - 362, 256, 256, 271, - 271, 287, 287, 304, - 304, 322, 322, 341, - 341, 362, 362, 383, - 383, 406, 406, 430, - 430, 455, 455, 482, - 482, 511, 511, 541, - 541, 573, 573, 607, - 607, 643, 643, 681, - 681, 722, 722, 764, - 764, 810, 810, 858, - 858, 908, 908, 962, - 962, 1019, 1019, 256 -}; - -const u16 tbl_tx_iqlo_cal_loft_ladder_40[] = { - 0x0200, 0x0300, 0x0400, 0x0700, - 0x0900, 0x0c00, 0x1200, 0x1201, - 0x1202, 0x1203, 0x1204, 0x1205, - 0x1206, 0x1207, 0x1907, 0x2307, - 0x3207, 0x4707 -}; - -const u16 tbl_tx_iqlo_cal_loft_ladder_20[] = { - 0x0300, 0x0500, 0x0700, 0x0900, - 0x0d00, 0x1100, 0x1900, 0x1901, - 0x1902, 0x1903, 0x1904, 0x1905, - 0x1906, 0x1907, 0x2407, 0x3207, - 0x4607, 0x6407 -}; - -const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[] = { - 0x0100, 0x0200, 0x0400, 0x0700, - 0x0900, 0x0c00, 0x1200, 0x1900, - 0x2300, 0x3200, 0x4700, 0x4701, - 0x4702, 0x4703, 0x4704, 0x4705, - 0x4706, 0x4707 -}; - -const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[] = { - 0x0200, 0x0300, 0x0600, 0x0900, - 0x0d00, 0x1100, 0x1900, 0x2400, - 0x3200, 0x4600, 0x6400, 0x6401, - 0x6402, 0x6403, 0x6404, 0x6405, - 0x6406, 0x6407 -}; - -const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3] = { }; - -const u16 tbl_tx_iqlo_cal_startcoefs[B43_NTAB_TX_IQLO_CAL_STARTCOEFS] = { }; - -const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = { - 0x8423, 0x8323, 0x8073, 0x8256, - 0x8045, 0x8223, 0x9423, 0x9323, - 0x9073, 0x9256, 0x9045, 0x9223 -}; - -const u16 tbl_tx_iqlo_cal_cmds_recal[] = { - 0x8101, 0x8253, 0x8053, 0x8234, - 0x8034, 0x9101, 0x9253, 0x9053, - 0x9234, 0x9034 -}; - -const u16 tbl_tx_iqlo_cal_cmds_fullcal[] = { - 0x8123, 0x8264, 0x8086, 0x8245, - 0x8056, 0x9123, 0x9264, 0x9086, - 0x9245, 0x9056 -}; - -const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = { - 0x8434, 0x8334, 0x8084, 0x8267, - 0x8056, 0x8234, 0x9434, 0x9334, - 0x9084, 0x9267, 0x9056, 0x9234 -}; - -const s16 tbl_tx_filter_coef_rev4[7][15] = { - { -377, 137, -407, 208, -1527, - 956, 93, 186, 93, 230, - -44, 230, 201, -191, 201 }, - { -77, 20, -98, 49, -93, - 60, 56, 111, 56, 26, - -5, 26, 34, -32, 34 }, - { -360, 164, -376, 164, -1533, - 576, 308, -314, 308, 121, - -73, 121, 91, 124, 91 }, - { -295, 200, -363, 142, -1391, - 826, 151, 301, 151, 151, - 301, 151, 602, -752, 602 }, - { -92, 58, -96, 49, -104, - 44, 17, 35, 17, 12, - 25, 12, 13, 27, 13 }, - { -375, 136, -399, 209, -1479, - 949, 130, 260, 130, 230, - -44, 230, 201, -191, 201 }, - { 0xed9, 0xc8, 0xe95, 0x8e, 0xa91, - 0x33a, 0x97, 0x12d, 0x97, 0x97, - 0x12d, 0x97, 0x25a, 0xd10, 0x25a } -}; - -/* addr0, addr1, bmask, shift */ -const struct nphy_rf_control_override_rev2 tbl_rf_control_override_rev2[] = { - { 0x78, 0x78, 0x0038, 3 }, /* for field == 0x0002 (fls == 2) */ - { 0x7A, 0x7D, 0x0001, 0 }, /* for field == 0x0004 (fls == 3) */ - { 0x7A, 0x7D, 0x0002, 1 }, /* for field == 0x0008 (fls == 4) */ - { 0x7A, 0x7D, 0x0004, 2 }, /* for field == 0x0010 (fls == 5) */ - { 0x7A, 0x7D, 0x0030, 4 }, /* for field == 0x0020 (fls == 6) */ - { 0x7A, 0x7D, 0x00C0, 6 }, /* for field == 0x0040 (fls == 7) */ - { 0x7A, 0x7D, 0x0100, 8 }, /* for field == 0x0080 (fls == 8) */ - { 0x7A, 0x7D, 0x0200, 9 }, /* for field == 0x0100 (fls == 9) */ - { 0x78, 0x78, 0x0004, 2 }, /* for field == 0x0200 (fls == 10) */ - { 0x7B, 0x7E, 0x01FF, 0 }, /* for field == 0x0400 (fls == 11) */ - { 0x7C, 0x7F, 0x01FF, 0 }, /* for field == 0x0800 (fls == 12) */ - { 0x78, 0x78, 0x0100, 8 }, /* for field == 0x1000 (fls == 13) */ - { 0x78, 0x78, 0x0200, 9 }, /* for field == 0x2000 (fls == 14) */ - { 0x78, 0x78, 0xF000, 12 } /* for field == 0x4000 (fls == 15) */ -}; - -/* val_mask, val_shift, en_addr0, val_addr0, en_addr1, val_addr1 */ -const struct nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = { - { 0x8000, 15, 0xE5, 0xF9, 0xE6, 0xFB }, /* field == 0x0001 (fls 1) */ - { 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */ - { 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */ - { 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */ - { 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */ - { 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */ - { 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */ - { 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */ - { 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */ - { 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */ - { 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */ - { 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */ - { 0xFFFF, 0, 0xE7, 0x7B, 0xEC, 0x7E }, /* field == 0x1000 (fls 13) */ - { 0xFFFF, 0, 0xE7, 0x7C, 0xEC, 0x7F }, /* field == 0x2000 (fls 14) */ - { 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */ -}; - -/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ -static const struct nphy_rf_control_override_rev7 - tbl_rf_control_override_rev7_over0[] = { - { 0x0004, 0x07A, 0x07D, 0x0002, 1 }, - { 0x0008, 0x07A, 0x07D, 0x0004, 2 }, - { 0x0010, 0x07A, 0x07D, 0x0010, 4 }, - { 0x0020, 0x07A, 0x07D, 0x0020, 5 }, - { 0x0040, 0x07A, 0x07D, 0x0040, 6 }, - { 0x0080, 0x07A, 0x07D, 0x0080, 7 }, - { 0x0400, 0x0F8, 0x0FA, 0x0070, 4 }, - { 0x0800, 0x07B, 0x07E, 0xFFFF, 0 }, - { 0x1000, 0x07C, 0x07F, 0xFFFF, 0 }, - { 0x6000, 0x348, 0x349, 0x00FF, 0 }, - { 0x2000, 0x348, 0x349, 0x000F, 0 }, -}; - -/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ -static const struct nphy_rf_control_override_rev7 - tbl_rf_control_override_rev7_over1[] = { - { 0x0002, 0x340, 0x341, 0x0002, 1 }, - { 0x0008, 0x340, 0x341, 0x0008, 3 }, - { 0x0020, 0x340, 0x341, 0x0020, 5 }, - { 0x0010, 0x340, 0x341, 0x0010, 4 }, - { 0x0004, 0x340, 0x341, 0x0004, 2 }, - { 0x0080, 0x340, 0x341, 0x0700, 8 }, - { 0x0800, 0x340, 0x341, 0x4000, 14 }, - { 0x0400, 0x340, 0x341, 0x2000, 13 }, - { 0x0200, 0x340, 0x341, 0x0800, 12 }, - { 0x0100, 0x340, 0x341, 0x0100, 11 }, - { 0x0040, 0x340, 0x341, 0x0040, 6 }, - { 0x0001, 0x340, 0x341, 0x0001, 0 }, -}; - -/* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ -static const struct nphy_rf_control_override_rev7 - tbl_rf_control_override_rev7_over2[] = { - { 0x0008, 0x344, 0x345, 0x0008, 3 }, - { 0x0002, 0x344, 0x345, 0x0002, 1 }, - { 0x0001, 0x344, 0x345, 0x0001, 0 }, - { 0x0004, 0x344, 0x345, 0x0004, 2 }, - { 0x0010, 0x344, 0x345, 0x0010, 4 }, -}; - -static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = { - { 10, 14, 19, 27 }, - { -5, 6, 10, 15 }, - { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, - { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, - 0x427E, - { 0x413F, 0x413F, 0x413F, 0x413F }, - 0x007E, 0x0066, 0x1074, - 0x18, 0x18, 0x18, - 0x01D0, 0x5, -}; -static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = { - { /* 2GHz */ - { /* PHY rev 3 */ - { 7, 11, 16, 23 }, - { -5, 6, 10, 14 }, - { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, - { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, - 0x627E, - { 0x613F, 0x613F, 0x613F, 0x613F }, - 0x107E, 0x0066, 0x0074, - 0x18, 0x18, 0x18, - 0x020D, 0x5, - }, - { /* PHY rev 4 */ - { 8, 12, 17, 25 }, - { -5, 6, 10, 14 }, - { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, - { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, - 0x527E, - { 0x513F, 0x513F, 0x513F, 0x513F }, - 0x007E, 0x0066, 0x0074, - 0x18, 0x18, 0x18, - 0x01A1, 0x5, - }, - { /* PHY rev 5 */ - { 9, 13, 18, 26 }, - { -3, 7, 11, 16 }, - { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, - { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, - 0x427E, /* invalid for external LNA! */ - { 0x413F, 0x413F, 0x413F, 0x413F }, /* invalid for external LNA! */ - 0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */ - 0x18, 0x18, 0x18, - 0x01D0, 0x9, - }, - { /* PHY rev 6+ */ - { 8, 13, 18, 25 }, - { -5, 6, 10, 14 }, - { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, - { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, - 0x527E, /* invalid for external LNA! */ - { 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */ - 0x007E, 0x0066, 0x0000, /* low is invalid (the last one) */ - 0x18, 0x18, 0x18, - 0x01D0, 0x5, - }, - }, - { /* 5GHz */ - { /* PHY rev 3 */ - { 7, 11, 17, 23 }, - { -6, 2, 6, 10 }, - { 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 }, - { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }, - 0x52DE, - { 0x516F, 0x516F, 0x516F, 0x516F }, - 0x00DE, 0x00CA, 0x00CC, - 0x1E, 0x1E, 0x1E, - 0x01A1, 25, - }, - { /* PHY rev 4 */ - { 8, 12, 18, 23 }, - { -5, 2, 6, 10 }, - { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, - { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, - 0x629E, - { 0x614F, 0x614F, 0x614F, 0x614F }, - 0x029E, 0x1084, 0x0086, - 0x24, 0x24, 0x24, - 0x0107, 25, - }, - { /* PHY rev 5 */ - { 6, 10, 16, 21 }, - { -7, 0, 4, 8 }, - { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, - { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, - 0x729E, - { 0x714F, 0x714F, 0x714F, 0x714F }, - 0x029E, 0x2084, 0x2086, - 0x24, 0x24, 0x24, - 0x00A9, 25, - }, - { /* PHY rev 6+ */ - { 6, 10, 16, 21 }, - { -7, 0, 4, 8 }, - { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, - { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, - 0x729E, - { 0x714F, 0x714F, 0x714F, 0x714F }, - 0x029E, 0x2084, 0x2086, - 0x24, 0x24, 0x24, /* low is invalid for radio rev 11! */ - 0x00F0, 25, - }, - }, -}; - -static inline void assert_ntab_array_sizes(void) -{ -#undef check -#define check(table, size) \ - BUILD_BUG_ON(ARRAY_SIZE(b43_ntab_##table) != B43_NTAB_##size##_SIZE) - - check(adjustpower0, C0_ADJPLT); - check(adjustpower1, C1_ADJPLT); - check(bdi, BDI); - check(channelest, CHANEST); - check(estimatepowerlt0, C0_ESTPLT); - check(estimatepowerlt1, C1_ESTPLT); - check(framelookup, FRAMELT); - check(framestruct, FRAMESTRUCT); - check(gainctl0, C0_GAINCTL); - check(gainctl1, C1_GAINCTL); - check(intlevel, INTLEVEL); - check(iqlt0, C0_IQLT); - check(iqlt1, C1_IQLT); - check(loftlt0, C0_LOFEEDTH); - check(loftlt1, C1_LOFEEDTH); - check(mcs, MCS); - check(noisevar10, NOISEVAR10); - check(noisevar11, NOISEVAR11); - check(pilot, PILOT); - check(pilotlt, PILOTLT); - check(tdi20a0, TDI20A0); - check(tdi20a1, TDI20A1); - check(tdi40a0, TDI40A0); - check(tdi40a1, TDI40A1); - check(tdtrn, TDTRN); - check(tmap, TMAP); - -#undef check -} - -u32 b43_ntab_read(struct b43_wldev *dev, u32 offset) -{ - u32 type, value; - - type = offset & B43_NTAB_TYPEMASK; - offset &= ~B43_NTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - switch (type) { - case B43_NTAB_8BIT: - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF; - break; - case B43_NTAB_16BIT: - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - break; - case B43_NTAB_32BIT: - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - value |= b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16; - break; - default: - B43_WARN_ON(1); - value = 0; - } - - return value; -} - -void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data) -{ - u32 type; - u8 *data = _data; - unsigned int i; - - type = offset & B43_NTAB_TYPEMASK; - offset &= ~B43_NTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - /* Auto increment broken + caching issue on BCM43224? */ - if (dev->dev->chip_id == 43224 && dev->dev->chip_rev == 1) { - b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i); - } - - switch (type) { - case B43_NTAB_8BIT: - *data = b43_phy_read(dev, B43_NPHY_TABLE_DATALO) & 0xFF; - data++; - break; - case B43_NTAB_16BIT: - *((u16 *)data) = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - data += 2; - break; - case B43_NTAB_32BIT: - *((u32 *)data) = - b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - *((u32 *)data) |= - b43_phy_read(dev, B43_NPHY_TABLE_DATAHI) << 16; - data += 4; - break; - default: - B43_WARN_ON(1); - } - } -} - -void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value) -{ - u32 type; - - type = offset & B43_NTAB_TYPEMASK; - offset &= 0xFFFF; - - switch (type) { - case B43_NTAB_8BIT: - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value); - break; - case B43_NTAB_16BIT: - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value); - break; - case B43_NTAB_32BIT: - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - - return; - - /* Some compiletime assertions... */ - assert_ntab_array_sizes(); -} - -void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data) -{ - u32 type, value; - const u8 *data = _data; - unsigned int i; - - type = offset & B43_NTAB_TYPEMASK; - offset &= ~B43_NTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - /* Auto increment broken + caching issue on BCM43224? */ - if ((offset >> 10) == 9 && dev->dev->chip_id == 43224 && - dev->dev->chip_rev == 1) { - b43_phy_read(dev, B43_NPHY_TABLE_DATALO); - b43_phy_write(dev, B43_NPHY_TABLE_ADDR, offset + i); - } - - switch (type) { - case B43_NTAB_8BIT: - value = *data; - data++; - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value); - break; - case B43_NTAB_16BIT: - value = *((u16 *)data); - data += 2; - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, value); - break; - case B43_NTAB_32BIT: - value = *((u32 *)data); - data += 4; - b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, value >> 16); - b43_phy_write(dev, B43_NPHY_TABLE_DATALO, - value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - } -} - -#define ntab_upload(dev, offset, data) do { \ - b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ - } while (0) - -static void b43_nphy_tables_init_shared_lut(struct b43_wldev *dev) -{ - ntab_upload(dev, B43_NTAB_C0_ESTPLT_R3, b43_ntab_estimatepowerlt0_r3); - ntab_upload(dev, B43_NTAB_C1_ESTPLT_R3, b43_ntab_estimatepowerlt1_r3); - ntab_upload(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3); - ntab_upload(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3); - ntab_upload(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3); - ntab_upload(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3); - ntab_upload(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3); - ntab_upload(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3); - ntab_upload(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3); - ntab_upload(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3); -} - -static void b43_nphy_tables_init_rev7_volatile(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - u8 antswlut; - int core, offset, i; - - const int antswlut0_offsets[] = { 0, 4, 8, }; /* Offsets for values */ - const u8 antswlut0_values[][3] = { - { 0x2, 0x12, 0x8 }, /* Core 0 */ - { 0x2, 0x18, 0x2 }, /* Core 1 */ - }; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - antswlut = sprom->fem.ghz5.antswlut; - else - antswlut = sprom->fem.ghz2.antswlut; - - switch (antswlut) { - case 0: - for (core = 0; core < 2; core++) { - for (i = 0; i < ARRAY_SIZE(antswlut0_values[0]); i++) { - offset = core ? 0x20 : 0x00; - offset += antswlut0_offsets[i]; - b43_ntab_write(dev, B43_NTAB8(9, offset), - antswlut0_values[core][i]); - } - } - break; - default: - b43err(dev->wl, "Unsupported antswlut: %d\n", antswlut); - break; - } -} - -static void b43_nphy_tables_init_rev16(struct b43_wldev *dev) -{ - /* Static tables */ - if (dev->phy.do_full_init) { - ntab_upload(dev, B43_NTAB_NOISEVAR_R7, b43_ntab_noisevar_r7); - b43_nphy_tables_init_shared_lut(dev); - } - - /* Volatile tables */ - b43_nphy_tables_init_rev7_volatile(dev); -} - -static void b43_nphy_tables_init_rev7(struct b43_wldev *dev) -{ - /* Static tables */ - if (dev->phy.do_full_init) { - ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3); - ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3); - ntab_upload(dev, B43_NTAB_TMAP_R7, b43_ntab_tmap_r7); - ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3); - ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3); - ntab_upload(dev, B43_NTAB_NOISEVAR_R7, b43_ntab_noisevar_r7); - ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3); - ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3); - ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3); - ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3); - ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3); - ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3); - ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3); - ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3); - b43_nphy_tables_init_shared_lut(dev); - } - - /* Volatile tables */ - b43_nphy_tables_init_rev7_volatile(dev); -} - -static void b43_nphy_tables_init_rev3(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - u8 antswlut; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) - antswlut = sprom->fem.ghz5.antswlut; - else - antswlut = sprom->fem.ghz2.antswlut; - - /* Static tables */ - if (dev->phy.do_full_init) { - ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3); - ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3); - ntab_upload(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3); - ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3); - ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3); - ntab_upload(dev, B43_NTAB_NOISEVAR_R3, b43_ntab_noisevar_r3); - ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3); - ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3); - ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3); - ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3); - ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3); - ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3); - ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3); - ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3); - b43_nphy_tables_init_shared_lut(dev); - } - - /* Volatile tables */ - if (antswlut < ARRAY_SIZE(b43_ntab_antswctl_r3)) - ntab_upload(dev, B43_NTAB_ANT_SW_CTL_R3, - b43_ntab_antswctl_r3[antswlut]); - else - B43_WARN_ON(1); -} - -static void b43_nphy_tables_init_rev0(struct b43_wldev *dev) -{ - /* Static tables */ - if (dev->phy.do_full_init) { - ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct); - ntab_upload(dev, B43_NTAB_FRAMELT, b43_ntab_framelookup); - ntab_upload(dev, B43_NTAB_TMAP, b43_ntab_tmap); - ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn); - ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel); - ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot); - ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0); - ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1); - ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0); - ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1); - ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest); - ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs); - ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10); - ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11); - } - - /* Volatile tables */ - ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi); - ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt); - ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0); - ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1); - ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0); - ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1); - ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0); - ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1); - ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0); - ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1); - ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0); - ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */ -void b43_nphy_tables_init(struct b43_wldev *dev) -{ - if (dev->phy.rev >= 16) - b43_nphy_tables_init_rev16(dev); - else if (dev->phy.rev >= 7) - b43_nphy_tables_init_rev7(dev); - else if (dev->phy.rev >= 3) - b43_nphy_tables_init_rev3(dev); - else - b43_nphy_tables_init_rev0(dev); -} - -/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ -static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - switch (phy->rev) { - case 17: - if (phy->radio_rev == 14) - return b43_ntab_tx_gain_ipa_2057_rev14_2g; - break; - case 16: - if (phy->radio_rev == 9) - return b43_ntab_tx_gain_ipa_2057_rev9_2g; - break; - case 8: - if (phy->radio_rev == 5) - return b43_ntab_tx_gain_ipa_2057_rev5_2g; - break; - case 6: - if (dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) - return b43_ntab_tx_gain_ipa_rev5_2g; - return b43_ntab_tx_gain_ipa_rev6_2g; - case 5: - return b43_ntab_tx_gain_ipa_rev5_2g; - case 4: - case 3: - return b43_ntab_tx_gain_ipa_rev3_2g; - } - - b43err(dev->wl, - "No 2GHz IPA gain table available for this device\n"); - return NULL; - } else { - switch (phy->rev) { - case 16: - if (phy->radio_rev == 9) - return b43_ntab_tx_gain_ipa_2057_rev9_5g; - break; - case 3 ... 6: - return b43_ntab_tx_gain_ipa_rev3_5g; - } - - b43err(dev->wl, - "No 5GHz IPA gain table available for this device\n"); - return NULL; - } -} - -const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - enum ieee80211_band band = b43_current_band(dev->wl); - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - if (dev->phy.rev < 3) - return b43_ntab_tx_gain_rev0_1_2; - - /* rev 3+ */ - if ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) || - (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)) { - return b43_nphy_get_ipa_gain_table(dev); - } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { - switch (phy->rev) { - case 6: - case 5: - return b43_ntab_tx_gain_epa_rev5_5g; - case 4: - return sprom->fem.ghz5.extpa_gain == 3 ? - b43_ntab_tx_gain_epa_rev4_5g : - b43_ntab_tx_gain_epa_rev4_hi_pwr_5g; - case 3: - return b43_ntab_tx_gain_epa_rev3_5g; - default: - b43err(dev->wl, - "No 5GHz EPA gain table available for this device\n"); - return NULL; - } - } else { - switch (phy->rev) { - case 6: - case 5: - if (sprom->fem.ghz2.extpa_gain == 3) - return b43_ntab_tx_gain_epa_rev3_hi_pwr_2g; - /* fall through */ - case 4: - case 3: - return b43_ntab_tx_gain_epa_rev3_2g; - default: - b43err(dev->wl, - "No 2GHz EPA gain table available for this device\n"); - return NULL; - } - } -} - -const s16 *b43_ntab_get_rf_pwr_offset_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - switch (phy->rev) { - case 17: - if (phy->radio_rev == 14) - return b43_ntab_rf_pwr_offset_2057_rev14_2g; - break; - case 16: - if (phy->radio_rev == 9) - return b43_ntab_rf_pwr_offset_2057_rev9_2g; - break; - } - - b43err(dev->wl, - "No 2GHz RF power table available for this device\n"); - return NULL; - } else { - switch (phy->rev) { - case 16: - if (phy->radio_rev == 9) - return b43_ntab_rf_pwr_offset_2057_rev9_5g; - break; - } - - b43err(dev->wl, - "No 5GHz RF power table available for this device\n"); - return NULL; - } -} - -struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent( - struct b43_wldev *dev, bool ghz5, bool ext_lna) -{ - struct b43_phy *phy = &dev->phy; - struct nphy_gain_ctl_workaround_entry *e; - u8 phy_idx; - - if (!ghz5 && dev->phy.rev >= 6 && dev->phy.radio_rev == 11) - return &nphy_gain_ctl_wa_phy6_radio11_ghz2; - - B43_WARN_ON(dev->phy.rev < 3); - if (dev->phy.rev >= 6) - phy_idx = 3; - else if (dev->phy.rev == 5) - phy_idx = 2; - else if (dev->phy.rev == 4) - phy_idx = 1; - else - phy_idx = 0; - e = &nphy_gain_ctl_workaround[ghz5][phy_idx]; - - /* Some workarounds to the workarounds... */ - if (!ghz5) { - u8 tr_iso = dev->dev->bus_sprom->fem.ghz2.tr_iso; - - if (tr_iso > 7) - tr_iso = 3; - - if (phy->rev >= 6) { - static const int gain_data[] = { 0x106a, 0x106c, 0x1074, - 0x107c, 0x007e, 0x107e, - 0x207e, 0x307e, }; - - e->cliplo_gain = gain_data[tr_iso]; - } else if (phy->rev == 5) { - static const int gain_data[] = { 0x0062, 0x0064, 0x006a, - 0x106a, 0x106c, 0x1074, - 0x107c, 0x207c, }; - - e->cliplo_gain = gain_data[tr_iso]; - } - - if (phy->rev >= 5 && ext_lna) { - e->rfseq_init[0] &= ~0x4000; - e->rfseq_init[1] &= ~0x4000; - e->rfseq_init[2] &= ~0x4000; - e->rfseq_init[3] &= ~0x4000; - e->init_gain &= ~0x4000; - } - } else { - if (phy->rev >= 6) { - if (phy->radio_rev == 11 && !b43_is_40mhz(dev)) - e->crsminu = 0x2d; - } else if (phy->rev == 4 && ext_lna) { - e->rfseq_init[0] &= ~0x4000; - e->rfseq_init[1] &= ~0x4000; - e->rfseq_init[2] &= ~0x4000; - e->rfseq_init[3] &= ~0x4000; - e->init_gain &= ~0x4000; - e->rfseq_init[0] |= 0x1000; - e->rfseq_init[1] |= 0x1000; - e->rfseq_init[2] |= 0x1000; - e->rfseq_init[3] |= 0x1000; - e->init_gain |= 0x1000; - } - } - - return e; -} - -const struct nphy_rf_control_override_rev7 *b43_nphy_get_rf_ctl_over_rev7( - struct b43_wldev *dev, u16 field, u8 override) -{ - const struct nphy_rf_control_override_rev7 *e; - u8 size, i; - - switch (override) { - case 0: - e = tbl_rf_control_override_rev7_over0; - size = ARRAY_SIZE(tbl_rf_control_override_rev7_over0); - break; - case 1: - e = tbl_rf_control_override_rev7_over1; - size = ARRAY_SIZE(tbl_rf_control_override_rev7_over1); - break; - case 2: - e = tbl_rf_control_override_rev7_over2; - size = ARRAY_SIZE(tbl_rf_control_override_rev7_over2); - break; - default: - b43err(dev->wl, "Invalid override value %d\n", override); - return NULL; - } - - for (i = 0; i < size; i++) { - if (e[i].field == field) - return &e[i]; - } - - return NULL; -} diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h deleted file mode 100644 index b51f386db..000000000 --- a/drivers/net/wireless/b43/tables_nphy.h +++ /dev/null @@ -1,222 +0,0 @@ -#ifndef B43_TABLES_NPHY_H_ -#define B43_TABLES_NPHY_H_ - -#include <linux/types.h> - -struct b43_phy_n_sfo_cfg { - u16 phy_bw1a; - u16 phy_bw2; - u16 phy_bw3; - u16 phy_bw4; - u16 phy_bw5; - u16 phy_bw6; -}; - -struct b43_wldev; - -struct nphy_txiqcal_ladder { - u8 percent; - u8 g_env; -}; - -struct nphy_rf_control_override_rev2 { - u8 addr0; - u8 addr1; - u16 bmask; - u8 shift; -}; - -struct nphy_rf_control_override_rev3 { - u16 val_mask; - u8 val_shift; - u8 en_addr0; - u8 val_addr0; - u8 en_addr1; - u8 val_addr1; -}; - -struct nphy_rf_control_override_rev7 { - u16 field; - u16 val_addr_core0; - u16 val_addr_core1; - u16 val_mask; - u8 val_shift; -}; - -struct nphy_gain_ctl_workaround_entry { - s8 lna1_gain[4]; - s8 lna2_gain[4]; - u8 gain_db[10]; - u8 gain_bits[10]; - - u16 init_gain; - u16 rfseq_init[4]; - - u16 cliphi_gain; - u16 clipmd_gain; - u16 cliplo_gain; - - u16 crsmin; - u16 crsminl; - u16 crsminu; - - u16 nbclip; - u16 wlclip; -}; - -/* Get entry with workaround values for gain ctl. Does not return NULL. */ -struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent( - struct b43_wldev *dev, bool ghz5, bool ext_lna); - - -/* The N-PHY tables. */ -#define B43_NTAB_TYPEMASK 0xF0000000 -#define B43_NTAB_8BIT 0x10000000 -#define B43_NTAB_16BIT 0x20000000 -#define B43_NTAB_32BIT 0x30000000 -#define B43_NTAB8(table, offset) (((table) << 10) | (offset) | B43_NTAB_8BIT) -#define B43_NTAB16(table, offset) (((table) << 10) | (offset) | B43_NTAB_16BIT) -#define B43_NTAB32(table, offset) (((table) << 10) | (offset) | B43_NTAB_32BIT) - -/* Static N-PHY tables */ -#define B43_NTAB_FRAMESTRUCT B43_NTAB32(0x0A, 0x000) /* Frame Struct Table */ -#define B43_NTAB_FRAMESTRUCT_SIZE 832 -#define B43_NTAB_FRAMELT B43_NTAB8 (0x18, 0x000) /* Frame Lookup Table */ -#define B43_NTAB_FRAMELT_SIZE 32 -#define B43_NTAB_TMAP B43_NTAB32(0x0C, 0x000) /* T Map Table */ -#define B43_NTAB_TMAP_SIZE 448 -#define B43_NTAB_TDTRN B43_NTAB32(0x0E, 0x000) /* TDTRN Table */ -#define B43_NTAB_TDTRN_SIZE 704 -#define B43_NTAB_INTLEVEL B43_NTAB32(0x0D, 0x000) /* Int Level Table */ -#define B43_NTAB_INTLEVEL_SIZE 7 -#define B43_NTAB_PILOT B43_NTAB16(0x0B, 0x000) /* Pilot Table */ -#define B43_NTAB_PILOT_SIZE 88 -#define B43_NTAB_PILOTLT B43_NTAB32(0x14, 0x000) /* Pilot Lookup Table */ -#define B43_NTAB_PILOTLT_SIZE 6 -#define B43_NTAB_TDI20A0 B43_NTAB32(0x13, 0x080) /* TDI Table 20 Antenna 0 */ -#define B43_NTAB_TDI20A0_SIZE 55 -#define B43_NTAB_TDI20A1 B43_NTAB32(0x13, 0x100) /* TDI Table 20 Antenna 1 */ -#define B43_NTAB_TDI20A1_SIZE 55 -#define B43_NTAB_TDI40A0 B43_NTAB32(0x13, 0x280) /* TDI Table 40 Antenna 0 */ -#define B43_NTAB_TDI40A0_SIZE 110 -#define B43_NTAB_TDI40A1 B43_NTAB32(0x13, 0x300) /* TDI Table 40 Antenna 1 */ -#define B43_NTAB_TDI40A1_SIZE 110 -#define B43_NTAB_BDI B43_NTAB16(0x15, 0x000) /* BDI Table */ -#define B43_NTAB_BDI_SIZE 6 -#define B43_NTAB_CHANEST B43_NTAB32(0x16, 0x000) /* Channel Estimate Table */ -#define B43_NTAB_CHANEST_SIZE 96 -#define B43_NTAB_MCS B43_NTAB8 (0x12, 0x000) /* MCS Table */ -#define B43_NTAB_MCS_SIZE 128 - -/* Volatile N-PHY tables */ -#define B43_NTAB_NOISEVAR10 B43_NTAB32(0x10, 0x000) /* Noise Var Table 10 */ -#define B43_NTAB_NOISEVAR10_SIZE 256 -#define B43_NTAB_NOISEVAR11 B43_NTAB32(0x10, 0x080) /* Noise Var Table 11 */ -#define B43_NTAB_NOISEVAR11_SIZE 256 -#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */ -#define B43_NTAB_C0_ESTPLT_SIZE 64 -#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */ -#define B43_NTAB_C0_ADJPLT_SIZE 128 -#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */ -#define B43_NTAB_C0_GAINCTL_SIZE 128 -#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */ -#define B43_NTAB_C0_IQLT_SIZE 128 -#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */ -#define B43_NTAB_C0_LOFEEDTH_SIZE 128 -#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */ -#define B43_NTAB_C1_ESTPLT_SIZE 64 -#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */ -#define B43_NTAB_C1_ADJPLT_SIZE 128 -#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */ -#define B43_NTAB_C1_GAINCTL_SIZE 128 -#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */ -#define B43_NTAB_C1_IQLT_SIZE 128 -#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */ -#define B43_NTAB_C1_LOFEEDTH_SIZE 128 - -/* Volatile N-PHY tables, PHY revision >= 3 */ -#define B43_NTAB_ANT_SW_CTL_R3 B43_NTAB16( 9, 0) /* antenna software control */ - -/* Static N-PHY tables, PHY revision >= 3 */ -#define B43_NTAB_FRAMESTRUCT_R3 B43_NTAB32(10, 0) /* frame struct */ -#define B43_NTAB_PILOT_R3 B43_NTAB16(11, 0) /* pilot */ -#define B43_NTAB_TMAP_R3 B43_NTAB32(12, 0) /* TM AP */ -#define B43_NTAB_INTLEVEL_R3 B43_NTAB32(13, 0) /* INT LV */ -#define B43_NTAB_TDTRN_R3 B43_NTAB32(14, 0) /* TD TRN */ -#define B43_NTAB_NOISEVAR_R3 B43_NTAB32(16, 0) /* noise variance */ -#define B43_NTAB_MCS_R3 B43_NTAB16(18, 0) /* MCS */ -#define B43_NTAB_TDI20A0_R3 B43_NTAB32(19, 128) /* TDI 20/0 */ -#define B43_NTAB_TDI20A1_R3 B43_NTAB32(19, 256) /* TDI 20/1 */ -#define B43_NTAB_TDI40A0_R3 B43_NTAB32(19, 640) /* TDI 40/0 */ -#define B43_NTAB_TDI40A1_R3 B43_NTAB32(19, 768) /* TDI 40/1 */ -#define B43_NTAB_PILOTLT_R3 B43_NTAB32(20, 0) /* PLT lookup */ -#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */ -#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */ -#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */ -#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */ -#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */ -#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */ -#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */ -#define B43_NTAB_C0_PAPD_COMP_R3 B43_NTAB16(26, 576) -#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */ -#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */ -#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */ -#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */ -#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */ -#define B43_NTAB_C1_PAPD_COMP_R3 B43_NTAB16(27, 576) - -/* Static N-PHY tables, PHY revision >= 7 */ -#define B43_NTAB_TMAP_R7 B43_NTAB32(12, 0) /* TM AP */ -#define B43_NTAB_NOISEVAR_R7 B43_NTAB32(16, 0) /* noise variance */ - -#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18 -#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18 -#define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_40_SIZE 18 -#define B43_NTAB_TX_IQLO_CAL_IQIMB_LADDER_20_SIZE 18 -#define B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3 11 -#define B43_NTAB_TX_IQLO_CAL_STARTCOEFS 9 -#define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3 12 -#define B43_NTAB_TX_IQLO_CAL_CMDS_RECAL 10 -#define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL 10 -#define B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3 12 - -u32 b43_ntab_read(struct b43_wldev *dev, u32 offset); -void b43_ntab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data); -void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value); -void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data); - -void b43_nphy_tables_init(struct b43_wldev *dev); - -const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev); - -const s16 *b43_ntab_get_rf_pwr_offset_table(struct b43_wldev *dev); - -extern const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[]; - -extern const u16 tbl_iqcal_gainparams[2][9][8]; -extern const struct nphy_txiqcal_ladder ladder_lo[]; -extern const struct nphy_txiqcal_ladder ladder_iq[]; -extern const u16 loscale[]; - -extern const u16 tbl_tx_iqlo_cal_loft_ladder_40[]; -extern const u16 tbl_tx_iqlo_cal_loft_ladder_20[]; -extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_40[]; -extern const u16 tbl_tx_iqlo_cal_iqimb_ladder_20[]; -extern const u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[]; -extern const u16 tbl_tx_iqlo_cal_startcoefs[]; -extern const u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[]; -extern const u16 tbl_tx_iqlo_cal_cmds_recal[]; -extern const u16 tbl_tx_iqlo_cal_cmds_fullcal[]; -extern const u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[]; -extern const s16 tbl_tx_filter_coef_rev4[7][15]; - -extern const struct nphy_rf_control_override_rev2 - tbl_rf_control_override_rev2[]; -extern const struct nphy_rf_control_override_rev3 - tbl_rf_control_override_rev3[]; -const struct nphy_rf_control_override_rev7 *b43_nphy_get_rf_ctl_over_rev7( - struct b43_wldev *dev, u16 field, u8 override); - -#endif /* B43_TABLES_NPHY_H_ */ diff --git a/drivers/net/wireless/b43/tables_phy_ht.c b/drivers/net/wireless/b43/tables_phy_ht.c deleted file mode 100644 index 176c49d74..000000000 --- a/drivers/net/wireless/b43/tables_phy_ht.c +++ /dev/null @@ -1,836 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n HT-PHY data tables - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "tables_phy_ht.h" -#include "phy_common.h" -#include "phy_ht.h" - -static const u16 b43_httab_0x12[] = { - 0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019, - 0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090, - 0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108, - 0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c, - 0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199, - 0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8, - 0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128, - 0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a, - 0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8, - 0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8, - 0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa, - 0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca, - 0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001, - 0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014, - 0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081, - 0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094, - 0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, - 0x0007, 0x0007, -}; - -static const u16 b43_httab_0x27[] = { - 0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a, - 0x001d, 0x0020, 0x0009, 0x000e, 0x0011, 0x0014, - 0x0017, 0x001a, 0x001d, 0x0020, 0x0009, 0x000e, - 0x0011, 0x0014, 0x0017, 0x001a, 0x001d, 0x0020, - 0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a, - 0x001d, 0x0020, -}; - -static const u16 b43_httab_0x26[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -static const u32 b43_httab_0x25[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_httab_0x2f[] = { - 0x00035700, 0x0002cc9a, 0x00026666, 0x0001581f, - 0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f, - 0x0001581f, 0x0001581f, 0x0001581f, 0x00035700, - 0x0002cc9a, 0x00026666, 0x0001581f, 0x0001581f, - 0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f, - 0x0001581f, 0x0001581f, -}; - -static const u16 b43_httab_0x1a[] = { - 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052, - 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e, - 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a, - 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046, - 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040, - 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a, - 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033, - 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b, - 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f, - 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e, - 0x000b, 0x0007, 0x0002, 0x00fd, -}; - -static const u16 b43_httab_0x1b[] = { - 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052, - 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e, - 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a, - 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046, - 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040, - 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a, - 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033, - 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b, - 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f, - 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e, - 0x000b, 0x0007, 0x0002, 0x00fd, -}; - -static const u16 b43_httab_0x1c[] = { - 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052, - 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e, - 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a, - 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046, - 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040, - 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a, - 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033, - 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b, - 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f, - 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e, - 0x000b, 0x0007, 0x0002, 0x00fd, -}; - -static const u32 b43_httab_0x1a_0xc0[] = { - 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, - 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, - 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, - 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, - 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, - 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, - 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, - 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, - 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, - 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, - 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, - 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, - 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, - 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, - 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, - 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, - 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, - 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, - 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, - 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, - 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, - 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, - 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, - 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, - 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, - 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, - 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, - 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, - 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, - 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, - 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, - 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, -}; - -static const u32 b43_httab_0x1a_0x140[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_httab_0x1b_0x140[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u32 b43_httab_0x1c_0x140[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u16 b43_httab_0x1a_0x1c0[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -static const u16 b43_httab_0x1b_0x1c0[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -static const u16 b43_httab_0x1c_0x1c0[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, -}; - -static const u16 b43_httab_0x1a_0x240[] = { - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, -}; - -static const u16 b43_httab_0x1b_0x240[] = { - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, -}; - -static const u16 b43_httab_0x1c_0x240[] = { - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, - 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, - 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, - 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, - 0x01d6, 0x01d6, -}; - -static const u32 b43_httab_0x1f[] = { - 0x00000000, 0x00000000, 0x00016023, 0x00006028, - 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037, - 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d, - 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9, - 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9, - 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6, - 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c, - 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b, - 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15, - 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9, - 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87, - 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3, - 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa, - 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff, - 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff, - 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff, -}; - -static const u32 b43_httab_0x21[] = { - 0x00000000, 0x00000000, 0x00016023, 0x00006028, - 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037, - 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d, - 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9, - 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9, - 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6, - 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c, - 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b, - 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15, - 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9, - 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87, - 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3, - 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa, - 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff, - 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff, - 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff, -}; - -static const u32 b43_httab_0x23[] = { - 0x00000000, 0x00000000, 0x00016023, 0x00006028, - 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037, - 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d, - 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9, - 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9, - 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6, - 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c, - 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b, - 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15, - 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9, - 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87, - 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3, - 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa, - 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff, - 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff, - 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff, -}; - -static const u32 b43_httab_0x20[] = { - 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035, - 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043, - 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054, - 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a, - 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085, - 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8, - 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3, - 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a, - 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e, - 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5, - 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212, - 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b, - 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348, - 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422, - 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533, - 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c, -}; - -static const u32 b43_httab_0x22[] = { - 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035, - 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043, - 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054, - 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a, - 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085, - 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8, - 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3, - 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a, - 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e, - 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5, - 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212, - 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b, - 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348, - 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422, - 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533, - 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c, -}; - -static const u32 b43_httab_0x24[] = { - 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035, - 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043, - 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054, - 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a, - 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085, - 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8, - 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3, - 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a, - 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e, - 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5, - 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212, - 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b, - 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348, - 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422, - 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533, - 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c, -}; - -/* Some late-init table */ -const u32 b43_httab_0x1a_0xc0_late[] = { - 0x10f90040, 0x10e10040, 0x10e1003c, 0x10c9003d, - 0x10b9003c, 0x10a9003d, 0x10a1003c, 0x1099003b, - 0x1091003b, 0x1089003a, 0x1081003a, 0x10790039, - 0x10710039, 0x1069003a, 0x1061003b, 0x1059003d, - 0x1051003f, 0x10490042, 0x1049003e, 0x1049003b, - 0x1041003e, 0x1041003b, 0x1039003e, 0x1039003b, - 0x10390038, 0x10390035, 0x1031003a, 0x10310036, - 0x10310033, 0x1029003a, 0x10290037, 0x10290034, - 0x10290031, 0x10210039, 0x10210036, 0x10210033, - 0x10210030, 0x1019003c, 0x10190039, 0x10190036, - 0x10190033, 0x10190030, 0x1019002d, 0x1019002b, - 0x10190028, 0x1011003a, 0x10110036, 0x10110033, - 0x10110030, 0x1011002e, 0x1011002b, 0x10110029, - 0x10110027, 0x10110024, 0x10110022, 0x10110020, - 0x1011001f, 0x1011001d, 0x1009003a, 0x10090037, - 0x10090034, 0x10090031, 0x1009002e, 0x1009002c, - 0x10090029, 0x10090027, 0x10090025, 0x10090023, - 0x10090021, 0x1009001f, 0x1009001d, 0x1009001b, - 0x1009001a, 0x10090018, 0x10090017, 0x10090016, - 0x10090015, 0x10090013, 0x10090012, 0x10090011, - 0x10090010, 0x1009000f, 0x1009000f, 0x1009000e, - 0x1009000d, 0x1009000c, 0x1009000c, 0x1009000b, - 0x1009000a, 0x1009000a, 0x10090009, 0x10090009, - 0x10090008, 0x10090008, 0x10090007, 0x10090007, - 0x10090007, 0x10090006, 0x10090006, 0x10090005, - 0x10090005, 0x10090005, 0x10090005, 0x10090004, - 0x10090004, 0x10090004, 0x10090004, 0x10090003, - 0x10090003, 0x10090003, 0x10090003, 0x10090003, - 0x10090003, 0x10090002, 0x10090002, 0x10090002, - 0x10090002, 0x10090002, 0x10090002, 0x10090002, - 0x10090002, 0x10090002, 0x10090001, 0x10090001, - 0x10090001, 0x10090001, 0x10090001, 0x10090001, -}; - -/************************************************** - * R/W ops. - **************************************************/ - -u32 b43_httab_read(struct b43_wldev *dev, u32 offset) -{ - u32 type, value; - - type = offset & B43_HTTAB_TYPEMASK; - offset &= ~B43_HTTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - switch (type) { - case B43_HTTAB_8BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF; - break; - case B43_HTTAB_16BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); - break; - case B43_HTTAB_32BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI); - value <<= 16; - value |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); - break; - default: - B43_WARN_ON(1); - value = 0; - } - - return value; -} - -void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data) -{ - u32 type; - u8 *data = _data; - unsigned int i; - - type = offset & B43_HTTAB_TYPEMASK; - offset &= ~B43_HTTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_HTTAB_8BIT: - *data = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF; - data++; - break; - case B43_HTTAB_16BIT: - *((u16 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); - data += 2; - break; - case B43_HTTAB_32BIT: - *((u32 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI); - *((u32 *)data) <<= 16; - *((u32 *)data) |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO); - data += 4; - break; - default: - B43_WARN_ON(1); - } - } -} - -void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value) -{ - u32 type; - - type = offset & B43_HTTAB_TYPEMASK; - offset &= 0xFFFF; - - switch (type) { - case B43_HTTAB_8BIT: - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - break; - case B43_HTTAB_16BIT: - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - break; - case B43_HTTAB_32BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - - return; -} - -void b43_httab_write_few(struct b43_wldev *dev, u32 offset, size_t num, ...) -{ - va_list args; - u32 type, value; - unsigned int i; - - type = offset & B43_HTTAB_TYPEMASK; - offset &= 0xFFFF; - - va_start(args, num); - switch (type) { - case B43_HTTAB_8BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - for (i = 0; i < num; i++) { - value = va_arg(args, int); - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - } - break; - case B43_HTTAB_16BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - for (i = 0; i < num; i++) { - value = va_arg(args, int); - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - } - break; - case B43_HTTAB_32BIT: - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - for (i = 0; i < num; i++) { - value = va_arg(args, int); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, - value >> 16); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, - value & 0xFFFF); - } - break; - default: - B43_WARN_ON(1); - } - va_end(args); - - return; -} - -void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data) -{ - u32 type, value; - const u8 *data = _data; - unsigned int i; - - type = offset & B43_HTTAB_TYPEMASK; - offset &= ~B43_HTTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_HTTAB_8BIT: - value = *data; - data++; - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - break; - case B43_HTTAB_16BIT: - value = *((u16 *)data); - data += 2; - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value); - break; - case B43_HTTAB_32BIT: - value = *((u32 *)data); - data += 4; - b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16); - b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, - value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - } -} - -/************************************************** - * Tables ops. - **************************************************/ - -#define httab_upload(dev, offset, data) do { \ - b43_httab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ - } while (0) -void b43_phy_ht_tables_init(struct b43_wldev *dev) -{ - BUILD_BUG_ON(ARRAY_SIZE(b43_httab_0x1a_0xc0_late) != - B43_HTTAB_1A_C0_LATE_SIZE); - - httab_upload(dev, B43_HTTAB16(0x12, 0), b43_httab_0x12); - httab_upload(dev, B43_HTTAB16(0x27, 0), b43_httab_0x27); - httab_upload(dev, B43_HTTAB16(0x26, 0), b43_httab_0x26); - httab_upload(dev, B43_HTTAB32(0x25, 0), b43_httab_0x25); - httab_upload(dev, B43_HTTAB32(0x2f, 0), b43_httab_0x2f); - httab_upload(dev, B43_HTTAB16(0x1a, 0), b43_httab_0x1a); - httab_upload(dev, B43_HTTAB16(0x1b, 0), b43_httab_0x1b); - httab_upload(dev, B43_HTTAB16(0x1c, 0), b43_httab_0x1c); - httab_upload(dev, B43_HTTAB32(0x1a, 0x0c0), b43_httab_0x1a_0xc0); - httab_upload(dev, B43_HTTAB32(0x1a, 0x140), b43_httab_0x1a_0x140); - httab_upload(dev, B43_HTTAB32(0x1b, 0x140), b43_httab_0x1b_0x140); - httab_upload(dev, B43_HTTAB32(0x1c, 0x140), b43_httab_0x1c_0x140); - httab_upload(dev, B43_HTTAB16(0x1a, 0x1c0), b43_httab_0x1a_0x1c0); - httab_upload(dev, B43_HTTAB16(0x1b, 0x1c0), b43_httab_0x1b_0x1c0); - httab_upload(dev, B43_HTTAB16(0x1c, 0x1c0), b43_httab_0x1c_0x1c0); - httab_upload(dev, B43_HTTAB16(0x1a, 0x240), b43_httab_0x1a_0x240); - httab_upload(dev, B43_HTTAB16(0x1b, 0x240), b43_httab_0x1b_0x240); - httab_upload(dev, B43_HTTAB16(0x1c, 0x240), b43_httab_0x1c_0x240); - httab_upload(dev, B43_HTTAB32(0x1f, 0), b43_httab_0x1f); - httab_upload(dev, B43_HTTAB32(0x21, 0), b43_httab_0x21); - httab_upload(dev, B43_HTTAB32(0x23, 0), b43_httab_0x23); - httab_upload(dev, B43_HTTAB32(0x20, 0), b43_httab_0x20); - httab_upload(dev, B43_HTTAB32(0x22, 0), b43_httab_0x22); - httab_upload(dev, B43_HTTAB32(0x24, 0), b43_httab_0x24); -} diff --git a/drivers/net/wireless/b43/tables_phy_ht.h b/drivers/net/wireless/b43/tables_phy_ht.h deleted file mode 100644 index 1b5ef2bc7..000000000 --- a/drivers/net/wireless/b43/tables_phy_ht.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef B43_TABLES_PHY_HT_H_ -#define B43_TABLES_PHY_HT_H_ - -/* The HT-PHY tables. */ -#define B43_HTTAB_TYPEMASK 0xF0000000 -#define B43_HTTAB_8BIT 0x10000000 -#define B43_HTTAB_16BIT 0x20000000 -#define B43_HTTAB_32BIT 0x30000000 -#define B43_HTTAB8(table, offset) (((table) << 10) | (offset) | B43_HTTAB_8BIT) -#define B43_HTTAB16(table, offset) (((table) << 10) | (offset) | B43_HTTAB_16BIT) -#define B43_HTTAB32(table, offset) (((table) << 10) | (offset) | B43_HTTAB_32BIT) - -u32 b43_httab_read(struct b43_wldev *dev, u32 offset); -void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data); -void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value); -void b43_httab_write_few(struct b43_wldev *dev, u32 offset, size_t num, ...); -void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data); - -void b43_phy_ht_tables_init(struct b43_wldev *dev); - -#define B43_HTTAB_1A_C0_LATE_SIZE 128 -extern const u32 b43_httab_0x1a_0xc0_late[]; - -#endif /* B43_TABLES_PHY_HT_H_ */ diff --git a/drivers/net/wireless/b43/tables_phy_lcn.c b/drivers/net/wireless/b43/tables_phy_lcn.c deleted file mode 100644 index e347b8d80..000000000 --- a/drivers/net/wireless/b43/tables_phy_lcn.c +++ /dev/null @@ -1,724 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11n LCN-PHY data tables - - Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "tables_phy_lcn.h" -#include "phy_common.h" -#include "phy_lcn.h" - -struct b43_lcntab_tx_gain_tbl_entry { - u8 gm; - u8 pga; - u8 pad; - u8 dac; - u8 bb_mult; -}; - -/************************************************** - * Static tables. - **************************************************/ - -static const u16 b43_lcntab_0x02[] = { - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, 0x014d, - 0x014d, 0x014d, 0x014d, 0x014d, -}; - -static const u16 b43_lcntab_0x01[] = { - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u32 b43_lcntab_0x0b[] = { - 0x000141f8, 0x000021f8, 0x000021fb, 0x000041fb, - 0x0001fedb, 0x0000217b, 0x00002133, 0x000040eb, - 0x0001fea3, 0x0000024b, -}; - -static const u32 b43_lcntab_0x0c[] = { - 0x00100001, 0x00200010, 0x00300001, 0x00400010, - 0x00500022, 0x00600122, 0x00700222, 0x00800322, - 0x00900422, 0x00a00522, 0x00b00622, 0x00c00722, - 0x00d00822, 0x00f00922, 0x00100a22, 0x00200b22, - 0x00300c22, 0x00400d22, 0x00500e22, 0x00600f22, -}; - -static const u32 b43_lcntab_0x0d[] = { - 0x00000000, 0x00000000, 0x10000000, 0x00000000, - 0x20000000, 0x00000000, 0x30000000, 0x00000000, - 0x40000000, 0x00000000, 0x50000000, 0x00000000, - 0x60000000, 0x00000000, 0x70000000, 0x00000000, - 0x80000000, 0x00000000, 0x90000000, 0x00000008, - 0xa0000000, 0x00000008, 0xb0000000, 0x00000008, - 0xc0000000, 0x00000008, 0xd0000000, 0x00000008, - 0xe0000000, 0x00000008, 0xf0000000, 0x00000008, - 0x00000000, 0x00000009, 0x10000000, 0x00000009, - 0x20000000, 0x00000019, 0x30000000, 0x00000019, - 0x40000000, 0x00000019, 0x50000000, 0x00000019, - 0x60000000, 0x00000019, 0x70000000, 0x00000019, - 0x80000000, 0x00000019, 0x90000000, 0x00000019, - 0xa0000000, 0x00000019, 0xb0000000, 0x00000019, - 0xc0000000, 0x00000019, 0xd0000000, 0x00000019, - 0xe0000000, 0x00000019, 0xf0000000, 0x00000019, - 0x00000000, 0x0000001a, 0x10000000, 0x0000001a, - 0x20000000, 0x0000001a, 0x30000000, 0x0000001a, - 0x40000000, 0x0000001a, 0x50000000, 0x00000002, - 0x60000000, 0x00000002, 0x70000000, 0x00000002, - 0x80000000, 0x00000002, 0x90000000, 0x00000002, - 0xa0000000, 0x00000002, 0xb0000000, 0x00000002, - 0xc0000000, 0x0000000a, 0xd0000000, 0x0000000a, - 0xe0000000, 0x0000000a, 0xf0000000, 0x0000000a, - 0x00000000, 0x0000000b, 0x10000000, 0x0000000b, - 0x20000000, 0x0000000b, 0x30000000, 0x0000000b, - 0x40000000, 0x0000000b, 0x50000000, 0x0000001b, - 0x60000000, 0x0000001b, 0x70000000, 0x0000001b, - 0x80000000, 0x0000001b, 0x90000000, 0x0000001b, - 0xa0000000, 0x0000001b, 0xb0000000, 0x0000001b, - 0xc0000000, 0x0000001b, 0xd0000000, 0x0000001b, - 0xe0000000, 0x0000001b, 0xf0000000, 0x0000001b, - 0x00000000, 0x0000001c, 0x10000000, 0x0000001c, - 0x20000000, 0x0000001c, 0x30000000, 0x0000001c, - 0x40000000, 0x0000001c, 0x50000000, 0x0000001c, - 0x60000000, 0x0000001c, 0x70000000, 0x0000001c, - 0x80000000, 0x0000001c, 0x90000000, 0x0000001c, -}; - -static const u16 b43_lcntab_0x0e[] = { - 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0406, - 0x0407, 0x0408, 0x0409, 0x040a, 0x058b, 0x058c, - 0x058d, 0x058e, 0x058f, 0x0090, 0x0091, 0x0092, - 0x0193, 0x0194, 0x0195, 0x0196, 0x0197, 0x0198, - 0x0199, 0x019a, 0x019b, 0x019c, 0x019d, 0x019e, - 0x019f, 0x01a0, 0x01a1, 0x01a2, 0x01a3, 0x01a4, - 0x01a5, 0x0000, -}; - -static const u16 b43_lcntab_0x0f[] = { - 0x000a, 0x0009, 0x0006, 0x0005, 0x000a, 0x0009, - 0x0006, 0x0005, 0x000a, 0x0009, 0x0006, 0x0005, - 0x000a, 0x0009, 0x0006, 0x0005, 0x000a, 0x0009, - 0x0006, 0x0005, 0x000a, 0x0009, 0x0006, 0x0005, - 0x000a, 0x0009, 0x0006, 0x0005, 0x000a, 0x0009, - 0x0006, 0x0005, 0x000a, 0x0009, 0x0006, 0x0005, - 0x000a, 0x0009, 0x0006, 0x0005, 0x000a, 0x0009, - 0x0006, 0x0005, 0x000a, 0x0009, 0x0006, 0x0005, - 0x000a, 0x0009, 0x0006, 0x0005, 0x000a, 0x0009, - 0x0006, 0x0005, 0x000a, 0x0009, 0x0006, 0x0005, - 0x000a, 0x0009, 0x0006, 0x0005, -}; - -static const u16 b43_lcntab_0x10[] = { - 0x005f, 0x0036, 0x0029, 0x001f, 0x005f, 0x0036, - 0x0029, 0x001f, 0x005f, 0x0036, 0x0029, 0x001f, - 0x005f, 0x0036, 0x0029, 0x001f, -}; - -static const u16 b43_lcntab_0x11[] = { - 0x0009, 0x000f, 0x0014, 0x0018, 0x00fe, 0x0007, - 0x000b, 0x000f, 0x00fb, 0x00fe, 0x0001, 0x0005, - 0x0008, 0x000b, 0x000e, 0x0011, 0x0014, 0x0017, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0003, 0x0006, 0x0009, 0x000c, 0x000f, - 0x0012, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0003, - 0x0006, 0x0009, 0x000c, 0x000f, 0x0012, 0x0015, - 0x0018, 0x001b, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0003, 0x00eb, 0x0000, 0x0000, -}; - -static const u32 b43_lcntab_0x12[] = { - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000004, 0x00000000, 0x00000004, 0x00000008, - 0x00000001, 0x00000005, 0x00000009, 0x0000000d, - 0x0000004d, 0x0000008d, 0x0000000d, 0x0000004d, - 0x0000008d, 0x000000cd, 0x0000004f, 0x0000008f, - 0x000000cf, 0x000000d3, 0x00000113, 0x00000513, - 0x00000913, 0x00000953, 0x00000d53, 0x00001153, - 0x00001193, 0x00005193, 0x00009193, 0x0000d193, - 0x00011193, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000004, - 0x00000000, 0x00000004, 0x00000008, 0x00000001, - 0x00000005, 0x00000009, 0x0000000d, 0x0000004d, - 0x0000008d, 0x0000000d, 0x0000004d, 0x0000008d, - 0x000000cd, 0x0000004f, 0x0000008f, 0x000000cf, - 0x000000d3, 0x00000113, 0x00000513, 0x00000913, - 0x00000953, 0x00000d53, 0x00001153, 0x00005153, - 0x00009153, 0x0000d153, 0x00011153, 0x00015153, - 0x00019153, 0x0001d153, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, -}; - -static const u16 b43_lcntab_0x14[] = { - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0002, 0x0003, 0x0001, 0x0003, 0x0002, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0002, 0x0003, - 0x0001, 0x0003, 0x0002, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, - 0x0001, 0x0001, -}; - -static const u16 b43_lcntab_0x17[] = { - 0x001a, 0x0034, 0x004e, 0x0068, 0x009c, 0x00d0, - 0x00ea, 0x0104, 0x0034, 0x0068, 0x009c, 0x00d0, - 0x0138, 0x01a0, 0x01d4, 0x0208, 0x004e, 0x009c, - 0x00ea, 0x0138, 0x01d4, 0x0270, 0x02be, 0x030c, - 0x0068, 0x00d0, 0x0138, 0x01a0, 0x0270, 0x0340, - 0x03a8, 0x0410, 0x0018, 0x009c, 0x00d0, 0x0104, - 0x00ea, 0x0138, 0x0186, 0x00d0, 0x0104, 0x0104, - 0x0138, 0x016c, 0x016c, 0x01a0, 0x0138, 0x0186, - 0x0186, 0x01d4, 0x0222, 0x0222, 0x0270, 0x0104, - 0x0138, 0x016c, 0x0138, 0x016c, 0x01a0, 0x01d4, - 0x01a0, 0x01d4, 0x0208, 0x0208, 0x023c, 0x0186, - 0x01d4, 0x0222, 0x01d4, 0x0222, 0x0270, 0x02be, - 0x0270, 0x02be, 0x030c, 0x030c, 0x035a, 0x0036, - 0x006c, 0x00a2, 0x00d8, 0x0144, 0x01b0, 0x01e6, - 0x021c, 0x006c, 0x00d8, 0x0144, 0x01b0, 0x0288, - 0x0360, 0x03cc, 0x0438, 0x00a2, 0x0144, 0x01e6, - 0x0288, 0x03cc, 0x0510, 0x05b2, 0x0654, 0x00d8, - 0x01b0, 0x0288, 0x0360, 0x0510, 0x06c0, 0x0798, - 0x0870, 0x0018, 0x0144, 0x01b0, 0x021c, 0x01e6, - 0x0288, 0x032a, 0x01b0, 0x021c, 0x021c, 0x0288, - 0x02f4, 0x02f4, 0x0360, 0x0288, 0x032a, 0x032a, - 0x03cc, 0x046e, 0x046e, 0x0510, 0x021c, 0x0288, - 0x02f4, 0x0288, 0x02f4, 0x0360, 0x03cc, 0x0360, - 0x03cc, 0x0438, 0x0438, 0x04a4, 0x032a, 0x03cc, - 0x046e, 0x03cc, 0x046e, 0x0510, 0x05b2, 0x0510, - 0x05b2, 0x0654, 0x0654, 0x06f6, -}; - -static const u16 b43_lcntab_0x00[] = { - 0x0200, 0x0300, 0x0400, 0x0600, 0x0800, 0x0b00, - 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, - 0x1006, 0x1007, 0x1707, 0x2007, 0x2d07, 0x4007, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0200, 0x0300, 0x0400, 0x0600, - 0x0800, 0x0b00, 0x1000, 0x1001, 0x1002, 0x1003, - 0x1004, 0x1005, 0x1006, 0x1007, 0x1707, 0x2007, - 0x2d07, 0x4007, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, -}; - -static const u32 b43_lcntab_0x18[] = { - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, - 0x00080000, 0x00080000, 0x00080000, 0x00080000, -}; - -/************************************************** - * TX gain. - **************************************************/ - -static const struct b43_lcntab_tx_gain_tbl_entry - b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0[B43_LCNTAB_TX_GAIN_SIZE] = { - { 0x03, 0x00, 0x1f, 0x0, 0x48 }, - { 0x03, 0x00, 0x1f, 0x0, 0x46 }, - { 0x03, 0x00, 0x1f, 0x0, 0x44 }, - { 0x03, 0x00, 0x1e, 0x0, 0x43 }, - { 0x03, 0x00, 0x1d, 0x0, 0x44 }, - { 0x03, 0x00, 0x1c, 0x0, 0x44 }, - { 0x03, 0x00, 0x1b, 0x0, 0x45 }, - { 0x03, 0x00, 0x1a, 0x0, 0x46 }, - { 0x03, 0x00, 0x19, 0x0, 0x46 }, - { 0x03, 0x00, 0x18, 0x0, 0x47 }, - { 0x03, 0x00, 0x17, 0x0, 0x48 }, - { 0x03, 0x00, 0x17, 0x0, 0x46 }, - { 0x03, 0x00, 0x16, 0x0, 0x47 }, - { 0x03, 0x00, 0x15, 0x0, 0x48 }, - { 0x03, 0x00, 0x15, 0x0, 0x46 }, - { 0x03, 0x00, 0x15, 0x0, 0x44 }, - { 0x03, 0x00, 0x15, 0x0, 0x42 }, - { 0x03, 0x00, 0x15, 0x0, 0x40 }, - { 0x03, 0x00, 0x15, 0x0, 0x3f }, - { 0x03, 0x00, 0x14, 0x0, 0x40 }, - { 0x03, 0x00, 0x13, 0x0, 0x41 }, - { 0x03, 0x00, 0x13, 0x0, 0x40 }, - { 0x03, 0x00, 0x12, 0x0, 0x41 }, - { 0x03, 0x00, 0x12, 0x0, 0x40 }, - { 0x03, 0x00, 0x11, 0x0, 0x41 }, - { 0x03, 0x00, 0x11, 0x0, 0x40 }, - { 0x03, 0x00, 0x10, 0x0, 0x41 }, - { 0x03, 0x00, 0x10, 0x0, 0x40 }, - { 0x03, 0x00, 0x10, 0x0, 0x3e }, - { 0x03, 0x00, 0x10, 0x0, 0x3c }, - { 0x03, 0x00, 0x10, 0x0, 0x3a }, - { 0x03, 0x00, 0x0f, 0x0, 0x3d }, - { 0x03, 0x00, 0x0f, 0x0, 0x3b }, - { 0x03, 0x00, 0x0e, 0x0, 0x3d }, - { 0x03, 0x00, 0x0e, 0x0, 0x3c }, - { 0x03, 0x00, 0x0e, 0x0, 0x3a }, - { 0x03, 0x00, 0x0d, 0x0, 0x3c }, - { 0x03, 0x00, 0x0d, 0x0, 0x3b }, - { 0x03, 0x00, 0x0c, 0x0, 0x3e }, - { 0x03, 0x00, 0x0c, 0x0, 0x3c }, - { 0x03, 0x00, 0x0c, 0x0, 0x3a }, - { 0x03, 0x00, 0x0b, 0x0, 0x3e }, - { 0x03, 0x00, 0x0b, 0x0, 0x3c }, - { 0x03, 0x00, 0x0b, 0x0, 0x3b }, - { 0x03, 0x00, 0x0b, 0x0, 0x39 }, - { 0x03, 0x00, 0x0a, 0x0, 0x3d }, - { 0x03, 0x00, 0x0a, 0x0, 0x3b }, - { 0x03, 0x00, 0x0a, 0x0, 0x39 }, - { 0x03, 0x00, 0x09, 0x0, 0x3e }, - { 0x03, 0x00, 0x09, 0x0, 0x3c }, - { 0x03, 0x00, 0x09, 0x0, 0x3a }, - { 0x03, 0x00, 0x09, 0x0, 0x39 }, - { 0x03, 0x00, 0x08, 0x0, 0x3e }, - { 0x03, 0x00, 0x08, 0x0, 0x3c }, - { 0x03, 0x00, 0x08, 0x0, 0x3a }, - { 0x03, 0x00, 0x08, 0x0, 0x39 }, - { 0x03, 0x00, 0x08, 0x0, 0x37 }, - { 0x03, 0x00, 0x07, 0x0, 0x3d }, - { 0x03, 0x00, 0x07, 0x0, 0x3c }, - { 0x03, 0x00, 0x07, 0x0, 0x3a }, - { 0x03, 0x00, 0x07, 0x0, 0x38 }, - { 0x03, 0x00, 0x07, 0x0, 0x37 }, - { 0x03, 0x00, 0x06, 0x0, 0x3e }, - { 0x03, 0x00, 0x06, 0x0, 0x3c }, - { 0x03, 0x00, 0x06, 0x0, 0x3a }, - { 0x03, 0x00, 0x06, 0x0, 0x39 }, - { 0x03, 0x00, 0x06, 0x0, 0x37 }, - { 0x03, 0x00, 0x06, 0x0, 0x36 }, - { 0x03, 0x00, 0x06, 0x0, 0x34 }, - { 0x03, 0x00, 0x05, 0x0, 0x3d }, - { 0x03, 0x00, 0x05, 0x0, 0x3b }, - { 0x03, 0x00, 0x05, 0x0, 0x39 }, - { 0x03, 0x00, 0x05, 0x0, 0x38 }, - { 0x03, 0x00, 0x05, 0x0, 0x36 }, - { 0x03, 0x00, 0x05, 0x0, 0x35 }, - { 0x03, 0x00, 0x05, 0x0, 0x33 }, - { 0x03, 0x00, 0x04, 0x0, 0x3e }, - { 0x03, 0x00, 0x04, 0x0, 0x3c }, - { 0x03, 0x00, 0x04, 0x0, 0x3a }, - { 0x03, 0x00, 0x04, 0x0, 0x39 }, - { 0x03, 0x00, 0x04, 0x0, 0x37 }, - { 0x03, 0x00, 0x04, 0x0, 0x36 }, - { 0x03, 0x00, 0x04, 0x0, 0x34 }, - { 0x03, 0x00, 0x04, 0x0, 0x33 }, - { 0x03, 0x00, 0x04, 0x0, 0x31 }, - { 0x03, 0x00, 0x04, 0x0, 0x30 }, - { 0x03, 0x00, 0x04, 0x0, 0x2e }, - { 0x03, 0x00, 0x03, 0x0, 0x3c }, - { 0x03, 0x00, 0x03, 0x0, 0x3a }, - { 0x03, 0x00, 0x03, 0x0, 0x39 }, - { 0x03, 0x00, 0x03, 0x0, 0x37 }, - { 0x03, 0x00, 0x03, 0x0, 0x36 }, - { 0x03, 0x00, 0x03, 0x0, 0x34 }, - { 0x03, 0x00, 0x03, 0x0, 0x33 }, - { 0x03, 0x00, 0x03, 0x0, 0x31 }, - { 0x03, 0x00, 0x03, 0x0, 0x30 }, - { 0x03, 0x00, 0x03, 0x0, 0x2e }, - { 0x03, 0x00, 0x03, 0x0, 0x2d }, - { 0x03, 0x00, 0x03, 0x0, 0x2c }, - { 0x03, 0x00, 0x03, 0x0, 0x2b }, - { 0x03, 0x00, 0x03, 0x0, 0x29 }, - { 0x03, 0x00, 0x02, 0x0, 0x3d }, - { 0x03, 0x00, 0x02, 0x0, 0x3b }, - { 0x03, 0x00, 0x02, 0x0, 0x39 }, - { 0x03, 0x00, 0x02, 0x0, 0x38 }, - { 0x03, 0x00, 0x02, 0x0, 0x36 }, - { 0x03, 0x00, 0x02, 0x0, 0x35 }, - { 0x03, 0x00, 0x02, 0x0, 0x33 }, - { 0x03, 0x00, 0x02, 0x0, 0x32 }, - { 0x03, 0x00, 0x02, 0x0, 0x30 }, - { 0x03, 0x00, 0x02, 0x0, 0x2f }, - { 0x03, 0x00, 0x02, 0x0, 0x2e }, - { 0x03, 0x00, 0x02, 0x0, 0x2c }, - { 0x03, 0x00, 0x02, 0x0, 0x2b }, - { 0x03, 0x00, 0x02, 0x0, 0x2a }, - { 0x03, 0x00, 0x02, 0x0, 0x29 }, - { 0x03, 0x00, 0x02, 0x0, 0x27 }, - { 0x03, 0x00, 0x02, 0x0, 0x26 }, - { 0x03, 0x00, 0x02, 0x0, 0x25 }, - { 0x03, 0x00, 0x02, 0x0, 0x24 }, - { 0x03, 0x00, 0x02, 0x0, 0x23 }, - { 0x03, 0x00, 0x02, 0x0, 0x22 }, - { 0x03, 0x00, 0x02, 0x0, 0x21 }, - { 0x03, 0x00, 0x02, 0x0, 0x20 }, - { 0x03, 0x00, 0x01, 0x0, 0x3f }, - { 0x03, 0x00, 0x01, 0x0, 0x3d }, - { 0x03, 0x00, 0x01, 0x0, 0x3b }, - { 0x03, 0x00, 0x01, 0x0, 0x39 }, -}; - -/************************************************** - * SW control. - **************************************************/ - -static const u16 b43_lcntab_sw_ctl_4313_epa_rev0[] = { - 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, - 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, - 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, - 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, - 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, - 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, - 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, - 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, - 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, - 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, - 0x0002, 0x0008, 0x0004, 0x0001, -}; - -/************************************************** - * R/W ops. - **************************************************/ - -u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset) -{ - u32 type, value; - - type = offset & B43_LCNTAB_TYPEMASK; - offset &= ~B43_LCNTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - switch (type) { - case B43_LCNTAB_8BIT: - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO) & 0xFF; - break; - case B43_LCNTAB_16BIT: - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO); - break; - case B43_LCNTAB_32BIT: - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - value = b43_phy_read(dev, B43_PHY_LCN_TABLE_DATALO); - value |= (b43_phy_read(dev, B43_PHY_LCN_TABLE_DATAHI) << 16); - break; - default: - B43_WARN_ON(1); - value = 0; - } - - return value; -} - -void b43_lcntab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data) -{ - u32 type; - u8 *data = _data; - unsigned int i; - - type = offset & B43_LCNTAB_TYPEMASK; - offset &= ~B43_LCNTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_LCNTAB_8BIT: - *data = b43_phy_read(dev, - B43_PHY_LCN_TABLE_DATALO) & 0xFF; - data++; - break; - case B43_LCNTAB_16BIT: - *((u16 *)data) = b43_phy_read(dev, - B43_PHY_LCN_TABLE_DATALO); - data += 2; - break; - case B43_LCNTAB_32BIT: - *((u32 *)data) = b43_phy_read(dev, - B43_PHY_LCN_TABLE_DATALO); - *((u32 *)data) |= (b43_phy_read(dev, - B43_PHY_LCN_TABLE_DATAHI) << 16); - data += 4; - break; - default: - B43_WARN_ON(1); - } - } -} - -void b43_lcntab_write(struct b43_wldev *dev, u32 offset, u32 value) -{ - u32 type; - - type = offset & B43_LCNTAB_TYPEMASK; - offset &= 0xFFFF; - - switch (type) { - case B43_LCNTAB_8BIT: - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value); - break; - case B43_LCNTAB_16BIT: - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value); - break; - case B43_LCNTAB_32BIT: - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, value >> 16); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - - return; -} - -void b43_lcntab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data) -{ - u32 type, value; - const u8 *data = _data; - unsigned int i; - - type = offset & B43_LCNTAB_TYPEMASK; - offset &= ~B43_LCNTAB_TYPEMASK; - B43_WARN_ON(offset > 0xFFFF); - - b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, offset); - - for (i = 0; i < nr_elements; i++) { - switch (type) { - case B43_LCNTAB_8BIT: - value = *data; - data++; - B43_WARN_ON(value & ~0xFF); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value); - break; - case B43_LCNTAB_16BIT: - value = *((u16 *)data); - data += 2; - B43_WARN_ON(value & ~0xFFFF); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, value); - break; - case B43_LCNTAB_32BIT: - value = *((u32 *)data); - data += 4; - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, - value >> 16); - b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, - value & 0xFFFF); - break; - default: - B43_WARN_ON(1); - } - } -} - -/************************************************** - * Tables ops. - **************************************************/ - -#define lcntab_upload(dev, offset, data) do { \ - b43_lcntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ - } while (0) -static void b43_phy_lcn_upload_static_tables(struct b43_wldev *dev) -{ - lcntab_upload(dev, B43_LCNTAB16(0x02, 0), b43_lcntab_0x02); - lcntab_upload(dev, B43_LCNTAB16(0x01, 0), b43_lcntab_0x01); - lcntab_upload(dev, B43_LCNTAB32(0x0b, 0), b43_lcntab_0x0b); - lcntab_upload(dev, B43_LCNTAB32(0x0c, 0), b43_lcntab_0x0c); - lcntab_upload(dev, B43_LCNTAB32(0x0d, 0), b43_lcntab_0x0d); - lcntab_upload(dev, B43_LCNTAB16(0x0e, 0), b43_lcntab_0x0e); - lcntab_upload(dev, B43_LCNTAB16(0x0f, 0), b43_lcntab_0x0f); - lcntab_upload(dev, B43_LCNTAB16(0x10, 0), b43_lcntab_0x10); - lcntab_upload(dev, B43_LCNTAB16(0x11, 0), b43_lcntab_0x11); - lcntab_upload(dev, B43_LCNTAB32(0x12, 0), b43_lcntab_0x12); - lcntab_upload(dev, B43_LCNTAB16(0x14, 0), b43_lcntab_0x14); - lcntab_upload(dev, B43_LCNTAB16(0x17, 0), b43_lcntab_0x17); - lcntab_upload(dev, B43_LCNTAB16(0x00, 0), b43_lcntab_0x00); - lcntab_upload(dev, B43_LCNTAB32(0x18, 0), b43_lcntab_0x18); -} - -static void b43_phy_lcn_load_tx_gain_tab(struct b43_wldev *dev, - const struct b43_lcntab_tx_gain_tbl_entry *gain_table) -{ - u32 i; - u32 val; - - u16 pa_gain = 0x70; - if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) - pa_gain = 0x10; - - for (i = 0; i < B43_LCNTAB_TX_GAIN_SIZE; i++) { - val = ((pa_gain << 24) | - (gain_table[i].pad << 16) | - (gain_table[i].pga << 8) | - gain_table[i].gm); - b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0xc0 + i), val); - - /* brcmsmac doesn't maskset, we follow newer wl here */ - val = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x140 + i)); - val &= 0x000fffff; - val |= ((gain_table[i].dac << 28) | - (gain_table[i].bb_mult << 20)); - b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x140 + i), val); - } -} - -/* wlc_lcnphy_load_rfpower */ -static void b43_phy_lcn_load_rfpower(struct b43_wldev *dev) -{ - u32 bbmult, rfgain; - u8 i; - - for (i = 0; i < 128; i++) { - bbmult = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x140 + i)); - bbmult >>= 20; - rfgain = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0xc0 + i)); - - /* TODO: calculate value for 0x240 + i table offset - * b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x240 + i), val); - */ - } -} - -/* Not implemented in brcmsmac, noticed in wl in MMIO dump */ -static void b43_phy_lcn_rewrite_rfpower_table(struct b43_wldev *dev) -{ - int i; - u32 tmp; - for (i = 0; i < 128; i++) { - tmp = b43_lcntab_read(dev, B43_LCNTAB32(0x7, 0x240 + i)); - b43_lcntab_write(dev, B43_LCNTAB32(0x7, 0x240 + i), tmp); - } -} - -/* wlc_lcnphy_clear_papd_comptable */ -static void b43_phy_lcn_clean_papd_comp_table(struct b43_wldev *dev) -{ - u8 i; - - for (i = 0; i < 0x80; i++) - b43_lcntab_write(dev, B43_LCNTAB32(0x18, i), 0x80000); -} - -/* wlc_lcnphy_tbl_init */ -void b43_phy_lcn_tables_init(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - - b43_phy_lcn_upload_static_tables(dev); - - if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { - if (sprom->boardflags_lo & B43_BFL_FEM) - b43_phy_lcn_load_tx_gain_tab(dev, - b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0); - else - b43err(dev->wl, - "TX gain table unknown for this card\n"); - } - - if (sprom->boardflags_lo & B43_BFL_FEM && - !(sprom->boardflags_hi & B43_BFH_FEM_BT)) - b43_lcntab_write_bulk(dev, B43_LCNTAB16(0xf, 0), - ARRAY_SIZE(b43_lcntab_sw_ctl_4313_epa_rev0), - b43_lcntab_sw_ctl_4313_epa_rev0); - else - b43err(dev->wl, "SW ctl table is unknown for this card\n"); - - b43_phy_lcn_load_rfpower(dev); - b43_phy_lcn_rewrite_rfpower_table(dev); - b43_phy_lcn_clean_papd_comp_table(dev); -} diff --git a/drivers/net/wireless/b43/tables_phy_lcn.h b/drivers/net/wireless/b43/tables_phy_lcn.h deleted file mode 100644 index caff9db68..000000000 --- a/drivers/net/wireless/b43/tables_phy_lcn.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef B43_TABLES_PHY_LCN_H_ -#define B43_TABLES_PHY_LCN_H_ - -/* The LCN-PHY tables. */ -#define B43_LCNTAB_TYPEMASK 0xF0000000 -#define B43_LCNTAB_8BIT 0x10000000 -#define B43_LCNTAB_16BIT 0x20000000 -#define B43_LCNTAB_32BIT 0x30000000 -#define B43_LCNTAB8(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_8BIT) -#define B43_LCNTAB16(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_16BIT) -#define B43_LCNTAB32(table, offset) (((table) << 10) | (offset) | B43_LCNTAB_32BIT) - -#define B43_LCNTAB_TX_GAIN_SIZE 128 - -u32 b43_lcntab_read(struct b43_wldev *dev, u32 offset); -void b43_lcntab_read_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, void *_data); -void b43_lcntab_write(struct b43_wldev *dev, u32 offset, u32 value); -void b43_lcntab_write_bulk(struct b43_wldev *dev, u32 offset, - unsigned int nr_elements, const void *_data); - -void b43_phy_lcn_tables_init(struct b43_wldev *dev); - -#endif /* B43_TABLES_PHY_LCN_H_ */ diff --git a/drivers/net/wireless/b43/wa.c b/drivers/net/wireless/b43/wa.c deleted file mode 100644 index c218c08fb..000000000 --- a/drivers/net/wireless/b43/wa.c +++ /dev/null @@ -1,634 +0,0 @@ -/* - - Broadcom B43 wireless driver - - PHY workarounds. - - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2007 Michael Buesch <m@bues.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "b43.h" -#include "main.h" -#include "tables.h" -#include "phy_common.h" -#include "wa.h" - -static void b43_wa_papd(struct b43_wldev *dev) -{ - u16 backup; - - backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0); - b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7); - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0); - b43_dummy_transmission(dev, true, true); - b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup); -} - -static void b43_wa_auxclipthr(struct b43_wldev *dev) -{ - b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800); -} - -static void b43_wa_afcdac(struct b43_wldev *dev) -{ - b43_phy_write(dev, 0x0035, 0x03FF); - b43_phy_write(dev, 0x0036, 0x0400); -} - -static void b43_wa_txdc_offset(struct b43_wldev *dev) -{ - b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051); -} - -void b43_wa_initgains(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); - b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); - if (phy->rev <= 2) - b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); - b43_radio_write16(dev, 0x0002, 0x1FBF); - - b43_phy_write(dev, 0x0024, 0x4680); - b43_phy_write(dev, 0x0020, 0x0003); - b43_phy_write(dev, 0x001D, 0x0F40); - b43_phy_write(dev, 0x001F, 0x1C00); - if (phy->rev <= 3) - b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); - else if (phy->rev == 5) { - b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); - b43_phy_write(dev, 0x00CC, 0x2121); - } - if (phy->rev >= 3) - b43_phy_write(dev, 0x00BA, 0x3ED5); -} - -static void b43_wa_divider(struct b43_wldev *dev) -{ - b43_phy_mask(dev, 0x002B, ~0x0100); - b43_phy_write(dev, 0x008E, 0x58C1); -} - -static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */ -{ - if (dev->phy.rev <= 2) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7); - } else { - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25); - } -} - -static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */ -{ - int i; - - if (0 /* FIXME: For APHY.rev=2 this might be needed */) { - for (i = 0; i < 8; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8); - for (i = 8; i < 16; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8); - } else { - for (i = 0; i < 64; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i); - } -} - -static void b43_wa_analog(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - u16 ofdmrev; - - ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION; - if (ofdmrev > 2) { - if (phy->type == B43_PHYTYPE_A) - b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808); - else - b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000); - } else { - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044); - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201); - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040); - } -} - -static void b43_wa_dac(struct b43_wldev *dev) -{ - if (dev->phy.analog == 1) - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, - (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008); - else - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, - (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010); -} - -static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */ -{ - int i; - - if (dev->phy.type == B43_PHYTYPE_A) - for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]); - else - for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]); -} - -static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */ -{ - struct b43_phy *phy = &dev->phy; - int i; - - if (phy->type == B43_PHYTYPE_A) { - if (phy->rev == 2) - for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]); - else - for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]); - } else { - if (phy->rev == 1) - for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]); - else - for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]); - } -} - -static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */ -{ - int i; - - for (i = 0; i < B43_TAB_ROTOR_SIZE; i++) - b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]); -} - -static void b43_write_null_nst(struct b43_wldev *dev) -{ - int i; - - for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, 0); -} - -static void b43_write_nst(struct b43_wldev *dev, const u16 *nst) -{ - int i; - - for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, nst[i]); -} - -static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */ -{ - struct b43_phy *phy = &dev->phy; - - if (phy->type == B43_PHYTYPE_A) { - if (phy->rev <= 1) - b43_write_null_nst(dev); - else if (phy->rev == 2) - b43_write_nst(dev, b43_tab_noisescalea2); - else if (phy->rev == 3) - b43_write_nst(dev, b43_tab_noisescalea3); - else - b43_write_nst(dev, b43_tab_noisescaleg3); - } else { - if (phy->rev >= 6) { - if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) - b43_write_nst(dev, b43_tab_noisescaleg3); - else - b43_write_nst(dev, b43_tab_noisescaleg2); - } else { - b43_write_nst(dev, b43_tab_noisescaleg1); - } - } -} - -static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */ -{ - int i; - - for (i = 0; i < B43_TAB_RETARD_SIZE; i++) - b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD, - i, b43_tab_retard[i]); -} - -static void b43_wa_txlna_gain(struct b43_wldev *dev) -{ - b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000); -} - -static void b43_wa_crs_reset(struct b43_wldev *dev) -{ - b43_phy_write(dev, 0x002C, 0x0064); -} - -static void b43_wa_2060txlna_gain(struct b43_wldev *dev) -{ - b43_hf_write(dev, b43_hf_read(dev) | - B43_HF_2060W); -} - -static void b43_wa_lms(struct b43_wldev *dev) -{ - b43_phy_maskset(dev, 0x0055, 0xFFC0, 0x0004); -} - -static void b43_wa_mixedsignal(struct b43_wldev *dev) -{ - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3); -} - -static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */ -{ - struct b43_phy *phy = &dev->phy; - int i; - const u16 *tab; - - if (phy->type == B43_PHYTYPE_A) { - tab = b43_tab_sigmasqr1; - } else if (phy->type == B43_PHYTYPE_G) { - tab = b43_tab_sigmasqr2; - } else { - B43_WARN_ON(1); - return; - } - - for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ, - i, tab[i]); - } -} - -static void b43_wa_iqadc(struct b43_wldev *dev) -{ - if (dev->phy.analog == 4) - b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0, - b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000); -} - -static void b43_wa_crs_ed(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->rev == 1) { - b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19); - } else if (phy->rev == 2) { - b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861); - b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271); - b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800); - } else { - b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098); - b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070); - b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080); - b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800); - } -} - -static void b43_wa_crs_thr(struct b43_wldev *dev) -{ - b43_phy_maskset(dev, B43_PHY_CRS0, ~0x03C0, 0xD000); -} - -static void b43_wa_crs_blank(struct b43_wldev *dev) -{ - b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A); -} - -static void b43_wa_cck_shiftbits(struct b43_wldev *dev) -{ - b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026); -} - -static void b43_wa_wrssi_offset(struct b43_wldev *dev) -{ - int i; - - if (dev->phy.rev == 1) { - for (i = 0; i < 16; i++) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1, - i, 0x0020); - } - } else { - for (i = 0; i < 32; i++) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI, - i, 0x0820); - } - } -} - -static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev) -{ - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15); - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20); -} - -static void b43_wa_altagc(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->rev == 1) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D); - b43_phy_write(dev, B43_PHY_LMS, 4); - } else { - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25); - } - - b43_phy_maskset(dev, B43_PHY_CCKSHIFTBITS_WA, 0x00FF, 0x5700); - b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x007F, 0x000F); - b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x3F80, 0x2B80); - b43_phy_maskset(dev, B43_PHY_ANTWRSETT, 0xF0FF, 0x0300); - b43_radio_set(dev, 0x7A, 0x0008); - b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x000F, 0x0008); - b43_phy_maskset(dev, B43_PHY_P1P2GAIN, ~0x0F00, 0x0600); - b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x0F00, 0x0700); - b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x0F00, 0x0100); - if (phy->rev == 1) { - b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x000F, 0x0007); - } - b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x00FF, 0x001C); - b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x3F00, 0x0200); - b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0x00FF, 0x001C); - b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x00FF, 0x0020); - b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x3F00, 0x0200); - b43_phy_maskset(dev, B43_PHY_OFDM(0x82), ~0x00FF, 0x002E); - b43_phy_maskset(dev, B43_PHY_OFDM(0x96), 0x00FF, 0x1A00); - b43_phy_maskset(dev, B43_PHY_OFDM(0x81), ~0x00FF, 0x0028); - b43_phy_maskset(dev, B43_PHY_OFDM(0x81), 0x00FF, 0x2C00); - if (phy->rev == 1) { - b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B); - b43_phy_maskset(dev, B43_PHY_OFDM(0x1B), ~0x001E, 0x0002); - } else { - b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x001E); - b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A); - b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, ~0x000F, 0x0004); - if (phy->rev >= 6) { - b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A); - b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, 0x0FFF, 0x3000); - } - } - b43_phy_maskset(dev, B43_PHY_DIVSRCHIDX, 0x8080, 0x7874); - b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00); - if (phy->rev == 1) { - b43_phy_maskset(dev, B43_PHY_DIVP1P2GAIN, ~0x0F00, 0x0600); - b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E); - b43_phy_maskset(dev, B43_PHY_ANTWRSETT, ~0x00FF, 0x001E); - b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28); - } else { - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28); - } - if (phy->rev >= 6) { - b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x0003); - b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x1000); - } - b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */ -} - -static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */ -{ - b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0x7654); -} - -static void b43_wa_cpll_nonpilot(struct b43_wldev *dev) -{ - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0); - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0); -} - -static void b43_wa_rssi_adc(struct b43_wldev *dev) -{ - if (dev->phy.analog == 4) - b43_phy_write(dev, 0x00DC, 0x7454); -} - -static void b43_wa_boards_a(struct b43_wldev *dev) -{ - if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && - dev->dev->board_type == SSB_BOARD_BU4306 && - dev->dev->board_rev < 0x30) { - b43_phy_write(dev, 0x0010, 0xE000); - b43_phy_write(dev, 0x0013, 0x0140); - b43_phy_write(dev, 0x0014, 0x0280); - } else { - if (dev->dev->board_type == SSB_BOARD_MP4318 && - dev->dev->board_rev < 0x20) { - b43_phy_write(dev, 0x0013, 0x0210); - b43_phy_write(dev, 0x0014, 0x0840); - } else { - b43_phy_write(dev, 0x0013, 0x0140); - b43_phy_write(dev, 0x0014, 0x0280); - } - if (dev->phy.rev <= 4) - b43_phy_write(dev, 0x0010, 0xE000); - else - b43_phy_write(dev, 0x0010, 0x2000); - b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039); - b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040); - } -} - -static void b43_wa_boards_g(struct b43_wldev *dev) -{ - struct ssb_sprom *sprom = dev->dev->bus_sprom; - struct b43_phy *phy = &dev->phy; - - if (dev->dev->board_vendor != SSB_BOARDVENDOR_BCM || - dev->dev->board_type != SSB_BOARD_BU4306 || - dev->dev->board_rev != 0x17) { - if (phy->rev < 2) { - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001); - } else { - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001); - if ((sprom->boardflags_lo & B43_BFL_EXTLNA) && - (phy->rev >= 7)) { - b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000); - b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002); - } - } - } - if (sprom->boardflags_lo & B43_BFL_FEM) { - b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120); - b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480); - } -} - -void b43_wa_all(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - if (phy->type == B43_PHYTYPE_A) { - switch (phy->rev) { - case 2: - b43_wa_papd(dev); - b43_wa_auxclipthr(dev); - b43_wa_afcdac(dev); - b43_wa_txdc_offset(dev); - b43_wa_initgains(dev); - b43_wa_divider(dev); - b43_wa_gt(dev); - b43_wa_rssi_lt(dev); - b43_wa_analog(dev); - b43_wa_dac(dev); - b43_wa_fft(dev); - b43_wa_nft(dev); - b43_wa_rt(dev); - b43_wa_nst(dev); - b43_wa_art(dev); - b43_wa_txlna_gain(dev); - b43_wa_crs_reset(dev); - b43_wa_2060txlna_gain(dev); - b43_wa_lms(dev); - break; - case 3: - b43_wa_papd(dev); - b43_wa_mixedsignal(dev); - b43_wa_rssi_lt(dev); - b43_wa_txdc_offset(dev); - b43_wa_initgains(dev); - b43_wa_dac(dev); - b43_wa_nft(dev); - b43_wa_nst(dev); - b43_wa_msst(dev); - b43_wa_analog(dev); - b43_wa_gt(dev); - b43_wa_txpuoff_rxpuon(dev); - b43_wa_txlna_gain(dev); - break; - case 5: - b43_wa_iqadc(dev); - case 6: - b43_wa_papd(dev); - b43_wa_rssi_lt(dev); - b43_wa_txdc_offset(dev); - b43_wa_initgains(dev); - b43_wa_dac(dev); - b43_wa_nft(dev); - b43_wa_nst(dev); - b43_wa_msst(dev); - b43_wa_analog(dev); - b43_wa_gt(dev); - b43_wa_txpuoff_rxpuon(dev); - b43_wa_txlna_gain(dev); - break; - case 7: - b43_wa_iqadc(dev); - b43_wa_papd(dev); - b43_wa_rssi_lt(dev); - b43_wa_txdc_offset(dev); - b43_wa_initgains(dev); - b43_wa_dac(dev); - b43_wa_nft(dev); - b43_wa_nst(dev); - b43_wa_msst(dev); - b43_wa_analog(dev); - b43_wa_gt(dev); - b43_wa_txpuoff_rxpuon(dev); - b43_wa_txlna_gain(dev); - b43_wa_rssi_adc(dev); - default: - B43_WARN_ON(1); - } - b43_wa_boards_a(dev); - } else if (phy->type == B43_PHYTYPE_G) { - switch (phy->rev) { - case 1://XXX review rev1 - b43_wa_crs_ed(dev); - b43_wa_crs_thr(dev); - b43_wa_crs_blank(dev); - b43_wa_cck_shiftbits(dev); - b43_wa_fft(dev); - b43_wa_nft(dev); - b43_wa_rt(dev); - b43_wa_nst(dev); - b43_wa_art(dev); - b43_wa_wrssi_offset(dev); - b43_wa_altagc(dev); - break; - case 2: - case 6: - case 7: - case 8: - case 9: - b43_wa_tr_ltov(dev); - b43_wa_crs_ed(dev); - b43_wa_rssi_lt(dev); - b43_wa_nft(dev); - b43_wa_nst(dev); - b43_wa_msst(dev); - b43_wa_wrssi_offset(dev); - b43_wa_altagc(dev); - b43_wa_analog(dev); - b43_wa_txpuoff_rxpuon(dev); - break; - default: - B43_WARN_ON(1); - } - b43_wa_boards_g(dev); - } else { /* No N PHY support so far, LP PHY is in phy_lp.c */ - B43_WARN_ON(1); - } - - b43_wa_cpll_nonpilot(dev); -} diff --git a/drivers/net/wireless/b43/wa.h b/drivers/net/wireless/b43/wa.h deleted file mode 100644 index e163c5e56..000000000 --- a/drivers/net/wireless/b43/wa.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef B43_WA_H_ -#define B43_WA_H_ - -void b43_wa_initgains(struct b43_wldev *dev); -void b43_wa_all(struct b43_wldev *dev); - -#endif /* B43_WA_H_ */ diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c deleted file mode 100644 index 426dc13c4..000000000 --- a/drivers/net/wireless/b43/xmit.c +++ /dev/null @@ -1,947 +0,0 @@ -/* - - Broadcom B43 wireless driver - - Transmission (TX/RX) related functions. - - Copyright (C) 2005 Martin Langer <martin-langer@gmx.de> - Copyright (C) 2005 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (C) 2005, 2006 Michael Buesch <m@bues.ch> - Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org> - Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include "xmit.h" -#include "phy_common.h" -#include "dma.h" -#include "pio.h" - -static const struct b43_tx_legacy_rate_phy_ctl_entry b43_tx_legacy_rate_phy_ctl[] = { - { B43_CCK_RATE_1MB, 0x0, 0x0 }, - { B43_CCK_RATE_2MB, 0x0, 0x1 }, - { B43_CCK_RATE_5MB, 0x0, 0x2 }, - { B43_CCK_RATE_11MB, 0x0, 0x3 }, - { B43_OFDM_RATE_6MB, B43_TXH_PHY1_CRATE_1_2, B43_TXH_PHY1_MODUL_BPSK }, - { B43_OFDM_RATE_9MB, B43_TXH_PHY1_CRATE_3_4, B43_TXH_PHY1_MODUL_BPSK }, - { B43_OFDM_RATE_12MB, B43_TXH_PHY1_CRATE_1_2, B43_TXH_PHY1_MODUL_QPSK }, - { B43_OFDM_RATE_18MB, B43_TXH_PHY1_CRATE_3_4, B43_TXH_PHY1_MODUL_QPSK }, - { B43_OFDM_RATE_24MB, B43_TXH_PHY1_CRATE_1_2, B43_TXH_PHY1_MODUL_QAM16 }, - { B43_OFDM_RATE_36MB, B43_TXH_PHY1_CRATE_3_4, B43_TXH_PHY1_MODUL_QAM16 }, - { B43_OFDM_RATE_48MB, B43_TXH_PHY1_CRATE_2_3, B43_TXH_PHY1_MODUL_QAM64 }, - { B43_OFDM_RATE_54MB, B43_TXH_PHY1_CRATE_3_4, B43_TXH_PHY1_MODUL_QAM64 }, -}; - -static const struct b43_tx_legacy_rate_phy_ctl_entry * -b43_tx_legacy_rate_phy_ctl_ent(u8 bitrate) -{ - const struct b43_tx_legacy_rate_phy_ctl_entry *e; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(b43_tx_legacy_rate_phy_ctl); i++) { - e = &(b43_tx_legacy_rate_phy_ctl[i]); - if (e->bitrate == bitrate) - return e; - } - - B43_WARN_ON(1); - return NULL; -} - -/* Extract the bitrate index out of a CCK PLCP header. */ -static int b43_plcp_get_bitrate_idx_cck(struct b43_plcp_hdr6 *plcp) -{ - switch (plcp->raw[0]) { - case 0x0A: - return 0; - case 0x14: - return 1; - case 0x37: - return 2; - case 0x6E: - return 3; - } - return -1; -} - -/* Extract the bitrate index out of an OFDM PLCP header. */ -static int b43_plcp_get_bitrate_idx_ofdm(struct b43_plcp_hdr6 *plcp, bool ghz5) -{ - /* For 2 GHz band first OFDM rate is at index 4, see main.c */ - int base = ghz5 ? 0 : 4; - - switch (plcp->raw[0] & 0xF) { - case 0xB: - return base + 0; - case 0xF: - return base + 1; - case 0xA: - return base + 2; - case 0xE: - return base + 3; - case 0x9: - return base + 4; - case 0xD: - return base + 5; - case 0x8: - return base + 6; - case 0xC: - return base + 7; - } - return -1; -} - -u8 b43_plcp_get_ratecode_cck(const u8 bitrate) -{ - switch (bitrate) { - case B43_CCK_RATE_1MB: - return 0x0A; - case B43_CCK_RATE_2MB: - return 0x14; - case B43_CCK_RATE_5MB: - return 0x37; - case B43_CCK_RATE_11MB: - return 0x6E; - } - B43_WARN_ON(1); - return 0; -} - -u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate) -{ - switch (bitrate) { - case B43_OFDM_RATE_6MB: - return 0xB; - case B43_OFDM_RATE_9MB: - return 0xF; - case B43_OFDM_RATE_12MB: - return 0xA; - case B43_OFDM_RATE_18MB: - return 0xE; - case B43_OFDM_RATE_24MB: - return 0x9; - case B43_OFDM_RATE_36MB: - return 0xD; - case B43_OFDM_RATE_48MB: - return 0x8; - case B43_OFDM_RATE_54MB: - return 0xC; - } - B43_WARN_ON(1); - return 0; -} - -void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, - const u16 octets, const u8 bitrate) -{ - __u8 *raw = plcp->raw; - - if (b43_is_ofdm_rate(bitrate)) { - u32 d; - - d = b43_plcp_get_ratecode_ofdm(bitrate); - B43_WARN_ON(octets & 0xF000); - d |= (octets << 5); - plcp->data = cpu_to_le32(d); - } else { - u32 plen; - - plen = octets * 16 / bitrate; - if ((octets * 16 % bitrate) > 0) { - plen++; - if ((bitrate == B43_CCK_RATE_11MB) - && ((octets * 8 % 11) < 4)) { - raw[1] = 0x84; - } else - raw[1] = 0x04; - } else - raw[1] = 0x04; - plcp->data |= cpu_to_le32(plen << 16); - raw[0] = b43_plcp_get_ratecode_cck(bitrate); - } -} - -/* TODO: verify if needed for SSLPN or LCN */ -static u16 b43_generate_tx_phy_ctl1(struct b43_wldev *dev, u8 bitrate) -{ - const struct b43_phy *phy = &dev->phy; - const struct b43_tx_legacy_rate_phy_ctl_entry *e; - u16 control = 0; - u16 bw; - - if (phy->type == B43_PHYTYPE_LP) - bw = B43_TXH_PHY1_BW_20; - else /* FIXME */ - bw = B43_TXH_PHY1_BW_20; - - if (0) { /* FIXME: MIMO */ - } else if (b43_is_cck_rate(bitrate) && phy->type != B43_PHYTYPE_LP) { - control = bw; - } else { - control = bw; - e = b43_tx_legacy_rate_phy_ctl_ent(bitrate); - if (e) { - control |= e->coding_rate; - control |= e->modulation; - } - control |= B43_TXH_PHY1_MODE_SISO; - } - - return control; -} - -static u8 b43_calc_fallback_rate(u8 bitrate) -{ - switch (bitrate) { - case B43_CCK_RATE_1MB: - return B43_CCK_RATE_1MB; - case B43_CCK_RATE_2MB: - return B43_CCK_RATE_1MB; - case B43_CCK_RATE_5MB: - return B43_CCK_RATE_2MB; - case B43_CCK_RATE_11MB: - return B43_CCK_RATE_5MB; - case B43_OFDM_RATE_6MB: - return B43_CCK_RATE_5MB; - case B43_OFDM_RATE_9MB: - return B43_OFDM_RATE_6MB; - case B43_OFDM_RATE_12MB: - return B43_OFDM_RATE_9MB; - case B43_OFDM_RATE_18MB: - return B43_OFDM_RATE_12MB; - case B43_OFDM_RATE_24MB: - return B43_OFDM_RATE_18MB; - case B43_OFDM_RATE_36MB: - return B43_OFDM_RATE_24MB; - case B43_OFDM_RATE_48MB: - return B43_OFDM_RATE_36MB; - case B43_OFDM_RATE_54MB: - return B43_OFDM_RATE_48MB; - } - B43_WARN_ON(1); - return 0; -} - -/* Generate a TX data header. */ -int b43_generate_txhdr(struct b43_wldev *dev, - u8 *_txhdr, - struct sk_buff *skb_frag, - struct ieee80211_tx_info *info, - u16 cookie) -{ - const unsigned char *fragment_data = skb_frag->data; - unsigned int fragment_len = skb_frag->len; - struct b43_txhdr *txhdr = (struct b43_txhdr *)_txhdr; - const struct b43_phy *phy = &dev->phy; - const struct ieee80211_hdr *wlhdr = - (const struct ieee80211_hdr *)fragment_data; - int use_encryption = !!info->control.hw_key; - __le16 fctl = wlhdr->frame_control; - struct ieee80211_rate *fbrate; - u8 rate, rate_fb; - int rate_ofdm, rate_fb_ofdm; - unsigned int plcp_fragment_len; - u32 mac_ctl = 0; - u16 phy_ctl = 0; - bool fill_phy_ctl1 = (phy->type == B43_PHYTYPE_LP || - phy->type == B43_PHYTYPE_N || - phy->type == B43_PHYTYPE_HT); - u8 extra_ft = 0; - struct ieee80211_rate *txrate; - struct ieee80211_tx_rate *rates; - - memset(txhdr, 0, sizeof(*txhdr)); - - txrate = ieee80211_get_tx_rate(dev->wl->hw, info); - rate = txrate ? txrate->hw_value : B43_CCK_RATE_1MB; - rate_ofdm = b43_is_ofdm_rate(rate); - fbrate = ieee80211_get_alt_retry_rate(dev->wl->hw, info, 0) ? : txrate; - rate_fb = fbrate->hw_value; - rate_fb_ofdm = b43_is_ofdm_rate(rate_fb); - - if (rate_ofdm) - txhdr->phy_rate = b43_plcp_get_ratecode_ofdm(rate); - else - txhdr->phy_rate = b43_plcp_get_ratecode_cck(rate); - txhdr->mac_frame_ctl = wlhdr->frame_control; - memcpy(txhdr->tx_receiver, wlhdr->addr1, ETH_ALEN); - - /* Calculate duration for fallback rate */ - if ((rate_fb == rate) || - (wlhdr->duration_id & cpu_to_le16(0x8000)) || - (wlhdr->duration_id == cpu_to_le16(0))) { - /* If the fallback rate equals the normal rate or the - * dur_id field contains an AID, CFP magic or 0, - * use the original dur_id field. */ - txhdr->dur_fb = wlhdr->duration_id; - } else { - txhdr->dur_fb = ieee80211_generic_frame_duration( - dev->wl->hw, info->control.vif, info->band, - fragment_len, fbrate); - } - - plcp_fragment_len = fragment_len + FCS_LEN; - if (use_encryption) { - u8 key_idx = info->control.hw_key->hw_key_idx; - struct b43_key *key; - int wlhdr_len; - size_t iv_len; - - B43_WARN_ON(key_idx >= ARRAY_SIZE(dev->key)); - key = &(dev->key[key_idx]); - - if (unlikely(!key->keyconf)) { - /* This key is invalid. This might only happen - * in a short timeframe after machine resume before - * we were able to reconfigure keys. - * Drop this packet completely. Do not transmit it - * unencrypted to avoid leaking information. */ - return -ENOKEY; - } - - /* Hardware appends ICV. */ - plcp_fragment_len += info->control.hw_key->icv_len; - - key_idx = b43_kidx_to_fw(dev, key_idx); - mac_ctl |= (key_idx << B43_TXH_MAC_KEYIDX_SHIFT) & - B43_TXH_MAC_KEYIDX; - mac_ctl |= (key->algorithm << B43_TXH_MAC_KEYALG_SHIFT) & - B43_TXH_MAC_KEYALG; - wlhdr_len = ieee80211_hdrlen(fctl); - if (key->algorithm == B43_SEC_ALGO_TKIP) { - u16 phase1key[5]; - int i; - /* we give the phase1key and iv16 here, the key is stored in - * shm. With that the hardware can do phase 2 and encryption. - */ - ieee80211_get_tkip_p1k(info->control.hw_key, skb_frag, phase1key); - /* phase1key is in host endian. Copy to little-endian txhdr->iv. */ - for (i = 0; i < 5; i++) { - txhdr->iv[i * 2 + 0] = phase1key[i]; - txhdr->iv[i * 2 + 1] = phase1key[i] >> 8; - } - /* iv16 */ - memcpy(txhdr->iv + 10, ((u8 *) wlhdr) + wlhdr_len, 3); - } else { - iv_len = min_t(size_t, info->control.hw_key->iv_len, - ARRAY_SIZE(txhdr->iv)); - memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len); - } - } - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_598.plcp), - plcp_fragment_len, rate); - break; - case B43_FW_HDR_351: - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_351.plcp), - plcp_fragment_len, rate); - break; - case B43_FW_HDR_410: - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->format_410.plcp), - plcp_fragment_len, rate); - break; - } - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp_fb), - plcp_fragment_len, rate_fb); - - /* Extra Frame Types */ - if (rate_fb_ofdm) - extra_ft |= B43_TXH_EFT_FB_OFDM; - else - extra_ft |= B43_TXH_EFT_FB_CCK; - - /* Set channel radio code. Note that the micrcode ORs 0x100 to - * this value before comparing it to the value in SHM, if this - * is a 5Ghz packet. - */ - txhdr->chan_radio_code = phy->channel; - - /* PHY TX Control word */ - if (rate_ofdm) - phy_ctl |= B43_TXH_PHY_ENC_OFDM; - else - phy_ctl |= B43_TXH_PHY_ENC_CCK; - if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) - phy_ctl |= B43_TXH_PHY_SHORTPRMBL; - - switch (b43_ieee80211_antenna_sanitize(dev, 0)) { - case 0: /* Default */ - phy_ctl |= B43_TXH_PHY_ANT01AUTO; - break; - case 1: /* Antenna 0 */ - phy_ctl |= B43_TXH_PHY_ANT0; - break; - case 2: /* Antenna 1 */ - phy_ctl |= B43_TXH_PHY_ANT1; - break; - case 3: /* Antenna 2 */ - phy_ctl |= B43_TXH_PHY_ANT2; - break; - case 4: /* Antenna 3 */ - phy_ctl |= B43_TXH_PHY_ANT3; - break; - default: - B43_WARN_ON(1); - } - - rates = info->control.rates; - /* MAC control */ - if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) - mac_ctl |= B43_TXH_MAC_ACK; - /* use hardware sequence counter as the non-TID counter */ - if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) - mac_ctl |= B43_TXH_MAC_HWSEQ; - if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) - mac_ctl |= B43_TXH_MAC_STMSDU; - if (!phy->gmode) - mac_ctl |= B43_TXH_MAC_5GHZ; - - /* Overwrite rates[0].count to make the retry calculation - * in the tx status easier. need the actual retry limit to - * detect whether the fallback rate was used. - */ - if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || - (rates[0].count <= dev->wl->hw->conf.long_frame_max_tx_count)) { - rates[0].count = dev->wl->hw->conf.long_frame_max_tx_count; - mac_ctl |= B43_TXH_MAC_LONGFRAME; - } else { - rates[0].count = dev->wl->hw->conf.short_frame_max_tx_count; - } - - /* Generate the RTS or CTS-to-self frame */ - if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || - (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) { - unsigned int len; - struct ieee80211_hdr *uninitialized_var(hdr); - int rts_rate, rts_rate_fb; - int rts_rate_ofdm, rts_rate_fb_ofdm; - struct b43_plcp_hdr6 *uninitialized_var(plcp); - struct ieee80211_rate *rts_cts_rate; - - rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info); - - rts_rate = rts_cts_rate ? rts_cts_rate->hw_value : B43_CCK_RATE_1MB; - rts_rate_ofdm = b43_is_ofdm_rate(rts_rate); - rts_rate_fb = b43_calc_fallback_rate(rts_rate); - rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb); - - if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { - struct ieee80211_cts *uninitialized_var(cts); - - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - cts = (struct ieee80211_cts *) - (txhdr->format_598.rts_frame); - break; - case B43_FW_HDR_351: - cts = (struct ieee80211_cts *) - (txhdr->format_351.rts_frame); - break; - case B43_FW_HDR_410: - cts = (struct ieee80211_cts *) - (txhdr->format_410.rts_frame); - break; - } - ieee80211_ctstoself_get(dev->wl->hw, info->control.vif, - fragment_data, fragment_len, - info, cts); - mac_ctl |= B43_TXH_MAC_SENDCTS; - len = sizeof(struct ieee80211_cts); - } else { - struct ieee80211_rts *uninitialized_var(rts); - - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - rts = (struct ieee80211_rts *) - (txhdr->format_598.rts_frame); - break; - case B43_FW_HDR_351: - rts = (struct ieee80211_rts *) - (txhdr->format_351.rts_frame); - break; - case B43_FW_HDR_410: - rts = (struct ieee80211_rts *) - (txhdr->format_410.rts_frame); - break; - } - ieee80211_rts_get(dev->wl->hw, info->control.vif, - fragment_data, fragment_len, - info, rts); - mac_ctl |= B43_TXH_MAC_SENDRTS; - len = sizeof(struct ieee80211_rts); - } - len += FCS_LEN; - - /* Generate the PLCP headers for the RTS/CTS frame */ - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - plcp = &txhdr->format_598.rts_plcp; - break; - case B43_FW_HDR_351: - plcp = &txhdr->format_351.rts_plcp; - break; - case B43_FW_HDR_410: - plcp = &txhdr->format_410.rts_plcp; - break; - } - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp, - len, rts_rate); - plcp = &txhdr->rts_plcp_fb; - b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)plcp, - len, rts_rate_fb); - - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - hdr = (struct ieee80211_hdr *) - (&txhdr->format_598.rts_frame); - break; - case B43_FW_HDR_351: - hdr = (struct ieee80211_hdr *) - (&txhdr->format_351.rts_frame); - break; - case B43_FW_HDR_410: - hdr = (struct ieee80211_hdr *) - (&txhdr->format_410.rts_frame); - break; - } - txhdr->rts_dur_fb = hdr->duration_id; - - if (rts_rate_ofdm) { - extra_ft |= B43_TXH_EFT_RTS_OFDM; - txhdr->phy_rate_rts = - b43_plcp_get_ratecode_ofdm(rts_rate); - } else { - extra_ft |= B43_TXH_EFT_RTS_CCK; - txhdr->phy_rate_rts = - b43_plcp_get_ratecode_cck(rts_rate); - } - if (rts_rate_fb_ofdm) - extra_ft |= B43_TXH_EFT_RTSFB_OFDM; - else - extra_ft |= B43_TXH_EFT_RTSFB_CCK; - - if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS && - fill_phy_ctl1) { - txhdr->phy_ctl1_rts = cpu_to_le16( - b43_generate_tx_phy_ctl1(dev, rts_rate)); - txhdr->phy_ctl1_rts_fb = cpu_to_le16( - b43_generate_tx_phy_ctl1(dev, rts_rate_fb)); - } - } - - /* Magic cookie */ - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - txhdr->format_598.cookie = cpu_to_le16(cookie); - break; - case B43_FW_HDR_351: - txhdr->format_351.cookie = cpu_to_le16(cookie); - break; - case B43_FW_HDR_410: - txhdr->format_410.cookie = cpu_to_le16(cookie); - break; - } - - if (fill_phy_ctl1) { - txhdr->phy_ctl1 = - cpu_to_le16(b43_generate_tx_phy_ctl1(dev, rate)); - txhdr->phy_ctl1_fb = - cpu_to_le16(b43_generate_tx_phy_ctl1(dev, rate_fb)); - } - - /* Apply the bitfields */ - txhdr->mac_ctl = cpu_to_le32(mac_ctl); - txhdr->phy_ctl = cpu_to_le16(phy_ctl); - txhdr->extra_ft = extra_ft; - - return 0; -} - -static s8 b43_rssi_postprocess(struct b43_wldev *dev, - u8 in_rssi, int ofdm, - int adjust_2053, int adjust_2050) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_g *gphy = phy->g; - s32 tmp; - - switch (phy->radio_ver) { - case 0x2050: - if (ofdm) { - tmp = in_rssi; - if (tmp > 127) - tmp -= 256; - tmp *= 73; - tmp /= 64; - if (adjust_2050) - tmp += 25; - else - tmp -= 3; - } else { - if (dev->dev->bus_sprom-> - boardflags_lo & B43_BFL_RSSI) { - if (in_rssi > 63) - in_rssi = 63; - B43_WARN_ON(phy->type != B43_PHYTYPE_G); - tmp = gphy->nrssi_lt[in_rssi]; - tmp = 31 - tmp; - tmp *= -131; - tmp /= 128; - tmp -= 57; - } else { - tmp = in_rssi; - tmp = 31 - tmp; - tmp *= -149; - tmp /= 128; - tmp -= 68; - } - if (phy->type == B43_PHYTYPE_G && adjust_2050) - tmp += 25; - } - break; - case 0x2060: - if (in_rssi > 127) - tmp = in_rssi - 256; - else - tmp = in_rssi; - break; - default: - tmp = in_rssi; - tmp -= 11; - tmp *= 103; - tmp /= 64; - if (adjust_2053) - tmp -= 109; - else - tmp -= 83; - } - - return (s8) tmp; -} - -//TODO -#if 0 -static s8 b43_rssinoise_postprocess(struct b43_wldev *dev, u8 in_rssi) -{ - struct b43_phy *phy = &dev->phy; - s8 ret; - - if (phy->type == B43_PHYTYPE_A) { - //TODO: Incomplete specs. - ret = 0; - } else - ret = b43_rssi_postprocess(dev, in_rssi, 0, 1, 1); - - return ret; -} -#endif - -void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr) -{ - struct ieee80211_rx_status status; - struct b43_plcp_hdr6 *plcp; - struct ieee80211_hdr *wlhdr; - const struct b43_rxhdr_fw4 *rxhdr = _rxhdr; - __le16 fctl; - u16 phystat0, phystat3; - u16 uninitialized_var(chanstat), uninitialized_var(mactime); - u32 uninitialized_var(macstat); - u16 chanid; - u16 phytype; - int padding, rate_idx; - - memset(&status, 0, sizeof(status)); - - /* Get metadata about the frame from the header. */ - phystat0 = le16_to_cpu(rxhdr->phy_status0); - phystat3 = le16_to_cpu(rxhdr->phy_status3); - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - macstat = le32_to_cpu(rxhdr->format_598.mac_status); - mactime = le16_to_cpu(rxhdr->format_598.mac_time); - chanstat = le16_to_cpu(rxhdr->format_598.channel); - break; - case B43_FW_HDR_410: - case B43_FW_HDR_351: - macstat = le32_to_cpu(rxhdr->format_351.mac_status); - mactime = le16_to_cpu(rxhdr->format_351.mac_time); - chanstat = le16_to_cpu(rxhdr->format_351.channel); - break; - } - phytype = chanstat & B43_RX_CHAN_PHYTYPE; - - if (unlikely(macstat & B43_RX_MAC_FCSERR)) { - dev->wl->ieee_stats.dot11FCSErrorCount++; - status.flag |= RX_FLAG_FAILED_FCS_CRC; - } - if (unlikely(phystat0 & (B43_RX_PHYST0_PLCPHCF | B43_RX_PHYST0_PLCPFV))) - status.flag |= RX_FLAG_FAILED_PLCP_CRC; - if (phystat0 & B43_RX_PHYST0_SHORTPRMBL) - status.flag |= RX_FLAG_SHORTPRE; - if (macstat & B43_RX_MAC_DECERR) { - /* Decryption with the given key failed. - * Drop the packet. We also won't be able to decrypt it with - * the key in software. */ - goto drop; - } - - /* Skip PLCP and padding */ - padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0; - if (unlikely(skb->len < (sizeof(struct b43_plcp_hdr6) + padding))) { - b43dbg(dev->wl, "RX: Packet size underrun (1)\n"); - goto drop; - } - plcp = (struct b43_plcp_hdr6 *)(skb->data + padding); - skb_pull(skb, sizeof(struct b43_plcp_hdr6) + padding); - /* The skb contains the Wireless Header + payload data now */ - if (unlikely(skb->len < (2 + 2 + 6 /*minimum hdr */ + FCS_LEN))) { - b43dbg(dev->wl, "RX: Packet size underrun (2)\n"); - goto drop; - } - wlhdr = (struct ieee80211_hdr *)(skb->data); - fctl = wlhdr->frame_control; - - if (macstat & B43_RX_MAC_DEC) { - unsigned int keyidx; - int wlhdr_len; - - keyidx = ((macstat & B43_RX_MAC_KEYIDX) - >> B43_RX_MAC_KEYIDX_SHIFT); - /* We must adjust the key index here. We want the "physical" - * key index, but the ucode passed it slightly different. - */ - keyidx = b43_kidx_to_raw(dev, keyidx); - B43_WARN_ON(keyidx >= ARRAY_SIZE(dev->key)); - - if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) { - wlhdr_len = ieee80211_hdrlen(fctl); - if (unlikely(skb->len < (wlhdr_len + 3))) { - b43dbg(dev->wl, - "RX: Packet size underrun (3)\n"); - goto drop; - } - status.flag |= RX_FLAG_DECRYPTED; - } - } - - /* Link quality statistics */ - switch (chanstat & B43_RX_CHAN_PHYTYPE) { - case B43_PHYTYPE_HT: - /* TODO: is max the right choice? */ - status.signal = max_t(__s8, - max(rxhdr->phy_ht_power0, rxhdr->phy_ht_power1), - rxhdr->phy_ht_power2); - break; - case B43_PHYTYPE_N: - /* Broadcom has code for min and avg, but always uses max */ - if (rxhdr->power0 == 16 || rxhdr->power0 == 32) - status.signal = max(rxhdr->power1, rxhdr->power2); - else - status.signal = max(rxhdr->power0, rxhdr->power1); - break; - case B43_PHYTYPE_A: - case B43_PHYTYPE_B: - case B43_PHYTYPE_G: - case B43_PHYTYPE_LP: - status.signal = b43_rssi_postprocess(dev, rxhdr->jssi, - (phystat0 & B43_RX_PHYST0_OFDM), - (phystat0 & B43_RX_PHYST0_GAINCTL), - (phystat3 & B43_RX_PHYST3_TRSTATE)); - break; - } - - if (phystat0 & B43_RX_PHYST0_OFDM) - rate_idx = b43_plcp_get_bitrate_idx_ofdm(plcp, - !!(chanstat & B43_RX_CHAN_5GHZ)); - else - rate_idx = b43_plcp_get_bitrate_idx_cck(plcp); - if (unlikely(rate_idx == -1)) { - /* PLCP seems to be corrupted. - * Drop the frame, if we are not interested in corrupted frames. */ - if (!(dev->wl->filter_flags & FIF_PLCPFAIL)) - goto drop; - } - status.rate_idx = rate_idx; - status.antenna = !!(phystat0 & B43_RX_PHYST0_ANT); - - /* - * All frames on monitor interfaces and beacons always need a full - * 64-bit timestamp. Monitor interfaces need it for diagnostic - * purposes and beacons for IBSS merging. - * This code assumes we get to process the packet within 16 bits - * of timestamp, i.e. about 65 milliseconds after the PHY received - * the first symbol. - */ - if (ieee80211_is_beacon(fctl) || dev->wl->radiotap_enabled) { - u16 low_mactime_now; - - b43_tsf_read(dev, &status.mactime); - low_mactime_now = status.mactime; - status.mactime = status.mactime & ~0xFFFFULL; - status.mactime += mactime; - if (low_mactime_now <= mactime) - status.mactime -= 0x10000; - status.flag |= RX_FLAG_MACTIME_START; - } - - chanid = (chanstat & B43_RX_CHAN_ID) >> B43_RX_CHAN_ID_SHIFT; - switch (chanstat & B43_RX_CHAN_PHYTYPE) { - case B43_PHYTYPE_A: - status.band = IEEE80211_BAND_5GHZ; - B43_WARN_ON(1); - /* FIXME: We don't really know which value the "chanid" contains. - * So the following assignment might be wrong. */ - status.freq = - ieee80211_channel_to_frequency(chanid, status.band); - break; - case B43_PHYTYPE_G: - status.band = IEEE80211_BAND_2GHZ; - /* Somewhere between 478.104 and 508.1084 firmware for G-PHY - * has been modified to be compatible with N-PHY and others. - */ - if (dev->fw.rev >= 508) - status.freq = ieee80211_channel_to_frequency(chanid, status.band); - else - status.freq = chanid + 2400; - break; - case B43_PHYTYPE_N: - case B43_PHYTYPE_LP: - case B43_PHYTYPE_HT: - /* chanid is the SHM channel cookie. Which is the plain - * channel number in b43. */ - if (chanstat & B43_RX_CHAN_5GHZ) - status.band = IEEE80211_BAND_5GHZ; - else - status.band = IEEE80211_BAND_2GHZ; - status.freq = - ieee80211_channel_to_frequency(chanid, status.band); - break; - default: - B43_WARN_ON(1); - goto drop; - } - - memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); - ieee80211_rx_ni(dev->wl->hw, skb); - -#if B43_DEBUG - dev->rx_count++; -#endif - return; -drop: - dev_kfree_skb_any(skb); -} - -void b43_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status) -{ - b43_debugfs_log_txstat(dev, status); - - if (status->intermediate) - return; - if (status->for_ampdu) - return; - if (!status->acked) - dev->wl->ieee_stats.dot11ACKFailureCount++; - if (status->rts_count) { - if (status->rts_count == 0xF) //FIXME - dev->wl->ieee_stats.dot11RTSFailureCount++; - else - dev->wl->ieee_stats.dot11RTSSuccessCount++; - } - - if (b43_using_pio_transfers(dev)) - b43_pio_handle_txstatus(dev, status); - else - b43_dma_handle_txstatus(dev, status); - - b43_phy_txpower_check(dev, 0); -} - -/* Fill out the mac80211 TXstatus report based on the b43-specific - * txstatus report data. This returns a boolean whether the frame was - * successfully transmitted. */ -bool b43_fill_txstatus_report(struct b43_wldev *dev, - struct ieee80211_tx_info *report, - const struct b43_txstatus *status) -{ - bool frame_success = true; - int retry_limit; - - /* preserve the confiured retry limit before clearing the status - * The xmit function has overwritten the rc's value with the actual - * retry limit done by the hardware */ - retry_limit = report->status.rates[0].count; - ieee80211_tx_info_clear_status(report); - - if (status->acked) { - /* The frame was ACKed. */ - report->flags |= IEEE80211_TX_STAT_ACK; - } else { - /* The frame was not ACKed... */ - if (!(report->flags & IEEE80211_TX_CTL_NO_ACK)) { - /* ...but we expected an ACK. */ - frame_success = false; - } - } - if (status->frame_count == 0) { - /* The frame was not transmitted at all. */ - report->status.rates[0].count = 0; - } else if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) { - /* - * If the short retries (RTS, not data frame) have exceeded - * the limit, the hw will not have tried the selected rate, - * but will have used the fallback rate instead. - * Don't let the rate control count attempts for the selected - * rate in this case, otherwise the statistics will be off. - */ - report->status.rates[0].count = 0; - report->status.rates[1].count = status->frame_count; - } else { - if (status->frame_count > retry_limit) { - report->status.rates[0].count = retry_limit; - report->status.rates[1].count = status->frame_count - - retry_limit; - - } else { - report->status.rates[0].count = status->frame_count; - report->status.rates[1].idx = -1; - } - } - - return frame_success; -} - -/* Stop any TX operation on the device (suspend the hardware queues) */ -void b43_tx_suspend(struct b43_wldev *dev) -{ - if (b43_using_pio_transfers(dev)) - b43_pio_tx_suspend(dev); - else - b43_dma_tx_suspend(dev); -} - -/* Resume any TX operation on the device (resume the hardware queues) */ -void b43_tx_resume(struct b43_wldev *dev) -{ - if (b43_using_pio_transfers(dev)) - b43_pio_tx_resume(dev); - else - b43_dma_tx_resume(dev); -} diff --git a/drivers/net/wireless/b43/xmit.h b/drivers/net/wireless/b43/xmit.h deleted file mode 100644 index ba6115308..000000000 --- a/drivers/net/wireless/b43/xmit.h +++ /dev/null @@ -1,416 +0,0 @@ -#ifndef B43_XMIT_H_ -#define B43_XMIT_H_ - -#include "main.h" -#include <net/mac80211.h> - - -#define _b43_declare_plcp_hdr(size) \ - struct b43_plcp_hdr##size { \ - union { \ - __le32 data; \ - __u8 raw[size]; \ - } __packed; \ - } __packed - -/* struct b43_plcp_hdr4 */ -_b43_declare_plcp_hdr(4); -/* struct b43_plcp_hdr6 */ -_b43_declare_plcp_hdr(6); - -#undef _b43_declare_plcp_hdr - -/* TX header for v4 firmware */ -struct b43_txhdr { - __le32 mac_ctl; /* MAC TX control */ - __le16 mac_frame_ctl; /* Copy of the FrameControl field */ - __le16 tx_fes_time_norm; /* TX FES Time Normal */ - __le16 phy_ctl; /* PHY TX control */ - __le16 phy_ctl1; /* PHY TX control word 1 */ - __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */ - __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */ - __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */ - __u8 phy_rate; /* PHY rate */ - __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ - __u8 extra_ft; /* Extra Frame Types */ - __u8 chan_radio_code; /* Channel Radio Code */ - __u8 iv[16]; /* Encryption IV */ - __u8 tx_receiver[6]; /* TX Frame Receiver address */ - __le16 tx_fes_time_fb; /* TX FES Time Fallback */ - struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */ - __le16 rts_dur_fb; /* RTS fallback duration */ - struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */ - __le16 dur_fb; /* Fallback duration */ - __le16 mimo_modelen; /* MIMO mode length */ - __le16 mimo_ratelen_fb; /* MIMO fallback rate length */ - __le32 timeout; /* Timeout */ - - union { - /* Tested with 598.314, 644.1001 and 666.2 */ - struct { - __le16 mimo_antenna; /* MIMO antenna select */ - __le16 preload_size; /* Preload size */ - PAD_BYTES(2); - __le16 cookie; /* TX frame cookie */ - __le16 tx_status; /* TX status */ - __le16 max_n_mpdus; - __le16 max_a_bytes_mrt; - __le16 max_a_bytes_fbr; - __le16 min_m_bytes; - struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ - __u8 rts_frame[16]; /* The RTS frame (if used) */ - PAD_BYTES(2); - struct b43_plcp_hdr6 plcp; /* Main PLCP header */ - } format_598 __packed; - - /* Tested with 410.2160, 478.104 and 508.* */ - struct { - __le16 mimo_antenna; /* MIMO antenna select */ - __le16 preload_size; /* Preload size */ - PAD_BYTES(2); - __le16 cookie; /* TX frame cookie */ - __le16 tx_status; /* TX status */ - struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ - __u8 rts_frame[16]; /* The RTS frame (if used) */ - PAD_BYTES(2); - struct b43_plcp_hdr6 plcp; /* Main PLCP header */ - } format_410 __packed; - - /* Tested with 351.126 */ - struct { - PAD_BYTES(2); - __le16 cookie; /* TX frame cookie */ - __le16 tx_status; /* TX status */ - struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ - __u8 rts_frame[16]; /* The RTS frame (if used) */ - PAD_BYTES(2); - struct b43_plcp_hdr6 plcp; /* Main PLCP header */ - } format_351 __packed; - - } __packed; -} __packed; - -struct b43_tx_legacy_rate_phy_ctl_entry { - u8 bitrate; - u16 coding_rate; - u16 modulation; -}; - -/* MAC TX control */ -#define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */ -#define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */ -#define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */ -#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */ -#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */ -#define B43_TXH_MAC_KEYIDX_SHIFT 20 -#define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ -#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */ -#define B43_TXH_MAC_KEYALG_SHIFT 16 -#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */ -#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */ -#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */ -#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */ -#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */ -#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */ -#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */ -#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */ -#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */ -#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */ -#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */ -#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */ -#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */ -#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */ -#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ -#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */ -#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */ -#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */ -#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */ - -/* Extra Frame Types */ -#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */ -#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */ -#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */ -#define B43_TXH_EFT_FB_HT 0x02 /* HT */ -#define B43_TXH_EFT_FB_VHT 0x03 /* VHT */ -#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */ -#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */ -#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */ -#define B43_TXH_EFT_RTS_HT 0x08 /* HT */ -#define B43_TXH_EFT_RTS_VHT 0x0C /* VHT */ -#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */ -#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */ -#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */ -#define B43_TXH_EFT_RTSFB_HT 0x20 /* HT */ -#define B43_TXH_EFT_RTSFB_VHT 0x30 /* VHT */ - -/* PHY TX control word */ -#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */ -#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */ -#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */ -#define B43_TXH_PHY_ENC_HT 0x0002 /* HT */ -#define B43_TXH_PHY_ENC_VHT 0x0003 /* VHT */ -#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ -#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */ -#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */ -#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */ -#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */ -#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */ -#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */ -#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */ -#define B43_TXH_PHY_TXPWR_SHIFT 10 - -/* PHY TX control word 1 */ -#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */ -#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ -#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ -#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ -#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ -#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ -#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */ -#define B43_TXH_PHY1_MODE 0x0038 /* Mode */ -#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ -#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ -#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ -#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ -#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */ -#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ -#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ -#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ -#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ -#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ -#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ -#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ -#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ -#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ -#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ -#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ -#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ - - -static inline -size_t b43_txhdr_size(struct b43_wldev *dev) -{ - switch (dev->fw.hdr_format) { - case B43_FW_HDR_598: - return 112 + sizeof(struct b43_plcp_hdr6); - case B43_FW_HDR_410: - return 104 + sizeof(struct b43_plcp_hdr6); - case B43_FW_HDR_351: - return 100 + sizeof(struct b43_plcp_hdr6); - } - return 0; -} - - -int b43_generate_txhdr(struct b43_wldev *dev, - u8 * txhdr, - struct sk_buff *skb_frag, - struct ieee80211_tx_info *txctl, u16 cookie); - -/* Transmit Status */ -struct b43_txstatus { - u16 cookie; /* The cookie from the txhdr */ - u16 seq; /* Sequence number */ - u8 phy_stat; /* PHY TX status */ - u8 frame_count; /* Frame transmit count */ - u8 rts_count; /* RTS transmit count */ - u8 supp_reason; /* Suppression reason */ - /* flags */ - u8 pm_indicated; /* PM mode indicated to AP */ - u8 intermediate; /* Intermediate status notification (not final) */ - u8 for_ampdu; /* Status is for an AMPDU (afterburner) */ - u8 acked; /* Wireless ACK received */ -}; - -/* txstatus supp_reason values */ -enum { - B43_TXST_SUPP_NONE, /* Not suppressed */ - B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */ - B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */ - B43_TXST_SUPP_PREV, /* Previous fragment failed */ - B43_TXST_SUPP_CHAN, /* Channel mismatch */ - B43_TXST_SUPP_LIFE, /* Lifetime expired */ - B43_TXST_SUPP_UNDER, /* Buffer underflow */ - B43_TXST_SUPP_ABNACK, /* Afterburner NACK */ -}; - -/* Receive header for v4 firmware. */ -struct b43_rxhdr_fw4 { - __le16 frame_len; /* Frame length */ - PAD_BYTES(2); - __le16 phy_status0; /* PHY RX Status 0 */ - union { - /* RSSI for A/B/G-PHYs */ - struct { - __u8 jssi; /* PHY RX Status 1: JSSI */ - __u8 sig_qual; /* PHY RX Status 1: Signal Quality */ - } __packed; - - /* RSSI for N-PHYs */ - struct { - __s8 power0; /* PHY RX Status 1: Power 0 */ - __s8 power1; /* PHY RX Status 1: Power 1 */ - } __packed; - } __packed; - union { - /* HT-PHY */ - struct { - PAD_BYTES(1); - __s8 phy_ht_power0; - } __packed; - - /* RSSI for N-PHYs */ - struct { - __s8 power2; - PAD_BYTES(1); - } __packed; - - __le16 phy_status2; /* PHY RX Status 2 */ - } __packed; - union { - /* HT-PHY */ - struct { - __s8 phy_ht_power1; - __s8 phy_ht_power2; - } __packed; - - __le16 phy_status3; /* PHY RX Status 3 */ - } __packed; - union { - /* Tested with 598.314, 644.1001 and 666.2 */ - struct { - __le16 phy_status4; /* PHY RX Status 4 */ - __le16 phy_status5; /* PHY RX Status 5 */ - __le32 mac_status; /* MAC RX status */ - __le16 mac_time; - __le16 channel; - } format_598 __packed; - - /* Tested with 351.126, 410.2160, 478.104 and 508.* */ - struct { - __le32 mac_status; /* MAC RX status */ - __le16 mac_time; - __le16 channel; - } format_351 __packed; - } __packed; -} __packed; - -/* PHY RX Status 0 */ -#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */ -#define B43_RX_PHYST0_PLCPHCF 0x0200 -#define B43_RX_PHYST0_PLCPFV 0x0100 -#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */ -#define B43_RX_PHYST0_LCRS 0x0040 -#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */ -#define B43_RX_PHYST0_UNSRATE 0x0010 -#define B43_RX_PHYST0_CLIP 0x000C -#define B43_RX_PHYST0_CLIP_SHIFT 2 -#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */ -#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */ -#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */ -#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */ -#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */ - -/* PHY RX Status 2 */ -#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */ -#define B43_RX_PHYST2_LNAG_SHIFT 14 -#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */ -#define B43_RX_PHYST2_PNAG_SHIFT 10 -#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */ - -/* PHY RX Status 3 */ -#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */ -#define B43_RX_PHYST3_DIGG_SHIFT 11 -#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */ - -/* MAC RX Status */ -#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */ -#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */ -#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */ -#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */ -#define B43_RX_MAC_AGGTYPE_SHIFT 17 -#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */ -#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */ -#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */ -#define B43_RX_MAC_KEYIDX_SHIFT 5 -#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */ -#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */ -#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */ -#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */ -#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */ - -/* RX channel */ -#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */ -#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */ -#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */ -#define B43_RX_CHAN_ID_SHIFT 3 -#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */ - - -u8 b43_plcp_get_ratecode_cck(const u8 bitrate); -u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); - -void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, - const u16 octets, const u8 bitrate); - -void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); - -void b43_handle_txstatus(struct b43_wldev *dev, - const struct b43_txstatus *status); -bool b43_fill_txstatus_report(struct b43_wldev *dev, - struct ieee80211_tx_info *report, - const struct b43_txstatus *status); - -void b43_tx_suspend(struct b43_wldev *dev); -void b43_tx_resume(struct b43_wldev *dev); - - -/* Helper functions for converting the key-table index from "firmware-format" - * to "raw-format" and back. The firmware API changed for this at some revision. - * We need to account for that here. */ -static inline int b43_new_kidx_api(struct b43_wldev *dev) -{ - /* FIXME: Not sure the change was at rev 351 */ - return (dev->fw.rev >= 351); -} -static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) -{ - u8 firmware_kidx; - if (b43_new_kidx_api(dev)) { - firmware_kidx = raw_kidx; - } else { - if (raw_kidx >= 4) /* Is per STA key? */ - firmware_kidx = raw_kidx - 4; - else - firmware_kidx = raw_kidx; /* TX default key */ - } - return firmware_kidx; -} -static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) -{ - u8 raw_kidx; - if (b43_new_kidx_api(dev)) - raw_kidx = firmware_kidx; - else - raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */ - return raw_kidx; -} - -/* struct b43_private_tx_info - TX info private to b43. - * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data - * - * @bouncebuffer: DMA Bouncebuffer (if used) - */ -struct b43_private_tx_info { - void *bouncebuffer; -}; - -static inline struct b43_private_tx_info * -b43_get_priv_tx_info(struct ieee80211_tx_info *info) -{ - BUILD_BUG_ON(sizeof(struct b43_private_tx_info) > - sizeof(info->rate_driver_data)); - return (struct b43_private_tx_info *)info->rate_driver_data; -} - -#endif /* B43_XMIT_H_ */ |