diff options
| author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-10-20 00:10:27 -0300 |
|---|---|---|
| committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2016-10-20 00:10:27 -0300 |
| commit | d0b2f91bede3bd5e3d24dd6803e56eee959c1797 (patch) | |
| tree | 7fee4ab0509879c373c4f2cbd5b8a5be5b4041ee /drivers/staging/comedi/drivers | |
| parent | e914f8eb445e8f74b00303c19c2ffceaedd16a05 (diff) | |
Linux-libre 4.8.2-gnupck-4.8.2-gnu
Diffstat (limited to 'drivers/staging/comedi/drivers')
31 files changed, 2598 insertions, 1883 deletions
diff --git a/drivers/staging/comedi/drivers/addi_apci_1564.c b/drivers/staging/comedi/drivers/addi_apci_1564.c index f1ccfbd4c..9bfb79c2e 100644 --- a/drivers/staging/comedi/drivers/addi_apci_1564.c +++ b/drivers/staging/comedi/drivers/addi_apci_1564.c @@ -21,9 +21,62 @@ * details. */ +/* + * Driver: addi_apci_1564 + * Description: ADDI-DATA APCI-1564 Digital I/O board + * Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564) + * Author: H Hartley Sweeten <hsweeten@visionengravers.com> + * Updated: Thu, 02 Jun 2016 13:12:46 -0700 + * Status: untested + * + * Configuration Options: not applicable, uses comedi PCI auto config + * + * This board has the following features: + * - 32 optically isolated digital inputs (24V), 16 of which can + * generate change-of-state (COS) interrupts (channels 4 to 19) + * - 32 optically isolated digital outputs (10V to 36V) + * - 1 8-bit watchdog for resetting the outputs + * - 1 12-bit timer + * - 3 32-bit counters + * - 2 diagnostic inputs + * + * The COS, timer, and counter subdevices all use the dev->read_subdev to + * return the interrupt status. The sample data is updated and returned when + * any of these subdevices generate an interrupt. The sample data format is: + * + * Bit Description + * ----- ------------------------------------------ + * 31 COS interrupt + * 30 timer interrupt + * 29 counter 2 interrupt + * 28 counter 1 interrupt + * 27 counter 0 interrupt + * 26:20 not used + * 19:4 COS digital input state (channels 19 to 4) + * 3:0 not used + * + * The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG + * instruction before they can be enabled by an async command. The COS + * interrupts will stay active until canceled. + * + * The timer subdevice does not use an async command. All control is handled + * by the (*insn_config). + * + * FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the + * datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes + * the raw data[1] to this register along with the raw data[2] value to the + * ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual + * timebase/reload operation please let me know. + * + * The counter subdevice also does not use an async command. All control is + * handled by the (*insn_config). + * + * FIXME: The operation of the counters is not really described in the + * datasheet I have. The (*insn_config) needs more work. + */ + #include <linux/module.h> #include <linux/interrupt.h> -#include <linux/sched.h> #include "../comedi_pci.h" #include "addi_tcw.h" @@ -77,6 +130,7 @@ #define APCI1564_DI_REG 0x00 #define APCI1564_DI_INT_MODE1_REG 0x04 #define APCI1564_DI_INT_MODE2_REG 0x08 +#define APCI1564_DI_INT_MODE_MASK 0x000ffff0 /* chans [19:4] */ #define APCI1564_DI_INT_STATUS_REG 0x0c #define APCI1564_DI_IRQ_REG 0x10 #define APCI1564_DI_IRQ_ENA BIT(2) @@ -90,14 +144,7 @@ #define APCI1564_DO_INT_STATUS_VCC BIT(0) #define APCI1564_DO_IRQ_REG 0x20 #define APCI1564_DO_IRQ_INTR BIT(0) -#define APCI1564_WDOG_REG 0x24 -#define APCI1564_WDOG_RELOAD_REG 0x28 -#define APCI1564_WDOG_TIMEBASE_REG 0x2c -#define APCI1564_WDOG_CTRL_REG 0x30 -#define APCI1564_WDOG_STATUS_REG 0x34 -#define APCI1564_WDOG_IRQ_REG 0x38 -#define APCI1564_WDOG_WARN_TIMEVAL_REG 0x3c -#define APCI1564_WDOG_WARN_TIMEBASE_REG 0x40 +#define APCI1564_WDOG_IOBASE 0x24 /* * devpriv->timer Register Map (see addi_tcw.h for register/bit defines) @@ -111,18 +158,24 @@ */ #define APCI1564_COUNTER(x) ((x) * 0x20) +/* + * The dev->read_subdev is used to return the interrupt events along with + * the state of the interrupt capable inputs. + */ +#define APCI1564_EVENT_COS BIT(31) +#define APCI1564_EVENT_TIMER BIT(30) +#define APCI1564_EVENT_COUNTER(x) BIT(27 + (x)) /* counter 0-2 */ +#define APCI1564_EVENT_MASK 0xfff0000f /* all but [19:4] */ + struct apci1564_private { unsigned long eeprom; /* base address of EEPROM register */ unsigned long timer; /* base address of 12-bit timer */ unsigned long counters; /* base address of 32-bit counters */ - unsigned int mode1; /* riding-edge/high level channels */ + unsigned int mode1; /* rising-edge/high level channels */ unsigned int mode2; /* falling-edge/low level channels */ unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */ - struct task_struct *tsk_current; }; -#include "addi-data/hwdrv_apci1564.c" - static int apci1564_reset(struct comedi_device *dev) { struct apci1564_private *devpriv = dev->private; @@ -138,7 +191,7 @@ static int apci1564_reset(struct comedi_device *dev) outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG); /* Reset the watchdog registers */ - addi_watchdog_reset(dev->iobase + APCI1564_WDOG_REG); + addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE); /* Reset the timer registers */ outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG); @@ -165,55 +218,54 @@ static irqreturn_t apci1564_interrupt(int irq, void *d) unsigned int ctrl; unsigned int chan; + s->state &= ~APCI1564_EVENT_MASK; + status = inl(dev->iobase + APCI1564_DI_IRQ_REG); if (status & APCI1564_DI_IRQ_ENA) { - /* disable the interrupt */ + /* get the COS interrupt state and set the event flag */ + s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG); + s->state &= APCI1564_DI_INT_MODE_MASK; + s->state |= APCI1564_EVENT_COS; + + /* clear the interrupt */ outl(status & ~APCI1564_DI_IRQ_ENA, dev->iobase + APCI1564_DI_IRQ_REG); - - s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG) & - 0xffff; - comedi_buf_write_samples(s, &s->state, 1); - comedi_handle_events(dev, s); - - /* enable the interrupt */ outl(status, dev->iobase + APCI1564_DI_IRQ_REG); } status = inl(devpriv->timer + ADDI_TCW_IRQ_REG); - if (status & 0x01) { - /* Disable Timer Interrupt */ + if (status & ADDI_TCW_IRQ) { + s->state |= APCI1564_EVENT_TIMER; + + /* clear the interrupt */ ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG); - - /* Send a signal to from kernel to user space */ - send_sig(SIGIO, devpriv->tsk_current, 0); - - /* Enable Timer Interrupt */ outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); } if (devpriv->counters) { - for (chan = 0; chan < 4; chan++) { + for (chan = 0; chan < 3; chan++) { unsigned long iobase; iobase = devpriv->counters + APCI1564_COUNTER(chan); status = inl(iobase + ADDI_TCW_IRQ_REG); - if (status & 0x01) { - /* Disable Counter Interrupt */ + if (status & ADDI_TCW_IRQ) { + s->state |= APCI1564_EVENT_COUNTER(chan); + + /* clear the interrupt */ ctrl = inl(iobase + ADDI_TCW_CTRL_REG); outl(0x0, iobase + ADDI_TCW_CTRL_REG); - - /* Send a signal to from kernel to user space */ - send_sig(SIGIO, devpriv->tsk_current, 0); - - /* Enable Counter Interrupt */ outl(ctrl, iobase + ADDI_TCW_CTRL_REG); } } } + if (s->state & APCI1564_EVENT_MASK) { + comedi_buf_write_samples(s, &s->state, 1); + comedi_handle_events(dev, s); + } + return IRQ_HANDLED; } @@ -255,7 +307,7 @@ static int apci1564_diag_insn_bits(struct comedi_device *dev, /* * Change-Of-State (COS) interrupt configuration * - * Channels 0 to 15 are interruptible. These channels can be configured + * Channels 4 to 19 are interruptible. These channels can be configured * to generate interrupts based on AND/OR logic for the desired channels. * * OR logic @@ -343,6 +395,10 @@ static int apci1564_cos_insn_config(struct comedi_device *dev, default: return -EINVAL; } + + /* ensure the mode bits are in-range for channels [19:4] */ + devpriv->mode1 &= APCI1564_DI_INT_MODE_MASK; + devpriv->mode2 &= APCI1564_DI_INT_MODE_MASK; break; default: return -EINVAL; @@ -409,7 +465,7 @@ static int apci1564_cos_cmd(struct comedi_device *dev, { struct apci1564_private *devpriv = dev->private; - if (!devpriv->ctrl) { + if (!devpriv->ctrl && !(devpriv->mode1 || devpriv->mode2)) { dev_warn(dev->class_dev, "Interrupts disabled due to mode configuration!\n"); return -EINVAL; @@ -433,6 +489,173 @@ static int apci1564_cos_cancel(struct comedi_device *dev, return 0; } +static int apci1564_timer_insn_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + unsigned int val; + + switch (data[0]) { + case INSN_CONFIG_ARM: + if (data[1] > s->maxdata) + return -EINVAL; + outl(data[1], devpriv->timer + ADDI_TCW_RELOAD_REG); + outl(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_TIMER_ENA, + devpriv->timer + ADDI_TCW_CTRL_REG); + break; + case INSN_CONFIG_DISARM: + outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG); + break; + case INSN_CONFIG_GET_COUNTER_STATUS: + data[1] = 0; + val = inl(devpriv->timer + ADDI_TCW_CTRL_REG); + if (val & ADDI_TCW_CTRL_IRQ_ENA) + data[1] |= COMEDI_COUNTER_ARMED; + if (val & ADDI_TCW_CTRL_TIMER_ENA) + data[1] |= COMEDI_COUNTER_COUNTING; + val = inl(devpriv->timer + ADDI_TCW_STATUS_REG); + if (val & ADDI_TCW_STATUS_OVERFLOW) + data[1] |= COMEDI_COUNTER_TERMINAL_COUNT; + data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING | + COMEDI_COUNTER_TERMINAL_COUNT; + break; + case INSN_CONFIG_SET_CLOCK_SRC: + if (data[2] > s->maxdata) + return -EINVAL; + outl(data[1], devpriv->timer + ADDI_TCW_TIMEBASE_REG); + outl(data[2], devpriv->timer + ADDI_TCW_RELOAD_REG); + break; + case INSN_CONFIG_GET_CLOCK_SRC: + data[1] = inl(devpriv->timer + ADDI_TCW_TIMEBASE_REG); + data[2] = inl(devpriv->timer + ADDI_TCW_RELOAD_REG); + break; + default: + return -EINVAL; + } + + return insn->n; +} + +static int apci1564_timer_insn_write(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + + /* just write the last last to the reload register */ + if (insn->n) { + unsigned int val = data[insn->n - 1]; + + outl(val, devpriv->timer + ADDI_TCW_RELOAD_REG); + } + + return insn->n; +} + +static int apci1564_timer_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + int i; + + /* return the actual value of the timer */ + for (i = 0; i < insn->n; i++) + data[i] = inl(devpriv->timer + ADDI_TCW_VAL_REG); + + return insn->n; +} + +static int apci1564_counter_insn_config(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); + unsigned int val; + + switch (data[0]) { + case INSN_CONFIG_ARM: + val = inl(iobase + ADDI_TCW_CTRL_REG); + val |= ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA; + outl(data[1], iobase + ADDI_TCW_RELOAD_REG); + outl(val, iobase + ADDI_TCW_CTRL_REG); + break; + case INSN_CONFIG_DISARM: + val = inl(iobase + ADDI_TCW_CTRL_REG); + val &= ~(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA); + outl(val, iobase + ADDI_TCW_CTRL_REG); + break; + case INSN_CONFIG_SET_COUNTER_MODE: + /* + * FIXME: The counter operation is not described in the + * datasheet. For now just write the raw data[1] value to + * the control register. + */ + outl(data[1], iobase + ADDI_TCW_CTRL_REG); + break; + case INSN_CONFIG_GET_COUNTER_STATUS: + data[1] = 0; + val = inl(iobase + ADDI_TCW_CTRL_REG); + if (val & ADDI_TCW_CTRL_IRQ_ENA) + data[1] |= COMEDI_COUNTER_ARMED; + if (val & ADDI_TCW_CTRL_CNTR_ENA) + data[1] |= COMEDI_COUNTER_COUNTING; + val = inl(iobase + ADDI_TCW_STATUS_REG); + if (val & ADDI_TCW_STATUS_OVERFLOW) + data[1] |= COMEDI_COUNTER_TERMINAL_COUNT; + data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING | + COMEDI_COUNTER_TERMINAL_COUNT; + break; + default: + return -EINVAL; + } + + return insn->n; +} + +static int apci1564_counter_insn_write(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); + + /* just write the last last to the reload register */ + if (insn->n) { + unsigned int val = data[insn->n - 1]; + + outl(val, iobase + ADDI_TCW_RELOAD_REG); + } + + return insn->n; +} + +static int apci1564_counter_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) +{ + struct apci1564_private *devpriv = dev->private; + unsigned int chan = CR_CHAN(insn->chanspec); + unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan); + int i; + + /* return the actual value of the counter */ + for (i = 0; i < insn->n; i++) + data[i] = inl(iobase + ADDI_TCW_VAL_REG); + + return insn->n; +} + static int apci1564_auto_attach(struct comedi_device *dev, unsigned long context_unused) { @@ -501,7 +724,7 @@ static int apci1564_auto_attach(struct comedi_device *dev, if (dev->irq) { dev->read_subdev = s; s->type = COMEDI_SUBD_DI; - s->subdev_flags = SDF_READABLE | SDF_CMD_READ; + s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_LSAMPL; s->n_chan = 1; s->maxdata = 1; s->range_table = &range_digital; @@ -543,7 +766,7 @@ static int apci1564_auto_attach(struct comedi_device *dev, /* Initialize the watchdog subdevice */ s = &dev->subdevices[5]; - ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_REG); + ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_IOBASE); if (ret) return ret; diff --git a/drivers/staging/comedi/drivers/adl_pci9118.c b/drivers/staging/comedi/drivers/adl_pci9118.c index 4437ea3ab..be70bd333 100644 --- a/drivers/staging/comedi/drivers/adl_pci9118.c +++ b/drivers/staging/comedi/drivers/adl_pci9118.c @@ -570,7 +570,7 @@ static int pci9118_ai_cancel(struct comedi_device *dev, /* set default config (disable burst and triggers) */ devpriv->ai_cfg = PCI9118_AI_CFG_PDTRG | PCI9118_AI_CFG_PETRG; outl(devpriv->ai_cfg, dev->iobase + PCI9118_AI_CFG_REG); - /* reset acqusition control */ + /* reset acquisition control */ devpriv->ai_ctrl = 0; outl(devpriv->ai_ctrl, dev->iobase + PCI9118_AI_CTRL_REG); outl(0, dev->iobase + PCI9118_AI_BURST_NUM_REG); @@ -1022,12 +1022,12 @@ static int pci9118_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* * Configure analog input and load the chanlist. - * The acqusition control bits are enabled later. + * The acquisition control bits are enabled later. */ pci9118_set_chanlist(dev, s, cmd->chanlist_len, cmd->chanlist, devpriv->ai_add_front, devpriv->ai_add_back); - /* Determine acqusition mode and calculate timing */ + /* Determine acquisition mode and calculate timing */ devpriv->ai_do = 0; if (cmd->scan_begin_src != TRIG_TIMER && cmd->convert_src == TRIG_TIMER) { @@ -1097,7 +1097,7 @@ static int pci9118_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) if (devpriv->ai_do == 0) { dev_err(dev->class_dev, - "Unable to determine acqusition mode! BUG in (*do_cmdtest)?\n"); + "Unable to determine acquisition mode! BUG in (*do_cmdtest)?\n"); return -EINVAL; } diff --git a/drivers/staging/comedi/drivers/adv_pci1760.c b/drivers/staging/comedi/drivers/adv_pci1760.c index d7dd1e55e..9f525ff72 100644 --- a/drivers/staging/comedi/drivers/adv_pci1760.c +++ b/drivers/staging/comedi/drivers/adv_pci1760.c @@ -196,6 +196,7 @@ static int pci1760_pwm_ns_to_div(unsigned int flags, unsigned int ns) break; case CMDF_ROUND_DOWN: divisor = ns / PCI1760_PWM_TIMEBASE; + break; default: return -EINVAL; } diff --git a/drivers/staging/comedi/drivers/cb_pcidas64.c b/drivers/staging/comedi/drivers/cb_pcidas64.c index c773b8ca6..1f9c08a84 100644 --- a/drivers/staging/comedi/drivers/cb_pcidas64.c +++ b/drivers/staging/comedi/drivers/cb_pcidas64.c @@ -1238,7 +1238,7 @@ static void disable_plx_interrupts(struct comedi_device *dev) devpriv->plx_intcsr_bits = 0; writel(devpriv->plx_intcsr_bits, - devpriv->plx9080_iobase + PLX_INTRCS_REG); + devpriv->plx9080_iobase + PLX_REG_INTCSR); } static void disable_ai_interrupts(struct comedi_device *dev) @@ -1291,14 +1291,14 @@ static void init_plx9080(struct comedi_device *dev) void __iomem *plx_iobase = devpriv->plx9080_iobase; devpriv->plx_control_bits = - readl(devpriv->plx9080_iobase + PLX_CONTROL_REG); + readl(devpriv->plx9080_iobase + PLX_REG_CNTRL); #ifdef __BIG_ENDIAN - bits = BIGEND_DMA0 | BIGEND_DMA1; + bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1; #else bits = 0; #endif - writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG); + writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND); disable_plx_interrupts(dev); @@ -1308,38 +1308,39 @@ static void init_plx9080(struct comedi_device *dev) /* configure dma0 mode */ bits = 0; /* enable ready input, not sure if this is necessary */ - bits |= PLX_DMA_EN_READYIN_BIT; + bits |= PLX_DMAMODE_READYIEN; /* enable bterm, not sure if this is necessary */ - bits |= PLX_EN_BTERM_BIT; + bits |= PLX_DMAMODE_BTERMIEN; /* enable dma chaining */ - bits |= PLX_EN_CHAIN_BIT; + bits |= PLX_DMAMODE_CHAINEN; /* enable interrupt on dma done * (probably don't need this, since chain never finishes) */ - bits |= PLX_EN_DMA_DONE_INTR_BIT; + bits |= PLX_DMAMODE_DONEIEN; /* don't increment local address during transfers * (we are transferring from a fixed fifo register) */ - bits |= PLX_LOCAL_ADDR_CONST_BIT; + bits |= PLX_DMAMODE_LACONST; /* route dma interrupt to pci bus */ - bits |= PLX_DMA_INTR_PCI_BIT; + bits |= PLX_DMAMODE_INTRPCI; /* enable demand mode */ - bits |= PLX_DEMAND_MODE_BIT; + bits |= PLX_DMAMODE_DEMAND; /* enable local burst mode */ - bits |= PLX_DMA_LOCAL_BURST_EN_BIT; + bits |= PLX_DMAMODE_BURSTEN; /* 4020 uses 32 bit dma */ if (board->layout == LAYOUT_4020) - bits |= PLX_LOCAL_BUS_32_WIDE_BITS; + bits |= PLX_DMAMODE_WIDTH32; else /* localspace0 bus is 16 bits wide */ - bits |= PLX_LOCAL_BUS_16_WIDE_BITS; - writel(bits, plx_iobase + PLX_DMA1_MODE_REG); + bits |= PLX_DMAMODE_WIDTH16; + writel(bits, plx_iobase + PLX_REG_DMAMODE1); if (ao_cmd_is_supported(board)) - writel(bits, plx_iobase + PLX_DMA0_MODE_REG); + writel(bits, plx_iobase + PLX_REG_DMAMODE0); /* enable interrupts on plx 9080 */ devpriv->plx_intcsr_bits |= - ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | - ICS_DMA0_E | ICS_DMA1_E; + PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN | + PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN | + PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN; writel(devpriv->plx_intcsr_bits, - devpriv->plx9080_iobase + PLX_INTRCS_REG); + devpriv->plx9080_iobase + PLX_REG_INTCSR); } static void disable_ai_pacing(struct comedi_device *dev) @@ -1533,8 +1534,8 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) cpu_to_le32((devpriv->ai_dma_desc_bus_addr + ((i + 1) % ai_dma_ring_count(board)) * sizeof(devpriv->ai_dma_desc[0])) | - PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | - PLX_XFER_LOCAL_TO_PCI); + PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR | + PLX_DMADPR_XFERL2P); } if (ao_cmd_is_supported(board)) { for (i = 0; i < AO_DMA_RING_COUNT; i++) { @@ -1548,8 +1549,8 @@ static int alloc_and_init_dma_members(struct comedi_device *dev) cpu_to_le32((devpriv->ao_dma_desc_bus_addr + ((i + 1) % (AO_DMA_RING_COUNT)) * sizeof(devpriv->ao_dma_desc[0])) | - PLX_DESC_IN_PCI_BIT | - PLX_INTR_TERM_COUNT); + PLX_DMADPR_DESCPCI | + PLX_DMADPR_TCINTR); } } return 0; @@ -1613,9 +1614,9 @@ static const int i2c_low_udelay = 10; static void i2c_set_sda(struct comedi_device *dev, int state) { struct pcidas64_private *devpriv = dev->private; - static const int data_bit = CTL_EE_W; + static const int data_bit = PLX_CNTRL_EEWB; void __iomem *plx_control_addr = devpriv->plx9080_iobase + - PLX_CONTROL_REG; + PLX_REG_CNTRL; if (state) { /* set data line high */ @@ -1634,9 +1635,9 @@ static void i2c_set_sda(struct comedi_device *dev, int state) static void i2c_set_scl(struct comedi_device *dev, int state) { struct pcidas64_private *devpriv = dev->private; - static const int clock_bit = CTL_USERO; + static const int clock_bit = PLX_CNTRL_USERO; void __iomem *plx_control_addr = devpriv->plx9080_iobase + - PLX_CONTROL_REG; + PLX_REG_CNTRL; if (state) { /* set clock line high */ @@ -1707,7 +1708,7 @@ static void i2c_write(struct comedi_device *dev, unsigned int address, */ /* make sure we dont send anything to eeprom */ - devpriv->plx_control_bits &= ~CTL_EE_CS; + devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; i2c_stop(dev); i2c_start(dev); @@ -2367,14 +2368,8 @@ static inline void dma_start_sync(struct comedi_device *dev, /* spinlock for plx dma control/status reg */ spin_lock_irqsave(&dev->spinlock, flags); - if (channel) - writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | - PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_iobase + PLX_DMA1_CS_REG); - else - writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | - PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_iobase + PLX_DMA0_CS_REG); + writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_iobase + PLX_REG_DMACSR(channel)); spin_unlock_irqrestore(&dev->spinlock, flags); } @@ -2552,21 +2547,17 @@ static inline void load_first_dma_descriptor(struct comedi_device *dev, * block. Initializing them to zero seems to fix the problem. */ if (dma_channel) { - writel(0, - devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG); - writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG); - writel(0, - devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1); writel(descriptor_bits, - devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG); + devpriv->plx9080_iobase + PLX_REG_DMADPR1); } else { - writel(0, - devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG); - writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); - writel(0, - devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0); + writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0); writel(descriptor_bits, - devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); + devpriv->plx9080_iobase + PLX_REG_DMADPR0); } } @@ -2643,9 +2634,9 @@ static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) /* give location of first dma descriptor */ load_first_dma_descriptor(dev, 1, devpriv->ai_dma_desc_bus_addr | - PLX_DESC_IN_PCI_BIT | - PLX_INTR_TERM_COUNT | - PLX_XFER_LOCAL_TO_PCI); + PLX_DMADPR_DESCPCI | + PLX_DMADPR_TCINTR | + PLX_DMADPR_XFERL2P); dma_start_sync(dev, 1); } @@ -2803,12 +2794,7 @@ static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel) int num_samples = 0; void __iomem *pci_addr_reg; - if (channel) - pci_addr_reg = - devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG; - else - pci_addr_reg = - devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; + pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel); /* loop until we have read all the full buffers */ for (j = 0, next_transfer_addr = readl(pci_addr_reg); @@ -2850,12 +2836,12 @@ static void handle_ai_interrupt(struct comedi_device *dev, } /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); - dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG); - if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */ - writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_iobase + PLX_DMA1_CS_REG); + dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1); + if (plx_status & PLX_INTCSR_DMA1IA) { /* dma chan 1 interrupt */ + writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_iobase + PLX_REG_DMACSR1); - if (dma1_status & PLX_DMA_EN_BIT) + if (dma1_status & PLX_DMACSR_ENABLE) drain_dma_buffers(dev, 1); } spin_unlock_irqrestore(&dev->spinlock, flags); @@ -2902,12 +2888,12 @@ static int last_ao_dma_load_completed(struct comedi_device *dev) unsigned short dma_status; buffer_index = prev_ao_dma_index(dev); - dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG); - if ((dma_status & PLX_DMA_DONE_BIT) == 0) + dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0); + if ((dma_status & PLX_DMACSR_DONE) == 0) return 0; transfer_address = - readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG); + readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0); if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index]) return 0; @@ -2917,8 +2903,8 @@ static int last_ao_dma_load_completed(struct comedi_device *dev) static inline int ao_dma_needs_restart(struct comedi_device *dev, unsigned short dma_status) { - if ((dma_status & PLX_DMA_DONE_BIT) == 0 || - (dma_status & PLX_DMA_EN_BIT) == 0) + if ((dma_status & PLX_DMACSR_DONE) == 0 || + (dma_status & PLX_DMACSR_ENABLE) == 0) return 0; if (last_ao_dma_load_completed(dev)) return 0; @@ -2931,9 +2917,8 @@ static void restart_ao_dma(struct comedi_device *dev) struct pcidas64_private *devpriv = dev->private; unsigned int dma_desc_bits; - dma_desc_bits = - readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG); - dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT; + dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0); + dma_desc_bits &= ~PLX_DMADPR_CHAINEND; load_first_dma_descriptor(dev, 0, dma_desc_bits); dma_start_sync(dev, 0); @@ -2974,14 +2959,14 @@ static unsigned int load_ao_dma_buffer(struct comedi_device *dev, devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes); /* set end of chain bit so we catch underruns */ next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next); - next_bits |= PLX_END_OF_CHAIN_BIT; + next_bits |= PLX_DMADPR_CHAINEND; devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits); /* * clear end of chain bit on previous buffer now that we have set it * for the last buffer */ next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next); - next_bits &= ~PLX_END_OF_CHAIN_BIT; + next_bits &= ~PLX_DMADPR_CHAINEND; devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits); devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT; @@ -2994,8 +2979,7 @@ static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd) struct pcidas64_private *devpriv = dev->private; unsigned int num_bytes; unsigned int next_transfer_addr; - void __iomem *pci_addr_reg = - devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG; + void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0; unsigned int buffer_index; do { @@ -3030,17 +3014,18 @@ static void handle_ao_interrupt(struct comedi_device *dev, /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); - dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG); - if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */ - if ((dma0_status & PLX_DMA_EN_BIT) && - !(dma0_status & PLX_DMA_DONE_BIT)) - writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_iobase + PLX_DMA0_CS_REG); - else - writeb(PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_iobase + PLX_DMA0_CS_REG); + dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0); + if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */ + if ((dma0_status & PLX_DMACSR_ENABLE) && + !(dma0_status & PLX_DMACSR_DONE)) { + writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_iobase + PLX_REG_DMACSR0); + } else { + writeb(PLX_DMACSR_CLEARINTR, + devpriv->plx9080_iobase + PLX_REG_DMACSR0); + } spin_unlock_irqrestore(&dev->spinlock, flags); - if (dma0_status & PLX_DMA_EN_BIT) { + if (dma0_status & PLX_DMACSR_ENABLE) { load_ao_dma(dev, cmd); /* try to recover from dma end-of-chain event */ if (ao_dma_needs_restart(dev, dma0_status)) @@ -3069,7 +3054,7 @@ static irqreturn_t handle_interrupt(int irq, void *d) uint32_t plx_status; uint32_t plx_bits; - plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG); + plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR); status = readw(devpriv->main_iobase + HW_STATUS_REG); /* @@ -3083,10 +3068,11 @@ static irqreturn_t handle_interrupt(int irq, void *d) handle_ai_interrupt(dev, status, plx_status); handle_ao_interrupt(dev, status, plx_status); - /* clear possible plx9080 interrupt sources */ - if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */ - plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG); - writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG); + /* clear possible plx9080 interrupt sources */ + if (plx_status & PLX_INTCSR_LDBIA) { + /* clear local doorbell interrupt */ + plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL); + writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL); } return IRQ_HANDLED; @@ -3324,7 +3310,7 @@ static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) set_dac_select_reg(dev, cmd); set_dac_interval_regs(dev, cmd); load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr | - PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT); + PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR); set_dac_control1_reg(dev, cmd); s->async->inttrig = ao_inttrig; @@ -3725,19 +3711,19 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) unsigned int bitstream = (read_command << 8) | address; unsigned int bit; void __iomem * const plx_control_addr = - devpriv->plx9080_iobase + PLX_CONTROL_REG; + devpriv->plx9080_iobase + PLX_REG_CNTRL; uint16_t value; static const int value_length = 16; static const int eeprom_udelay = 1; udelay(eeprom_udelay); - devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS; + devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS; /* make sure we don't send anything to the i2c bus on 4020 */ - devpriv->plx_control_bits |= CTL_USERO; + devpriv->plx_control_bits |= PLX_CNTRL_USERO; writel(devpriv->plx_control_bits, plx_control_addr); /* activate serial eeprom */ udelay(eeprom_udelay); - devpriv->plx_control_bits |= CTL_EE_CS; + devpriv->plx_control_bits |= PLX_CNTRL_EECS; writel(devpriv->plx_control_bits, plx_control_addr); /* write read command and desired memory address */ @@ -3745,16 +3731,16 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) /* set bit to be written */ udelay(eeprom_udelay); if (bitstream & bit) - devpriv->plx_control_bits |= CTL_EE_W; + devpriv->plx_control_bits |= PLX_CNTRL_EEWB; else - devpriv->plx_control_bits &= ~CTL_EE_W; + devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB; writel(devpriv->plx_control_bits, plx_control_addr); /* clock in bit */ udelay(eeprom_udelay); - devpriv->plx_control_bits |= CTL_EE_CLK; + devpriv->plx_control_bits |= PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); udelay(eeprom_udelay); - devpriv->plx_control_bits &= ~CTL_EE_CLK; + devpriv->plx_control_bits &= ~PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); } /* read back value from eeprom memory location */ @@ -3762,19 +3748,19 @@ static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address) for (bit = 1 << (value_length - 1); bit; bit >>= 1) { /* clock out bit */ udelay(eeprom_udelay); - devpriv->plx_control_bits |= CTL_EE_CLK; + devpriv->plx_control_bits |= PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); udelay(eeprom_udelay); - devpriv->plx_control_bits &= ~CTL_EE_CLK; + devpriv->plx_control_bits &= ~PLX_CNTRL_EESK; writel(devpriv->plx_control_bits, plx_control_addr); udelay(eeprom_udelay); - if (readl(plx_control_addr) & CTL_EE_R) + if (readl(plx_control_addr) & PLX_CNTRL_EERB) value |= bit; } /* deactivate eeprom serial input */ udelay(eeprom_udelay); - devpriv->plx_control_bits &= ~CTL_EE_CS; + devpriv->plx_control_bits &= ~PLX_CNTRL_EECS; writel(devpriv->plx_control_bits, plx_control_addr); return value; @@ -3962,7 +3948,8 @@ static int setup_subdevices(struct comedi_device *dev) /* serial EEPROM, if present */ s = &dev->subdevices[8]; - if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) { + if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) & + PLX_CNTRL_EEPRESENT) { s->type = COMEDI_SUBD_MEMORY; s->subdev_flags = SDF_READABLE | SDF_INTERNAL; s->n_chan = 128; @@ -4019,16 +4006,16 @@ static int auto_attach(struct comedi_device *dev, } /* figure out what local addresses are */ - local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) & - LRNG_MEM_MASK; - local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) & - local_range & LMAP_MEM_MASK; + local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) & + PLX_LASRR_MEM_MASK; + local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) & + local_range & PLX_LASBA_MEM_MASK; devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase & ~local_range) | local_decode; - local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) & - LRNG_MEM_MASK; - local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) & - local_range & LMAP_MEM_MASK; + local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) & + PLX_LASRR_MEM_MASK; + local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) & + local_range & PLX_LASBA_MEM_MASK; devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase & ~local_range) | local_decode; diff --git a/drivers/staging/comedi/drivers/comedi_bond.c b/drivers/staging/comedi/drivers/comedi_bond.c index 50b76eccb..64a5ea381 100644 --- a/drivers/staging/comedi/drivers/comedi_bond.c +++ b/drivers/staging/comedi/drivers/comedi_bond.c @@ -55,16 +55,16 @@ struct bonded_device { struct comedi_device *dev; - unsigned minor; - unsigned subdev; - unsigned nchans; + unsigned int minor; + unsigned int subdev; + unsigned int nchans; }; struct comedi_bond_private { char name[256]; struct bonded_device **devs; - unsigned ndevs; - unsigned nchans; + unsigned int ndevs; + unsigned int nchans; }; static int bonding_dio_insn_bits(struct comedi_device *dev, diff --git a/drivers/staging/comedi/drivers/daqboard2000.c b/drivers/staging/comedi/drivers/daqboard2000.c index 73a46e3a6..b00f24ad9 100644 --- a/drivers/staging/comedi/drivers/daqboard2000.c +++ b/drivers/staging/comedi/drivers/daqboard2000.c @@ -116,12 +116,12 @@ #define DAQBOARD2000_SUBSYSTEM_IDS4 0x0004 /* Daqboard/2000 - 4 Dacs */ /* Initialization bits for the Serial EEPROM Control Register */ -#define DAQBOARD2000_SECRProgPinHi 0x8001767e -#define DAQBOARD2000_SECRProgPinLo 0x8000767e -#define DAQBOARD2000_SECRLocalBusHi 0xc000767e -#define DAQBOARD2000_SECRLocalBusLo 0x8000767e -#define DAQBOARD2000_SECRReloadHi 0xa000767e -#define DAQBOARD2000_SECRReloadLo 0x8000767e +#define DB2K_SECR_PROG_PIN_HI 0x8001767e +#define DB2K_SECR_PROG_PIN_LO 0x8000767e +#define DB2K_SECR_LOCAL_BUS_HI 0xc000767e +#define DB2K_SECR_LOCAL_BUS_LO 0x8000767e +#define DB2K_SECR_RELOAD_HI 0xa000767e +#define DB2K_SECR_RELOAD_LO 0x8000767e /* SECR status bits */ #define DAQBOARD2000_EEPROM_PRESENT 0x10000000 @@ -151,119 +151,108 @@ static const struct comedi_lrange range_daqboard2000_ai = { /* * Register Memory Map */ -#define acqControl 0x00 /* u16 */ -#define acqScanListFIFO 0x02 /* u16 */ -#define acqPacerClockDivLow 0x04 /* u32 */ -#define acqScanCounter 0x08 /* u16 */ -#define acqPacerClockDivHigh 0x0a /* u16 */ -#define acqTriggerCount 0x0c /* u16 */ -#define acqResultsFIFO 0x10 /* u16 */ -#define acqResultsShadow 0x14 /* u16 */ -#define acqAdcResult 0x18 /* u16 */ -#define dacScanCounter 0x1c /* u16 */ -#define dacControl 0x20 /* u16 */ -#define dacFIFO 0x24 /* s16 */ -#define dacPacerClockDiv 0x2a /* u16 */ -#define refDacs 0x2c /* u16 */ -#define dioControl 0x30 /* u16 */ -#define dioP3hsioData 0x32 /* s16 */ -#define dioP3Control 0x34 /* u16 */ -#define calEepromControl 0x36 /* u16 */ -#define dacSetting(x) (0x38 + (x)*2) /* s16 */ -#define dioP2ExpansionIO8Bit 0x40 /* s16 */ -#define ctrTmrControl 0x80 /* u16 */ -#define ctrInput(x) (0x88 + (x)*2) /* s16 */ -#define timerDivisor(x) (0xa0 + (x)*2) /* u16 */ -#define dmaControl 0xb0 /* u16 */ -#define trigControl 0xb2 /* u16 */ -#define calEeprom 0xb8 /* u16 */ -#define acqDigitalMark 0xba /* u16 */ -#define trigDacs 0xbc /* u16 */ -#define dioP2ExpansionIO16Bit(x) (0xc0 + (x)*2) /* s16 */ +#define DB2K_REG_ACQ_CONTROL 0x00 /* u16 (w) */ +#define DB2K_REG_ACQ_STATUS 0x00 /* u16 (r) */ +#define DB2K_REG_ACQ_SCAN_LIST_FIFO 0x02 /* u16 */ +#define DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW 0x04 /* u32 */ +#define DB2K_REG_ACQ_SCAN_COUNTER 0x08 /* u16 */ +#define DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH 0x0a /* u16 */ +#define DB2K_REG_ACQ_TRIGGER_COUNT 0x0c /* u16 */ +#define DB2K_REG_ACQ_RESULTS_FIFO 0x10 /* u16 */ +#define DB2K_REG_ACQ_RESULTS_SHADOW 0x14 /* u16 */ +#define DB2K_REG_ACQ_ADC_RESULT 0x18 /* u16 */ +#define DB2K_REG_DAC_SCAN_COUNTER 0x1c /* u16 */ +#define DB2K_REG_DAC_CONTROL 0x20 /* u16 (w) */ +#define DB2K_REG_DAC_STATUS 0x20 /* u16 (r) */ +#define DB2K_REG_DAC_FIFO 0x24 /* s16 */ +#define DB2K_REG_DAC_PACER_CLOCK_DIV 0x2a /* u16 */ +#define DB2K_REG_REF_DACS 0x2c /* u16 */ +#define DB2K_REG_DIO_CONTROL 0x30 /* u16 */ +#define DB2K_REG_P3_HSIO_DATA 0x32 /* s16 */ +#define DB2K_REG_P3_CONTROL 0x34 /* u16 */ +#define DB2K_REG_CAL_EEPROM_CONTROL 0x36 /* u16 */ +#define DB2K_REG_DAC_SETTING(x) (0x38 + (x) * 2) /* s16 */ +#define DB2K_REG_DIO_P2_EXP_IO_8_BIT 0x40 /* s16 */ +#define DB2K_REG_COUNTER_TIMER_CONTROL 0x80 /* u16 */ +#define DB2K_REG_COUNTER_INPUT(x) (0x88 + (x) * 2) /* s16 */ +#define DB2K_REG_TIMER_DIV(x) (0xa0 + (x) * 2) /* u16 */ +#define DB2K_REG_DMA_CONTROL 0xb0 /* u16 */ +#define DB2K_REG_TRIG_CONTROL 0xb2 /* u16 */ +#define DB2K_REG_CAL_EEPROM 0xb8 /* u16 */ +#define DB2K_REG_ACQ_DIGITAL_MARK 0xba /* u16 */ +#define DB2K_REG_TRIG_DACS 0xbc /* u16 */ +#define DB2K_REG_DIO_P2_EXP_IO_16_BIT(x) (0xc0 + (x) * 2) /* s16 */ /* Scan Sequencer programming */ -#define DAQBOARD2000_SeqStartScanList 0x0011 -#define DAQBOARD2000_SeqStopScanList 0x0010 +#define DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST 0x0011 +#define DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST 0x0010 /* Prepare for acquisition */ -#define DAQBOARD2000_AcqResetScanListFifo 0x0004 -#define DAQBOARD2000_AcqResetResultsFifo 0x0002 -#define DAQBOARD2000_AcqResetConfigPipe 0x0001 - -/* Acqusition status bits */ -#define DAQBOARD2000_AcqResultsFIFOMore1Sample 0x0001 -#define DAQBOARD2000_AcqResultsFIFOHasValidData 0x0002 -#define DAQBOARD2000_AcqResultsFIFOOverrun 0x0004 -#define DAQBOARD2000_AcqLogicScanning 0x0008 -#define DAQBOARD2000_AcqConfigPipeFull 0x0010 -#define DAQBOARD2000_AcqScanListFIFOEmpty 0x0020 -#define DAQBOARD2000_AcqAdcNotReady 0x0040 -#define DAQBOARD2000_ArbitrationFailure 0x0080 -#define DAQBOARD2000_AcqPacerOverrun 0x0100 -#define DAQBOARD2000_DacPacerOverrun 0x0200 -#define DAQBOARD2000_AcqHardwareError 0x01c0 - -/* Scan Sequencer programming */ -#define DAQBOARD2000_SeqStartScanList 0x0011 -#define DAQBOARD2000_SeqStopScanList 0x0010 +#define DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO 0x0004 +#define DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO 0x0002 +#define DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE 0x0001 /* Pacer Clock Control */ -#define DAQBOARD2000_AdcPacerInternal 0x0030 -#define DAQBOARD2000_AdcPacerExternal 0x0032 -#define DAQBOARD2000_AdcPacerEnable 0x0031 -#define DAQBOARD2000_AdcPacerEnableDacPacer 0x0034 -#define DAQBOARD2000_AdcPacerDisable 0x0030 -#define DAQBOARD2000_AdcPacerNormalMode 0x0060 -#define DAQBOARD2000_AdcPacerCompatibilityMode 0x0061 -#define DAQBOARD2000_AdcPacerInternalOutEnable 0x0008 -#define DAQBOARD2000_AdcPacerExternalRising 0x0100 +#define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL 0x0030 +#define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL 0x0032 +#define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE 0x0031 +#define DB2K_ACQ_CONTROL_ADC_PACER_ENABLE_DAC_PACER 0x0034 +#define DB2K_ACQ_CONTROL_ADC_PACER_DISABLE 0x0030 +#define DB2K_ACQ_CONTROL_ADC_PACER_NORMAL_MODE 0x0060 +#define DB2K_ACQ_CONTROL_ADC_PACER_COMPATIBILITY_MODE 0x0061 +#define DB2K_ACQ_CONTROL_ADC_PACER_INTERNAL_OUT_ENABLE 0x0008 +#define DB2K_ACQ_CONTROL_ADC_PACER_EXTERNAL_RISING 0x0100 + +/* Acquisition status bits */ +#define DB2K_ACQ_STATUS_RESULTS_FIFO_MORE_1_SAMPLE 0x0001 +#define DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA 0x0002 +#define DB2K_ACQ_STATUS_RESULTS_FIFO_OVERRUN 0x0004 +#define DB2K_ACQ_STATUS_LOGIC_SCANNING 0x0008 +#define DB2K_ACQ_STATUS_CONFIG_PIPE_FULL 0x0010 +#define DB2K_ACQ_STATUS_SCAN_LIST_FIFO_EMPTY 0x0020 +#define DB2K_ACQ_STATUS_ADC_NOT_READY 0x0040 +#define DB2K_ACQ_STATUS_ARBITRATION_FAILURE 0x0080 +#define DB2K_ACQ_STATUS_ADC_PACER_OVERRUN 0x0100 +#define DB2K_ACQ_STATUS_DAC_PACER_OVERRUN 0x0200 /* DAC status */ -#define DAQBOARD2000_DacFull 0x0001 -#define DAQBOARD2000_RefBusy 0x0002 -#define DAQBOARD2000_TrgBusy 0x0004 -#define DAQBOARD2000_CalBusy 0x0008 -#define DAQBOARD2000_Dac0Busy 0x0010 -#define DAQBOARD2000_Dac1Busy 0x0020 -#define DAQBOARD2000_Dac2Busy 0x0040 -#define DAQBOARD2000_Dac3Busy 0x0080 +#define DB2K_DAC_STATUS_DAC_FULL 0x0001 +#define DB2K_DAC_STATUS_REF_BUSY 0x0002 +#define DB2K_DAC_STATUS_TRIG_BUSY 0x0004 +#define DB2K_DAC_STATUS_CAL_BUSY 0x0008 +#define DB2K_DAC_STATUS_DAC_BUSY(x) (0x0010 << (x)) /* DAC control */ -#define DAQBOARD2000_Dac0Enable 0x0021 -#define DAQBOARD2000_Dac1Enable 0x0031 -#define DAQBOARD2000_Dac2Enable 0x0041 -#define DAQBOARD2000_Dac3Enable 0x0051 -#define DAQBOARD2000_DacEnableBit 0x0001 -#define DAQBOARD2000_Dac0Disable 0x0020 -#define DAQBOARD2000_Dac1Disable 0x0030 -#define DAQBOARD2000_Dac2Disable 0x0040 -#define DAQBOARD2000_Dac3Disable 0x0050 -#define DAQBOARD2000_DacResetFifo 0x0004 -#define DAQBOARD2000_DacPatternDisable 0x0060 -#define DAQBOARD2000_DacPatternEnable 0x0061 -#define DAQBOARD2000_DacSelectSignedData 0x0002 -#define DAQBOARD2000_DacSelectUnsignedData 0x0000 +#define DB2K_DAC_CONTROL_ENABLE_BIT 0x0001 +#define DB2K_DAC_CONTROL_DATA_IS_SIGNED 0x0002 +#define DB2K_DAC_CONTROL_RESET_FIFO 0x0004 +#define DB2K_DAC_CONTROL_DAC_DISABLE(x) (0x0020 + ((x) << 4)) +#define DB2K_DAC_CONTROL_DAC_ENABLE(x) (0x0021 + ((x) << 4)) +#define DB2K_DAC_CONTROL_PATTERN_DISABLE 0x0060 +#define DB2K_DAC_CONTROL_PATTERN_ENABLE 0x0061 /* Trigger Control */ -#define DAQBOARD2000_TrigAnalog 0x0000 -#define DAQBOARD2000_TrigTTL 0x0010 -#define DAQBOARD2000_TrigTransHiLo 0x0004 -#define DAQBOARD2000_TrigTransLoHi 0x0000 -#define DAQBOARD2000_TrigAbove 0x0000 -#define DAQBOARD2000_TrigBelow 0x0004 -#define DAQBOARD2000_TrigLevelSense 0x0002 -#define DAQBOARD2000_TrigEdgeSense 0x0000 -#define DAQBOARD2000_TrigEnable 0x0001 -#define DAQBOARD2000_TrigDisable 0x0000 +#define DB2K_TRIG_CONTROL_TYPE_ANALOG 0x0000 +#define DB2K_TRIG_CONTROL_TYPE_TTL 0x0010 +#define DB2K_TRIG_CONTROL_EDGE_HI_LO 0x0004 +#define DB2K_TRIG_CONTROL_EDGE_LO_HI 0x0000 +#define DB2K_TRIG_CONTROL_LEVEL_ABOVE 0x0000 +#define DB2K_TRIG_CONTROL_LEVEL_BELOW 0x0004 +#define DB2K_TRIG_CONTROL_SENSE_LEVEL 0x0002 +#define DB2K_TRIG_CONTROL_SENSE_EDGE 0x0000 +#define DB2K_TRIG_CONTROL_ENABLE 0x0001 +#define DB2K_TRIG_CONTROL_DISABLE 0x0000 /* Reference Dac Selection */ -#define DAQBOARD2000_PosRefDacSelect 0x0100 -#define DAQBOARD2000_NegRefDacSelect 0x0000 +#define DB2K_REF_DACS_SET 0x0080 +#define DB2K_REF_DACS_SELECT_POS_REF 0x0100 +#define DB2K_REF_DACS_SELECT_NEG_REF 0x0000 struct daq200_boardtype { const char *name; int id; }; + static const struct daq200_boardtype boardtypes[] = { {"ids2", DAQBOARD2000_SUBSYSTEM_IDS2}, {"ids4", DAQBOARD2000_SUBSYSTEM_IDS4}, @@ -276,15 +265,16 @@ struct daqboard2000_private { void __iomem *plx; }; -static void writeAcqScanListEntry(struct comedi_device *dev, u16 entry) +static void daqboard2000_write_acq_scan_list_entry(struct comedi_device *dev, + u16 entry) { - /* udelay(4); */ - writew(entry & 0x00ff, dev->mmio + acqScanListFIFO); - /* udelay(4); */ - writew((entry >> 8) & 0x00ff, dev->mmio + acqScanListFIFO); + writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); + writew((entry >> 8) & 0x00ff, + dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); } -static void setup_sampling(struct comedi_device *dev, int chan, int gain) +static void daqboard2000_setup_sampling(struct comedi_device *dev, int chan, + int gain) { u16 word0, word1, word2, word3; @@ -315,17 +305,13 @@ static void setup_sampling(struct comedi_device *dev, int chan, int gain) word3 = 0; break; } -/* - dev->eeprom.correctionDACSE[i][j][k].offset = 0x800; - dev->eeprom.correctionDACSE[i][j][k].gain = 0xc00; -*/ /* These should be read from EEPROM */ - word2 |= 0x0800; - word3 |= 0xc000; - writeAcqScanListEntry(dev, word0); - writeAcqScanListEntry(dev, word1); - writeAcqScanListEntry(dev, word2); - writeAcqScanListEntry(dev, word3); + word2 |= 0x0800; /* offset */ + word3 |= 0xc000; /* gain */ + daqboard2000_write_acq_scan_list_entry(dev, word0); + daqboard2000_write_acq_scan_list_entry(dev, word1); + daqboard2000_write_acq_scan_list_entry(dev, word2); + daqboard2000_write_acq_scan_list_entry(dev, word3); } static int daqboard2000_ai_status(struct comedi_device *dev, @@ -335,7 +321,7 @@ static int daqboard2000_ai_status(struct comedi_device *dev, { unsigned int status; - status = readw(dev->mmio + acqControl); + status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); if (status & context) return 0; return -EBUSY; @@ -350,50 +336,58 @@ static int daqboard2000_ai_insn_read(struct comedi_device *dev, int ret; int i; - writew(DAQBOARD2000_AcqResetScanListFifo | - DAQBOARD2000_AcqResetResultsFifo | - DAQBOARD2000_AcqResetConfigPipe, dev->mmio + acqControl); + writew(DB2K_ACQ_CONTROL_RESET_SCAN_LIST_FIFO | + DB2K_ACQ_CONTROL_RESET_RESULTS_FIFO | + DB2K_ACQ_CONTROL_RESET_CONFIG_PIPE, + dev->mmio + DB2K_REG_ACQ_CONTROL); /* * If pacer clock is not set to some high value (> 10 us), we * risk multiple samples to be put into the result FIFO. */ /* 1 second, should be long enough */ - writel(1000000, dev->mmio + acqPacerClockDivLow); - writew(0, dev->mmio + acqPacerClockDivHigh); + writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW); + writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH); gain = CR_RANGE(insn->chanspec); chan = CR_CHAN(insn->chanspec); - /* This doesn't look efficient. I decided to take the conservative + /* + * This doesn't look efficient. I decided to take the conservative * approach when I did the insn conversion. Perhaps it would be * better to have broken it completely, then someone would have been - * forced to fix it. --ds */ + * forced to fix it. --ds + */ for (i = 0; i < insn->n; i++) { - setup_sampling(dev, chan, gain); + daqboard2000_setup_sampling(dev, chan, gain); /* Enable reading from the scanlist FIFO */ - writew(DAQBOARD2000_SeqStartScanList, dev->mmio + acqControl); + writew(DB2K_ACQ_CONTROL_SEQ_START_SCAN_LIST, + dev->mmio + DB2K_REG_ACQ_CONTROL); ret = comedi_timeout(dev, s, insn, daqboard2000_ai_status, - DAQBOARD2000_AcqConfigPipeFull); + DB2K_ACQ_STATUS_CONFIG_PIPE_FULL); if (ret) return ret; - writew(DAQBOARD2000_AdcPacerEnable, dev->mmio + acqControl); + writew(DB2K_ACQ_CONTROL_ADC_PACER_ENABLE, + dev->mmio + DB2K_REG_ACQ_CONTROL); ret = comedi_timeout(dev, s, insn, daqboard2000_ai_status, - DAQBOARD2000_AcqLogicScanning); + DB2K_ACQ_STATUS_LOGIC_SCANNING); if (ret) return ret; - ret = comedi_timeout(dev, s, insn, daqboard2000_ai_status, - DAQBOARD2000_AcqResultsFIFOHasValidData); + ret = + comedi_timeout(dev, s, insn, daqboard2000_ai_status, + DB2K_ACQ_STATUS_RESULTS_FIFO_HAS_DATA); if (ret) return ret; - data[i] = readw(dev->mmio + acqResultsFIFO); - writew(DAQBOARD2000_AdcPacerDisable, dev->mmio + acqControl); - writew(DAQBOARD2000_SeqStopScanList, dev->mmio + acqControl); + data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); + writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE, + dev->mmio + DB2K_REG_ACQ_CONTROL); + writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST, + dev->mmio + DB2K_REG_ACQ_CONTROL); } return i; @@ -407,8 +401,8 @@ static int daqboard2000_ao_eoc(struct comedi_device *dev, unsigned int chan = CR_CHAN(insn->chanspec); unsigned int status; - status = readw(dev->mmio + dacControl); - if ((status & ((chan + 1) * 0x0010)) == 0) + status = readw(dev->mmio + DB2K_REG_DAC_STATUS); + if ((status & DB2K_DAC_STATUS_DAC_BUSY(chan)) == 0) return 0; return -EBUSY; } @@ -425,7 +419,7 @@ static int daqboard2000_ao_insn_write(struct comedi_device *dev, unsigned int val = data[i]; int ret; - writew(val, dev->mmio + dacSetting(chan)); + writew(val, dev->mmio + DB2K_REG_DAC_SETTING(chan)); ret = comedi_timeout(dev, s, insn, daqboard2000_ao_eoc, 0); if (ret) @@ -437,39 +431,39 @@ static int daqboard2000_ao_insn_write(struct comedi_device *dev, return insn->n; } -static void daqboard2000_resetLocalBus(struct comedi_device *dev) +static void daqboard2000_reset_local_bus(struct comedi_device *dev) { struct daqboard2000_private *devpriv = dev->private; - writel(DAQBOARD2000_SECRLocalBusHi, devpriv->plx + 0x6c); + writel(DB2K_SECR_LOCAL_BUS_HI, devpriv->plx + 0x6c); mdelay(10); - writel(DAQBOARD2000_SECRLocalBusLo, devpriv->plx + 0x6c); + writel(DB2K_SECR_LOCAL_BUS_LO, devpriv->plx + 0x6c); mdelay(10); } -static void daqboard2000_reloadPLX(struct comedi_device *dev) +static void daqboard2000_reload_plx(struct comedi_device *dev) { struct daqboard2000_private *devpriv = dev->private; - writel(DAQBOARD2000_SECRReloadLo, devpriv->plx + 0x6c); + writel(DB2K_SECR_RELOAD_LO, devpriv->plx + 0x6c); mdelay(10); - writel(DAQBOARD2000_SECRReloadHi, devpriv->plx + 0x6c); + writel(DB2K_SECR_RELOAD_HI, devpriv->plx + 0x6c); mdelay(10); - writel(DAQBOARD2000_SECRReloadLo, devpriv->plx + 0x6c); + writel(DB2K_SECR_RELOAD_LO, devpriv->plx + 0x6c); mdelay(10); } -static void daqboard2000_pulseProgPin(struct comedi_device *dev) +static void daqboard2000_pulse_prog_pin(struct comedi_device *dev) { struct daqboard2000_private *devpriv = dev->private; - writel(DAQBOARD2000_SECRProgPinHi, devpriv->plx + 0x6c); + writel(DB2K_SECR_PROG_PIN_HI, devpriv->plx + 0x6c); mdelay(10); - writel(DAQBOARD2000_SECRProgPinLo, devpriv->plx + 0x6c); + writel(DB2K_SECR_PROG_PIN_LO, devpriv->plx + 0x6c); mdelay(10); /* Not in the original code, but I like symmetry... */ } -static int daqboard2000_pollCPLD(struct comedi_device *dev, int mask) +static int daqboard2000_poll_cpld(struct comedi_device *dev, int mask) { int result = 0; int i; @@ -482,17 +476,17 @@ static int daqboard2000_pollCPLD(struct comedi_device *dev, int mask) result = 1; break; } - udelay(100); + usleep_range(100, 1000); } udelay(5); return result; } -static int daqboard2000_writeCPLD(struct comedi_device *dev, int data) +static int daqboard2000_write_cpld(struct comedi_device *dev, int data) { int result = 0; - udelay(10); + usleep_range(10, 20); writew(data, dev->mmio + 0x1000); if ((readw(dev->mmio + 0x1000) & DAQBOARD2000_CPLD_INIT) == DAQBOARD2000_CPLD_INIT) { @@ -501,9 +495,9 @@ static int daqboard2000_writeCPLD(struct comedi_device *dev, int data) return result; } -static int initialize_daqboard2000(struct comedi_device *dev, - const u8 *cpld_array, size_t len, - unsigned long context) +static int daqboard2000_load_firmware(struct comedi_device *dev, + const u8 *cpld_array, size_t len, + unsigned long context) { struct daqboard2000_private *devpriv = dev->private; int result = -EIO; @@ -518,10 +512,10 @@ static int initialize_daqboard2000(struct comedi_device *dev, return -EIO; for (retry = 0; retry < 3; retry++) { - daqboard2000_resetLocalBus(dev); - daqboard2000_reloadPLX(dev); - daqboard2000_pulseProgPin(dev); - if (daqboard2000_pollCPLD(dev, DAQBOARD2000_CPLD_INIT)) { + daqboard2000_reset_local_bus(dev); + daqboard2000_reload_plx(dev); + daqboard2000_pulse_prog_pin(dev); + if (daqboard2000_poll_cpld(dev, DAQBOARD2000_CPLD_INIT)) { for (i = 0; i < len; i++) { if (cpld_array[i] == 0xff && cpld_array[i + 1] == 0x20) @@ -530,12 +524,12 @@ static int initialize_daqboard2000(struct comedi_device *dev, for (; i < len; i += 2) { int data = (cpld_array[i] << 8) + cpld_array[i + 1]; - if (!daqboard2000_writeCPLD(dev, data)) + if (!daqboard2000_write_cpld(dev, data)) break; } if (i >= len) { - daqboard2000_resetLocalBus(dev); - daqboard2000_reloadPLX(dev); + daqboard2000_reset_local_bus(dev); + daqboard2000_reload_plx(dev); result = 0; break; } @@ -544,79 +538,83 @@ static int initialize_daqboard2000(struct comedi_device *dev, return result; } -static void daqboard2000_adcStopDmaTransfer(struct comedi_device *dev) +static void daqboard2000_adc_stop_dma_transfer(struct comedi_device *dev) { } -static void daqboard2000_adcDisarm(struct comedi_device *dev) +static void daqboard2000_adc_disarm(struct comedi_device *dev) { /* Disable hardware triggers */ udelay(2); - writew(DAQBOARD2000_TrigAnalog | DAQBOARD2000_TrigDisable, - dev->mmio + trigControl); + writew(DB2K_TRIG_CONTROL_TYPE_ANALOG | DB2K_TRIG_CONTROL_DISABLE, + dev->mmio + DB2K_REG_TRIG_CONTROL); udelay(2); - writew(DAQBOARD2000_TrigTTL | DAQBOARD2000_TrigDisable, - dev->mmio + trigControl); + writew(DB2K_TRIG_CONTROL_TYPE_TTL | DB2K_TRIG_CONTROL_DISABLE, + dev->mmio + DB2K_REG_TRIG_CONTROL); /* Stop the scan list FIFO from loading the configuration pipe */ udelay(2); - writew(DAQBOARD2000_SeqStopScanList, dev->mmio + acqControl); + writew(DB2K_ACQ_CONTROL_SEQ_STOP_SCAN_LIST, + dev->mmio + DB2K_REG_ACQ_CONTROL); /* Stop the pacer clock */ udelay(2); - writew(DAQBOARD2000_AdcPacerDisable, dev->mmio + acqControl); + writew(DB2K_ACQ_CONTROL_ADC_PACER_DISABLE, + dev->mmio + DB2K_REG_ACQ_CONTROL); /* Stop the input dma (abort channel 1) */ - daqboard2000_adcStopDmaTransfer(dev); + daqboard2000_adc_stop_dma_transfer(dev); } -static void daqboard2000_activateReferenceDacs(struct comedi_device *dev) +static void daqboard2000_activate_reference_dacs(struct comedi_device *dev) { unsigned int val; int timeout; /* Set the + reference dac value in the FPGA */ - writew(0x80 | DAQBOARD2000_PosRefDacSelect, dev->mmio + refDacs); + writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_POS_REF, + dev->mmio + DB2K_REG_REF_DACS); for (timeout = 0; timeout < 20; timeout++) { - val = readw(dev->mmio + dacControl); - if ((val & DAQBOARD2000_RefBusy) == 0) + val = readw(dev->mmio + DB2K_REG_DAC_STATUS); + if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0) break; udelay(2); } /* Set the - reference dac value in the FPGA */ - writew(0x80 | DAQBOARD2000_NegRefDacSelect, dev->mmio + refDacs); + writew(DB2K_REF_DACS_SET | DB2K_REF_DACS_SELECT_NEG_REF, + dev->mmio + DB2K_REG_REF_DACS); for (timeout = 0; timeout < 20; timeout++) { - val = readw(dev->mmio + dacControl); - if ((val & DAQBOARD2000_RefBusy) == 0) + val = readw(dev->mmio + DB2K_REG_DAC_STATUS); + if ((val & DB2K_DAC_STATUS_REF_BUSY) == 0) break; udelay(2); } } -static void daqboard2000_initializeCtrs(struct comedi_device *dev) +static void daqboard2000_initialize_ctrs(struct comedi_device *dev) { } -static void daqboard2000_initializeTmrs(struct comedi_device *dev) +static void daqboard2000_initialize_tmrs(struct comedi_device *dev) { } -static void daqboard2000_dacDisarm(struct comedi_device *dev) +static void daqboard2000_dac_disarm(struct comedi_device *dev) { } -static void daqboard2000_initializeAdc(struct comedi_device *dev) +static void daqboard2000_initialize_adc(struct comedi_device *dev) { - daqboard2000_adcDisarm(dev); - daqboard2000_activateReferenceDacs(dev); - daqboard2000_initializeCtrs(dev); - daqboard2000_initializeTmrs(dev); + daqboard2000_adc_disarm(dev); + daqboard2000_activate_reference_dacs(dev); + daqboard2000_initialize_ctrs(dev); + daqboard2000_initialize_tmrs(dev); } -static void daqboard2000_initializeDac(struct comedi_device *dev) +static void daqboard2000_initialize_dac(struct comedi_device *dev) { - daqboard2000_dacDisarm(dev); + daqboard2000_dac_disarm(dev); } static int daqboard2000_8255_cb(struct comedi_device *dev, @@ -683,12 +681,12 @@ static int daqboard2000_auto_attach(struct comedi_device *dev, result = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev, DAQBOARD2000_FIRMWARE, - initialize_daqboard2000, 0); + daqboard2000_load_firmware, 0); if (result < 0) return result; - daqboard2000_initializeAdc(dev); - daqboard2000_initializeDac(dev); + daqboard2000_initialize_adc(dev); + daqboard2000_initialize_dac(dev); s = &dev->subdevices[0]; /* ai subdevice */ @@ -714,7 +712,7 @@ static int daqboard2000_auto_attach(struct comedi_device *dev, s = &dev->subdevices[2]; return subdev_8255_init(dev, s, daqboard2000_8255_cb, - dioP2ExpansionIO8Bit); + DB2K_REG_DIO_P2_EXP_IO_8_BIT); } static void daqboard2000_detach(struct comedi_device *dev) diff --git a/drivers/staging/comedi/drivers/das16.c b/drivers/staging/comedi/drivers/das16.c index fd8e0b76f..5d157951f 100644 --- a/drivers/staging/comedi/drivers/das16.c +++ b/drivers/staging/comedi/drivers/das16.c @@ -92,37 +92,37 @@ #define DAS16_AO_LSB_REG(x) ((x) ? 0x06 : 0x04) #define DAS16_AO_MSB_REG(x) ((x) ? 0x07 : 0x05) #define DAS16_STATUS_REG 0x08 -#define DAS16_STATUS_BUSY (1 << 7) -#define DAS16_STATUS_UNIPOLAR (1 << 6) -#define DAS16_STATUS_MUXBIT (1 << 5) -#define DAS16_STATUS_INT (1 << 4) +#define DAS16_STATUS_BUSY BIT(7) +#define DAS16_STATUS_UNIPOLAR BIT(6) +#define DAS16_STATUS_MUXBIT BIT(5) +#define DAS16_STATUS_INT BIT(4) #define DAS16_CTRL_REG 0x09 -#define DAS16_CTRL_INTE (1 << 7) +#define DAS16_CTRL_INTE BIT(7) #define DAS16_CTRL_IRQ(x) (((x) & 0x7) << 4) -#define DAS16_CTRL_DMAE (1 << 2) +#define DAS16_CTRL_DMAE BIT(2) #define DAS16_CTRL_PACING_MASK (3 << 0) #define DAS16_CTRL_INT_PACER (3 << 0) #define DAS16_CTRL_EXT_PACER (2 << 0) #define DAS16_CTRL_SOFT_PACER (0 << 0) #define DAS16_PACER_REG 0x0a #define DAS16_PACER_BURST_LEN(x) (((x) & 0xf) << 4) -#define DAS16_PACER_CTR0 (1 << 1) -#define DAS16_PACER_TRIG0 (1 << 0) +#define DAS16_PACER_CTR0 BIT(1) +#define DAS16_PACER_TRIG0 BIT(0) #define DAS16_GAIN_REG 0x0b #define DAS16_TIMER_BASE_REG 0x0c /* to 0x0f */ #define DAS1600_CONV_REG 0x404 -#define DAS1600_CONV_DISABLE (1 << 6) +#define DAS1600_CONV_DISABLE BIT(6) #define DAS1600_BURST_REG 0x405 -#define DAS1600_BURST_VAL (1 << 6) +#define DAS1600_BURST_VAL BIT(6) #define DAS1600_ENABLE_REG 0x406 -#define DAS1600_ENABLE_VAL (1 << 6) +#define DAS1600_ENABLE_VAL BIT(6) #define DAS1600_STATUS_REG 0x407 -#define DAS1600_STATUS_BME (1 << 6) -#define DAS1600_STATUS_ME (1 << 5) -#define DAS1600_STATUS_CD (1 << 4) -#define DAS1600_STATUS_WS (1 << 1) -#define DAS1600_STATUS_CLK_10MHZ (1 << 0) +#define DAS1600_STATUS_BME BIT(6) +#define DAS1600_STATUS_ME BIT(5) +#define DAS1600_STATUS_CD BIT(4) +#define DAS1600_STATUS_WS BIT(1) +#define DAS1600_STATUS_CLK_10MHZ BIT(0) static const struct comedi_lrange range_das1x01_bip = { 4, { @@ -198,6 +198,7 @@ enum { das16_pg_1601, das16_pg_1602, }; + static const int *const das16_gainlists[] = { NULL, das16jr_gainlist, @@ -428,8 +429,10 @@ static const struct das16_board das16_boards[] = { }, }; -/* Period for timer interrupt in jiffies. It's a function - * to deal with possibility of dynamic HZ patches */ +/* + * Period for timer interrupt in jiffies. It's a function + * to deal with possibility of dynamic HZ patches + */ static inline int timer_period(void) { return HZ / 20; diff --git a/drivers/staging/comedi/drivers/das16m1.c b/drivers/staging/comedi/drivers/das16m1.c index 3a37373fb..bb8d6ec06 100644 --- a/drivers/staging/comedi/drivers/das16m1.c +++ b/drivers/staging/comedi/drivers/das16m1.c @@ -1,56 +1,52 @@ /* - comedi/drivers/das16m1.c - CIO-DAS16/M1 driver - Author: Frank Mori Hess, based on code from the das16 - driver. - Copyright (C) 2001 Frank Mori Hess <fmhess@users.sourceforge.net> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * Comedi driver for CIO-DAS16/M1 + * Author: Frank Mori Hess, based on code from the das16 driver. + * Copyright (C) 2001 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + /* -Driver: das16m1 -Description: CIO-DAS16/M1 -Author: Frank Mori Hess <fmhess@users.sourceforge.net> -Devices: [Measurement Computing] CIO-DAS16/M1 (das16m1) -Status: works - -This driver supports a single board - the CIO-DAS16/M1. -As far as I know, there are no other boards that have -the same register layout. Even the CIO-DAS16/M1/16 is -significantly different. - -I was _barely_ able to reach the full 1 MHz capability -of this board, using a hard real-time interrupt -(set the TRIG_RT flag in your struct comedi_cmd and use -rtlinux or RTAI). The board can't do dma, so the bottleneck is -pulling the data across the ISA bus. I timed the interrupt -handler, and it took my computer ~470 microseconds to pull 512 -samples from the board. So at 1 Mhz sampling rate, -expect your CPU to be spending almost all of its -time in the interrupt handler. - -This board has some unusual restrictions for its channel/gain list. If the -list has 2 or more channels in it, then two conditions must be satisfied: -(1) - even/odd channels must appear at even/odd indices in the list -(2) - the list must have an even number of entries. - -Options: - [0] - base io address - [1] - irq (optional, but you probably want it) - -irq can be omitted, although the cmd interface will not work without it. -*/ + * Driver: das16m1 + * Description: CIO-DAS16/M1 + * Author: Frank Mori Hess <fmhess@users.sourceforge.net> + * Devices: [Measurement Computing] CIO-DAS16/M1 (das16m1) + * Status: works + * + * This driver supports a single board - the CIO-DAS16/M1. As far as I know, + * there are no other boards that have the same register layout. Even the + * CIO-DAS16/M1/16 is significantly different. + * + * I was _barely_ able to reach the full 1 MHz capability of this board, using + * a hard real-time interrupt (set the TRIG_RT flag in your struct comedi_cmd + * and use rtlinux or RTAI). The board can't do dma, so the bottleneck is + * pulling the data across the ISA bus. I timed the interrupt handler, and it + * took my computer ~470 microseconds to pull 512 samples from the board. So + * at 1 Mhz sampling rate, expect your CPU to be spending almost all of its + * time in the interrupt handler. + * + * This board has some unusual restrictions for its channel/gain list. If the + * list has 2 or more channels in it, then two conditions must be satisfied: + * (1) - even/odd channels must appear at even/odd indices in the list + * (2) - the list must have an even number of entries. + * + * Configuration options: + * [0] - base io address + * [1] - irq (optional, but you probably want it) + * + * irq can be omitted, although the cmd interface will not work without it. + */ #include <linux/module.h> #include <linux/slab.h> @@ -60,52 +56,38 @@ irq can be omitted, although the cmd interface will not work without it. #include "8255.h" #include "comedi_8254.h" -#define DAS16M1_SIZE2 8 - -#define FIFO_SIZE 1024 /* 1024 sample fifo */ - /* - CIO-DAS16_M1.pdf - - "cio-das16/m1" - - 0 a/d bits 0-3, mux start 12 bit - 1 a/d bits 4-11 unused - 2 status control - 3 di 4 bit do 4 bit - 4 unused clear interrupt - 5 interrupt, pacer - 6 channel/gain queue address - 7 channel/gain queue data - 89ab 8254 - cdef 8254 - 400 8255 - 404-407 8254 - -*/ - -#define DAS16M1_AI 0 /* 16-bit wide register */ -#define AI_CHAN(x) ((x) & 0xf) -#define DAS16M1_CS 2 -#define EXT_TRIG_BIT 0x1 -#define OVRUN 0x20 -#define IRQDATA 0x80 -#define DAS16M1_DIO 3 -#define DAS16M1_CLEAR_INTR 4 -#define DAS16M1_INTR_CONTROL 5 -#define EXT_PACER 0x2 -#define INT_PACER 0x3 -#define PACER_MASK 0x3 -#define INTE 0x80 -#define DAS16M1_QUEUE_ADDR 6 -#define DAS16M1_QUEUE_DATA 7 -#define Q_CHAN(x) ((x) & 0x7) -#define Q_RANGE(x) (((x) & 0xf) << 4) -#define UNIPOLAR 0x40 -#define DAS16M1_8254_FIRST 0x8 -#define DAS16M1_8254_SECOND 0xc -#define DAS16M1_82C55 0x400 -#define DAS16M1_8254_THIRD 0x404 + * Register map (dev->iobase) + */ +#define DAS16M1_AI_REG 0x00 /* 16-bit register */ +#define DAS16M1_AI_TO_CHAN(x) (((x) >> 0) & 0xf) +#define DAS16M1_AI_TO_SAMPLE(x) (((x) >> 4) & 0xfff) +#define DAS16M1_CS_REG 0x02 +#define DAS16M1_CS_EXT_TRIG BIT(0) +#define DAS16M1_CS_OVRUN BIT(5) +#define DAS16M1_CS_IRQDATA BIT(7) +#define DAS16M1_DI_REG 0x03 +#define DAS16M1_DO_REG 0x03 +#define DAS16M1_CLR_INTR_REG 0x04 +#define DAS16M1_INTR_CTRL_REG 0x05 +#define DAS16M1_INTR_CTRL_PACER(x) (((x) & 0x3) << 0) +#define DAS16M1_INTR_CTRL_PACER_EXT DAS16M1_INTR_CTRL_PACER(2) +#define DAS16M1_INTR_CTRL_PACER_INT DAS16M1_INTR_CTRL_PACER(3) +#define DAS16M1_INTR_CTRL_PACER_MASK DAS16M1_INTR_CTRL_PACER(3) +#define DAS16M1_INTR_CTRL_IRQ(x) (((x) & 0x7) << 4) +#define DAS16M1_INTR_CTRL_INTE BIT(7) +#define DAS16M1_Q_ADDR_REG 0x06 +#define DAS16M1_Q_REG 0x07 +#define DAS16M1_Q_CHAN(x) (((x) & 0x7) << 0) +#define DAS16M1_Q_RANGE(x) (((x) & 0xf) << 4) +#define DAS16M1_8254_IOBASE1 0x08 +#define DAS16M1_8254_IOBASE2 0x0c +#define DAS16M1_8255_IOBASE 0x400 +#define DAS16M1_8254_IOBASE3 0x404 + +#define DAS16M1_SIZE2 0x08 + +#define DAS16M1_AI_FIFO_SZ 1024 /* # samples */ static const struct comedi_lrange range_das16m1 = { 9, { @@ -121,29 +103,46 @@ static const struct comedi_lrange range_das16m1 = { } }; -struct das16m1_private_struct { +struct das16m1_private { struct comedi_8254 *counter; - unsigned int control_state; - unsigned int adc_count; /* number of samples completed */ - /* initial value in lower half of hardware conversion counter, - * needed to keep track of whether new count has been loaded into - * counter yet (loaded by first sample conversion) */ + unsigned int intr_ctrl; + unsigned int adc_count; u16 initial_hw_count; - unsigned short ai_buffer[FIFO_SIZE]; + unsigned short ai_buffer[DAS16M1_AI_FIFO_SZ]; unsigned long extra_iobase; }; -static inline unsigned short munge_sample(unsigned short data) +static void das16m1_ai_set_queue(struct comedi_device *dev, + unsigned int *chanspec, unsigned int len) { - return (data >> 4) & 0xfff; + unsigned int i; + + for (i = 0; i < len; i++) { + unsigned int chan = CR_CHAN(chanspec[i]); + unsigned int range = CR_RANGE(chanspec[i]); + + outb(i, dev->iobase + DAS16M1_Q_ADDR_REG); + outb(DAS16M1_Q_CHAN(chan) | DAS16M1_Q_RANGE(range), + dev->iobase + DAS16M1_Q_REG); + } } -static void munge_sample_array(unsigned short *array, unsigned int num_elements) +static void das16m1_ai_munge(struct comedi_device *dev, + struct comedi_subdevice *s, + void *data, unsigned int num_bytes, + unsigned int start_chan_index) { + unsigned short *array = data; + unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes); unsigned int i; - for (i = 0; i < num_elements; i++) - array[i] = munge_sample(array[i]); + /* + * The fifo values have the channel number in the lower 4-bits and + * the sample in the upper 12-bits. This just shifts the values + * to remove the channel numbers. + */ + for (i = 0; i < nsamples; i++) + array[i] = DAS16M1_AI_TO_SAMPLE(array[i]); } static int das16m1_ai_check_chanlist(struct comedi_device *dev, @@ -174,8 +173,9 @@ static int das16m1_ai_check_chanlist(struct comedi_device *dev, return 0; } -static int das16m1_cmd_test(struct comedi_device *dev, - struct comedi_subdevice *s, struct comedi_cmd *cmd) +static int das16m1_ai_cmdtest(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_cmd *cmd) { int err = 0; @@ -245,17 +245,13 @@ static int das16m1_cmd_test(struct comedi_device *dev, return 0; } -static int das16m1_cmd_exec(struct comedi_device *dev, - struct comedi_subdevice *s) +static int das16m1_ai_cmd(struct comedi_device *dev, + struct comedi_subdevice *s) { - struct das16m1_private_struct *devpriv = dev->private; + struct das16m1_private *devpriv = dev->private; struct comedi_async *async = s->async; struct comedi_cmd *cmd = &async->cmd; - unsigned int byte, i; - - /* disable interrupts and internal pacer */ - devpriv->control_state &= ~INTE & ~PACER_MASK; - outb(devpriv->control_state, dev->iobase + DAS16M1_INTR_CONTROL); + unsigned int byte; /* set software count */ devpriv->adc_count = 0; @@ -274,48 +270,47 @@ static int das16m1_cmd_exec(struct comedi_device *dev, */ devpriv->initial_hw_count = comedi_8254_read(devpriv->counter, 1); - /* setup channel/gain queue */ - for (i = 0; i < cmd->chanlist_len; i++) { - outb(i, dev->iobase + DAS16M1_QUEUE_ADDR); - byte = - Q_CHAN(CR_CHAN(cmd->chanlist[i])) | - Q_RANGE(CR_RANGE(cmd->chanlist[i])); - outb(byte, dev->iobase + DAS16M1_QUEUE_DATA); - } + das16m1_ai_set_queue(dev, cmd->chanlist, cmd->chanlist_len); /* enable interrupts and set internal pacer counter mode and counts */ - devpriv->control_state &= ~PACER_MASK; + devpriv->intr_ctrl &= ~DAS16M1_INTR_CTRL_PACER_MASK; if (cmd->convert_src == TRIG_TIMER) { comedi_8254_update_divisors(dev->pacer); comedi_8254_pacer_enable(dev->pacer, 1, 2, true); - devpriv->control_state |= INT_PACER; + devpriv->intr_ctrl |= DAS16M1_INTR_CTRL_PACER_INT; } else { /* TRIG_EXT */ - devpriv->control_state |= EXT_PACER; + devpriv->intr_ctrl |= DAS16M1_INTR_CTRL_PACER_EXT; } /* set control & status register */ byte = 0; - /* if we are using external start trigger (also board dislikes having - * both start and conversion triggers external simultaneously) */ + /* + * If we are using external start trigger (also board dislikes having + * both start and conversion triggers external simultaneously). + */ if (cmd->start_src == TRIG_EXT && cmd->convert_src != TRIG_EXT) - byte |= EXT_TRIG_BIT; + byte |= DAS16M1_CS_EXT_TRIG; - outb(byte, dev->iobase + DAS16M1_CS); - /* clear interrupt bit */ - outb(0, dev->iobase + DAS16M1_CLEAR_INTR); + outb(byte, dev->iobase + DAS16M1_CS_REG); + + /* clear interrupt */ + outb(0, dev->iobase + DAS16M1_CLR_INTR_REG); - devpriv->control_state |= INTE; - outb(devpriv->control_state, dev->iobase + DAS16M1_INTR_CONTROL); + devpriv->intr_ctrl |= DAS16M1_INTR_CTRL_INTE; + outb(devpriv->intr_ctrl, dev->iobase + DAS16M1_INTR_CTRL_REG); return 0; } -static int das16m1_cancel(struct comedi_device *dev, struct comedi_subdevice *s) +static int das16m1_ai_cancel(struct comedi_device *dev, + struct comedi_subdevice *s) { - struct das16m1_private_struct *devpriv = dev->private; + struct das16m1_private *devpriv = dev->private; - devpriv->control_state &= ~INTE & ~PACER_MASK; - outb(devpriv->control_state, dev->iobase + DAS16M1_INTR_CONTROL); + /* disable interrupts and pacer */ + devpriv->intr_ctrl &= ~(DAS16M1_INTR_CTRL_INTE | + DAS16M1_INTR_CTRL_PACER_MASK); + outb(devpriv->intr_ctrl, dev->iobase + DAS16M1_INTR_CTRL_REG); return 0; } @@ -327,67 +322,58 @@ static int das16m1_ai_eoc(struct comedi_device *dev, { unsigned int status; - status = inb(dev->iobase + DAS16M1_CS); - if (status & IRQDATA) + status = inb(dev->iobase + DAS16M1_CS_REG); + if (status & DAS16M1_CS_IRQDATA) return 0; return -EBUSY; } -static int das16m1_ai_rinsn(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das16m1_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - struct das16m1_private_struct *devpriv = dev->private; int ret; - int n; - int byte; - - /* disable interrupts and internal pacer */ - devpriv->control_state &= ~INTE & ~PACER_MASK; - outb(devpriv->control_state, dev->iobase + DAS16M1_INTR_CONTROL); - - /* setup channel/gain queue */ - outb(0, dev->iobase + DAS16M1_QUEUE_ADDR); - byte = - Q_CHAN(CR_CHAN(insn->chanspec)) | Q_RANGE(CR_RANGE(insn->chanspec)); - outb(byte, dev->iobase + DAS16M1_QUEUE_DATA); - - for (n = 0; n < insn->n; n++) { - /* clear IRQDATA bit */ - outb(0, dev->iobase + DAS16M1_CLEAR_INTR); + int i; + + das16m1_ai_set_queue(dev, &insn->chanspec, 1); + + for (i = 0; i < insn->n; i++) { + unsigned short val; + + /* clear interrupt */ + outb(0, dev->iobase + DAS16M1_CLR_INTR_REG); /* trigger conversion */ - outb(0, dev->iobase); + outb(0, dev->iobase + DAS16M1_AI_REG); ret = comedi_timeout(dev, s, insn, das16m1_ai_eoc, 0); if (ret) return ret; - data[n] = munge_sample(inw(dev->iobase)); + val = inw(dev->iobase + DAS16M1_AI_REG); + data[i] = DAS16M1_AI_TO_SAMPLE(val); } - return n; + return insn->n; } -static int das16m1_di_rbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int das16m1_di_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - unsigned int bits; - - bits = inb(dev->iobase + DAS16M1_DIO) & 0xf; - data[1] = bits; - data[0] = 0; + data[1] = inb(dev->iobase + DAS16M1_DI_REG) & 0xf; return insn->n; } -static int das16m1_do_wbits(struct comedi_device *dev, - struct comedi_subdevice *s, - struct comedi_insn *insn, - unsigned int *data) +static int das16m1_do_insn_bits(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { if (comedi_dio_update_state(s, data)) - outb(s->state, dev->iobase + DAS16M1_DIO); + outb(s->state, dev->iobase + DAS16M1_DO_REG); data[1] = s->state; @@ -396,33 +382,33 @@ static int das16m1_do_wbits(struct comedi_device *dev, static void das16m1_handler(struct comedi_device *dev, unsigned int status) { - struct das16m1_private_struct *devpriv = dev->private; - struct comedi_subdevice *s; - struct comedi_async *async; - struct comedi_cmd *cmd; + struct das16m1_private *devpriv = dev->private; + struct comedi_subdevice *s = dev->read_subdev; + struct comedi_async *async = s->async; + struct comedi_cmd *cmd = &async->cmd; u16 num_samples; u16 hw_counter; - s = dev->read_subdev; - async = s->async; - cmd = &async->cmd; - /* figure out how many samples are in fifo */ hw_counter = comedi_8254_read(devpriv->counter, 1); - /* make sure hardware counter reading is not bogus due to initial value - * not having been loaded yet */ + /* + * Make sure hardware counter reading is not bogus due to initial + * value not having been loaded yet. + */ if (devpriv->adc_count == 0 && hw_counter == devpriv->initial_hw_count) { num_samples = 0; } else { - /* The calculation of num_samples looks odd, but it uses the + /* + * The calculation of num_samples looks odd, but it uses the * following facts. 16 bit hardware counter is initialized with * value of zero (which really means 0x1000). The counter * decrements by one on each conversion (when the counter * decrements from zero it goes to 0xffff). num_samples is a * 16 bit variable, so it will roll over in a similar fashion * to the hardware counter. Work it out, and this is what you - * get. */ + * get. + */ num_samples = -hw_counter - devpriv->adc_count; } /* check if we only need some of the points */ @@ -431,10 +417,9 @@ static void das16m1_handler(struct comedi_device *dev, unsigned int status) num_samples = cmd->stop_arg * cmd->chanlist_len; } /* make sure we dont try to get too many points if fifo has overrun */ - if (num_samples > FIFO_SIZE) - num_samples = FIFO_SIZE; + if (num_samples > DAS16M1_AI_FIFO_SZ) + num_samples = DAS16M1_AI_FIFO_SZ; insw(dev->iobase, devpriv->ai_buffer, num_samples); - munge_sample_array(devpriv->ai_buffer, num_samples); comedi_buf_write_samples(s, devpriv->ai_buffer, num_samples); devpriv->adc_count += num_samples; @@ -445,9 +430,11 @@ static void das16m1_handler(struct comedi_device *dev, unsigned int status) } } - /* this probably won't catch overruns since the card doesn't generate - * overrun interrupts, but we might as well try */ - if (status & OVRUN) { + /* + * This probably won't catch overruns since the card doesn't generate + * overrun interrupts, but we might as well try. + */ + if (status & DAS16M1_CS_OVRUN) { async->events |= COMEDI_CB_ERROR; dev_err(dev->class_dev, "fifo overflow\n"); } @@ -455,14 +442,15 @@ static void das16m1_handler(struct comedi_device *dev, unsigned int status) comedi_handle_events(dev, s); } -static int das16m1_poll(struct comedi_device *dev, struct comedi_subdevice *s) +static int das16m1_ai_poll(struct comedi_device *dev, + struct comedi_subdevice *s) { unsigned long flags; unsigned int status; /* prevent race with interrupt handler */ spin_lock_irqsave(&dev->spinlock, flags); - status = inb(dev->iobase + DAS16M1_CS); + status = inb(dev->iobase + DAS16M1_CS_REG); das16m1_handler(dev, status); spin_unlock_irqrestore(&dev->spinlock, flags); @@ -481,9 +469,9 @@ static irqreturn_t das16m1_interrupt(int irq, void *d) /* prevent race with comedi_poll() */ spin_lock(&dev->spinlock); - status = inb(dev->iobase + DAS16M1_CS); + status = inb(dev->iobase + DAS16M1_CS_REG); - if ((status & (IRQDATA | OVRUN)) == 0) { + if ((status & (DAS16M1_CS_IRQDATA | DAS16M1_CS_OVRUN)) == 0) { dev_err(dev->class_dev, "spurious interrupt\n"); spin_unlock(&dev->spinlock); return IRQ_NONE; @@ -492,7 +480,7 @@ static irqreturn_t das16m1_interrupt(int irq, void *d) das16m1_handler(dev, status); /* clear interrupt */ - outb(0, dev->iobase + DAS16M1_CLEAR_INTR); + outb(0, dev->iobase + DAS16M1_CLR_INTR_REG); spin_unlock(&dev->spinlock); return IRQ_HANDLED; @@ -522,15 +510,10 @@ static int das16m1_irq_bits(unsigned int irq) } } -/* - * Options list: - * 0 I/O base - * 1 IRQ - */ static int das16m1_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - struct das16m1_private_struct *devpriv; + struct das16m1_private *devpriv; struct comedi_subdevice *s; int ret; @@ -541,12 +524,12 @@ static int das16m1_attach(struct comedi_device *dev, ret = comedi_request_region(dev, it->options[0], 0x10); if (ret) return ret; - /* Request an additional region for the 8255 */ - ret = __comedi_request_region(dev, dev->iobase + DAS16M1_82C55, + /* Request an additional region for the 8255 and 3rd 8254 */ + ret = __comedi_request_region(dev, dev->iobase + DAS16M1_8255_IOBASE, DAS16M1_SIZE2); if (ret) return ret; - devpriv->extra_iobase = dev->iobase + DAS16M1_82C55; + devpriv->extra_iobase = dev->iobase + DAS16M1_8255_IOBASE; /* only irqs 2, 3, 4, 5, 6, 7, 10, 11, 12, 14, and 15 are valid */ if ((1 << it->options[1]) & 0xdcfc) { @@ -556,12 +539,12 @@ static int das16m1_attach(struct comedi_device *dev, dev->irq = it->options[1]; } - dev->pacer = comedi_8254_init(dev->iobase + DAS16M1_8254_SECOND, + dev->pacer = comedi_8254_init(dev->iobase + DAS16M1_8254_IOBASE2, I8254_OSC_BASE_10MHZ, I8254_IO8, 0); if (!dev->pacer) return -ENOMEM; - devpriv->counter = comedi_8254_init(dev->iobase + DAS16M1_8254_FIRST, + devpriv->counter = comedi_8254_init(dev->iobase + DAS16M1_8254_IOBASE1, 0, I8254_IO8, 0); if (!devpriv->counter) return -ENOMEM; @@ -570,61 +553,62 @@ static int das16m1_attach(struct comedi_device *dev, if (ret) return ret; + /* Analog Input subdevice */ s = &dev->subdevices[0]; - /* ai */ - s->type = COMEDI_SUBD_AI; - s->subdev_flags = SDF_READABLE | SDF_DIFF; - s->n_chan = 8; - s->maxdata = (1 << 12) - 1; - s->range_table = &range_das16m1; - s->insn_read = das16m1_ai_rinsn; + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | SDF_DIFF; + s->n_chan = 8; + s->maxdata = 0x0fff; + s->range_table = &range_das16m1; + s->insn_read = das16m1_ai_insn_read; if (dev->irq) { dev->read_subdev = s; - s->subdev_flags |= SDF_CMD_READ; - s->len_chanlist = 256; - s->do_cmdtest = das16m1_cmd_test; - s->do_cmd = das16m1_cmd_exec; - s->cancel = das16m1_cancel; - s->poll = das16m1_poll; + s->subdev_flags |= SDF_CMD_READ; + s->len_chanlist = 256; + s->do_cmdtest = das16m1_ai_cmdtest; + s->do_cmd = das16m1_ai_cmd; + s->cancel = das16m1_ai_cancel; + s->poll = das16m1_ai_poll; + s->munge = das16m1_ai_munge; } + /* Digital Input subdevice */ s = &dev->subdevices[1]; - /* di */ - s->type = COMEDI_SUBD_DI; - s->subdev_flags = SDF_READABLE; - s->n_chan = 4; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = das16m1_di_rbits; - + s->type = COMEDI_SUBD_DI; + s->subdev_flags = SDF_READABLE; + s->n_chan = 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = das16m1_di_insn_bits; + + /* Digital Output subdevice */ s = &dev->subdevices[2]; - /* do */ - s->type = COMEDI_SUBD_DO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 4; - s->maxdata = 1; - s->range_table = &range_digital; - s->insn_bits = das16m1_do_wbits; - + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 4; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = das16m1_do_insn_bits; + + /* Digital I/O subdevice (8255) */ s = &dev->subdevices[3]; - /* 8255 */ - ret = subdev_8255_init(dev, s, NULL, DAS16M1_82C55); + ret = subdev_8255_init(dev, s, NULL, DAS16M1_8255_IOBASE); if (ret) return ret; /* initialize digital output lines */ - outb(0, dev->iobase + DAS16M1_DIO); + outb(0, dev->iobase + DAS16M1_DO_REG); /* set the interrupt level */ - devpriv->control_state = das16m1_irq_bits(dev->irq) << 4; - outb(devpriv->control_state, dev->iobase + DAS16M1_INTR_CONTROL); + devpriv->intr_ctrl = DAS16M1_INTR_CTRL_IRQ(das16m1_irq_bits(dev->irq)); + outb(devpriv->intr_ctrl, dev->iobase + DAS16M1_INTR_CTRL_REG); return 0; } static void das16m1_detach(struct comedi_device *dev) { - struct das16m1_private_struct *devpriv = dev->private; + struct das16m1_private *devpriv = dev->private; if (devpriv) { if (devpriv->extra_iobase) @@ -643,5 +627,5 @@ static struct comedi_driver das16m1_driver = { module_comedi_driver(das16m1_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for CIO-DAS16/M1 ISA cards"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/das6402.c b/drivers/staging/comedi/drivers/das6402.c index 1701294b7..0fdf5e021 100644 --- a/drivers/staging/comedi/drivers/das6402.c +++ b/drivers/staging/comedi/drivers/das6402.c @@ -50,48 +50,50 @@ #define DAS6402_AO_LSB_REG(x) (0x04 + ((x) * 2)) #define DAS6402_AO_MSB_REG(x) (0x05 + ((x) * 2)) #define DAS6402_STATUS_REG 0x08 -#define DAS6402_STATUS_FFNE (1 << 0) -#define DAS6402_STATUS_FHALF (1 << 1) -#define DAS6402_STATUS_FFULL (1 << 2) -#define DAS6402_STATUS_XINT (1 << 3) -#define DAS6402_STATUS_INT (1 << 4) -#define DAS6402_STATUS_XTRIG (1 << 5) -#define DAS6402_STATUS_INDGT (1 << 6) -#define DAS6402_STATUS_10MHZ (1 << 7) -#define DAS6402_STATUS_W_CLRINT (1 << 0) -#define DAS6402_STATUS_W_CLRXTR (1 << 1) -#define DAS6402_STATUS_W_CLRXIN (1 << 2) -#define DAS6402_STATUS_W_EXTEND (1 << 4) -#define DAS6402_STATUS_W_ARMED (1 << 5) -#define DAS6402_STATUS_W_POSTMODE (1 << 6) -#define DAS6402_STATUS_W_10MHZ (1 << 7) +#define DAS6402_STATUS_FFNE BIT(0) +#define DAS6402_STATUS_FHALF BIT(1) +#define DAS6402_STATUS_FFULL BIT(2) +#define DAS6402_STATUS_XINT BIT(3) +#define DAS6402_STATUS_INT BIT(4) +#define DAS6402_STATUS_XTRIG BIT(5) +#define DAS6402_STATUS_INDGT BIT(6) +#define DAS6402_STATUS_10MHZ BIT(7) +#define DAS6402_STATUS_W_CLRINT BIT(0) +#define DAS6402_STATUS_W_CLRXTR BIT(1) +#define DAS6402_STATUS_W_CLRXIN BIT(2) +#define DAS6402_STATUS_W_EXTEND BIT(4) +#define DAS6402_STATUS_W_ARMED BIT(5) +#define DAS6402_STATUS_W_POSTMODE BIT(6) +#define DAS6402_STATUS_W_10MHZ BIT(7) #define DAS6402_CTRL_REG 0x09 -#define DAS6402_CTRL_SOFT_TRIG (0 << 0) -#define DAS6402_CTRL_EXT_FALL_TRIG (1 << 0) -#define DAS6402_CTRL_EXT_RISE_TRIG (2 << 0) -#define DAS6402_CTRL_PACER_TRIG (3 << 0) -#define DAS6402_CTRL_BURSTEN (1 << 2) -#define DAS6402_CTRL_XINTE (1 << 3) +#define DAS6402_CTRL_TRIG(x) ((x) << 0) +#define DAS6402_CTRL_SOFT_TRIG DAS6402_CTRL_TRIG(0) +#define DAS6402_CTRL_EXT_FALL_TRIG DAS6402_CTRL_TRIG(1) +#define DAS6402_CTRL_EXT_RISE_TRIG DAS6402_CTRL_TRIG(2) +#define DAS6402_CTRL_PACER_TRIG DAS6402_CTRL_TRIG(3) +#define DAS6402_CTRL_BURSTEN BIT(2) +#define DAS6402_CTRL_XINTE BIT(3) #define DAS6402_CTRL_IRQ(x) ((x) << 4) -#define DAS6402_CTRL_INTE (1 << 7) +#define DAS6402_CTRL_INTE BIT(7) #define DAS6402_TRIG_REG 0x0a -#define DAS6402_TRIG_TGEN (1 << 0) -#define DAS6402_TRIG_TGSEL (1 << 1) -#define DAS6402_TRIG_TGPOL (1 << 2) -#define DAS6402_TRIG_PRETRIG (1 << 3) +#define DAS6402_TRIG_TGEN BIT(0) +#define DAS6402_TRIG_TGSEL BIT(1) +#define DAS6402_TRIG_TGPOL BIT(2) +#define DAS6402_TRIG_PRETRIG BIT(3) #define DAS6402_AO_RANGE(_chan, _range) ((_range) << ((_chan) ? 6 : 4)) #define DAS6402_AO_RANGE_MASK(_chan) (3 << ((_chan) ? 6 : 4)) #define DAS6402_MODE_REG 0x0b -#define DAS6402_MODE_RANGE(x) ((x) << 0) -#define DAS6402_MODE_POLLED (0 << 2) -#define DAS6402_MODE_FIFONEPTY (1 << 2) -#define DAS6402_MODE_FIFOHFULL (2 << 2) -#define DAS6402_MODE_EOB (3 << 2) -#define DAS6402_MODE_ENHANCED (1 << 4) -#define DAS6402_MODE_SE (1 << 5) -#define DAS6402_MODE_UNI (1 << 6) -#define DAS6402_MODE_DMA1 (0 << 7) -#define DAS6402_MODE_DMA3 (1 << 7) +#define DAS6402_MODE_RANGE(x) ((x) << 2) +#define DAS6402_MODE_POLLED DAS6402_MODE_RANGE(0) +#define DAS6402_MODE_FIFONEPTY DAS6402_MODE_RANGE(1) +#define DAS6402_MODE_FIFOHFULL DAS6402_MODE_RANGE(2) +#define DAS6402_MODE_EOB DAS6402_MODE_RANGE(3) +#define DAS6402_MODE_ENHANCED BIT(4) +#define DAS6402_MODE_SE BIT(5) +#define DAS6402_MODE_UNI BIT(6) +#define DAS6402_MODE_DMA(x) ((x) << 7) +#define DAS6402_MODE_DMA1 DAS6402_MODE_DMA(0) +#define DAS6402_MODE_DMA3 DAS6402_MODE_DMA(1) #define DAS6402_TIMER_BASE 0x0c static const struct comedi_lrange das6402_ai_ranges = { diff --git a/drivers/staging/comedi/drivers/das800.c b/drivers/staging/comedi/drivers/das800.c index b02f12201..fd4cb4911 100644 --- a/drivers/staging/comedi/drivers/das800.c +++ b/drivers/staging/comedi/drivers/das800.c @@ -1,56 +1,56 @@ /* - comedi/drivers/das800.c - Driver for Keitley das800 series boards and compatibles - Copyright (C) 2000 Frank Mori Hess <fmhess@users.sourceforge.net> - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2000 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/das800.c + * Driver for Keitley das800 series boards and compatibles + * Copyright (C) 2000 Frank Mori Hess <fmhess@users.sourceforge.net> + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2000 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* -Driver: das800 -Description: Keithley Metrabyte DAS800 (& compatibles) -Author: Frank Mori Hess <fmhess@users.sourceforge.net> -Devices: [Keithley Metrabyte] DAS-800 (das-800), DAS-801 (das-801), - DAS-802 (das-802), - [Measurement Computing] CIO-DAS800 (cio-das800), - CIO-DAS801 (cio-das801), CIO-DAS802 (cio-das802), - CIO-DAS802/16 (cio-das802/16) -Status: works, cio-das802/16 untested - email me if you have tested it - -Configuration options: - [0] - I/O port base address - [1] - IRQ (optional, required for timed or externally triggered conversions) - -Notes: - IRQ can be omitted, although the cmd interface will not work without it. - - All entries in the channel/gain list must use the same gain and be - consecutive channels counting upwards in channel number (these are - hardware limitations.) - - I've never tested the gain setting stuff since I only have a - DAS-800 board with fixed gain. - - The cio-das802/16 does not have a fifo-empty status bit! Therefore - only fifo-half-full transfers are possible with this card. - -cmd triggers supported: - start_src: TRIG_NOW | TRIG_EXT - scan_begin_src: TRIG_FOLLOW - scan_end_src: TRIG_COUNT - convert_src: TRIG_TIMER | TRIG_EXT - stop_src: TRIG_NONE | TRIG_COUNT -*/ + * Driver: das800 + * Description: Keithley Metrabyte DAS800 (& compatibles) + * Author: Frank Mori Hess <fmhess@users.sourceforge.net> + * Devices: [Keithley Metrabyte] DAS-800 (das-800), DAS-801 (das-801), + * DAS-802 (das-802), + * [Measurement Computing] CIO-DAS800 (cio-das800), + * CIO-DAS801 (cio-das801), CIO-DAS802 (cio-das802), + * CIO-DAS802/16 (cio-das802/16) + * Status: works, cio-das802/16 untested - email me if you have tested it + * + * Configuration options: + * [0] - I/O port base address + * [1] - IRQ (optional, required for timed or externally triggered conversions) + * + * Notes: + * IRQ can be omitted, although the cmd interface will not work without it. + * + * All entries in the channel/gain list must use the same gain and be + * consecutive channels counting upwards in channel number (these are + * hardware limitations.) + * + * I've never tested the gain setting stuff since I only have a + * DAS-800 board with fixed gain. + * + * The cio-das802/16 does not have a fifo-empty status bit! Therefore + * only fifo-half-full transfers are possible with this card. + * + * cmd triggers supported: + * start_src: TRIG_NOW | TRIG_EXT + * scan_begin_src: TRIG_FOLLOW + * scan_end_src: TRIG_COUNT + * convert_src: TRIG_TIMER | TRIG_EXT + * stop_src: TRIG_NONE | TRIG_COUNT + */ #include <linux/module.h> #include <linux/interrupt.h> @@ -218,7 +218,7 @@ struct das800_private { }; static void das800_ind_write(struct comedi_device *dev, - unsigned val, unsigned reg) + unsigned int val, unsigned int reg) { /* * Select dev->iobase + 2 to be desired register @@ -228,7 +228,7 @@ static void das800_ind_write(struct comedi_device *dev, outb(val, dev->iobase + 2); } -static unsigned das800_ind_read(struct comedi_device *dev, unsigned reg) +static unsigned int das800_ind_read(struct comedi_device *dev, unsigned int reg) { /* * Select dev->iobase + 7 to be desired register diff --git a/drivers/staging/comedi/drivers/dmm32at.c b/drivers/staging/comedi/drivers/dmm32at.c index 958c0d4aa..b8606ded0 100644 --- a/drivers/staging/comedi/drivers/dmm32at.c +++ b/drivers/staging/comedi/drivers/dmm32at.c @@ -46,73 +46,75 @@ #define DMM32AT_AI_START_CONV_REG 0x00 #define DMM32AT_AI_LSB_REG 0x00 #define DMM32AT_AUX_DOUT_REG 0x01 -#define DMM32AT_AUX_DOUT2 (1 << 2) /* J3.42 - OUT2 (OUT2EN) */ -#define DMM32AT_AUX_DOUT1 (1 << 1) /* J3.43 */ -#define DMM32AT_AUX_DOUT0 (1 << 0) /* J3.44 - OUT0 (OUT0EN) */ +#define DMM32AT_AUX_DOUT2 BIT(2) /* J3.42 - OUT2 (OUT2EN) */ +#define DMM32AT_AUX_DOUT1 BIT(1) /* J3.43 */ +#define DMM32AT_AUX_DOUT0 BIT(0) /* J3.44 - OUT0 (OUT0EN) */ #define DMM32AT_AI_MSB_REG 0x01 #define DMM32AT_AI_LO_CHAN_REG 0x02 #define DMM32AT_AI_HI_CHAN_REG 0x03 #define DMM32AT_AUX_DI_REG 0x04 -#define DMM32AT_AUX_DI_DACBUSY (1 << 7) -#define DMM32AT_AUX_DI_CALBUSY (1 << 6) -#define DMM32AT_AUX_DI3 (1 << 3) /* J3.45 - ADCLK (CLKSEL) */ -#define DMM32AT_AUX_DI2 (1 << 2) /* J3.46 - GATE12 (GT12EN) */ -#define DMM32AT_AUX_DI1 (1 << 1) /* J3.47 - GATE0 (GT0EN) */ -#define DMM32AT_AUX_DI0 (1 << 0) /* J3.48 - CLK0 (SRC0) */ +#define DMM32AT_AUX_DI_DACBUSY BIT(7) +#define DMM32AT_AUX_DI_CALBUSY BIT(6) +#define DMM32AT_AUX_DI3 BIT(3) /* J3.45 - ADCLK (CLKSEL) */ +#define DMM32AT_AUX_DI2 BIT(2) /* J3.46 - GATE12 (GT12EN) */ +#define DMM32AT_AUX_DI1 BIT(1) /* J3.47 - GATE0 (GT0EN) */ +#define DMM32AT_AUX_DI0 BIT(0) /* J3.48 - CLK0 (SRC0) */ #define DMM32AT_AO_LSB_REG 0x04 #define DMM32AT_AO_MSB_REG 0x05 #define DMM32AT_AO_MSB_DACH(x) ((x) << 6) #define DMM32AT_FIFO_DEPTH_REG 0x06 #define DMM32AT_FIFO_CTRL_REG 0x07 -#define DMM32AT_FIFO_CTRL_FIFOEN (1 << 3) -#define DMM32AT_FIFO_CTRL_SCANEN (1 << 2) -#define DMM32AT_FIFO_CTRL_FIFORST (1 << 1) +#define DMM32AT_FIFO_CTRL_FIFOEN BIT(3) +#define DMM32AT_FIFO_CTRL_SCANEN BIT(2) +#define DMM32AT_FIFO_CTRL_FIFORST BIT(1) #define DMM32AT_FIFO_STATUS_REG 0x07 -#define DMM32AT_FIFO_STATUS_EF (1 << 7) -#define DMM32AT_FIFO_STATUS_HF (1 << 6) -#define DMM32AT_FIFO_STATUS_FF (1 << 5) -#define DMM32AT_FIFO_STATUS_OVF (1 << 4) -#define DMM32AT_FIFO_STATUS_FIFOEN (1 << 3) -#define DMM32AT_FIFO_STATUS_SCANEN (1 << 2) +#define DMM32AT_FIFO_STATUS_EF BIT(7) +#define DMM32AT_FIFO_STATUS_HF BIT(6) +#define DMM32AT_FIFO_STATUS_FF BIT(5) +#define DMM32AT_FIFO_STATUS_OVF BIT(4) +#define DMM32AT_FIFO_STATUS_FIFOEN BIT(3) +#define DMM32AT_FIFO_STATUS_SCANEN BIT(2) #define DMM32AT_FIFO_STATUS_PAGE_MASK (3 << 0) #define DMM32AT_CTRL_REG 0x08 -#define DMM32AT_CTRL_RESETA (1 << 5) -#define DMM32AT_CTRL_RESETD (1 << 4) -#define DMM32AT_CTRL_INTRST (1 << 3) -#define DMM32AT_CTRL_PAGE_8254 (0 << 0) -#define DMM32AT_CTRL_PAGE_8255 (1 << 0) -#define DMM32AT_CTRL_PAGE_CALIB (3 << 0) +#define DMM32AT_CTRL_RESETA BIT(5) +#define DMM32AT_CTRL_RESETD BIT(4) +#define DMM32AT_CTRL_INTRST BIT(3) +#define DMM32AT_CTRL_PAGE(x) ((x) << 0) +#define DMM32AT_CTRL_PAGE_8254 DMM32AT_CTRL_PAGE(0) +#define DMM32AT_CTRL_PAGE_8255 DMM32AT_CTRL_PAGE(1) +#define DMM32AT_CTRL_PAGE_CALIB DMM32AT_CTRL_PAGE(3) #define DMM32AT_AI_STATUS_REG 0x08 -#define DMM32AT_AI_STATUS_STS (1 << 7) -#define DMM32AT_AI_STATUS_SD1 (1 << 6) -#define DMM32AT_AI_STATUS_SD0 (1 << 5) +#define DMM32AT_AI_STATUS_STS BIT(7) +#define DMM32AT_AI_STATUS_SD1 BIT(6) +#define DMM32AT_AI_STATUS_SD0 BIT(5) #define DMM32AT_AI_STATUS_ADCH_MASK (0x1f << 0) #define DMM32AT_INTCLK_REG 0x09 -#define DMM32AT_INTCLK_ADINT (1 << 7) -#define DMM32AT_INTCLK_DINT (1 << 6) -#define DMM32AT_INTCLK_TINT (1 << 5) -#define DMM32AT_INTCLK_CLKEN (1 << 1) /* 1=see below 0=software */ -#define DMM32AT_INTCLK_CLKSEL (1 << 0) /* 1=OUT2 0=EXTCLK */ +#define DMM32AT_INTCLK_ADINT BIT(7) +#define DMM32AT_INTCLK_DINT BIT(6) +#define DMM32AT_INTCLK_TINT BIT(5) +#define DMM32AT_INTCLK_CLKEN BIT(1) /* 1=see below 0=software */ +#define DMM32AT_INTCLK_CLKSEL BIT(0) /* 1=OUT2 0=EXTCLK */ #define DMM32AT_CTRDIO_CFG_REG 0x0a -#define DMM32AT_CTRDIO_CFG_FREQ12 (1 << 7) /* CLK12 1=100KHz 0=10MHz */ -#define DMM32AT_CTRDIO_CFG_FREQ0 (1 << 6) /* CLK0 1=10KHz 0=10MHz */ -#define DMM32AT_CTRDIO_CFG_OUT2EN (1 << 5) /* J3.42 1=OUT2 is DOUT2 */ -#define DMM32AT_CTRDIO_CFG_OUT0EN (1 << 4) /* J3,44 1=OUT0 is DOUT0 */ -#define DMM32AT_CTRDIO_CFG_GT0EN (1 << 2) /* J3.47 1=DIN1 is GATE0 */ -#define DMM32AT_CTRDIO_CFG_SRC0 (1 << 1) /* CLK0 is 0=FREQ0 1=J3.48 */ -#define DMM32AT_CTRDIO_CFG_GT12EN (1 << 0) /* J3.46 1=DIN2 is GATE12 */ +#define DMM32AT_CTRDIO_CFG_FREQ12 BIT(7) /* CLK12 1=100KHz 0=10MHz */ +#define DMM32AT_CTRDIO_CFG_FREQ0 BIT(6) /* CLK0 1=10KHz 0=10MHz */ +#define DMM32AT_CTRDIO_CFG_OUT2EN BIT(5) /* J3.42 1=OUT2 is DOUT2 */ +#define DMM32AT_CTRDIO_CFG_OUT0EN BIT(4) /* J3,44 1=OUT0 is DOUT0 */ +#define DMM32AT_CTRDIO_CFG_GT0EN BIT(2) /* J3.47 1=DIN1 is GATE0 */ +#define DMM32AT_CTRDIO_CFG_SRC0 BIT(1) /* CLK0 is 0=FREQ0 1=J3.48 */ +#define DMM32AT_CTRDIO_CFG_GT12EN BIT(0) /* J3.46 1=DIN2 is GATE12 */ #define DMM32AT_AI_CFG_REG 0x0b -#define DMM32AT_AI_CFG_SCINT_20US (0 << 4) -#define DMM32AT_AI_CFG_SCINT_15US (1 << 4) -#define DMM32AT_AI_CFG_SCINT_10US (2 << 4) -#define DMM32AT_AI_CFG_SCINT_5US (3 << 4) -#define DMM32AT_AI_CFG_RANGE (1 << 3) /* 0=5V 1=10V */ -#define DMM32AT_AI_CFG_ADBU (1 << 2) /* 0=bipolar 1=unipolar */ +#define DMM32AT_AI_CFG_SCINT(x) ((x) << 4) +#define DMM32AT_AI_CFG_SCINT_20US DMM32AT_AI_CFG_SCINT(0) +#define DMM32AT_AI_CFG_SCINT_15US DMM32AT_AI_CFG_SCINT(1) +#define DMM32AT_AI_CFG_SCINT_10US DMM32AT_AI_CFG_SCINT(2) +#define DMM32AT_AI_CFG_SCINT_5US DMM32AT_AI_CFG_SCINT(3) +#define DMM32AT_AI_CFG_RANGE BIT(3) /* 0=5V 1=10V */ +#define DMM32AT_AI_CFG_ADBU BIT(2) /* 0=bipolar 1=unipolar */ #define DMM32AT_AI_CFG_GAIN(x) ((x) << 0) #define DMM32AT_AI_READBACK_REG 0x0b -#define DMM32AT_AI_READBACK_WAIT (1 << 7) /* DMM32AT_AI_STATUS_STS */ -#define DMM32AT_AI_READBACK_RANGE (1 << 3) -#define DMM32AT_AI_READBACK_ADBU (1 << 2) +#define DMM32AT_AI_READBACK_WAIT BIT(7) /* DMM32AT_AI_STATUS_STS */ +#define DMM32AT_AI_READBACK_RANGE BIT(3) +#define DMM32AT_AI_READBACK_ADBU BIT(2) #define DMM32AT_AI_READBACK_GAIN_MASK (3 << 0) #define DMM32AT_CLK1 0x0d diff --git a/drivers/staging/comedi/drivers/dt2801.c b/drivers/staging/comedi/drivers/dt2801.c index 6c7b4d27c..c2ce1eb87 100644 --- a/drivers/staging/comedi/drivers/dt2801.c +++ b/drivers/staging/comedi/drivers/dt2801.c @@ -4,30 +4,30 @@ * */ /* -Driver: dt2801 -Description: Data Translation DT2801 series and DT01-EZ -Author: ds -Status: works -Devices: [Data Translation] DT2801 (dt2801), DT2801-A, DT2801/5716A, - DT2805, DT2805/5716A, DT2808, DT2818, DT2809, DT01-EZ - -This driver can autoprobe the type of board. - -Configuration options: - [0] - I/O port base address - [1] - unused - [2] - A/D reference 0=differential, 1=single-ended - [3] - A/D range - 0 = [-10, 10] - 1 = [0,10] - [4] - D/A 0 range - 0 = [-10, 10] - 1 = [-5,5] - 2 = [-2.5,2.5] - 3 = [0,10] - 4 = [0,5] - [5] - D/A 1 range (same choices) -*/ + * Driver: dt2801 + * Description: Data Translation DT2801 series and DT01-EZ + * Author: ds + * Status: works + * Devices: [Data Translation] DT2801 (dt2801), DT2801-A, DT2801/5716A, + * DT2805, DT2805/5716A, DT2808, DT2818, DT2809, DT01-EZ + * + * This driver can autoprobe the type of board. + * + * Configuration options: + * [0] - I/O port base address + * [1] - unused + * [2] - A/D reference 0=differential, 1=single-ended + * [3] - A/D range + * 0 = [-10, 10] + * 1 = [0,10] + * [4] - D/A 0 range + * 0 = [-10, 10] + * 1 = [-5,5] + * 2 = [-2.5,2.5] + * 3 = [0,10] + * 4 = [0,5] + * [5] - D/A 1 range (same choices) + */ #include <linux/module.h> #include "../comedidev.h" @@ -65,9 +65,10 @@ Configuration options: #define DT_C_SET_AD 0xd #define DT_C_READ_AD 0xe -/* Command modifiers (only used with read/write), EXTTRIG can be - used with some other commands. -*/ +/* + * Command modifiers (only used with read/write), EXTTRIG can be + * used with some other commands. + */ #define DT_MOD_DMA BIT(4) #define DT_MOD_CONT BIT(5) #define DT_MOD_EXTCLK BIT(6) @@ -135,9 +136,10 @@ struct dt2801_board { int dabits; }; -/* Typeid's for the different boards of the DT2801-series - (taken from the test-software, that comes with the board) - */ +/* + * Typeid's for the different boards of the DT2801-series + * (taken from the test-software, that comes with the board) + */ static const struct dt2801_board boardtypes[] = { { .name = "dt2801", @@ -209,15 +211,18 @@ struct dt2801_private { const struct comedi_lrange *dac_range_types[2]; }; -/* These are the low-level routines: - writecommand: write a command to the board - writedata: write data byte - readdata: read data byte +/* + * These are the low-level routines: + * writecommand: write a command to the board + * writedata: write data byte + * readdata: read data byte */ -/* Only checks DataOutReady-flag, not the Ready-flag as it is done - in the examples of the manual. I don't see why this should be - necessary. */ +/* + * Only checks DataOutReady-flag, not the Ready-flag as it is done + * in the examples of the manual. I don't see why this should be + * necessary. + */ static int dt2801_readdata(struct comedi_device *dev, int *data) { int stat = 0; @@ -517,14 +522,14 @@ static int dt2801_dio_insn_config(struct comedi_device *dev, } /* - options: - [0] - i/o base - [1] - unused - [2] - a/d 0=differential, 1=single-ended - [3] - a/d range 0=[-10,10], 1=[0,10] - [4] - dac0 range 0=[-10,10], 1=[-5,5], 2=[-2.5,2.5] 3=[0,10], 4=[0,5] - [5] - dac1 range 0=[-10,10], 1=[-5,5], 2=[-2.5,2.5] 3=[0,10], 4=[0,5] -*/ + * options: + * [0] - i/o base + * [1] - unused + * [2] - a/d 0=differential, 1=single-ended + * [3] - a/d range 0=[-10,10], 1=[0,10] + * [4] - dac0 range 0=[-10,10], 1=[-5,5], 2=[-2.5,2.5] 3=[0,10], 4=[0,5] + * [5] - dac1 range 0=[-10,10], 1=[-5,5], 2=[-2.5,2.5] 3=[0,10], 4=[0,5] + */ static int dt2801_attach(struct comedi_device *dev, struct comedi_devconfig *it) { const struct dt2801_board *board; diff --git a/drivers/staging/comedi/drivers/dt2811.c b/drivers/staging/comedi/drivers/dt2811.c index a80773291..8bbd93814 100644 --- a/drivers/staging/comedi/drivers/dt2811.c +++ b/drivers/staging/comedi/drivers/dt2811.c @@ -1,224 +1,469 @@ /* - comedi/drivers/dt2811.c - Hardware driver for Data Translation DT2811 - - COMEDI - Linux Control and Measurement Device Interface - History: - Base Version - David A. Schleef <ds@schleef.org> - December 1998 - Updated to work. David does not have a DT2811 - board any longer so this was suffering from bitrot. - Updated performed by ... - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + * Comedi driver for Data Translation DT2811 + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ + /* -Driver: dt2811 -Description: Data Translation DT2811 -Author: ds -Devices: [Data Translation] DT2811-PGL (dt2811-pgl), DT2811-PGH (dt2811-pgh) -Status: works - -Configuration options: - [0] - I/O port base address - [1] - IRQ, although this is currently unused - [2] - A/D reference - 0 = signle-ended - 1 = differential - 2 = pseudo-differential (common reference) - [3] - A/D range - 0 = [-5, 5] - 1 = [-2.5, 2.5] - 2 = [0, 5] - [4] - D/A 0 range (same choices) - [4] - D/A 1 range (same choices) -*/ + * Driver: dt2811 + * Description: Data Translation DT2811 + * Author: ds + * Devices: [Data Translation] DT2811-PGL (dt2811-pgl), DT2811-PGH (dt2811-pgh) + * Status: works + * + * Configuration options: + * [0] - I/O port base address + * [1] - IRQ (optional, needed for async command support) + * [2] - A/D reference (# of analog inputs) + * 0 = single-ended (16 channels) + * 1 = differential (8 channels) + * 2 = pseudo-differential (16 channels) + * [3] - A/D range (deprecated, see below) + * [4] - D/A 0 range (deprecated, see below) + * [5] - D/A 1 range (deprecated, see below) + * + * Notes: + * - A/D ranges are not programmable but the gain is. The AI subdevice has + * a range_table containing all the possible analog input range/gain + * options for the dt2811-pgh or dt2811-pgl. Use the range that matches + * your board configuration and the desired gain to correctly convert + * between data values and physical units and to set the correct output + * gain. + * - D/A ranges are not programmable. The AO subdevice has a range_table + * containing all the possible analog output ranges. Use the range + * that matches your board configuration to convert between data + * values and physical units. + */ #include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/delay.h> + #include "../comedidev.h" -static const struct comedi_lrange range_dt2811_pgh_ai_5_unipolar = { - 4, { - UNI_RANGE(5), - UNI_RANGE(2.5), - UNI_RANGE(1.25), - UNI_RANGE(0.625) - } +/* + * Register I/O map + */ +#define DT2811_ADCSR_REG 0x00 /* r/w A/D Control/Status */ +#define DT2811_ADCSR_ADDONE BIT(7) /* r 1=A/D conv done */ +#define DT2811_ADCSR_ADERROR BIT(6) /* r 1=A/D error */ +#define DT2811_ADCSR_ADBUSY BIT(5) /* r 1=A/D busy */ +#define DT2811_ADCSR_CLRERROR BIT(4) +#define DT2811_ADCSR_DMAENB BIT(3) /* r/w 1=dma ena */ +#define DT2811_ADCSR_INTENB BIT(2) /* r/w 1=interupts ena */ +#define DT2811_ADCSR_ADMODE(x) (((x) & 0x3) << 0) + +#define DT2811_ADGCR_REG 0x01 /* r/w A/D Gain/Channel */ +#define DT2811_ADGCR_GAIN(x) (((x) & 0x3) << 6) +#define DT2811_ADGCR_CHAN(x) (((x) & 0xf) << 0) + +#define DT2811_ADDATA_LO_REG 0x02 /* r A/D Data low byte */ +#define DT2811_ADDATA_HI_REG 0x03 /* r A/D Data high byte */ + +#define DT2811_DADATA_LO_REG(x) (0x02 + ((x) * 2)) /* w D/A Data low */ +#define DT2811_DADATA_HI_REG(x) (0x03 + ((x) * 2)) /* w D/A Data high */ + +#define DT2811_DI_REG 0x06 /* r Digital Input Port 0 */ +#define DT2811_DO_REG 0x06 /* w Digital Output Port 1 */ + +#define DT2811_TMRCTR_REG 0x07 /* r/w Timer/Counter */ +#define DT2811_TMRCTR_MANTISSA(x) (((x) & 0x7) << 3) +#define DT2811_TMRCTR_EXPONENT(x) (((x) & 0x7) << 0) + +#define DT2811_OSC_BASE 1666 /* 600 kHz = 1666.6667ns */ + +/* + * Timer frequency control: + * DT2811_TMRCTR_MANTISSA DT2811_TMRCTR_EXPONENT + * val divisor frequency val multiply divisor/divide frequency by + * 0 1 600 kHz 0 1 + * 1 10 60 kHz 1 10 + * 2 2 300 kHz 2 100 + * 3 3 200 kHz 3 1000 + * 4 4 150 kHz 4 10000 + * 5 5 120 kHz 5 100000 + * 6 6 100 kHz 6 1000000 + * 7 12 50 kHz 7 10000000 + */ +const unsigned int dt2811_clk_dividers[] = { + 1, 10, 2, 3, 4, 5, 6, 12 }; -static const struct comedi_lrange range_dt2811_pgh_ai_2_5_bipolar = { - 4, { - BIP_RANGE(2.5), - BIP_RANGE(1.25), - BIP_RANGE(0.625), - BIP_RANGE(0.3125) - } +const unsigned int dt2811_clk_multipliers[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; -static const struct comedi_lrange range_dt2811_pgh_ai_5_bipolar = { - 4, { - BIP_RANGE(5), - BIP_RANGE(2.5), - BIP_RANGE(1.25), - BIP_RANGE(0.625) +/* + * The Analog Input range is set using jumpers on the board. + * + * Input Range W9 W10 + * -5V to +5V In Out + * -2.5V to +2.5V In In + * 0V to +5V Out In + * + * The gain may be set to 1, 2, 4, or 8 (on the dt2811-pgh) or to + * 1, 10, 100, 500 (on the dt2811-pgl). + */ +static const struct comedi_lrange dt2811_pgh_ai_ranges = { + 12, { + BIP_RANGE(5), /* range 0: gain=1 */ + BIP_RANGE(2.5), /* range 1: gain=2 */ + BIP_RANGE(1.25), /* range 2: gain=4 */ + BIP_RANGE(0.625), /* range 3: gain=8 */ + + BIP_RANGE(2.5), /* range 0+4: gain=1 */ + BIP_RANGE(1.25), /* range 1+4: gain=2 */ + BIP_RANGE(0.625), /* range 2+4: gain=4 */ + BIP_RANGE(0.3125), /* range 3+4: gain=8 */ + + UNI_RANGE(5), /* range 0+8: gain=1 */ + UNI_RANGE(2.5), /* range 1+8: gain=2 */ + UNI_RANGE(1.25), /* range 2+8: gain=4 */ + UNI_RANGE(0.625) /* range 3+8: gain=8 */ } }; -static const struct comedi_lrange range_dt2811_pgl_ai_5_unipolar = { - 4, { - UNI_RANGE(5), - UNI_RANGE(0.5), - UNI_RANGE(0.05), - UNI_RANGE(0.01) +static const struct comedi_lrange dt2811_pgl_ai_ranges = { + 12, { + BIP_RANGE(5), /* range 0: gain=1 */ + BIP_RANGE(0.5), /* range 1: gain=10 */ + BIP_RANGE(0.05), /* range 2: gain=100 */ + BIP_RANGE(0.01), /* range 3: gain=500 */ + + BIP_RANGE(2.5), /* range 0+4: gain=1 */ + BIP_RANGE(0.25), /* range 1+4: gain=10 */ + BIP_RANGE(0.025), /* range 2+4: gain=100 */ + BIP_RANGE(0.005), /* range 3+4: gain=500 */ + + UNI_RANGE(5), /* range 0+8: gain=1 */ + UNI_RANGE(0.5), /* range 1+8: gain=10 */ + UNI_RANGE(0.05), /* range 2+8: gain=100 */ + UNI_RANGE(0.01) /* range 3+8: gain=500 */ } }; -static const struct comedi_lrange range_dt2811_pgl_ai_2_5_bipolar = { - 4, { +/* + * The Analog Output range is set per-channel using jumpers on the board. + * + * DAC0 Jumpers DAC1 Jumpers + * Output Range W5 W6 W7 W8 W1 W2 W3 W4 + * -5V to +5V In Out In Out In Out In Out + * -2.5V to +2.5V In Out Out In In Out Out In + * 0 to +5V Out In Out In Out In Out In + */ +static const struct comedi_lrange dt2811_ao_ranges = { + 3, { + BIP_RANGE(5), /* default setting from factory */ BIP_RANGE(2.5), - BIP_RANGE(0.25), - BIP_RANGE(0.025), - BIP_RANGE(0.005) + UNI_RANGE(5) } }; -static const struct comedi_lrange range_dt2811_pgl_ai_5_bipolar = { - 4, { - BIP_RANGE(5), - BIP_RANGE(0.5), - BIP_RANGE(0.05), - BIP_RANGE(0.01) - } +struct dt2811_board { + const char *name; + unsigned int is_pgh:1; }; -/* +static const struct dt2811_board dt2811_boards[] = { + { + .name = "dt2811-pgh", + .is_pgh = 1, + }, { + .name = "dt2811-pgl", + }, +}; - 0x00 ADCSR R/W A/D Control/Status Register - bit 7 - (R) 1 indicates A/D conversion done - reading ADDAT clears bit - (W) ignored - bit 6 - (R) 1 indicates A/D error - (W) ignored - bit 5 - (R) 1 indicates A/D busy, cleared at end - of conversion - (W) ignored - bit 4 - (R) 0 - (W) - bit 3 - (R) 0 - bit 2 - (R/W) 1 indicates interrupts enabled - bits 1,0 - (R/W) mode bits - 00 single conversion on ADGCR load - 01 continuous conversion, internal clock, - (clock enabled on ADGCR load) - 10 continuous conversion, internal clock, - external trigger - 11 continuous conversion, external clock, - external trigger - - 0x01 ADGCR R/W A/D Gain/Channel Register - bit 6,7 - (R/W) gain select - 00 gain=1, both PGH, PGL models - 01 gain=2 PGH, 10 PGL - 10 gain=4 PGH, 100 PGL - 11 gain=8 PGH, 500 PGL - bit 4,5 - reserved - bit 3-0 - (R/W) channel select - channel number from 0-15 - - 0x02,0x03 (R) ADDAT A/D Data Register - (W) DADAT0 D/A Data Register 0 - 0x02 low byte - 0x03 high byte - - 0x04,0x05 (W) DADAT0 D/A Data Register 1 - - 0x06 (R) DIO0 Digital Input Port 0 - (W) DIO1 Digital Output Port 1 - - 0x07 TMRCTR (R/W) Timer/Counter Register - bits 6,7 - reserved - bits 5-3 - Timer frequency control (mantissa) - 543 divisor freqency (kHz) - 000 1 600 - 001 10 60 - 010 2 300 - 011 3 200 - 100 4 150 - 101 5 120 - 110 6 100 - 111 12 50 - bits 2-0 - Timer frequency control (exponent) - 210 multiply divisor/divide frequency by - 000 1 - 001 10 - 010 100 - 011 1000 - 100 10000 - 101 100000 - 110 1000000 - 111 10000000 +struct dt2811_private { + unsigned int ai_divisor; +}; - */ +static unsigned int dt2811_ai_read_sample(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + unsigned int val; -#define TIMEOUT 10000 + val = inb(dev->iobase + DT2811_ADDATA_LO_REG) | + (inb(dev->iobase + DT2811_ADDATA_HI_REG) << 8); -#define DT2811_ADCSR 0 -#define DT2811_ADGCR 1 -#define DT2811_ADDATLO 2 -#define DT2811_ADDATHI 3 -#define DT2811_DADAT0LO 2 -#define DT2811_DADAT0HI 3 -#define DT2811_DADAT1LO 4 -#define DT2811_DADAT1HI 5 -#define DT2811_DIO 6 -#define DT2811_TMRCTR 7 + return val & s->maxdata; +} -/* - * flags - */ +static irqreturn_t dt2811_interrupt(int irq, void *d) +{ + struct comedi_device *dev = d; + struct comedi_subdevice *s = dev->read_subdev; + struct comedi_async *async = s->async; + struct comedi_cmd *cmd = &async->cmd; + unsigned int status; -/* ADCSR */ + if (!dev->attached) + return IRQ_NONE; -#define DT2811_ADDONE 0x80 -#define DT2811_ADERROR 0x40 -#define DT2811_ADBUSY 0x20 -#define DT2811_CLRERROR 0x10 -#define DT2811_INTENB 0x04 -#define DT2811_ADMODE 0x03 + status = inb(dev->iobase + DT2811_ADCSR_REG); -struct dt2811_board { - const char *name; - const struct comedi_lrange *bip_5; - const struct comedi_lrange *bip_2_5; - const struct comedi_lrange *unip_5; -}; + if (status & DT2811_ADCSR_ADERROR) { + async->events |= COMEDI_CB_OVERFLOW; -enum { card_2811_pgh, card_2811_pgl }; + outb(status | DT2811_ADCSR_CLRERROR, + dev->iobase + DT2811_ADCSR_REG); + } -struct dt2811_private { - int ntrig; - int curadchan; - enum { - adc_singleended, adc_diff, adc_pseudo_diff - } adc_mux; - enum { - dac_bipolar_5, dac_bipolar_2_5, dac_unipolar_5 - } dac_range[2]; - const struct comedi_lrange *range_type_list[2]; -}; + if (status & DT2811_ADCSR_ADDONE) { + unsigned short val; -static const struct comedi_lrange *dac_range_types[] = { - &range_bipolar5, - &range_bipolar2_5, - &range_unipolar5 -}; + val = dt2811_ai_read_sample(dev, s); + comedi_buf_write_samples(s, &val, 1); + } + + if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) + async->events |= COMEDI_CB_EOA; + + comedi_handle_events(dev, s); + + return IRQ_HANDLED; +} + +static int dt2811_ai_cancel(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + /* + * Mode 0 + * Single conversion + * + * Loading a chanspec will trigger a conversion. + */ + outb(DT2811_ADCSR_ADMODE(0), dev->iobase + DT2811_ADCSR_REG); + + return 0; +} + +static void dt2811_ai_set_chanspec(struct comedi_device *dev, + unsigned int chanspec) +{ + unsigned int chan = CR_CHAN(chanspec); + unsigned int range = CR_RANGE(chanspec); + + outb(DT2811_ADGCR_CHAN(chan) | DT2811_ADGCR_GAIN(range), + dev->iobase + DT2811_ADGCR_REG); +} + +static int dt2811_ai_cmd(struct comedi_device *dev, + struct comedi_subdevice *s) +{ + struct dt2811_private *devpriv = dev->private; + struct comedi_cmd *cmd = &s->async->cmd; + unsigned int mode; + + if (cmd->start_src == TRIG_NOW) { + /* + * Mode 1 + * Continuous conversion, internal trigger and clock + * + * This resets the trigger flip-flop, disabling A/D strobes. + * The timer/counter register is loaded with the division + * ratio which will give the required sample rate. + * + * Loading the first chanspec sets the trigger flip-flop, + * enabling the timer/counter. A/D strobes are then generated + * at the rate set by the internal clock/divider. + */ + mode = DT2811_ADCSR_ADMODE(1); + } else { /* TRIG_EXT */ + if (cmd->convert_src == TRIG_TIMER) { + /* + * Mode 2 + * Continuous conversion, external trigger + * + * Similar to Mode 1, with the exception that the + * trigger flip-flop must be set by a negative edge + * on the external trigger input. + */ + mode = DT2811_ADCSR_ADMODE(2); + } else { /* TRIG_EXT */ + /* + * Mode 3 + * Continuous conversion, external trigger, clock + * + * Similar to Mode 2, with the exception that the + * conversion rate is set by the frequency on the + * external clock/divider. + */ + mode = DT2811_ADCSR_ADMODE(3); + } + } + outb(mode | DT2811_ADCSR_INTENB, dev->iobase + DT2811_ADCSR_REG); + + /* load timer */ + outb(devpriv->ai_divisor, dev->iobase + DT2811_TMRCTR_REG); + + /* load chanspec - enables timer */ + dt2811_ai_set_chanspec(dev, cmd->chanlist[0]); + + return 0; +} + +static unsigned int dt2811_ns_to_timer(unsigned int *nanosec, + unsigned int flags) +{ + unsigned long long ns = *nanosec; + unsigned int ns_lo = COMEDI_MIN_SPEED; + unsigned int ns_hi = 0; + unsigned int divisor_hi = 0; + unsigned int divisor_lo = 0; + unsigned int _div; + unsigned int _mult; + + /* + * Work through all the divider/multiplier values to find the two + * closest divisors to generate the requested nanosecond timing. + */ + for (_div = 0; _div <= 7; _div++) { + for (_mult = 0; _mult <= 7; _mult++) { + unsigned int div = dt2811_clk_dividers[_div]; + unsigned int mult = dt2811_clk_multipliers[_mult]; + unsigned long long divider = div * mult; + unsigned int divisor = DT2811_TMRCTR_MANTISSA(_div) | + DT2811_TMRCTR_EXPONENT(_mult); + + /* + * The timer can be configured to run at a slowest + * speed of 0.005hz (600 Khz/120000000), which requires + * 37-bits to represent the nanosecond value. Limit the + * slowest timing to what comedi handles (32-bits). + */ + ns = divider * DT2811_OSC_BASE; + if (ns > COMEDI_MIN_SPEED) + continue; + + /* Check for fastest found timing */ + if (ns <= *nanosec && ns > ns_hi) { + ns_hi = ns; + divisor_hi = divisor; + } + /* Check for slowest found timing */ + if (ns >= *nanosec && ns < ns_lo) { + ns_lo = ns; + divisor_lo = divisor; + } + } + } + + /* + * The slowest found timing will be invalid if the requested timing + * is faster than what can be generated by the timer. Fix it so that + * CMDF_ROUND_UP returns valid timing. + */ + if (ns_lo == COMEDI_MIN_SPEED) { + ns_lo = ns_hi; + divisor_lo = divisor_hi; + } + /* + * The fastest found timing will be invalid if the requested timing + * is less than what can be generated by the timer. Fix it so that + * CMDF_ROUND_NEAREST and CMDF_ROUND_DOWN return valid timing. + */ + if (ns_hi == 0) { + ns_hi = ns_lo; + divisor_hi = divisor_lo; + } + + switch (flags & CMDF_ROUND_MASK) { + case CMDF_ROUND_NEAREST: + default: + if (ns_hi - *nanosec < *nanosec - ns_lo) { + *nanosec = ns_lo; + return divisor_lo; + } + *nanosec = ns_hi; + return divisor_hi; + case CMDF_ROUND_UP: + *nanosec = ns_lo; + return divisor_lo; + case CMDF_ROUND_DOWN: + *nanosec = ns_hi; + return divisor_hi; + } +} + +static int dt2811_ai_cmdtest(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_cmd *cmd) +{ + struct dt2811_private *devpriv = dev->private; + unsigned int arg; + int err = 0; + + /* Step 1 : check if triggers are trivially valid */ + + err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); + err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_FOLLOW); + err |= comedi_check_trigger_src(&cmd->convert_src, + TRIG_TIMER | TRIG_EXT); + err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); + err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); + + if (err) + return 1; + + /* Step 2a : make sure trigger sources are unique */ + + err |= comedi_check_trigger_is_unique(cmd->start_src); + err |= comedi_check_trigger_is_unique(cmd->convert_src); + err |= comedi_check_trigger_is_unique(cmd->stop_src); + + /* Step 2b : and mutually compatible */ + + if (cmd->convert_src == TRIG_EXT && cmd->start_src != TRIG_EXT) + err |= -EINVAL; + + if (err) + return 2; + + /* Step 3: check if arguments are trivially valid */ + + err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); + err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); + if (cmd->convert_src == TRIG_TIMER) + err |= comedi_check_trigger_arg_min(&cmd->convert_arg, 12500); + err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, + cmd->chanlist_len); + if (cmd->stop_src == TRIG_COUNT) + err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); + else /* TRIG_NONE */ + err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); + + if (err) + return 3; + + /* Step 4: fix up any arguments */ + + if (cmd->convert_src == TRIG_TIMER) { + arg = cmd->convert_arg; + devpriv->ai_divisor = dt2811_ns_to_timer(&arg, cmd->flags); + err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); + } else { /* TRIG_EXT */ + /* The convert_arg is used to set the divisor. */ + devpriv->ai_divisor = cmd->convert_arg; + } + + if (err) + return 4; + + /* Step 5: check channel list if it exists */ + + return 0; +} static int dt2811_ai_eoc(struct comedi_device *dev, struct comedi_subdevice *s, @@ -227,32 +472,33 @@ static int dt2811_ai_eoc(struct comedi_device *dev, { unsigned int status; - status = inb(dev->iobase + DT2811_ADCSR); - if ((status & DT2811_ADBUSY) == 0) + status = inb(dev->iobase + DT2811_ADCSR_REG); + if ((status & DT2811_ADCSR_ADBUSY) == 0) return 0; return -EBUSY; } -static int dt2811_ai_insn(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) +static int dt2811_ai_insn_read(struct comedi_device *dev, + struct comedi_subdevice *s, + struct comedi_insn *insn, + unsigned int *data) { - int chan = CR_CHAN(insn->chanspec); int ret; int i; + /* We will already be in Mode 0 */ for (i = 0; i < insn->n; i++) { - outb(chan, dev->iobase + DT2811_ADGCR); + /* load chanspec and trigger conversion */ + dt2811_ai_set_chanspec(dev, insn->chanspec); ret = comedi_timeout(dev, s, insn, dt2811_ai_eoc, 0); if (ret) return ret; - data[i] = inb(dev->iobase + DT2811_ADDATLO); - data[i] |= inb(dev->iobase + DT2811_ADDATHI) << 8; - data[i] &= 0xfff; + data[i] = dt2811_ai_read_sample(dev, s); } - return i; + return insn->n; } static int dt2811_ao_insn_write(struct comedi_device *dev, @@ -266,9 +512,9 @@ static int dt2811_ao_insn_write(struct comedi_device *dev, for (i = 0; i < insn->n; i++) { val = data[i]; - outb(val & 0xff, dev->iobase + DT2811_DADAT0LO + 2 * chan); + outb(val & 0xff, dev->iobase + DT2811_DADATA_LO_REG(chan)); outb((val >> 8) & 0xff, - dev->iobase + DT2811_DADAT0HI + 2 * chan); + dev->iobase + DT2811_DADATA_HI_REG(chan)); } s->readback[chan] = val; @@ -277,9 +523,10 @@ static int dt2811_ao_insn_write(struct comedi_device *dev, static int dt2811_di_insn_bits(struct comedi_device *dev, struct comedi_subdevice *s, - struct comedi_insn *insn, unsigned int *data) + struct comedi_insn *insn, + unsigned int *data) { - data[1] = inb(dev->iobase + DT2811_DIO); + data[1] = inb(dev->iobase + DT2811_DI_REG); return insn->n; } @@ -290,185 +537,118 @@ static int dt2811_do_insn_bits(struct comedi_device *dev, unsigned int *data) { if (comedi_dio_update_state(s, data)) - outb(s->state, dev->iobase + DT2811_DIO); + outb(s->state, dev->iobase + DT2811_DO_REG); data[1] = s->state; return insn->n; } -/* - options[0] Board base address - options[1] IRQ - options[2] Input configuration - 0 == single-ended - 1 == differential - 2 == pseudo-differential - options[3] Analog input range configuration - 0 == bipolar 5 (-5V -- +5V) - 1 == bipolar 2.5V (-2.5V -- +2.5V) - 2 == unipolar 5V (0V -- +5V) - options[4] Analog output 0 range configuration - 0 == bipolar 5 (-5V -- +5V) - 1 == bipolar 2.5V (-2.5V -- +2.5V) - 2 == unipolar 5V (0V -- +5V) - options[5] Analog output 1 range configuration - 0 == bipolar 5 (-5V -- +5V) - 1 == bipolar 2.5V (-2.5V -- +2.5V) - 2 == unipolar 5V (0V -- +5V) -*/ +static void dt2811_reset(struct comedi_device *dev) +{ + /* This is the initialization sequence from the users manual */ + outb(DT2811_ADCSR_ADMODE(0), dev->iobase + DT2811_ADCSR_REG); + usleep_range(100, 1000); + inb(dev->iobase + DT2811_ADDATA_LO_REG); + inb(dev->iobase + DT2811_ADDATA_HI_REG); + outb(DT2811_ADCSR_ADMODE(0) | DT2811_ADCSR_CLRERROR, + dev->iobase + DT2811_ADCSR_REG); +} + static int dt2811_attach(struct comedi_device *dev, struct comedi_devconfig *it) { - /* int i; */ const struct dt2811_board *board = dev->board_ptr; struct dt2811_private *devpriv; - int ret; struct comedi_subdevice *s; + int ret; + + devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); + if (!devpriv) + return -ENOMEM; ret = comedi_request_region(dev, it->options[0], 0x8); if (ret) return ret; -#if 0 - outb(0, dev->iobase + DT2811_ADCSR); - udelay(100); - i = inb(dev->iobase + DT2811_ADDATLO); - i = inb(dev->iobase + DT2811_ADDATHI); -#endif + dt2811_reset(dev); + + /* IRQ's 2,3,5,7 are valid for async command support */ + if (it->options[1] <= 7 && (BIT(it->options[1]) & 0xac)) { + ret = request_irq(it->options[1], dt2811_interrupt, 0, + dev->board_name, dev); + if (ret == 0) + dev->irq = it->options[1]; + } ret = comedi_alloc_subdevices(dev, 4); if (ret) return ret; - devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); - if (!devpriv) - return -ENOMEM; - - switch (it->options[2]) { - case 0: - devpriv->adc_mux = adc_singleended; - break; - case 1: - devpriv->adc_mux = adc_diff; - break; - case 2: - devpriv->adc_mux = adc_pseudo_diff; - break; - default: - devpriv->adc_mux = adc_singleended; - break; - } - switch (it->options[4]) { - case 0: - devpriv->dac_range[0] = dac_bipolar_5; - break; - case 1: - devpriv->dac_range[0] = dac_bipolar_2_5; - break; - case 2: - devpriv->dac_range[0] = dac_unipolar_5; - break; - default: - devpriv->dac_range[0] = dac_bipolar_5; - break; - } - switch (it->options[5]) { - case 0: - devpriv->dac_range[1] = dac_bipolar_5; - break; - case 1: - devpriv->dac_range[1] = dac_bipolar_2_5; - break; - case 2: - devpriv->dac_range[1] = dac_unipolar_5; - break; - default: - devpriv->dac_range[1] = dac_bipolar_5; - break; - } - + /* Analog Input subdevice */ s = &dev->subdevices[0]; - /* initialize the ADC subdevice */ - s->type = COMEDI_SUBD_AI; - s->subdev_flags = SDF_READABLE | SDF_GROUND; - s->n_chan = devpriv->adc_mux == adc_diff ? 8 : 16; - s->insn_read = dt2811_ai_insn; - s->maxdata = 0xfff; - switch (it->options[3]) { - case 0: - default: - s->range_table = board->bip_5; - break; - case 1: - s->range_table = board->bip_2_5; - break; - case 2: - s->range_table = board->unip_5; - break; + s->type = COMEDI_SUBD_AI; + s->subdev_flags = SDF_READABLE | + ((it->options[2] == 1) ? SDF_DIFF : + (it->options[2] == 2) ? SDF_COMMON : SDF_GROUND); + s->n_chan = (it->options[2] == 1) ? 8 : 16; + s->maxdata = 0x0fff; + s->range_table = board->is_pgh ? &dt2811_pgh_ai_ranges + : &dt2811_pgl_ai_ranges; + s->insn_read = dt2811_ai_insn_read; + if (dev->irq) { + dev->read_subdev = s; + s->subdev_flags |= SDF_CMD_READ; + s->len_chanlist = 1; + s->do_cmdtest = dt2811_ai_cmdtest; + s->do_cmd = dt2811_ai_cmd; + s->cancel = dt2811_ai_cancel; } + /* Analog Output subdevice */ s = &dev->subdevices[1]; - /* ao subdevice */ - s->type = COMEDI_SUBD_AO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 2; - s->maxdata = 0xfff; - s->range_table_list = devpriv->range_type_list; - devpriv->range_type_list[0] = dac_range_types[devpriv->dac_range[0]]; - devpriv->range_type_list[1] = dac_range_types[devpriv->dac_range[1]]; - s->insn_write = dt2811_ao_insn_write; + s->type = COMEDI_SUBD_AO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 2; + s->maxdata = 0x0fff; + s->range_table = &dt2811_ao_ranges; + s->insn_write = dt2811_ao_insn_write; ret = comedi_alloc_subdev_readback(s); if (ret) return ret; + /* Digital Input subdevice */ s = &dev->subdevices[2]; - /* di subdevice */ - s->type = COMEDI_SUBD_DI; - s->subdev_flags = SDF_READABLE; - s->n_chan = 8; - s->insn_bits = dt2811_di_insn_bits; - s->maxdata = 1; - s->range_table = &range_digital; - + s->type = COMEDI_SUBD_DI; + s->subdev_flags = SDF_READABLE; + s->n_chan = 8; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = dt2811_di_insn_bits; + + /* Digital Output subdevice */ s = &dev->subdevices[3]; - /* do subdevice */ - s->type = COMEDI_SUBD_DO; - s->subdev_flags = SDF_WRITABLE; - s->n_chan = 8; - s->insn_bits = dt2811_do_insn_bits; - s->maxdata = 1; - s->state = 0; - s->range_table = &range_digital; + s->type = COMEDI_SUBD_DO; + s->subdev_flags = SDF_WRITABLE; + s->n_chan = 8; + s->maxdata = 1; + s->range_table = &range_digital; + s->insn_bits = dt2811_do_insn_bits; return 0; } -static const struct dt2811_board boardtypes[] = { - { - .name = "dt2811-pgh", - .bip_5 = &range_dt2811_pgh_ai_5_bipolar, - .bip_2_5 = &range_dt2811_pgh_ai_2_5_bipolar, - .unip_5 = &range_dt2811_pgh_ai_5_unipolar, - }, { - .name = "dt2811-pgl", - .bip_5 = &range_dt2811_pgl_ai_5_bipolar, - .bip_2_5 = &range_dt2811_pgl_ai_2_5_bipolar, - .unip_5 = &range_dt2811_pgl_ai_5_unipolar, - }, -}; - static struct comedi_driver dt2811_driver = { .driver_name = "dt2811", .module = THIS_MODULE, .attach = dt2811_attach, .detach = comedi_legacy_detach, - .board_name = &boardtypes[0].name, - .num_names = ARRAY_SIZE(boardtypes), + .board_name = &dt2811_boards[0].name, + .num_names = ARRAY_SIZE(dt2811_boards), .offset = sizeof(struct dt2811_board), }; module_comedi_driver(dt2811_driver); MODULE_AUTHOR("Comedi http://www.comedi.org"); -MODULE_DESCRIPTION("Comedi low-level driver"); +MODULE_DESCRIPTION("Comedi driver for Data Translation DT2811 series boards"); MODULE_LICENSE("GPL"); diff --git a/drivers/staging/comedi/drivers/dt2814.c b/drivers/staging/comedi/drivers/dt2814.c index 66705f9a0..2f903bedc 100644 --- a/drivers/staging/comedi/drivers/dt2814.c +++ b/drivers/staging/comedi/drivers/dt2814.c @@ -1,38 +1,38 @@ /* - comedi/drivers/dt2814.c - Hardware driver for Data Translation DT2814 - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/dt2814.c + * Hardware driver for Data Translation DT2814 + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* -Driver: dt2814 -Description: Data Translation DT2814 -Author: ds -Status: complete -Devices: [Data Translation] DT2814 (dt2814) - -Configuration options: - [0] - I/O port base address - [1] - IRQ - -This card has 16 analog inputs multiplexed onto a 12 bit ADC. There -is a minimally useful onboard clock. The base frequency for the -clock is selected by jumpers, and the clock divider can be selected -via programmed I/O. Unfortunately, the clock divider can only be -a power of 10, from 1 to 10^7, of which only 3 or 4 are useful. In -addition, the clock does not seem to be very accurate. -*/ + * Driver: dt2814 + * Description: Data Translation DT2814 + * Author: ds + * Status: complete + * Devices: [Data Translation] DT2814 (dt2814) + * + * Configuration options: + * [0] - I/O port base address + * [1] - IRQ + * + * This card has 16 analog inputs multiplexed onto a 12 bit ADC. There + * is a minimally useful onboard clock. The base frequency for the + * clock is selected by jumpers, and the clock divider can be selected + * via programmed I/O. Unfortunately, the clock divider can only be + * a power of 10, from 1 to 10^7, of which only 3 or 4 are useful. In + * addition, the clock does not seem to be very accurate. + */ #include <linux/module.h> #include <linux/interrupt.h> @@ -215,8 +215,10 @@ static irqreturn_t dt2814_interrupt(int irq, void *d) int i; outb(0, dev->iobase + DT2814_CSR); - /* note: turning off timed mode triggers another - sample. */ + /* + * note: turning off timed mode triggers another + * sample. + */ for (i = 0; i < DT2814_TIMEOUT; i++) { if (inb(dev->iobase + DT2814_CSR) & DT2814_FINISH) diff --git a/drivers/staging/comedi/drivers/dt2815.c b/drivers/staging/comedi/drivers/dt2815.c index fb08569c1..0be77cc40 100644 --- a/drivers/staging/comedi/drivers/dt2815.c +++ b/drivers/staging/comedi/drivers/dt2815.c @@ -1,55 +1,55 @@ /* - comedi/drivers/dt2815.c - Hardware driver for Data Translation DT2815 - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + * comedi/drivers/dt2815.c + * Hardware driver for Data Translation DT2815 + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1999 Anders Blomdell <anders.blomdell@control.lth.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ /* -Driver: dt2815 -Description: Data Translation DT2815 -Author: ds -Status: mostly complete, untested -Devices: [Data Translation] DT2815 (dt2815) - -I'm not sure anyone has ever tested this board. If you have information -contrary, please update. - -Configuration options: - [0] - I/O port base base address - [1] - IRQ (unused) - [2] - Voltage unipolar/bipolar configuration - 0 == unipolar 5V (0V -- +5V) - 1 == bipolar 5V (-5V -- +5V) - [3] - Current offset configuration - 0 == disabled (0mA -- +32mAV) - 1 == enabled (+4mA -- +20mAV) - [4] - Firmware program configuration - 0 == program 1 (see manual table 5-4) - 1 == program 2 (see manual table 5-4) - 2 == program 3 (see manual table 5-4) - 3 == program 4 (see manual table 5-4) - [5] - Analog output 0 range configuration - 0 == voltage - 1 == current - [6] - Analog output 1 range configuration (same options) - [7] - Analog output 2 range configuration (same options) - [8] - Analog output 3 range configuration (same options) - [9] - Analog output 4 range configuration (same options) - [10] - Analog output 5 range configuration (same options) - [11] - Analog output 6 range configuration (same options) - [12] - Analog output 7 range configuration (same options) -*/ + * Driver: dt2815 + * Description: Data Translation DT2815 + * Author: ds + * Status: mostly complete, untested + * Devices: [Data Translation] DT2815 (dt2815) + * + * I'm not sure anyone has ever tested this board. If you have information + * contrary, please update. + * + * Configuration options: + * [0] - I/O port base base address + * [1] - IRQ (unused) + * [2] - Voltage unipolar/bipolar configuration + * 0 == unipolar 5V (0V -- +5V) + * 1 == bipolar 5V (-5V -- +5V) + * [3] - Current offset configuration + * 0 == disabled (0mA -- +32mAV) + * 1 == enabled (+4mA -- +20mAV) + * [4] - Firmware program configuration + * 0 == program 1 (see manual table 5-4) + * 1 == program 2 (see manual table 5-4) + * 2 == program 3 (see manual table 5-4) + * 3 == program 4 (see manual table 5-4) + * [5] - Analog output 0 range configuration + * 0 == voltage + * 1 == current + * [6] - Analog output 1 range configuration (same options) + * [7] - Analog output 2 range configuration (same options) + * [8] - Analog output 3 range configuration (same options) + * [9] - Analog output 4 range configuration (same options) + * [10] - Analog output 5 range configuration (same options) + * [11] - Analog output 6 range configuration (same options) + * [12] - Analog output 7 range configuration (same options) + */ #include <linux/module.h> #include "../comedidev.h" @@ -120,27 +120,27 @@ static int dt2815_ao_insn(struct comedi_device *dev, struct comedi_subdevice *s, } /* - options[0] Board base address - options[1] IRQ (not applicable) - options[2] Voltage unipolar/bipolar configuration - 0 == unipolar 5V (0V -- +5V) - 1 == bipolar 5V (-5V -- +5V) - options[3] Current offset configuration - 0 == disabled (0mA -- +32mAV) - 1 == enabled (+4mA -- +20mAV) - options[4] Firmware program configuration - 0 == program 1 (see manual table 5-4) - 1 == program 2 (see manual table 5-4) - 2 == program 3 (see manual table 5-4) - 3 == program 4 (see manual table 5-4) - options[5] Analog output 0 range configuration - 0 == voltage - 1 == current - options[6] Analog output 1 range configuration - ... - options[12] Analog output 7 range configuration - 0 == voltage - 1 == current + * options[0] Board base address + * options[1] IRQ (not applicable) + * options[2] Voltage unipolar/bipolar configuration + * 0 == unipolar 5V (0V -- +5V) + * 1 == bipolar 5V (-5V -- +5V) + * options[3] Current offset configuration + * 0 == disabled (0mA -- +32mAV) + * 1 == enabled (+4mA -- +20mAV) + * options[4] Firmware program configuration + * 0 == program 1 (see manual table 5-4) + * 1 == program 2 (see manual table 5-4) + * 2 == program 3 (see manual table 5-4) + * 3 == program 4 (see manual table 5-4) + * options[5] Analog output 0 range configuration + * 0 == voltage + * 1 == current + * options[6] Analog output 1 range configuration + * ... + * options[12] Analog output 7 range configuration + * 0 == voltage + * 1 == current */ static int dt2815_attach(struct comedi_device *dev, struct comedi_devconfig *it) diff --git a/drivers/staging/comedi/drivers/dt2817.c b/drivers/staging/comedi/drivers/dt2817.c index 5131deebf..39d2566e4 100644 --- a/drivers/staging/comedi/drivers/dt2817.c +++ b/drivers/staging/comedi/drivers/dt2817.c @@ -1,37 +1,37 @@ /* - comedi/drivers/dt2817.c - Hardware driver for Data Translation DT2817 - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 1998 David A. Schleef <ds@schleef.org> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/dt2817.c + * Hardware driver for Data Translation DT2817 + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 1998 David A. Schleef <ds@schleef.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* -Driver: dt2817 -Description: Data Translation DT2817 -Author: ds -Status: complete -Devices: [Data Translation] DT2817 (dt2817) - -A very simple digital I/O card. Four banks of 8 lines, each bank -is configurable for input or output. One wonders why it takes a -50 page manual to describe this thing. - -The driver (which, btw, is much less than 50 pages) has 1 subdevice -with 32 channels, configurable in groups of 8. - -Configuration options: - [0] - I/O port base base address -*/ + * Driver: dt2817 + * Description: Data Translation DT2817 + * Author: ds + * Status: complete + * Devices: [Data Translation] DT2817 (dt2817) + * + * A very simple digital I/O card. Four banks of 8 lines, each bank + * is configurable for input or output. One wonders why it takes a + * 50 page manual to describe this thing. + * + * The driver (which, btw, is much less than 50 pages) has 1 subdevice + * with 32 channels, configurable in groups of 8. + * + * Configuration options: + * [0] - I/O port base base address + */ #include <linux/module.h> #include "../comedidev.h" diff --git a/drivers/staging/comedi/drivers/gsc_hpdi.c b/drivers/staging/comedi/drivers/gsc_hpdi.c index 63b5cbc44..af4b4175a 100644 --- a/drivers/staging/comedi/drivers/gsc_hpdi.c +++ b/drivers/staging/comedi/drivers/gsc_hpdi.c @@ -158,10 +158,7 @@ static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel) unsigned int size; unsigned int next; - if (channel) - next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG); - else - next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG); + next = readl(devpriv->plx9080_mmio + PLX_REG_DMAPADR(channel)); idx = devpriv->dma_desc_index; start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr); @@ -201,8 +198,9 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d) if (!dev->attached) return IRQ_NONE; - plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG); - if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) + plx_status = readl(devpriv->plx9080_mmio + PLX_REG_INTCSR); + if ((plx_status & + (PLX_INTCSR_DMA0IA | PLX_INTCSR_DMA1IA | PLX_INTCSR_PLIA)) == 0) return IRQ_NONE; hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG); @@ -213,32 +211,32 @@ static irqreturn_t gsc_hpdi_interrupt(int irq, void *d) /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); - dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG); - if (plx_status & ICS_DMA0_A) { + dma0_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR0); + if (plx_status & PLX_INTCSR_DMA0IA) { /* dma chan 0 interrupt */ - writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_mmio + PLX_DMA0_CS_REG); + writeb((dma0_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_mmio + PLX_REG_DMACSR0); - if (dma0_status & PLX_DMA_EN_BIT) + if (dma0_status & PLX_DMACSR_ENABLE) gsc_hpdi_drain_dma(dev, 0); } spin_unlock_irqrestore(&dev->spinlock, flags); /* spin lock makes sure no one else changes plx dma control reg */ spin_lock_irqsave(&dev->spinlock, flags); - dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG); - if (plx_status & ICS_DMA1_A) { + dma1_status = readb(devpriv->plx9080_mmio + PLX_REG_DMACSR1); + if (plx_status & PLX_INTCSR_DMA1IA) { /* XXX */ /* dma chan 1 interrupt */ - writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_mmio + PLX_DMA1_CS_REG); + writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_mmio + PLX_REG_DMACSR1); } spin_unlock_irqrestore(&dev->spinlock, flags); /* clear possible plx9080 interrupt sources */ - if (plx_status & ICS_LDIA) { + if (plx_status & PLX_INTCSR_LDBIA) { /* clear local doorbell interrupt */ - plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG); - writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG); + plx_bits = readl(devpriv->plx9080_mmio + PLX_REG_L2PDBELL); + writel(plx_bits, devpriv->plx9080_mmio + PLX_REG_L2PDBELL); } if (hpdi_board_status & RX_OVERRUN_BIT) { @@ -307,19 +305,19 @@ static int gsc_hpdi_cmd(struct comedi_device *dev, * occasionally cause problems with transfer of first dma * block. Initializing them to zero seems to fix the problem. */ - writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG); - writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG); - writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG); + writel(0, devpriv->plx9080_mmio + PLX_REG_DMASIZ0); + writel(0, devpriv->plx9080_mmio + PLX_REG_DMAPADR0); + writel(0, devpriv->plx9080_mmio + PLX_REG_DMALADR0); /* give location of first dma descriptor */ - bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT | - PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI; - writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG); + bits = devpriv->dma_desc_phys_addr | PLX_DMADPR_DESCPCI | + PLX_DMADPR_TCINTR | PLX_DMADPR_XFERL2P; + writel(bits, devpriv->plx9080_mmio + PLX_REG_DMADPR0); /* enable dma transfer */ spin_lock_irqsave(&dev->spinlock, flags); - writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT, - devpriv->plx9080_mmio + PLX_DMA0_CS_REG); + writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR, + devpriv->plx9080_mmio + PLX_REG_DMACSR0); spin_unlock_irqrestore(&dev->spinlock, flags); if (cmd->stop_src == TRIG_COUNT) @@ -424,8 +422,8 @@ static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev, { struct hpdi_private *devpriv = dev->private; dma_addr_t phys_addr = devpriv->dma_desc_phys_addr; - u32 next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT | - PLX_XFER_LOCAL_TO_PCI; + u32 next_bits = PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR | + PLX_DMADPR_XFERL2P; unsigned int offset = 0; unsigned int idx = 0; unsigned int i; @@ -536,9 +534,10 @@ static int gsc_hpdi_init(struct comedi_device *dev) /* enable interrupts */ plx_intcsr_bits = - ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE | - ICS_DMA0_E; - writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG); + PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN | + PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN | + PLX_INTCSR_DMA0IEN; + writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_REG_INTCSR); return 0; } @@ -550,13 +549,13 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev) void __iomem *plx_iobase = devpriv->plx9080_mmio; #ifdef __BIG_ENDIAN - bits = BIGEND_DMA0 | BIGEND_DMA1; + bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1; #else bits = 0; #endif - writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG); + writel(bits, devpriv->plx9080_mmio + PLX_REG_BIGEND); - writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG); + writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR); gsc_hpdi_abort_dma(dev, 0); gsc_hpdi_abort_dma(dev, 1); @@ -564,27 +563,27 @@ static void gsc_hpdi_init_plx9080(struct comedi_device *dev) /* configure dma0 mode */ bits = 0; /* enable ready input */ - bits |= PLX_DMA_EN_READYIN_BIT; + bits |= PLX_DMAMODE_READYIEN; /* enable dma chaining */ - bits |= PLX_EN_CHAIN_BIT; + bits |= PLX_DMAMODE_CHAINEN; /* * enable interrupt on dma done * (probably don't need this, since chain never finishes) */ - bits |= PLX_EN_DMA_DONE_INTR_BIT; + bits |= PLX_DMAMODE_DONEIEN; /* * don't increment local address during transfers * (we are transferring from a fixed fifo register) */ - bits |= PLX_LOCAL_ADDR_CONST_BIT; + bits |= PLX_DMAMODE_LACONST; /* route dma interrupt to pci bus */ - bits |= PLX_DMA_INTR_PCI_BIT; + bits |= PLX_DMAMODE_INTRPCI; /* enable demand mode */ - bits |= PLX_DEMAND_MODE_BIT; + bits |= PLX_DMAMODE_DEMAND; /* enable local burst mode */ - bits |= PLX_DMA_LOCAL_BURST_EN_BIT; - bits |= PLX_LOCAL_BUS_32_WIDE_BITS; - writel(bits, plx_iobase + PLX_DMA0_MODE_REG); + bits |= PLX_DMAMODE_BURSTEN; + bits |= PLX_DMAMODE_WIDTH32; + writel(bits, plx_iobase + PLX_REG_DMAMODE0); } static int gsc_hpdi_auto_attach(struct comedi_device *dev, @@ -680,7 +679,7 @@ static void gsc_hpdi_detach(struct comedi_device *dev) free_irq(dev->irq, dev); if (devpriv) { if (devpriv->plx9080_mmio) { - writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG); + writel(0, devpriv->plx9080_mmio + PLX_REG_INTCSR); iounmap(devpriv->plx9080_mmio); } if (dev->mmio) diff --git a/drivers/staging/comedi/drivers/jr3_pci.c b/drivers/staging/comedi/drivers/jr3_pci.c index f1793bd50..4bd7326cf 100644 --- a/drivers/staging/comedi/drivers/jr3_pci.c +++ b/drivers/staging/comedi/drivers/jr3_pci.c @@ -1,20 +1,20 @@ /* - comedi/drivers/jr3_pci.c - hardware driver for JR3/PCI force sensor board - - COMEDI - Linux Control and Measurement Device Interface - Copyright (C) 2007 Anders Blomdell <anders.blomdell@control.lth.se> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*/ + * comedi/drivers/jr3_pci.c + * hardware driver for JR3/PCI force sensor board + * + * COMEDI - Linux Control and Measurement Device Interface + * Copyright (C) 2007 Anders Blomdell <anders.blomdell@control.lth.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ /* * Driver: jr3_pci * Description: JR3/PCI force sensor board @@ -226,7 +226,7 @@ static unsigned int jr3_pci_ai_read_chan(struct comedi_device *dev, if (chan < 56) { unsigned int axis = chan % 8; - unsigned filter = chan / 8; + unsigned int filter = chan / 8; switch (axis) { case 0: @@ -685,7 +685,7 @@ static int jr3_pci_auto_attach(struct comedi_device *dev, if (sizeof(struct jr3_channel) != 0xc00) { dev_err(dev->class_dev, "sizeof(struct jr3_channel) = %x [expected %x]\n", - (unsigned)sizeof(struct jr3_channel), 0xc00); + (unsigned int)sizeof(struct jr3_channel), 0xc00); return -EINVAL; } diff --git a/drivers/staging/comedi/drivers/me_daq.c b/drivers/staging/comedi/drivers/me_daq.c index 5d877a2e6..0e2f9f346 100644 --- a/drivers/staging/comedi/drivers/me_daq.c +++ b/drivers/staging/comedi/drivers/me_daq.c @@ -150,7 +150,7 @@ struct me_private_data { unsigned short dac_ctrl; /* Mirror of the DAC_CONTROL register */ }; -static inline void sleep(unsigned sec) +static inline void sleep(unsigned int sec) { schedule_timeout_interruptible(sec * HZ); } diff --git a/drivers/staging/comedi/drivers/mpc624.c b/drivers/staging/comedi/drivers/mpc624.c index 826e4399c..9bda76143 100644 --- a/drivers/staging/comedi/drivers/mpc624.c +++ b/drivers/staging/comedi/drivers/mpc624.c @@ -103,7 +103,7 @@ static const struct comedi_lrange range_mpc624_bipolar1 = { /* BIP_RANGE(1.01) this is correct, */ /* but my MPC-624 actually seems to have a range of 2.02 */ BIP_RANGE(2.02) - } + } }; static const struct comedi_lrange range_mpc624_bipolar10 = { @@ -112,7 +112,7 @@ static const struct comedi_lrange range_mpc624_bipolar10 = { /* BIP_RANGE(10.1) this is correct, */ /* but my MPC-624 actually seems to have a range of 20.2 */ BIP_RANGE(20.2) - } + } }; static unsigned int mpc624_ai_get_sample(struct comedi_device *dev, diff --git a/drivers/staging/comedi/drivers/ni_65xx.c b/drivers/staging/comedi/drivers/ni_65xx.c index 251117be1..07f38e385 100644 --- a/drivers/staging/comedi/drivers/ni_65xx.c +++ b/drivers/staging/comedi/drivers/ni_65xx.c @@ -151,10 +151,10 @@ enum ni_65xx_boardid { struct ni_65xx_board { const char *name; - unsigned num_dio_ports; - unsigned num_di_ports; - unsigned num_do_ports; - unsigned legacy_invert:1; + unsigned int num_dio_ports; + unsigned int num_di_ports; + unsigned int num_do_ports; + unsigned int legacy_invert:1; }; static const struct ni_65xx_board ni_65xx_boards[] = { @@ -360,7 +360,7 @@ static int ni_65xx_dio_insn_config(struct comedi_device *dev, unsigned long base_port = (unsigned long)s->private; unsigned int chan = CR_CHAN(insn->chanspec); unsigned int chan_mask = NI_65XX_CHAN_TO_MASK(chan); - unsigned port = base_port + NI_65XX_CHAN_TO_PORT(chan); + unsigned int port = base_port + NI_65XX_CHAN_TO_PORT(chan); unsigned int interval; unsigned int val; @@ -428,14 +428,14 @@ static int ni_65xx_dio_insn_bits(struct comedi_device *dev, unsigned long base_port = (unsigned long)s->private; unsigned int base_chan = CR_CHAN(insn->chanspec); int last_port_offset = NI_65XX_CHAN_TO_PORT(s->n_chan - 1); - unsigned read_bits = 0; + unsigned int read_bits = 0; int port_offset; for (port_offset = NI_65XX_CHAN_TO_PORT(base_chan); port_offset <= last_port_offset; port_offset++) { - unsigned port = base_port + port_offset; + unsigned int port = base_port + port_offset; int base_port_channel = NI_65XX_PORT_TO_CHAN(port_offset); - unsigned port_mask, port_data, bits; + unsigned int port_mask, port_data, bits; int bitshift = base_port_channel - base_chan; if (bitshift >= 32) @@ -640,7 +640,7 @@ static int ni_65xx_auto_attach(struct comedi_device *dev, struct pci_dev *pcidev = comedi_to_pci_dev(dev); const struct ni_65xx_board *board = NULL; struct comedi_subdevice *s; - unsigned i; + unsigned int i; int ret; if (context < ARRAY_SIZE(ni_65xx_boards)) diff --git a/drivers/staging/comedi/drivers/ni_pcidio.c b/drivers/staging/comedi/drivers/ni_pcidio.c index ed04dea91..c5ee05028 100644 --- a/drivers/staging/comedi/drivers/ni_pcidio.c +++ b/drivers/staging/comedi/drivers/ni_pcidio.c @@ -170,12 +170,12 @@ comedi_nonfree_firmware tarball available from http://www.comedi.org #define DMA_Line_Control_Group1 76 #define DMA_Line_Control_Group2 108 /* channel zero is none */ -static inline unsigned primary_DMAChannel_bits(unsigned channel) +static inline unsigned int primary_DMAChannel_bits(unsigned int channel) { return channel & 0x3; } -static inline unsigned secondary_DMAChannel_bits(unsigned channel) +static inline unsigned int secondary_DMAChannel_bits(unsigned int channel) { return (channel << 2) & 0xc; } diff --git a/drivers/staging/comedi/drivers/ni_pcimio.c b/drivers/staging/comedi/drivers/ni_pcimio.c index 344aa343e..d8917392b 100644 --- a/drivers/staging/comedi/drivers/ni_pcimio.c +++ b/drivers/staging/comedi/drivers/ni_pcimio.c @@ -1064,12 +1064,12 @@ static void m_series_init_eeprom_buffer(struct comedi_device *dev) struct mite *mite = devpriv->mite; resource_size_t daq_phys_addr; static const int Start_Cal_EEPROM = 0x400; - static const unsigned window_size = 10; + static const unsigned int window_size = 10; static const int serial_number_eeprom_offset = 0x4; static const int serial_number_eeprom_length = 0x4; - unsigned old_iodwbsr_bits; - unsigned old_iodwbsr1_bits; - unsigned old_iodwcr1_bits; + unsigned int old_iodwbsr_bits; + unsigned int old_iodwbsr1_bits; + unsigned int old_iodwcr1_bits; int i; /* IO Window 1 needs to be temporarily mapped to read the eeprom */ diff --git a/drivers/staging/comedi/drivers/pcmmio.c b/drivers/staging/comedi/drivers/pcmmio.c index 10472e6dd..70ad497dd 100644 --- a/drivers/staging/comedi/drivers/pcmmio.c +++ b/drivers/staging/comedi/drivers/pcmmio.c @@ -84,25 +84,25 @@ #define PCMMIO_AI_LSB_REG 0x00 #define PCMMIO_AI_MSB_REG 0x01 #define PCMMIO_AI_CMD_REG 0x02 -#define PCMMIO_AI_CMD_SE (1 << 7) -#define PCMMIO_AI_CMD_ODD_CHAN (1 << 6) +#define PCMMIO_AI_CMD_SE BIT(7) +#define PCMMIO_AI_CMD_ODD_CHAN BIT(6) #define PCMMIO_AI_CMD_CHAN_SEL(x) (((x) & 0x3) << 4) #define PCMMIO_AI_CMD_RANGE(x) (((x) & 0x3) << 2) #define PCMMIO_RESOURCE_REG 0x02 #define PCMMIO_RESOURCE_IRQ(x) (((x) & 0xf) << 0) #define PCMMIO_AI_STATUS_REG 0x03 -#define PCMMIO_AI_STATUS_DATA_READY (1 << 7) -#define PCMMIO_AI_STATUS_DATA_DMA_PEND (1 << 6) -#define PCMMIO_AI_STATUS_CMD_DMA_PEND (1 << 5) -#define PCMMIO_AI_STATUS_IRQ_PEND (1 << 4) -#define PCMMIO_AI_STATUS_DATA_DRQ_ENA (1 << 2) -#define PCMMIO_AI_STATUS_REG_SEL (1 << 3) -#define PCMMIO_AI_STATUS_CMD_DRQ_ENA (1 << 1) -#define PCMMIO_AI_STATUS_IRQ_ENA (1 << 0) +#define PCMMIO_AI_STATUS_DATA_READY BIT(7) +#define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6) +#define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5) +#define PCMMIO_AI_STATUS_IRQ_PEND BIT(4) +#define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2) +#define PCMMIO_AI_STATUS_REG_SEL BIT(3) +#define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1) +#define PCMMIO_AI_STATUS_IRQ_ENA BIT(0) #define PCMMIO_AI_RES_ENA_REG 0x03 #define PCMMIO_AI_RES_ENA_CMD_REG_ACCESS (0 << 3) -#define PCMMIO_AI_RES_ENA_AI_RES_ACCESS (1 << 3) -#define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS (1 << 4) +#define PCMMIO_AI_RES_ENA_AI_RES_ACCESS BIT(3) +#define PCMMIO_AI_RES_ENA_DIO_RES_ACCESS BIT(4) #define PCMMIO_AI_2ND_ADC_OFFSET 0x04 #define PCMMIO_AO_LSB_REG 0x08 @@ -125,14 +125,14 @@ #define PCMMIO_AO_CMD_CHAN_SEL(x) (((x) & 0x03) << 1) #define PCMMIO_AO_CMD_CHAN_SEL_ALL (0x0f << 0) #define PCMMIO_AO_STATUS_REG 0x0b -#define PCMMIO_AO_STATUS_DATA_READY (1 << 7) -#define PCMMIO_AO_STATUS_DATA_DMA_PEND (1 << 6) -#define PCMMIO_AO_STATUS_CMD_DMA_PEND (1 << 5) -#define PCMMIO_AO_STATUS_IRQ_PEND (1 << 4) -#define PCMMIO_AO_STATUS_DATA_DRQ_ENA (1 << 2) -#define PCMMIO_AO_STATUS_REG_SEL (1 << 3) -#define PCMMIO_AO_STATUS_CMD_DRQ_ENA (1 << 1) -#define PCMMIO_AO_STATUS_IRQ_ENA (1 << 0) +#define PCMMIO_AO_STATUS_DATA_READY BIT(7) +#define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6) +#define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5) +#define PCMMIO_AO_STATUS_IRQ_PEND BIT(4) +#define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2) +#define PCMMIO_AO_STATUS_REG_SEL BIT(3) +#define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1) +#define PCMMIO_AO_STATUS_IRQ_ENA BIT(0) #define PCMMIO_AO_RESOURCE_ENA_REG 0x0b #define PCMMIO_AO_2ND_DAC_OFFSET 0x04 diff --git a/drivers/staging/comedi/drivers/pcmuio.c b/drivers/staging/comedi/drivers/pcmuio.c index 7ea813022..8ad64f262 100644 --- a/drivers/staging/comedi/drivers/pcmuio.c +++ b/drivers/staging/comedi/drivers/pcmuio.c @@ -307,7 +307,7 @@ static void pcmuio_stop_intr(struct comedi_device *dev, static void pcmuio_handle_intr_subdev(struct comedi_device *dev, struct comedi_subdevice *s, - unsigned triggered) + unsigned int triggered) { struct pcmuio_private *devpriv = dev->private; int asic = pcmuio_subdevice_to_asic(s); diff --git a/drivers/staging/comedi/drivers/plx9080.h b/drivers/staging/comedi/drivers/plx9080.h index 8d1aee00b..0e20cc5c9 100644 --- a/drivers/staging/comedi/drivers/plx9080.h +++ b/drivers/staging/comedi/drivers/plx9080.h @@ -3,15 +3,6 @@ * * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net> * - * I modified this file from the plx9060.h header for the - * wanXL device driver in the linux kernel, - * for the register offsets and bit definitions. Made minor modifications, - * added plx9080 registers and - * stripped out stuff that was specifically for the wanXL driver. - * Note: I've only made sure the definitions are correct as far - * as I make use of them. There are still various plx9060-isms - * left in this header file. - * ******************************************************************** * * Copyright (C) 1999 RG Studio s.c. @@ -28,392 +19,611 @@ #ifndef __COMEDI_PLX9080_H #define __COMEDI_PLX9080_H -/* descriptor block used for chained dma transfers */ +#include <linux/compiler.h> +#include <linux/types.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/io.h> + +/** + * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080 + * @pci_start_addr: PCI Bus address for transfer (DMAPADR). + * @local_start_addr: Local Bus address for transfer (DMALADR). + * @transfer_size: Transfer size in bytes (max 8 MiB) (DMASIZ). + * @next: Address of next descriptor + flags (DMADPR). + * + * Describes the format of a scatter-gather DMA descriptor for the PLX + * PCI 9080. All members are raw, little-endian register values that + * will be transferred by the DMA engine from local or PCI memory into + * corresponding registers for the DMA channel. + * + * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0 + * of @next contain flags describing the address space of the next + * descriptor (local or PCI), an "end of chain" marker, an "interrupt on + * terminal count" bit, and a data transfer direction. + */ struct plx_dma_desc { __le32 pci_start_addr; __le32 local_start_addr; - /* transfer_size is in bytes, only first 23 bits of register are used */ __le32 transfer_size; - /* - * address of next descriptor (quad word aligned), plus some - * additional bits (see PLX_DMA0_DESCRIPTOR_REG) - */ __le32 next; }; -/********************************************************************** -** Register Offsets and Bit Definitions -** -** Note: All offsets zero relative. IE. Some standard base address -** must be added to the Register Number to properly access the register. -** -**********************************************************************/ - -/* L, Local Addr Space 0 Range Register */ -#define PLX_LAS0RNG_REG 0x0000 -/* L, Local Addr Space 1 Range Register */ -#define PLX_LAS1RNG_REG 0x00f0 -#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */ -#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */ -#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */ -#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */ -/* bits that specify range for memory io */ -#define LRNG_MEM_MASK 0xfffffff0 -/* bits that specify range for normal io */ -#define LRNG_IO_MASK 0xfffffffa -/* L, Local Addr Space 0 Remap Register */ -#define PLX_LAS0MAP_REG 0x0004 -/* L, Local Addr Space 1 Remap Register */ -#define PLX_LAS1MAP_REG 0x00f4 -#define LMAP_EN 0x00000001 /* Enable slave decode */ -/* bits that specify decode for memory io */ -#define LMAP_MEM_MASK 0xfffffff0 -/* bits that specify decode bits for normal io */ -#define LMAP_IO_MASK 0xfffffffa - /* - * Mode/Arbitration Register. + * Register Offsets and Bit Definitions */ -#define PLX_MARB_REG 0x8 /* L, Local Arbitration Register */ -#define PLX_DMAARB_REG 0xac -enum marb_bits { - MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */ - MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */ - MARB_LTEN = 0x00010000, /* Latency Timer Enable */ - MARB_LPEN = 0x00020000, /* Pause Timer Enable */ - MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */ - MARB_DMA_PRIORITY_MASK = 0x00180000, - /* local bus direct slave give up bus mode */ - MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000, - /* direct slave LLOCKo# enable */ - MARB_DS_LLOCK_ENABLE = 0x00400000, - MARB_PCI_REQUEST_MODE = 0x00800000, - MARB_PCIV21_MODE = 0x01000000, /* pci specification v2.1 mode */ - MARB_PCI_READ_NO_WRITE_MODE = 0x02000000, - MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000, - /* gate local bus latency timer with BREQ */ - MARB_GATE_TIMER_WITH_BREQ = 0x08000000, - MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000, - MARB_USE_SUBSYSTEM_IDS = 0x20000000, -}; - -#define PLX_BIGEND_REG 0xc -enum bigend_bits { - /* use big endian ordering for configuration register accesses */ - BIGEND_CONFIG = 0x1, - BIGEND_DIRECT_MASTER = 0x2, - BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4, - BIGEND_ROM = 0x8, - /* - * use byte lane consisting of most significant bits instead of - * least significant - */ - BIGEND_BYTE_LANE = 0x10, - BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20, - BIGEND_DMA1 = 0x40, - BIGEND_DMA0 = 0x80, -}; +/* Local Address Space 0 Range Register */ +#define PLX_REG_LAS0RR 0x0000 +/* Local Address Space 1 Range Register */ +#define PLX_REG_LAS1RR 0x00f0 + +#define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */ +#define PLX_LASRR_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */ +#define PLX_LASRR_LT1MB (BIT(1) * 1) /* Locate in 1st meg */ +#define PLX_LASRR_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */ +#define PLX_LASRR_MLOC_MASK GENMASK(2, 1) /* Memory location bits */ +#define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */ +/* bits that specify range for memory space decode bits */ +#define PLX_LASRR_MEM_MASK GENMASK(31, 4) +/* bits that specify range for i/o space decode bits */ +#define PLX_LASRR_IO_MASK GENMASK(31, 2) + +/* Local Address Space 0 Local Base Address (Remap) Register */ +#define PLX_REG_LAS0BA 0x0004 +/* Local Address Space 1 Local Base Address (Remap) Register */ +#define PLX_REG_LAS1BA 0x00f4 + +#define PLX_LASBA_EN BIT(0) /* Enable slave decode */ +/* bits that specify local base address for memory space */ +#define PLX_LASBA_MEM_MASK GENMASK(31, 4) +/* bits that specify local base address for i/o space */ +#define PLX_LASBA_IO_MASK GENMASK(31, 2) + +/* Mode/Arbitration Register */ +#define PLX_REG_MARBR 0x0008 +/* DMA Arbitration Register (alias of MARBR). */ +#define PLX_REG_DMAARB 0x00ac + +/* Local Bus Latency Timer */ +#define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff)) +#define PLX_MARBR_LT_MASK GENMASK(7, 0) +#define PLX_MARBR_LT_SHIFT 0 +/* Local Bus Pause Timer */ +#define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff)) +#define PLX_MARBR_PT_MASK GENMASK(15, 8) +#define PLX_MARBR_PT_SHIFT 8 +/* Local Bus Latency Timer Enable */ +#define PLX_MARBR_LTEN BIT(16) +/* Local Bus Pause Timer Enable */ +#define PLX_MARBR_PTEN BIT(17) +/* Local Bus BREQ Enable */ +#define PLX_MARBR_BREQEN BIT(18) +/* DMA Channel Priority */ +#define PLX_MARBR_PRIO_ROT (BIT(19) * 0) /* Rotational priority */ +#define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */ +#define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */ +#define PLX_MARBR_PRIO_MASK GENMASK(20, 19) +/* Local Bus Direct Slave Give Up Bus Mode */ +#define PLX_MARBR_DSGUBM BIT(21) +/* Direct Slace LLOCKo# Enable */ +#define PLX_MARBR_DSLLOCKOEN BIT(22) +/* PCI Request Mode */ +#define PLX_MARBR_PCIREQM BIT(23) +/* PCI Specification v2.1 Mode */ +#define PLX_MARBR_PCIV21M BIT(24) +/* PCI Read No Write Mode */ +#define PLX_MARBR_PCIRNWM BIT(25) +/* PCI Read with Write Flush Mode */ +#define PLX_MARBR_PCIRWFM BIT(26) +/* Gate Local Bus Latency Timer with BREQ */ +#define PLX_MARBR_GLTBREQ BIT(27) +/* PCI Read No Flush Mode */ +#define PLX_MARBR_PCIRNFM BIT(28) /* -** Note: The Expansion ROM stuff is only relevant to the PC environment. -** This expansion ROM code is executed by the host CPU at boot time. -** For this reason no bit definitions are provided here. + * Make reads from PCI Configuration register 0 return Subsystem ID and + * Subsystem Vendor ID instead of Device ID and Vendor ID */ -#define PLX_ROMRNG_REG 0x0010 /* L, Expn ROM Space Range Register */ -/* L, Local Addr Space Range Register */ -#define PLX_ROMMAP_REG 0x0014 - -#define PLX_REGION0_REG 0x0018 /* L, Local Bus Region 0 Descriptor */ -#define RGN_WIDTH 0x00000002 /* Local bus width bits */ -#define RGN_8BITS 0x00000000 /* 08 bit Local Bus */ -#define RGN_16BITS 0x00000001 /* 16 bit Local Bus */ -#define RGN_32BITS 0x00000002 /* 32 bit Local Bus */ -#define RGN_MWS 0x0000003C /* Memory Access Wait States */ -#define RGN_0MWS 0x00000000 -#define RGN_1MWS 0x00000004 -#define RGN_2MWS 0x00000008 -#define RGN_3MWS 0x0000000C -#define RGN_4MWS 0x00000010 -#define RGN_6MWS 0x00000018 -#define RGN_8MWS 0x00000020 -#define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */ -#define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */ -#define RGN_READ_PREFETCH_DISABLE 0x00000100 -#define RGN_ROM_PREFETCH_DISABLE 0x00000200 -#define RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400 -#define RGN_RWS 0x003C0000 /* Expn ROM Wait States */ -#define RGN_RRE 0x00400000 /* ROM Space Ready Input Enable */ -#define RGN_RBE 0x00800000 /* ROM Space Bterm Input Enable */ -#define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */ -#define RGN_RBEN 0x04000000 /* ROM Space Burst Enable */ -#define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */ -#define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */ - -#define PLX_REGION1_REG 0x00f8 /* L, Local Bus Region 1 Descriptor */ - -#define PLX_DMRNG_REG 0x001C /* L, Direct Master Range Register */ - -#define PLX_LBAPMEM_REG 0x0020 /* L, Lcl Base Addr for PCI mem space */ - -#define PLX_LBAPIO_REG 0x0024 /* L, Lcl Base Addr for PCI I/O space */ - -#define PLX_DMMAP_REG 0x0028 /* L, Direct Master Remap Register */ -#define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */ -#define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */ -#define DMM_LCK 0x00000004 /* LOCK Input Enable */ -#define DMM_PF4 0x00000008 /* Prefetch 4 Mode Enable */ -#define DMM_THROT 0x00000010 /* Assert IRDY when read FIFO full */ -#define DMM_PAF0 0x00000000 /* Programmable Almost fill level */ -#define DMM_PAF1 0x00000020 /* Programmable Almost fill level */ -#define DMM_PAF2 0x00000040 /* Programmable Almost fill level */ -#define DMM_PAF3 0x00000060 /* Programmable Almost fill level */ -#define DMM_PAF4 0x00000080 /* Programmable Almost fill level */ -#define DMM_PAF5 0x000000A0 /* Programmable Almost fill level */ -#define DMM_PAF6 0x000000C0 /* Programmable Almost fill level */ -#define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */ -#define DMM_MAP 0xFFFF0000 /* Remap Address Bits */ - -#define PLX_CAR_REG 0x002C /* L, Configuration Address Register */ -#define CAR_CT0 0x00000000 /* Config Type 0 */ -#define CAR_CT1 0x00000001 /* Config Type 1 */ -#define CAR_REG 0x000000FC /* Register Number Bits */ -#define CAR_FUN 0x00000700 /* Function Number Bits */ -#define CAR_DEV 0x0000F800 /* Device Number Bits */ -#define CAR_BUS 0x00FF0000 /* Bus Number Bits */ -#define CAR_CFG 0x80000000 /* Config Spc Access Enable */ - -#define PLX_DBR_IN_REG 0x0060 /* L, PCI to Local Doorbell Register */ - -#define PLX_DBR_OUT_REG 0x0064 /* L, Local to PCI Doorbell Register */ - -#define PLX_INTRCS_REG 0x0068 /* L, Interrupt Control/Status Reg */ -#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */ -#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */ -#define ICS_SERR 0x00000004 /* Generate PCI SERR# */ -#define ICS_MBIE 0x00000008 /* mailbox interrupt enable */ -#define ICS_PIE 0x00000100 /* PCI Interrupt Enable */ -#define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */ -#define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */ -#define ICS_PLIE 0x00000800 /* PCI Local Int Enable */ -#define ICS_RAE 0x00001000 /* Retry Abort Enable */ -#define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */ -#define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */ -#define ICS_LIA 0x00008000 /* Local Interrupt Active */ -#define ICS_LIE 0x00010000 /* Local Interrupt Enable */ -#define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */ -#define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */ -#define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */ -#define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */ -#define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */ -#define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */ -#define ICS_BIA 0x00800000 /* BIST Interrupt Active */ -#define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */ -#define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */ -#define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */ -#define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */ -/* mailbox x is active */ -#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) - -#define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */ -#define CTL_RDMA 0x0000000E /* DMA Read Command */ -#define CTL_WDMA 0x00000070 /* DMA Write Command */ -#define CTL_RMEM 0x00000600 /* Memory Read Command */ -#define CTL_WMEM 0x00007000 /* Memory Write Command */ -#define CTL_USERO 0x00010000 /* USERO output pin control bit */ -#define CTL_USERI 0x00020000 /* USERI input pin bit */ -#define CTL_EE_CLK 0x01000000 /* EEPROM Clock line */ -#define CTL_EE_CS 0x02000000 /* EEPROM Chip Select */ -#define CTL_EE_W 0x04000000 /* EEPROM Write bit */ -#define CTL_EE_R 0x08000000 /* EEPROM Read bit */ -#define CTL_EECHK 0x10000000 /* EEPROM Present bit */ -#define CTL_EERLD 0x20000000 /* EEPROM Reload Register */ -#define CTL_RESET 0x40000000 /* !! Adapter Reset !! */ -#define CTL_READY 0x80000000 /* Local Init Done */ - -#define PLX_ID_REG 0x70 /* hard-coded plx vendor and device ids */ - -#define PLX_REVISION_REG 0x74 /* silicon revision */ - -#define PLX_DMA0_MODE_REG 0x80 /* dma channel 0 mode register */ -#define PLX_DMA1_MODE_REG 0x94 /* dma channel 0 mode register */ -#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1 -#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3 -#define PLX_LOCAL_BUS_WIDTH_MASK 0x3 -#define PLX_DMA_EN_READYIN_BIT 0x40 /* enable ready in input */ -#define PLX_EN_BTERM_BIT 0x80 /* enable BTERM# input */ -#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 /* enable local burst mode */ -#define PLX_EN_CHAIN_BIT 0x200 /* enables chaining */ -/* enables interrupt on dma done */ -#define PLX_EN_DMA_DONE_INTR_BIT 0x400 -/* hold local address constant (don't increment) */ -#define PLX_LOCAL_ADDR_CONST_BIT 0x800 -/* enables demand-mode for dma transfer */ -#define PLX_DEMAND_MODE_BIT 0x1000 -#define PLX_EOT_ENABLE_BIT 0x4000 -#define PLX_STOP_MODE_BIT 0x8000 -/* routes dma interrupt to pci bus (instead of local bus) */ -#define PLX_DMA_INTR_PCI_BIT 0x20000 - -/* pci address that dma transfers start at */ -#define PLX_DMA0_PCI_ADDRESS_REG 0x84 -#define PLX_DMA1_PCI_ADDRESS_REG 0x98 - -/* local address that dma transfers start at */ -#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 -#define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c - -/* number of bytes to transfer (first 23 bits) */ -#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c -#define PLX_DMA1_TRANSFER_SIZE_REG 0xa0 - -#define PLX_DMA0_DESCRIPTOR_REG 0x90 /* descriptor pointer register */ -#define PLX_DMA1_DESCRIPTOR_REG 0xa4 -/* descriptor is located in pci space (not local space) */ -#define PLX_DESC_IN_PCI_BIT 0x1 -#define PLX_END_OF_CHAIN_BIT 0x2 /* end of chain bit */ -/* interrupt when this descriptor's transfer is finished */ -#define PLX_INTR_TERM_COUNT 0x4 -/* transfer from local to pci bus (not pci to local) */ -#define PLX_XFER_LOCAL_TO_PCI 0x8 - -#define PLX_DMA0_CS_REG 0xa8 /* command status register */ -#define PLX_DMA1_CS_REG 0xa9 -#define PLX_DMA_EN_BIT 0x1 /* enable dma channel */ -#define PLX_DMA_START_BIT 0x2 /* start dma transfer */ -#define PLX_DMA_ABORT_BIT 0x4 /* abort dma transfer */ -#define PLX_CLEAR_DMA_INTR_BIT 0x8 /* clear dma interrupt */ -#define PLX_DMA_DONE_BIT 0x10 /* transfer done status bit */ - -#define PLX_DMA0_THRESHOLD_REG 0xb0 /* command status register */ +#define PLX_MARBR_SUBSYSIDS BIT(29) + +/* Big/Little Endian Descriptor Register */ +#define PLX_REG_BIGEND 0x000c + +/* Configuration Register Big Endian Mode */ +#define PLX_BIGEND_CONFIG BIT(0) +/* Direct Master Big Endian Mode */ +#define PLX_BIGEND_DM BIT(1) +/* Direct Slave Address Space 0 Big Endian Mode */ +#define PLX_BIGEND_DSAS0 BIT(2) +/* Direct Slave Expansion ROM Big Endian Mode */ +#define PLX_BIGEND_EROM BIT(3) +/* Big Endian Byte Lane Mode - use most significant byte lanes */ +#define PLX_BIGEND_BEBLM BIT(4) +/* Direct Slave Address Space 1 Big Endian Mode */ +#define PLX_BIGEND_DSAS1 BIT(5) +/* DMA Channel 1 Big Endian Mode */ +#define PLX_BIGEND_DMA1 BIT(6) +/* DMA Channel 0 Big Endian Mode */ +#define PLX_BIGEND_DMA0 BIT(7) +/* DMA Channel N Big Endian Mode (N <= 1) */ +#define PLX_BIGEND_DMA(n) ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0) /* - * Accesses near the end of memory can cause the PLX chip - * to pre-fetch data off of end-of-ram. Limit the size of - * memory so host-side accesses cannot occur. + * Note: The Expansion ROM stuff is only relevant to the PC environment. + * This expansion ROM code is executed by the host CPU at boot time. + * For this reason no bit definitions are provided here. */ -#define PLX_PREFETCH 32 +/* Expansion ROM Range Register */ +#define PLX_REG_EROMRR 0x0010 +/* Expansion ROM Local Base Address (Remap) Register */ +#define PLX_REG_EROMBA 0x0014 + +/* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */ +#define PLX_REG_LBRD0 0x0018 +/* Local Address Space 1 Bus Region Descriptor Register */ +#define PLX_REG_LBRD1 0x00f8 + +/* Memory Space Local Bus Width */ +#define PLX_LBRD_MSWIDTH8 (BIT(0) * 0) /* 8 bits wide */ +#define PLX_LBRD_MSWIDTH16 (BIT(0) * 1) /* 16 bits wide */ +#define PLX_LBRD_MSWIDTH32 (BIT(0) * 2) /* 32 bits wide */ +#define PLX_LBRD_MSWIDTH32A (BIT(0) * 3) /* 32 bits wide */ +#define PLX_LBRD_MSWIDTH_MASK GENMASK(1, 0) +#define PLX_LBRD_MSWIDTH_SHIFT 0 +/* Memory Space Internal Wait States */ +#define PLX_LBRD_MSIWS(x) (BIT(2) * ((x) & 0xf)) +#define PLX_LBRD_MSIWS_MASK GENMASK(5, 2) +#define PLX_LBRD_MSIWS_SHIFT 2 +/* Memory Space Ready Input Enable */ +#define PLX_LBRD_MSREADYIEN BIT(6) +/* Memory Space BTERM# Input Enable */ +#define PLX_LBRD_MSBTERMIEN BIT(7) +/* Memory Space 0 Prefetch Disable (LBRD0 only) */ +#define PLX_LBRD0_MSPREDIS BIT(8) +/* Memory Space 1 Burst Enable (LBRD1 only) */ +#define PLX_LBRD1_MSBURSTEN BIT(8) +/* Expansion ROM Space Prefetch Disable (LBRD0 only) */ +#define PLX_LBRD0_EROMPREDIS BIT(9) +/* Memory Space 1 Prefetch Disable (LBRD1 only) */ +#define PLX_LBRD1_MSPREDIS BIT(9) +/* Read Prefetch Count Enable */ +#define PLX_LBRD_RPFCOUNTEN BIT(10) +/* Prefetch Counter */ +#define PLX_LBRD_PFCOUNT(x) (BIT(11) * ((x) & 0xf)) +#define PLX_LBRD_PFCOUNT_MASK GENMASK(14, 11) +#define PLX_LBRD_PFCOUNT_SHIFT 11 +/* Expansion ROM Space Local Bus Width (LBRD0 only) */ +#define PLX_LBRD0_EROMWIDTH8 (BIT(16) * 0) /* 8 bits wide */ +#define PLX_LBRD0_EROMWIDTH16 (BIT(16) * 1) /* 16 bits wide */ +#define PLX_LBRD0_EROMWIDTH32 (BIT(16) * 2) /* 32 bits wide */ +#define PLX_LBRD0_EROMWIDTH32A (BIT(16) * 3) /* 32 bits wide */ +#define PLX_LBRD0_EROMWIDTH_MASK GENMASK(17, 16) +#define PLX_LBRD0_EROMWIDTH_SHIFT 16 +/* Expansion ROM Space Internal Wait States (LBRD0 only) */ +#define PLX_LBRD0_EROMIWS(x) (BIT(18) * ((x) & 0xf)) +#define PLX_LBRD0_EROMIWS_MASK GENMASK(21, 18) +#define PLX_LBRD0_EROMIWS_SHIFT 18 +/* Expansion ROM Space Ready Input Enable (LBDR0 only) */ +#define PLX_LBRD0_EROMREADYIEN BIT(22) +/* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */ +#define PLX_LBRD0_EROMBTERMIEN BIT(23) +/* Memory Space 0 Burst Enable (LBRD0 only) */ +#define PLX_LBRD0_MSBURSTEN BIT(24) +/* Extra Long Load From Serial EEPROM (LBRD0 only) */ +#define PLX_LBRD0_EELONGLOAD BIT(25) +/* Expansion ROM Space Burst Enable (LBRD0 only) */ +#define PLX_LBRD0_EROMBURSTEN BIT(26) +/* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */ +#define PLX_LBRD0_DSWMTRDY BIT(27) +/* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */ +#define PLX_LBRD0_TRDELAY(x) (BIT(28) * ((x) & 0xF)) +#define PLX_LBRD0_TRDELAY_MASK GENMASK(31, 28) +#define PLX_LBRD0_TRDELAY_SHIFT 28 + +/* Local Range Register for Direct Master to PCI */ +#define PLX_REG_DMRR 0x001c + +/* Local Bus Base Address Register for Direct Master to PCI Memory */ +#define PLX_REG_DMLBAM 0x0020 + +/* Local Base Address Register for Direct Master to PCI IO/CFG */ +#define PLX_REG_DMLBAI 0x0024 + +/* PCI Base Address (Remap) Register for Direct Master to PCI Memory */ +#define PLX_REG_DMPBAM 0x0028 + +/* Direct Master Memory Access Enable */ +#define PLX_DMPBAM_MEMACCEN BIT(0) +/* Direct Master I/O Access Enable */ +#define PLX_DMPBAM_IOACCEN BIT(1) +/* LLOCK# Input Enable */ +#define PLX_DMPBAM_LLOCKIEN BIT(2) +/* Direct Master Read Prefetch Size Control (bits 12, 3) */ +#define PLX_DMPBAM_RPSIZECONT ((BIT(12) * 0) | (BIT(3) * 0)) +#define PLX_DMPBAM_RPSIZE4 ((BIT(12) * 0) | (BIT(3) * 1)) +#define PLX_DMPBAM_RPSIZE8 ((BIT(12) * 1) | (BIT(3) * 0)) +#define PLX_DMPBAM_RPSIZE16 ((BIT(12) * 1) | (BIT(3) * 1)) +#define PLX_DMPBAM_RPSIZE_MASK (BIT(12) | BIT(3)) +/* Direct Master PCI Read Mode - deassert IRDY when FIFO full */ +#define PLX_DMPBAM_RMIRDY BIT(4) +/* Programmable Almost Full Level (bits 10, 8:5) */ +#define PLX_DMPBAM_PAFL(x) ((BIT(10) * !!((x) & 0x10)) | \ + (BIT(5) * ((x) & 0xf))) +#define PLX_DMPBAM_TO_PAFL(v) ((((BIT(10) & (v)) >> 1) | \ + (GENMASK(8, 5) & (v))) >> 5) +#define PLX_DMPBAM_PAFL_MASK (BIT(10) | GENMASK(8, 5)) +/* Write And Invalidate Mode */ +#define PLX_DMPBAM_WIM BIT(9) +/* Direct Master Prefetch Limit */ +#define PLX_DBPBAM_PFLIMIT BIT(11) +/* I/O Remap Select */ +#define PLX_DMPBAM_IOREMAPSEL BIT(13) +/* Direct Master Write Delay */ +#define PLX_DMPBAM_WDELAYNONE (BIT(14) * 0) +#define PLX_DMPBAM_WDELAY4 (BIT(14) * 1) +#define PLX_DMPBAM_WDELAY8 (BIT(14) * 2) +#define PLX_DMPBAM_WDELAY16 (BIT(14) * 3) +#define PLX_DMPBAM_WDELAY_MASK GENMASK(15, 14) +/* Remap of Local-to-PCI Space Into PCI Address Space */ +#define PLX_DMPBAM_REMAP_MASK GENMASK(31, 16) + +/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */ +#define PLX_REG_DMCFGA 0x002c + +/* Congiguration Type */ +#define PLX_DMCFGA_TYPE0 (BIT(0) * 0) +#define PLX_DMCFGA_TYPE1 (BIT(0) * 1) +#define PLX_DMCFGA_TYPE_MASK GENMASK(1, 0) +/* Register Number */ +#define PLX_DMCFGA_REGNUM(x) (BIT(2) * ((x) & 0x3f)) +#define PLX_DMCFGA_REGNUM_MASK GENMASK(7, 2) +#define PLX_DMCFGA_REGNUM_SHIFT 2 +/* Function Number */ +#define PLX_DMCFGA_FUNCNUM(x) (BIT(8) * ((x) & 0x7)) +#define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8) +#define PLX_DMCFGA_FUNCNUM_SHIFT 8 +/* Device Number */ +#define PLX_DMCFGA_DEVNUM(x) (BIT(11) * ((x) & 0x1f)) +#define PLX_DMCFGA_DEVNUM_MASK GENMASK(15, 11) +#define PLX_DMCFGA_DEVNUM_SHIFT 11 +/* Bus Number */ +#define PLX_DMCFGA_BUSNUM(x) (BIT(16) * ((x) & 0xff)) +#define PLX_DMCFGA_BUSNUM_MASK GENMASK(23, 16) +#define PLX_DMCFGA_BUSNUM_SHIFT 16 +/* Configuration Enable */ +#define PLX_DMCFGA_CONFIGEN BIT(31) /* - * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox - * Registers. The PUTS (Power-Up Test Suite) handles the board-side - * interface/interaction using the first 4 registers. Specifications for - * the use of the full PUTS' command and status interface is contained - * within a separate SBE PUTS Manual. The Host-Side Device Driver only - * uses a subset of the full PUTS interface. + * Mailbox Register N (N <= 7) + * + * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0 + * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced + * by the Outbound Queue Port. However, Mailbox Register 0 and 1 are always + * accessible at alternative offsets if the I2O feature is enabled. */ +#define PLX_REG_MBOX(n) (0x0040 + (n) * 4) +#define PLX_REG_MBOX0 PLX_REG_MBOX(0) +#define PLX_REG_MBOX1 PLX_REG_MBOX(1) +#define PLX_REG_MBOX2 PLX_REG_MBOX(2) +#define PLX_REG_MBOX3 PLX_REG_MBOX(3) +#define PLX_REG_MBOX4 PLX_REG_MBOX(4) +#define PLX_REG_MBOX5 PLX_REG_MBOX(5) +#define PLX_REG_MBOX6 PLX_REG_MBOX(6) +#define PLX_REG_MBOX7 PLX_REG_MBOX(7) + +/* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */ +#define PLX_REG_ALT_MBOX(n) ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n)) +#define PLX_REG_ALT_MBOX0 PLX_REG_ALT_MBOX(0) +#define PLX_REG_ALT_MBOX1 PLX_REG_ALT_MBOX(1) + +/* PCI-to-Local Doorbell Register */ +#define PLX_REG_P2LDBELL 0x0060 + +/* Local-to-PCI Doorbell Register */ +#define PLX_REG_L2PDBELL 0x0064 + +/* Interrupt Control/Status Register */ +#define PLX_REG_INTCSR 0x0068 + +/* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */ +#define PLX_INTCSR_LSEABORTEN BIT(0) +/* Enable Local Bus LSERR# when PCI parity error occurs */ +#define PLX_INTCSR_LSEPARITYEN BIT(1) +/* Generate PCI Bus SERR# when set to 1 */ +#define PLX_INTCSR_GENSERR BIT(2) +/* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */ +#define PLX_INTCSR_MBIEN BIT(3) +/* PCI Interrupt Enable */ +#define PLX_INTCSR_PIEN BIT(8) +/* PCI Doorbell Interrupt Enable */ +#define PLX_INTCSR_PDBIEN BIT(9) +/* PCI Abort Interrupt Enable */ +#define PLX_INTCSR_PABORTIEN BIT(10) +/* PCI Local Interrupt Enable */ +#define PLX_INTCSR_PLIEN BIT(11) +/* Retry Abort Enable (for diagnostic purposes only) */ +#define PLX_INTCSR_RAEN BIT(12) +/* PCI Doorbell Interrupt Active (read-only) */ +#define PLX_INTCSR_PDBIA BIT(13) +/* PCI Abort Interrupt Active (read-only) */ +#define PLX_INTCSR_PABORTIA BIT(14) +/* Local Interrupt (LINTi#) Active (read-only) */ +#define PLX_INTCSR_PLIA BIT(15) +/* Local Interrupt Output (LINTo#) Enable */ +#define PLX_INTCSR_LIOEN BIT(16) +/* Local Doorbell Interrupt Enable */ +#define PLX_INTCSR_LDBIEN BIT(17) +/* DMA Channel 0 Interrupt Enable */ +#define PLX_INTCSR_DMA0IEN BIT(18) +/* DMA Channel 1 Interrupt Enable */ +#define PLX_INTCSR_DMA1IEN BIT(19) +/* DMA Channel N Interrupt Enable (N <= 1) */ +#define PLX_INTCSR_DMAIEN(n) ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN) +/* Local Doorbell Interrupt Active (read-only) */ +#define PLX_INTCSR_LDBIA BIT(20) +/* DMA Channel 0 Interrupt Active (read-only) */ +#define PLX_INTCSR_DMA0IA BIT(21) +/* DMA Channel 1 Interrupt Active (read-only) */ +#define PLX_INTCSR_DMA1IA BIT(22) +/* DMA Channel N Interrupt Active (N <= 1) (read-only) */ +#define PLX_INTCSR_DMAIA(n) ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA) +/* BIST Interrupt Active (read-only) */ +#define PLX_INTCSR_BISTIA BIT(23) +/* Direct Master Not Bus Master During Master Or Target Abort (read-only) */ +#define PLX_INTCSR_ABNOTDM BIT(24) +/* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */ +#define PLX_INTCSR_ABNOTDMA0 BIT(25) +/* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */ +#define PLX_INTCSR_ABNOTDMA1 BIT(26) +/* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */ +#define PLX_INTCSR_ABNOTDMA(n) ((n) ? PLX_INTCSR_ABNOTDMA1 \ + : PLX_INTCSR_ABNOTDMA0) +/* Target Abort Not Generated After 256 Master Retries (read-only) */ +#define PLX_INTCSR_ABNOTRETRY BIT(27) +/* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */ +#define PLX_INTCSR_MB0IA BIT(28) +/* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */ +#define PLX_INTCSR_MB1IA BIT(29) +/* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */ +#define PLX_INTCSR_MB2IA BIT(30) +/* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */ +#define PLX_INTCSR_MB3IA BIT(31) +/* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */ +#define PLX_INTCSR_MBIA(n) BIT(28 + (n)) -/*****************************************/ -/*** MAILBOX #(-1) - MEM ACCESS STS ***/ -/*****************************************/ - -#define MBX_STS_VALID 0x57584744 /* 'WXGD' */ -#define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */ - -/*****************************************/ -/*** MAILBOX #0 - PUTS STATUS ***/ -/*****************************************/ - -#define MBX_STS_MASK 0x000000ff /* PUTS Status Register bits */ -#define MBX_STS_TMASK 0x0000000f /* register bits for TEST number */ - -#define MBX_STS_PCIRESET 0x00000100 /* Host issued PCI reset request */ -#define MBX_STS_BUSY 0x00000080 /* PUTS is in progress */ -#define MBX_STS_ERROR 0x00000040 /* PUTS has failed */ /* - * Undefined -> status in transition. We are in process of changing bits; - * we SET Error bit before RESET of Busy bit + * Serial EEPROM Control, PCI Command Codes, User I/O Control, + * Init Control Register */ -#define MBX_STS_RESERVED 0x000000c0 - -#define MBX_RESERVED_5 0x00000020 /* FYI: reserved/unused bit */ -#define MBX_RESERVED_4 0x00000010 /* FYI: reserved/unused bit */ - -/******************************************/ -/*** MAILBOX #1 - PUTS COMMANDS ***/ -/******************************************/ - +#define PLX_REG_CNTRL 0x006c + +/* PCI Read Command Code For DMA */ +#define PLX_CNTRL_CCRDMA(x) (BIT(0) * ((x) & 0xf)) +#define PLX_CNTRL_CCRDMA_MASK GENMASK(3, 0) +#define PLX_CNTRL_CCRDMA_SHIFT 0 +#define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14) /* value after reset */ +/* PCI Write Command Code For DMA 0 */ +#define PLX_CNTRL_CCWDMA(x) (BIT(4) * ((x) & 0xf)) +#define PLX_CNTRL_CCWDMA_MASK GENMASK(7, 4) +#define PLX_CNTRL_CCWDMA_SHIFT 4 +#define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7) /* value after reset */ +/* PCI Memory Read Command Code For Direct Master */ +#define PLX_CNTRL_CCRDM(x) (BIT(8) * ((x) & 0xf)) +#define PLX_CNTRL_CCRDM_MASK GENMASK(11, 8) +#define PLX_CNTRL_CCRDM_SHIFT 8 +#define PLX_CNTRL_CCRDM_NORMAL PLX_CNTRL_CCRDM(6) /* value after reset */ +/* PCI Memory Write Command Code For Direct Master */ +#define PLX_CNTRL_CCWDM(x) (BIT(12) * ((x) & 0xf)) +#define PLX_CNTRL_CCWDM_MASK GENMASK(15, 12) +#define PLX_CNTRL_CCWDM_SHIFT 12 +#define PLX_CNTRL_CCWDM_NORMAL PLX_CNTRL_CCWDM(7) /* value after reset */ +/* General Purpose Output (USERO) */ +#define PLX_CNTRL_USERO BIT(16) +/* General Purpose Input (USERI) (read-only) */ +#define PLX_CNTRL_USERI BIT(17) +/* Serial EEPROM Clock Output (EESK) */ +#define PLX_CNTRL_EESK BIT(24) +/* Serial EEPROM Chip Select Output (EECS) */ +#define PLX_CNTRL_EECS BIT(25) +/* Serial EEPROM Data Write Bit (EEDI (sic)) */ +#define PLX_CNTRL_EEWB BIT(26) +/* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */ +#define PLX_CNTRL_EERB BIT(27) +/* Serial EEPROM Present (read-only) */ +#define PLX_CNTRL_EEPRESENT BIT(28) +/* Reload Configuration Registers from EEPROM */ +#define PLX_CNTRL_EERELOAD BIT(29) +/* PCI Adapter Software Reset (asserts LRESETo#) */ +#define PLX_CNTRL_RESET BIT(30) +/* Local Init Status (read-only) */ +#define PLX_CNTRL_INITDONE BIT(31) /* - * Any attempt to execute an unimplement command results in the PUTS - * interface executing a NOOP and continuing as if the offending command - * completed normally. Note: this supplies a simple method to interrogate - * mailbox command processing functionality. + * Combined command code stuff for convenience. */ +#define PLX_CNTRL_CC_MASK \ + (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \ + PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK) +#define PLX_CNTRL_CC_NORMAL \ + (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \ + PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */ + +/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */ +#define PLX_REG_PCIHIDR 0x0070 + +/* Hard-coded ID for PLX PCI 9080 */ +#define PLX_PCIHIDR_9080 0x908010b5 + +/* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */ +#define PLX_REG_PCIHREV 0x0074 + +/* DMA Channel N Mode Register (N <= 1) */ +#define PLX_REG_DMAMODE(n) ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0) +#define PLX_REG_DMAMODE0 0x0080 +#define PLX_REG_DMAMODE1 0x0094 + +/* Local Bus Width */ +#define PLX_DMAMODE_WIDTH8 (BIT(0) * 0) /* 8 bits wide */ +#define PLX_DMAMODE_WIDTH16 (BIT(0) * 1) /* 16 bits wide */ +#define PLX_DMAMODE_WIDTH32 (BIT(0) * 2) /* 32 bits wide */ +#define PLX_DMAMODE_WIDTH32A (BIT(0) * 3) /* 32 bits wide */ +#define PLX_DMAMODE_WIDTH_MASK GENMASK(1, 0) +#define PLX_DMAMODE_WIDTH_SHIFT 0 +/* Internal Wait States */ +#define PLX_DMAMODE_IWS(x) (BIT(2) * ((x) & 0xf)) +#define PLX_DMAMODE_IWS_MASK GENMASK(5, 2) +#define PLX_DMAMODE_SHIFT 2 +/* Ready Input Enable */ +#define PLX_DMAMODE_READYIEN BIT(6) +/* BTERM# Input Enable */ +#define PLX_DMAMODE_BTERMIEN BIT(7) +/* Local Burst Enable */ +#define PLX_DMAMODE_BURSTEN BIT(8) +/* Chaining Enable */ +#define PLX_DMAMODE_CHAINEN BIT(9) +/* Done Interrupt Enable */ +#define PLX_DMAMODE_DONEIEN BIT(10) +/* Hold Local Address Constant */ +#define PLX_DMAMODE_LACONST BIT(11) +/* Demand Mode */ +#define PLX_DMAMODE_DEMAND BIT(12) +/* Write And Invalidate Mode */ +#define PLX_DMAMODE_WINVALIDATE BIT(13) +/* DMA EOT Enable - enables EOT0# or EOT1# input pin */ +#define PLX_DMAMODE_EOTEN BIT(14) +/* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */ +#define PLX_DMAMODE_STOP BIT(15) +/* DMA Clear Count Mode - count in descriptor cleared on completion */ +#define PLX_DMAMODE_CLRCOUNT BIT(16) +/* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */ +#define PLX_DMAMODE_INTRPCI BIT(17) + +/* DMA Channel N PCI Address Register (N <= 1) */ +#define PLX_REG_DMAPADR(n) ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0) +#define PLX_REG_DMAPADR0 0x0084 +#define PLX_REG_DMAPADR1 0x0098 + +/* DMA Channel N Local Address Register (N <= 1) */ +#define PLX_REG_DMALADR(n) ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0) +#define PLX_REG_DMALADR0 0x0088 +#define PLX_REG_DMALADR1 0x009c + +/* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */ +#define PLX_REG_DMASIZ(n) ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0) +#define PLX_REG_DMASIZ0 0x008c +#define PLX_REG_DMASIZ1 0x00a0 + +/* DMA Channel N Descriptor Pointer Register (N <= 1) */ +#define PLX_REG_DMADPR(n) ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0) +#define PLX_REG_DMADPR0 0x0090 +#define PLX_REG_DMADPR1 0x00a4 + +/* Descriptor Located In PCI Address Space (not local address space) */ +#define PLX_DMADPR_DESCPCI BIT(0) +/* End Of Chain */ +#define PLX_DMADPR_CHAINEND BIT(1) +/* Interrupt After Terminal Count */ +#define PLX_DMADPR_TCINTR BIT(2) +/* Direction Of Transfer Local Bus To PCI (not PCI to local) */ +#define PLX_DMADPR_XFERL2P BIT(3) +/* Next Descriptor Address Bits 31:4 (16 byte boundary) */ +#define PLX_DMADPR_NEXT_MASK GENMASK(31, 4) + +/* DMA Channel N Command/Status Register (N <= 1) (8-bit) */ +#define PLX_REG_DMACSR(n) ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0) +#define PLX_REG_DMACSR0 0x00a8 +#define PLX_REG_DMACSR1 0x00a9 + +/* Channel Enable */ +#define PLX_DMACSR_ENABLE BIT(0) +/* Channel Start - write 1 to start transfer (write-only) */ +#define PLX_DMACSR_START BIT(1) +/* Channel Abort - write 1 to abort transfer (write-only) */ +#define PLX_DMACSR_ABORT BIT(2) +/* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */ +#define PLX_DMACSR_CLEARINTR BIT(3) +/* Channel Done - transfer complete/inactive (read-only) */ +#define PLX_DMACSR_DONE BIT(4) + +/* DMA Threshold Register */ +#define PLX_REG_DMATHR 0x00b0 -#define MBX_CMD_MASK 0xffff0000 /* PUTS Command Register bits */ - -#define MBX_CMD_ABORTJ 0x85000000 /* abort and jump */ -#define MBX_CMD_RESETP 0x86000000 /* reset and pause at start */ -#define MBX_CMD_PAUSE 0x87000000 /* pause immediately */ -#define MBX_CMD_PAUSEC 0x88000000 /* pause on completion */ -#define MBX_CMD_RESUME 0x89000000 /* resume operation */ -#define MBX_CMD_STEP 0x8a000000 /* single step tests */ - -#define MBX_CMD_BSWAP 0x8c000000 /* identify byte swap scheme */ -#define MBX_CMD_BSWAP_0 0x8c000000 /* use scheme 0 */ -#define MBX_CMD_BSWAP_1 0x8c000001 /* use scheme 1 */ - -/* setup host memory access window size */ -#define MBX_CMD_SETHMS 0x8d000000 -/* setup host memory access base address */ -#define MBX_CMD_SETHBA 0x8e000000 -/* perform memory setup and continue (IE. Done) */ -#define MBX_CMD_MGO 0x8f000000 -#define MBX_CMD_NOOP 0xFF000000 /* dummy, illegal command */ - -/*****************************************/ -/*** MAILBOX #2 - MEMORY SIZE ***/ -/*****************************************/ - -#define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */ - -#define MBX_MEMSZ_128KB 0x00020000 /* 128 kilobyte board */ -#define MBX_MEMSZ_256KB 0x00040000 /* 256 kilobyte board */ -#define MBX_MEMSZ_512KB 0x00080000 /* 512 kilobyte board */ -#define MBX_MEMSZ_1MB 0x00100000 /* 1 megabyte board */ -#define MBX_MEMSZ_2MB 0x00200000 /* 2 megabyte board */ -#define MBX_MEMSZ_4MB 0x00400000 /* 4 megabyte board */ -#define MBX_MEMSZ_8MB 0x00800000 /* 8 megabyte board */ -#define MBX_MEMSZ_16MB 0x01000000 /* 16 megabyte board */ - -/***************************************/ -/*** MAILBOX #2 - BOARD TYPE ***/ -/***************************************/ - -#define MBX_BTYPE_MASK 0x0000ffff /* PUTS Board Type Register */ -/* PUTS Board Family Register */ -#define MBX_BTYPE_FAMILY_MASK 0x0000ff00 -#define MBX_BTYPE_SUBTYPE_MASK 0x000000ff /* PUTS Board Subtype */ - -#define MBX_BTYPE_PLX9060 0x00000100 /* PLX family type */ -#define MBX_BTYPE_PLX9080 0x00000300 /* PLX wanXL100s family type */ - -#define MBX_BTYPE_WANXL_4 0x00000104 /* wanXL400, 4-port */ -#define MBX_BTYPE_WANXL_2 0x00000102 /* wanXL200, 2-port */ -#define MBX_BTYPE_WANXL_1s 0x00000301 /* wanXL100s, 1-port */ -#define MBX_BTYPE_WANXL_1t 0x00000401 /* wanXL100T1, 1-port */ +/* + * DMA Threshold constraints: + * (C0PLAF + 1) + (C0PLAE + 1) <= 32 + * (C0LPAF + 1) + (C0LPAE + 1) <= 32 + * (C1PLAF + 1) + (C1PLAE + 1) <= 16 + * (C1LPAF + 1) + (C1LPAE + 1) <= 16 + */ -/*****************************************/ -/*** MAILBOX #3 - SHMQ MAILBOX ***/ -/*****************************************/ +/* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C0PLAF(x) (BIT(0) * ((x) & 0xf)) +#define PLX_DMATHR_C0PLAF_MASK GENMASK(3, 0) +#define PLX_DMATHR_C0PLAF_SHIFT 0 +/* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C0LPAE(x) (BIT(4) * ((x) & 0xf)) +#define PLX_DMATHR_C0LPAE_MASK GENMASK(7, 4) +#define PLX_DMATHR_C0LPAE_SHIFT 4 +/* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C0LPAF(x) (BIT(8) * ((x) & 0xf)) +#define PLX_DMATHR_C0LPAF_MASK GENMASK(11, 8) +#define PLX_DMATHR_C0LPAF_SHIFT 8 +/* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C0PLAE(x) (BIT(12) * ((x) & 0xf)) +#define PLX_DMATHR_C0PLAE_MASK GENMASK(15, 12) +#define PLX_DMATHR_C0PLAE_SHIFT 12 +/* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C1PLAF(x) (BIT(16) * ((x) & 0xf)) +#define PLX_DMATHR_C1PLAF_MASK GENMASK(19, 16) +#define PLX_DMATHR_C1PLAF_SHIFT 16 +/* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C1LPAE(x) (BIT(20) * ((x) & 0xf)) +#define PLX_DMATHR_C1LPAE_MASK GENMASK(23, 20) +#define PLX_DMATHR_C1LPAE_SHIFT 20 +/* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */ +#define PLX_DMATHR_C1LPAF(x) (BIT(24) * ((x) & 0xf)) +#define PLX_DMATHR_C1LPAF_MASK GENMASK(27, 24) +#define PLX_DMATHR_C1LPAF_SHIFT 24 +/* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */ +#define PLX_DMATHR_C1PLAE(x) (BIT(28) * ((x) & 0xf)) +#define PLX_DMATHR_C1PLAE_MASK GENMASK(31, 28) +#define PLX_DMATHR_C1PLAE_SHIFT 28 -#define MBX_SMBX_MASK 0x000000ff /* PUTS SHMQ Mailbox bits */ +/* + * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR, + * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted. + * They are used by the I2O feature. (IQP and OQP occupy the usual offsets of + * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and + * MBOX1 are accessible via alternative offsets. + */ -/***************************************/ -/*** GENERIC HOST-SIDE DRIVER ***/ -/***************************************/ +/* Queue Status/Control Register */ +#define PLX_REG_QSR 0x00e8 -#define MBX_ERR 0 -#define MBX_OK 1 +/* Value of QSR after reset - disables I2O feature completely. */ +#define PLX_QSR_VALUE_AFTER_RESET 0x00000050 -/* mailbox check routine - type of testing */ -#define MBXCHK_STS 0x00 /* check for PUTS status */ -#define MBXCHK_NOWAIT 0x01 /* dont care about PUTS status */ +/* + * Accesses near the end of memory can cause the PLX chip + * to pre-fetch data off of end-of-ram. Limit the size of + * memory so host-side accesses cannot occur. + */ -/* system allocates this many bytes for address mapping mailbox space */ -#define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */ -#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360 - 1) +#define PLX_PREFETCH 32 +/** + * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer + * @iobase: Remapped base address of configuration registers. + * @channel: DMA channel number (0 or 1). + * + * Aborts the DMA transfer on the channel, which must have been enabled + * and started beforehand. + * + * Return: + * %0 on success. + * -%ETIMEDOUT if timed out waiting for abort to complete. + */ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) { void __iomem *dma_cs_addr; @@ -421,29 +631,26 @@ static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel) const int timeout = 10000; unsigned int i; - if (channel) - dma_cs_addr = iobase + PLX_DMA1_CS_REG; - else - dma_cs_addr = iobase + PLX_DMA0_CS_REG; + dma_cs_addr = iobase + PLX_REG_DMACSR(channel); - /* abort dma transfer if necessary */ + /* abort dma transfer if necessary */ dma_status = readb(dma_cs_addr); - if ((dma_status & PLX_DMA_EN_BIT) == 0) + if ((dma_status & PLX_DMACSR_ENABLE) == 0) return 0; - /* wait to make sure done bit is zero */ - for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) { + /* wait to make sure done bit is zero */ + for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) { udelay(1); dma_status = readb(dma_cs_addr); } if (i == timeout) return -ETIMEDOUT; - /* disable and abort channel */ - writeb(PLX_DMA_ABORT_BIT, dma_cs_addr); - /* wait for dma done bit */ + /* disable and abort channel */ + writeb(PLX_DMACSR_ABORT, dma_cs_addr); + /* wait for dma done bit */ dma_status = readb(dma_cs_addr); - for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) { + for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) { udelay(1); dma_status = readb(dma_cs_addr); } diff --git a/drivers/staging/comedi/drivers/quatech_daqp_cs.c b/drivers/staging/comedi/drivers/quatech_daqp_cs.c index e9e431391..802f51e46 100644 --- a/drivers/staging/comedi/drivers/quatech_daqp_cs.c +++ b/drivers/staging/comedi/drivers/quatech_daqp_cs.c @@ -643,7 +643,7 @@ static int daqp_ao_insn_write(struct comedi_device *dev, outb(0, dev->iobase + DAQP_AUX_REG); for (i = 0; i > insn->n; i++) { - unsigned val = data[i]; + unsigned int val = data[i]; int ret; /* D/A transfer rate is about 8ms */ diff --git a/drivers/staging/comedi/drivers/rtd520.c b/drivers/staging/comedi/drivers/rtd520.c index 9b6c56773..e00e9c626 100644 --- a/drivers/staging/comedi/drivers/rtd520.c +++ b/drivers/staging/comedi/drivers/rtd520.c @@ -362,7 +362,7 @@ struct rtd_private { long ai_count; /* total transfer size (samples) */ int xfer_count; /* # to transfer data. 0->1/2FIFO */ int flags; /* flag event modes */ - unsigned fifosz; + unsigned int fifosz; /* 8254 Timer/Counter gate and clock sources */ unsigned char timer_gate_src[3]; @@ -491,9 +491,9 @@ static void rtd_load_channelgain_list(struct comedi_device *dev, static int rtd520_probe_fifo_depth(struct comedi_device *dev) { unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND); - unsigned i; - static const unsigned limit = 0x2000; - unsigned fifo_size = 0; + unsigned int i; + static const unsigned int limit = 0x2000; + unsigned int fifo_size = 0; writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); rtd_load_channelgain_list(dev, 1, &chanspec); @@ -501,7 +501,7 @@ static int rtd520_probe_fifo_depth(struct comedi_device *dev) writel(0, dev->mmio + LAS0_ADC_CONVERSION); /* convert samples */ for (i = 0; i < limit; ++i) { - unsigned fifo_status; + unsigned int fifo_status; /* trigger conversion */ writew(0, dev->mmio + LAS0_ADC); usleep_range(1, 1000); @@ -1175,7 +1175,7 @@ static void rtd_reset(struct comedi_device *dev) writel(0, dev->mmio + LAS0_BOARD_RESET); usleep_range(100, 1000); /* needed? */ - writel(0, devpriv->lcfg + PLX_INTRCS_REG); + writel(0, devpriv->lcfg + PLX_REG_INTCSR); writew(0, dev->mmio + LAS0_IT); writew(~0, dev->mmio + LAS0_CLEAR); readw(dev->mmio + LAS0_CLEAR); @@ -1316,7 +1316,8 @@ static int rtd_auto_attach(struct comedi_device *dev, devpriv->fifosz = ret; if (dev->irq) - writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG); + writel(PLX_INTCSR_PIEN | PLX_INTCSR_PLIEN, + devpriv->lcfg + PLX_REG_INTCSR); return 0; } diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index c5e08635e..4a87b4b52 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -708,7 +708,7 @@ static uint16_t s626_get_mode_a(struct comedi_device *dev, uint16_t cra; uint16_t crb; uint16_t setup; - unsigned cntsrc, clkmult, clkpol, encmode; + unsigned int cntsrc, clkmult, clkpol, encmode; /* Fetch CRA and CRB register images. */ cra = s626_debi_read(dev, S626_LP_CRA(chan)); @@ -763,7 +763,7 @@ static uint16_t s626_get_mode_b(struct comedi_device *dev, uint16_t cra; uint16_t crb; uint16_t setup; - unsigned cntsrc, clkmult, clkpol, encmode; + unsigned int cntsrc, clkmult, clkpol, encmode; /* Fetch CRA and CRB register images. */ cra = s626_debi_read(dev, S626_LP_CRA(chan)); @@ -838,7 +838,7 @@ static void s626_set_mode_a(struct comedi_device *dev, struct s626_private *devpriv = dev->private; uint16_t cra; uint16_t crb; - unsigned cntsrc, clkmult, clkpol; + unsigned int cntsrc, clkmult, clkpol; /* Initialize CRA and CRB images. */ /* Preload trigger is passed through. */ @@ -916,7 +916,7 @@ static void s626_set_mode_b(struct comedi_device *dev, struct s626_private *devpriv = dev->private; uint16_t cra; uint16_t crb; - unsigned cntsrc, clkmult, clkpol; + unsigned int cntsrc, clkmult, clkpol; /* Initialize CRA and CRB images. */ /* IndexSrc is passed through. */ diff --git a/drivers/staging/comedi/drivers/s626.h b/drivers/staging/comedi/drivers/s626.h index b83424e75..6a00a64c6 100644 --- a/drivers/staging/comedi/drivers/s626.h +++ b/drivers/staging/comedi/drivers/s626.h @@ -29,8 +29,10 @@ #define S626_ENCODER_CHANNELS 6 #define S626_DIO_CHANNELS 48 #define S626_DIO_BANKS 3 /* Number of DIO groups. */ -#define S626_DIO_EXTCHANS 40 /* Number of extended-capability - * DIO channels. */ +#define S626_DIO_EXTCHANS 40 /* + * Number of extended-capability + * DIO channels. + */ #define S626_NUM_TRIMDACS 12 /* Number of valid TrimDAC channels. */ @@ -48,21 +50,29 @@ #define S626_GSEL_BIPOLAR10V 0x00A0 /* S626_LP_GSEL setting 10V bipolar. */ /* Error codes that must be visible to this base class. */ -#define S626_ERR_ILLEGAL_PARM 0x00010000 /* Illegal function parameter - * value was specified. */ +#define S626_ERR_ILLEGAL_PARM 0x00010000 /* + * Illegal function parameter + * value was specified. + */ #define S626_ERR_I2C 0x00020000 /* I2C error. */ -#define S626_ERR_COUNTERSETUP 0x00200000 /* Illegal setup specified for - * counter channel. */ +#define S626_ERR_COUNTERSETUP 0x00200000 /* + * Illegal setup specified for + * counter channel. + */ #define S626_ERR_DEBI_TIMEOUT 0x00400000 /* DEBI transfer timed out. */ /* * Organization (physical order) and size (in DWORDs) of logical DMA buffers * contained by ANA_DMABUF. */ -#define S626_ADC_DMABUF_DWORDS 40 /* ADC DMA buffer must hold 16 samples, - * plus pre/post garbage samples. */ -#define S626_DAC_WDMABUF_DWORDS 1 /* DAC output DMA buffer holds a single - * sample. */ +#define S626_ADC_DMABUF_DWORDS 40 /* + * ADC DMA buffer must hold 16 samples, + * plus pre/post garbage samples. + */ +#define S626_DAC_WDMABUF_DWORDS 1 /* + * DAC output DMA buffer holds a single + * sample. + */ /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */ @@ -95,60 +105,90 @@ #define S626_RPS_IRQ 0x60000000 /* IRQ */ #define S626_RPS_LOGICAL_OR 0x08000000 /* Logical OR conditionals. */ -#define S626_RPS_INVERT 0x04000000 /* Test for negated - * semaphores. */ +#define S626_RPS_INVERT 0x04000000 /* + * Test for negated + * semaphores. + */ #define S626_RPS_DEBI 0x00000002 /* DEBI done */ -#define S626_RPS_SIG0 0x00200000 /* RPS semaphore 0 - * (used by ADC). */ -#define S626_RPS_SIG1 0x00400000 /* RPS semaphore 1 - * (used by DAC). */ -#define S626_RPS_SIG2 0x00800000 /* RPS semaphore 2 - * (not used). */ +#define S626_RPS_SIG0 0x00200000 /* + * RPS semaphore 0 + * (used by ADC). + */ +#define S626_RPS_SIG1 0x00400000 /* + * RPS semaphore 1 + * (used by DAC). + */ +#define S626_RPS_SIG2 0x00800000 /* + * RPS semaphore 2 + * (not used). + */ #define S626_RPS_GPIO2 0x00080000 /* RPS GPIO2 */ #define S626_RPS_GPIO3 0x00100000 /* RPS GPIO3 */ -#define S626_RPS_SIGADC S626_RPS_SIG0 /* Trigger/status for - * ADC's RPS program. */ -#define S626_RPS_SIGDAC S626_RPS_SIG1 /* Trigger/status for - * DAC's RPS program. */ +#define S626_RPS_SIGADC S626_RPS_SIG0 /* + * Trigger/status for + * ADC's RPS program. + */ +#define S626_RPS_SIGDAC S626_RPS_SIG1 /* + * Trigger/status for + * DAC's RPS program. + */ /* RPS clock parameters. */ -#define S626_RPSCLK_SCALAR 8 /* This is apparent ratio of - * PCI/RPS clks (undocumented!!). */ +#define S626_RPSCLK_SCALAR 8 /* + * This is apparent ratio of + * PCI/RPS clks (undocumented!!). + */ #define S626_RPSCLK_PER_US (33 / S626_RPSCLK_SCALAR) - /* Number of RPS clocks in one - * microsecond. */ + /* + * Number of RPS clocks in one + * microsecond. + */ /* Event counter source addresses. */ #define S626_SBA_RPS_A0 0x27 /* Time of RPS0 busy, in PCI clocks. */ /* GPIO constants. */ -#define S626_GPIO_BASE 0x10004000 /* GPIO 0,2,3 = inputs, - * GPIO3 = IRQ; GPIO1 = out. */ +#define S626_GPIO_BASE 0x10004000 /* + * GPIO 0,2,3 = inputs, + * GPIO3 = IRQ; GPIO1 = out. + */ #define S626_GPIO1_LO 0x00000000 /* GPIO1 set to LOW. */ #define S626_GPIO1_HI 0x00001000 /* GPIO1 set to HIGH. */ /* Primary Status Register (PSR) constants. */ #define S626_PSR_DEBI_E 0x00040000 /* DEBI event flag. */ #define S626_PSR_DEBI_S 0x00080000 /* DEBI status flag. */ -#define S626_PSR_A2_IN 0x00008000 /* Audio output DMA2 protection - * address reached. */ -#define S626_PSR_AFOU 0x00000800 /* Audio FIFO under/overflow - * detected. */ -#define S626_PSR_GPIO2 0x00000020 /* GPIO2 input pin: 0=AdcBusy, - * 1=AdcIdle. */ -#define S626_PSR_EC0S 0x00000001 /* Event counter 0 threshold - * reached. */ +#define S626_PSR_A2_IN 0x00008000 /* + * Audio output DMA2 protection + * address reached. + */ +#define S626_PSR_AFOU 0x00000800 /* + * Audio FIFO under/overflow + * detected. + */ +#define S626_PSR_GPIO2 0x00000020 /* + * GPIO2 input pin: 0=AdcBusy, + * 1=AdcIdle. + */ +#define S626_PSR_EC0S 0x00000001 /* + * Event counter 0 threshold + * reached. + */ /* Secondary Status Register (SSR) constants. */ -#define S626_SSR_AF2_OUT 0x00000200 /* Audio 2 output FIFO - * under/overflow detected. */ +#define S626_SSR_AF2_OUT 0x00000200 /* + * Audio 2 output FIFO + * under/overflow detected. + */ /* Master Control Register 1 (MC1) constants. */ #define S626_MC1_SOFT_RESET 0x80000000 /* Invoke 7146 soft reset. */ -#define S626_MC1_SHUTDOWN 0x3FFF0000 /* Shut down all MC1-controlled - * enables. */ +#define S626_MC1_SHUTDOWN 0x3FFF0000 /* + * Shut down all MC1-controlled + * enables. + */ #define S626_MC1_ERPS1 0x2000 /* Enab/disable RPS task 1. */ #define S626_MC1_ERPS0 0x1000 /* Enab/disable RPS task 0. */ @@ -177,15 +217,23 @@ #define S626_P_DEBIAD 0x0088 /* DEBI target address. */ #define S626_P_I2CCTRL 0x008C /* I2C control. */ #define S626_P_I2CSTAT 0x0090 /* I2C status. */ -#define S626_P_BASEA2_IN 0x00AC /* Audio input 2 base physical DMAbuf - * address. */ -#define S626_P_PROTA2_IN 0x00B0 /* Audio input 2 physical DMAbuf - * protection address. */ +#define S626_P_BASEA2_IN 0x00AC /* + * Audio input 2 base physical DMAbuf + * address. + */ +#define S626_P_PROTA2_IN 0x00B0 /* + * Audio input 2 physical DMAbuf + * protection address. + */ #define S626_P_PAGEA2_IN 0x00B4 /* Audio input 2 paging attributes. */ -#define S626_P_BASEA2_OUT 0x00B8 /* Audio output 2 base physical DMAbuf - * address. */ -#define S626_P_PROTA2_OUT 0x00BC /* Audio output 2 physical DMAbuf - * protection address. */ +#define S626_P_BASEA2_OUT 0x00B8 /* + * Audio output 2 base physical DMAbuf + * address. + */ +#define S626_P_PROTA2_OUT 0x00BC /* + * Audio output 2 physical DMAbuf + * protection address. + */ #define S626_P_PAGEA2_OUT 0x00C0 /* Audio output 2 paging attributes. */ #define S626_P_RPSPAGE0 0x00C4 /* RPS0 page. */ #define S626_P_RPSPAGE1 0x00C8 /* RPS1 page. */ @@ -205,8 +253,10 @@ #define S626_P_PSR 0x0110 /* Primary status. */ #define S626_P_SSR 0x0114 /* Secondary status. */ #define S626_P_EC1R 0x0118 /* Event counter set 1. */ -#define S626_P_ADP4 0x0138 /* Logical audio DMA pointer of audio - * input FIFO A2_IN. */ +#define S626_P_ADP4 0x0138 /* + * Logical audio DMA pointer of audio + * input FIFO A2_IN. + */ #define S626_P_FB_BUFFER1 0x0144 /* Audio feedback buffer 1. */ #define S626_P_FB_BUFFER2 0x0148 /* Audio feedback buffer 2. */ #define S626_P_TSL1 0x0180 /* Audio time slot list 1. */ @@ -243,13 +293,19 @@ #define S626_LP_RDMISC2 0x0082 /* Read Misc2. */ /* Bit masks for MISC1 register that are the same for reads and writes. */ -#define S626_MISC1_WENABLE 0x8000 /* enab writes to MISC2 (except Clear - * Watchdog bit). */ +#define S626_MISC1_WENABLE 0x8000 /* + * enab writes to MISC2 (except Clear + * Watchdog bit). + */ #define S626_MISC1_WDISABLE 0x0000 /* Disable writes to MISC2. */ -#define S626_MISC1_EDCAP 0x1000 /* Enable edge capture on DIO chans - * specified by S626_LP_WRCAPSELx. */ -#define S626_MISC1_NOEDCAP 0x0000 /* Disable edge capture on specified - * DIO chans. */ +#define S626_MISC1_EDCAP 0x1000 /* + * Enable edge capture on DIO chans + * specified by S626_LP_WRCAPSELx. + */ +#define S626_MISC1_NOEDCAP 0x0000 /* + * Disable edge capture on specified + * DIO chans. + */ /* Bit masks for MISC1 register reads. */ #define S626_RDMISC1_WDTIMEOUT 0x4000 /* Watchdog timer timed out. */ @@ -268,35 +324,49 @@ #define S626_A1_RUN 0x20000000 /* Run A1 based on TSL1. */ #define S626_A1_SWAP 0x00200000 /* Use big-endian for A1. */ #define S626_A2_SWAP 0x00100000 /* Use big-endian for A2. */ -#define S626_WS_MODES 0x00019999 /* WS0 = TSL1 trigger input, - * WS1-WS4 = CS* outputs. */ - -#if S626_PLATFORM == S626_INTEL /* Base ACON1 config: always run - * A1 based on TSL1. */ +#define S626_WS_MODES 0x00019999 /* + * WS0 = TSL1 trigger input, + * WS1-WS4 = CS* outputs. + */ + +#if S626_PLATFORM == S626_INTEL /* + * Base ACON1 config: always run + * A1 based on TSL1. + */ #define S626_ACON1_BASE (S626_WS_MODES | S626_A1_RUN) #elif S626_PLATFORM == S626_MOTOROLA #define S626_ACON1_BASE \ (S626_WS_MODES | S626_A1_RUN | S626_A1_SWAP | S626_A2_SWAP) #endif -#define S626_ACON1_ADCSTART S626_ACON1_BASE /* Start ADC: run A1 - * based on TSL1. */ +#define S626_ACON1_ADCSTART S626_ACON1_BASE /* + * Start ADC: run A1 + * based on TSL1. + */ #define S626_ACON1_DACSTART (S626_ACON1_BASE | S626_A2_RUN) /* Start transmit to DAC: run A2 based on TSL2. */ #define S626_ACON1_DACSTOP S626_ACON1_BASE /* Halt A2. */ /* Bit masks for ACON2 register. */ #define S626_A1_CLKSRC_BCLK1 0x00000000 /* A1 bit rate = BCLK1 (ADC). */ -#define S626_A2_CLKSRC_X1 0x00800000 /* A2 bit rate = ACLK/1 - * (DACs). */ -#define S626_A2_CLKSRC_X2 0x00C00000 /* A2 bit rate = ACLK/2 - * (DACs). */ -#define S626_A2_CLKSRC_X4 0x01400000 /* A2 bit rate = ACLK/4 - * (DACs). */ +#define S626_A2_CLKSRC_X1 0x00800000 /* + * A2 bit rate = ACLK/1 + * (DACs). + */ +#define S626_A2_CLKSRC_X2 0x00C00000 /* + * A2 bit rate = ACLK/2 + * (DACs). + */ +#define S626_A2_CLKSRC_X4 0x01400000 /* + * A2 bit rate = ACLK/4 + * (DACs). + */ #define S626_INVERT_BCLK2 0x00100000 /* Invert BCLK2 (DACs). */ #define S626_BCLK2_OE 0x00040000 /* Enable BCLK2 (DACs). */ -#define S626_ACON2_XORMASK 0x000C0000 /* XOR mask for ACON2 - * active-low bits. */ +#define S626_ACON2_XORMASK 0x000C0000 /* + * XOR mask for ACON2 + * active-low bits. + */ #define S626_ACON2_INIT (S626_ACON2_XORMASK ^ \ (S626_A1_CLKSRC_BCLK1 | S626_A2_CLKSRC_X2 | \ @@ -308,12 +378,18 @@ #define S626_WS3 0x10000000 #define S626_WS4 0x08000000 #define S626_RSD1 0x01000000 /* Shift A1 data in on SD1. */ -#define S626_SDW_A1 0x00800000 /* Store rcv'd char at next char - * slot of DWORD1 buffer. */ -#define S626_SIB_A1 0x00400000 /* Store rcv'd char at next - * char slot of FB1 buffer. */ -#define S626_SF_A1 0x00200000 /* Write unsigned long - * buffer to input FIFO. */ +#define S626_SDW_A1 0x00800000 /* + * Store rcv'd char at next char + * slot of DWORD1 buffer. + */ +#define S626_SIB_A1 0x00400000 /* + * Store rcv'd char at next + * char slot of FB1 buffer. + */ +#define S626_SF_A1 0x00200000 /* + * Write unsigned long + * buffer to input FIFO. + */ /* Select parallel-to-serial converter's data source: */ #define S626_XFIFO_0 0x00000000 /* Data fifo byte 0. */ @@ -324,31 +400,45 @@ #define S626_XFB1 0x00000050 /* FB_BUFFER byte 1. */ #define S626_XFB2 0x00000060 /* FB_BUFFER byte 2. */ #define S626_XFB3 0x00000070 /* FB_BUFFER byte 3. */ -#define S626_SIB_A2 0x00000200 /* Store next dword from A2's +#define S626_SIB_A2 0x00000200 /* + * Store next dword from A2's * input shifter to FB2 - * buffer. */ -#define S626_SF_A2 0x00000100 /* Store next dword from A2's + * buffer. + */ +#define S626_SF_A2 0x00000100 /* + * Store next dword from A2's * input shifter to its input - * fifo. */ -#define S626_LF_A2 0x00000080 /* Load next dword from A2's + * fifo. + */ +#define S626_LF_A2 0x00000080 /* + * Load next dword from A2's * output fifo into its - * output dword buffer. */ + * output dword buffer. + */ #define S626_XSD2 0x00000008 /* Shift data out on SD2. */ #define S626_RSD3 0x00001800 /* Shift data in on SD3. */ #define S626_RSD2 0x00001000 /* Shift data in on SD2. */ -#define S626_LOW_A2 0x00000002 /* Drive last SD low for 7 clks, - * then tri-state. */ +#define S626_LOW_A2 0x00000002 /* + * Drive last SD low for 7 clks, + * then tri-state. + */ #define S626_EOS 0x00000001 /* End of superframe. */ /* I2C configuration constants. */ -#define S626_I2C_CLKSEL 0x0400 /* I2C bit rate = - * PCIclk/480 = 68.75 KHz. */ -#define S626_I2C_BITRATE 68.75 /* I2C bus data bit rate +#define S626_I2C_CLKSEL 0x0400 /* + * I2C bit rate = + * PCIclk/480 = 68.75 KHz. + */ +#define S626_I2C_BITRATE 68.75 /* + * I2C bus data bit rate * (determined by - * S626_I2C_CLKSEL) in KHz. */ -#define S626_I2C_WRTIME 15.0 /* Worst case time, in msec, + * S626_I2C_CLKSEL) in KHz. + */ +#define S626_I2C_WRTIME 15.0 /* + * Worst case time, in msec, * for EEPROM internal write - * op. */ + * op. + */ /* I2C manifest constants. */ @@ -368,8 +458,10 @@ #define S626_I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) /* DEBI command constants. */ -#define S626_DEBI_CMD_SIZE16 (2 << 17) /* Transfer size is always - * 2 bytes. */ +#define S626_DEBI_CMD_SIZE16 (2 << 17) /* + * Transfer size is always + * 2 bytes. + */ #define S626_DEBI_CMD_READ 0x00010000 /* Read operation. */ #define S626_DEBI_CMD_WRITE 0x00000000 /* Write operation. */ @@ -380,42 +472,58 @@ #define S626_DEBI_CMD_WRWORD (S626_DEBI_CMD_WRITE | S626_DEBI_CMD_SIZE16) /* DEBI configuration constants. */ -#define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* Enable external interrupt - * on GPIO3. */ +#define S626_DEBI_CFG_XIRQ_EN 0x80000000 /* + * Enable external interrupt + * on GPIO3. + */ #define S626_DEBI_CFG_XRESUME 0x40000000 /* Resume block */ - /* Transfer when XIRQ - * deasserted. */ + /* + * Transfer when XIRQ + * deasserted. + */ #define S626_DEBI_CFG_TOQ 0x03C00000 /* Timeout (15 PCI cycles). */ #define S626_DEBI_CFG_FAST 0x10000000 /* Fast mode enable. */ /* 4-bit field that specifies DEBI timeout value in PCI clock cycles: */ -#define S626_DEBI_CFG_TOUT_BIT 22 /* Finish DEBI cycle after this many - * clocks. */ +#define S626_DEBI_CFG_TOUT_BIT 22 /* + * Finish DEBI cycle after this many + * clocks. + */ /* 2-bit field that specifies Endian byte lane steering: */ -#define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* Straight - don't swap any - * bytes (Intel). */ +#define S626_DEBI_CFG_SWAP_NONE 0x00000000 /* + * Straight - don't swap any + * bytes (Intel). + */ #define S626_DEBI_CFG_SWAP_2 0x00100000 /* 2-byte swap (Motorola). */ #define S626_DEBI_CFG_SWAP_4 0x00200000 /* 4-byte swap. */ -#define S626_DEBI_CFG_SLAVE16 0x00080000 /* Slave is able to serve - * 16-bit cycles. */ -#define S626_DEBI_CFG_INC 0x00040000 /* Enable address increment - * for block transfers. */ +#define S626_DEBI_CFG_SLAVE16 0x00080000 /* + * Slave is able to serve + * 16-bit cycles. + */ +#define S626_DEBI_CFG_INC 0x00040000 /* + * Enable address increment + * for block transfers. + */ #define S626_DEBI_CFG_INTEL 0x00020000 /* Intel style local bus. */ #define S626_DEBI_CFG_TIMEROFF 0x00010000 /* Disable timer. */ #if S626_PLATFORM == S626_INTEL -#define S626_DEBI_TOUT 7 /* Wait 7 PCI clocks (212 ns) before - * polling RDY. */ +#define S626_DEBI_TOUT 7 /* + * Wait 7 PCI clocks (212 ns) before + * polling RDY. + */ /* Intel byte lane steering (pass through all byte lanes). */ #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_NONE #elif S626_PLATFORM == S626_MOTOROLA -#define S626_DEBI_TOUT 15 /* Wait 15 PCI clocks (454 ns) maximum - * before timing out. */ +#define S626_DEBI_TOUT 15 /* + * Wait 15 PCI clocks (454 ns) maximum + * before timing out. + */ /* Motorola byte lane steering. */ #define S626_DEBI_SWAP S626_DEBI_CFG_SWAP_2 @@ -429,10 +537,14 @@ /* LoadSrc values: */ #define S626_LOADSRC_INDX 0 /* Preload core in response to Index. */ -#define S626_LOADSRC_OVER 1 /* Preload core in response to - * Overflow. */ -#define S626_LOADSRCB_OVERA 2 /* Preload B core in response to - * A Overflow. */ +#define S626_LOADSRC_OVER 1 /* + * Preload core in response to + * Overflow. + */ +#define S626_LOADSRCB_OVERA 2 /* + * Preload B core in response to + * A Overflow. + */ #define S626_LOADSRC_NONE 3 /* Never preload core. */ /* IntSrc values: */ @@ -469,10 +581,14 @@ #define S626_CNTSRC_SYSCLK_DOWN 3 /* System clock down */ /* ClkPol values: */ -#define S626_CLKPOL_POS 0 /* Counter/Extender clock is - * active high. */ -#define S626_CLKPOL_NEG 1 /* Counter/Extender clock is - * active low. */ +#define S626_CLKPOL_POS 0 /* + * Counter/Extender clock is + * active high. + */ +#define S626_CLKPOL_NEG 1 /* + * Counter/Extender clock is + * active low. + */ #define S626_CNTDIR_UP 0 /* Timer counts up. */ #define S626_CNTDIR_DOWN 1 /* Timer counts down. */ @@ -488,8 +604,10 @@ /* Sanity-check limits for parameters. */ -#define S626_NUM_COUNTERS 6 /* Maximum valid counter - * logical channel number. */ +#define S626_NUM_COUNTERS 6 /* + * Maximum valid counter + * logical channel number. + */ #define S626_NUM_INTSOURCES 4 #define S626_NUM_LATCHSOURCES 4 #define S626_NUM_CLKMULTS 4 diff --git a/drivers/staging/comedi/drivers/serial2002.c b/drivers/staging/comedi/drivers/serial2002.c index 7a1defcf2..0d33e520f 100644 --- a/drivers/staging/comedi/drivers/serial2002.c +++ b/drivers/staging/comedi/drivers/serial2002.c @@ -95,7 +95,7 @@ struct serial_data { #define S2002_CFG_SIGN(x) (((x) >> 13) & 0x1) #define S2002_CFG_BASE(x) (((x) >> 14) & 0xfffff) -static long serial2002_tty_ioctl(struct file *f, unsigned op, +static long serial2002_tty_ioctl(struct file *f, unsigned int op, unsigned long param) { if (f->f_op->unlocked_ioctl) @@ -379,7 +379,10 @@ static int serial2002_setup_subdevice(struct comedi_subdevice *s, range_table_list[chan] = (const struct comedi_lrange *)&range[j]; } - maxdata_list[chan] = ((long long)1 << cfg[j].bits) - 1; + if (cfg[j].bits < 32) + maxdata_list[chan] = (1u << cfg[j].bits) - 1; + else + maxdata_list[chan] = 0xffffffff; chan++; } } |