diff options
author | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2015-08-18 00:33:29 -0300 |
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committer | André Fabian Silva Delgado <emulatorman@parabola.nu> | 2015-08-18 00:33:29 -0300 |
commit | 6ece15cc69504348ad484564d14968c542987053 (patch) | |
tree | cd6194a333518d78edd611023f2e255e4b66c8c9 /include | |
parent | 0a2bb03fe20f81dc4cac96d7fe0e4194ae6efffd (diff) |
Linux-libre 4.1.6-gnu
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/mtd/nand.h | 10 | ||||
-rw-r--r-- | include/uapi/linux/pci_regs.h | 1 |
2 files changed, 6 insertions, 5 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 3d4ea7eb2..12b75f3ba 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -176,17 +176,17 @@ typedef enum { /* Chip may not exist, so silence any errors in scan */ #define NAND_SCAN_SILENT_NODEV 0x00040000 /* - * This option could be defined by controller drivers to protect against - * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers - */ -#define NAND_USE_BOUNCE_BUFFER 0x00080000 -/* * Autodetect nand buswidth with readid/onfi. * This suppose the driver will configure the hardware in 8 bits mode * when calling nand_scan_ident, and update its configuration * before calling nand_scan_tail. */ #define NAND_BUSWIDTH_AUTO 0x00080000 +/* + * This option could be defined by controller drivers to protect against + * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers + */ +#define NAND_USE_BOUNCE_BUFFER 0x00100000 /* Options set by nand scan */ /* Nand scan has allocated controller struct */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index efe344357..413417f37 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -319,6 +319,7 @@ #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ #define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ #define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ +#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ /* MSI-X Table entry format */ |