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Diffstat (limited to 'arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi123
1 files changed, 111 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 1bd507bfa..2a4e10bc8 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -56,6 +56,89 @@
};
};
+&bus_wcore {
+ devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
+ <&nocp_mem1_0>, <&nocp_mem1_1>;
+ vdd-supply = <&buck3_reg>;
+ exynos,saturation-ratio = <100>;
+ status = "okay";
+};
+
+&bus_noc {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_fsys_apb {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_fsys {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_fsys2 {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_mfc {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_gen {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_peri {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_g2d {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_g2d_acp {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_jpeg {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_jpeg_apb {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_disp1_fimd {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_disp1 {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_gscl_scaler {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
+&bus_mscl {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
&clock_audss {
assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
<&clock_audss EXYNOS_MOUT_I2S>,
@@ -92,13 +175,6 @@
s2mps11_pmic@66 {
compatible = "samsung,s2mps11-pmic";
reg = <0x66>;
- s2mps11,buck2-ramp-delay = <12>;
- s2mps11,buck34-ramp-delay = <12>;
- s2mps11,buck16-ramp-delay = <12>;
- s2mps11,buck6-ramp-enable = <1>;
- s2mps11,buck2-ramp-enable = <1>;
- s2mps11,buck3-ramp-enable = <1>;
- s2mps11,buck4-ramp-enable = <1>;
samsung,s2mps11-acokb-ground;
interrupt-parent = <&gpx0>;
@@ -121,10 +197,9 @@
};
ldo3_reg: LDO3 {
- regulator-name = "vdd_ldo3";
+ regulator-name = "vddq_mmc0";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-always-on;
};
ldo5_reg: LDO5 {
@@ -184,10 +259,9 @@
};
ldo13_reg: LDO13 {
- regulator-name = "vdd_ldo13";
+ regulator-name = "vddq_mmc2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- regulator-always-on;
};
ldo15_reg: LDO15 {
@@ -211,11 +285,16 @@
regulator-always-on;
};
+ ldo18_reg: LDO18 {
+ regulator-name = "vdd_emmc_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
ldo19_reg: LDO19 {
regulator-name = "vdd_sd";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- regulator-always-on;
};
ldo24_reg: LDO24 {
@@ -347,6 +426,8 @@
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
+ vmmc-supply = <&ldo18_reg>;
+ vqmmc-supply = <&ldo3_reg>;
};
&mmc_2 {
@@ -359,6 +440,24 @@
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
bus-width = <4>;
cap-sd-highspeed;
+ vmmc-supply = <&ldo19_reg>;
+ vqmmc-supply = <&ldo13_reg>;
+};
+
+&nocp_mem0_0 {
+ status = "okay";
+};
+
+&nocp_mem0_1 {
+ status = "okay";
+};
+
+&nocp_mem1_0 {
+ status = "okay";
+};
+
+&nocp_mem1_1 {
+ status = "okay";
};
&pinctrl_0 {