diff options
Diffstat (limited to 'arch/arm/boot/dts/qcom-apq8084.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8084.dtsi | 108 |
1 files changed, 108 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fcffecae3..08214cbae 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -10,6 +10,17 @@ compatible = "qcom,apq8084"; interrupt-parent = <&intc>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_mem: smem_region@fa00000 { + reg = <0xfa00000 0x200000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -89,6 +100,15 @@ clock-frequency = <19200000>; }; + smem { + compatible = "qcom,smem"; + + qcom,rpm-msg-ram = <&rpm_msg_ram>; + memory-region = <&smem_mem>; + + hwlocks = <&tcsr_mutex 3>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -103,6 +123,11 @@ <0xf9002000 0x1000>; }; + apcs: syscon@f9011000 { + compatible = "syscon"; + reg = <0xf9011000 0x1000>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; @@ -225,6 +250,22 @@ reg = <0xfc400000 0x4000>; }; + tcsr_mutex_regs: syscon@fd484000 { + compatible = "syscon"; + reg = <0xfd484000 0x2000>; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_regs 0 0x80>; + #hwlock-cells = <1>; + }; + + rpm_msg_ram: memory@fc428000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0xfc428000 0x4000>; + }; + tlmm: pinctrl@fd510000 { compatible = "qcom,apq8084-pinctrl"; reg = <0xfd510000 0x4000>; @@ -282,4 +323,71 @@ #interrupt-cells = <4>; }; }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <0 168 1>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-apq8084"; + qcom,smd-channels = "rpm_requests"; + + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + + pma8084_s1: s1 {}; + pma8084_s2: s2 {}; + pma8084_s3: s3 {}; + pma8084_s4: s4 {}; + pma8084_s5: s5 {}; + pma8084_s6: s6 {}; + pma8084_s7: s7 {}; + pma8084_s8: s8 {}; + pma8084_s9: s9 {}; + pma8084_s10: s10 {}; + pma8084_s11: s11 {}; + pma8084_s12: s12 {}; + + pma8084_l1: l1 {}; + pma8084_l2: l2 {}; + pma8084_l3: l3 {}; + pma8084_l4: l4 {}; + pma8084_l5: l5 {}; + pma8084_l6: l6 {}; + pma8084_l7: l7 {}; + pma8084_l8: l8 {}; + pma8084_l9: l9 {}; + pma8084_l10: l10 {}; + pma8084_l11: l11 {}; + pma8084_l12: l12 {}; + pma8084_l13: l13 {}; + pma8084_l14: l14 {}; + pma8084_l15: l15 {}; + pma8084_l16: l16 {}; + pma8084_l17: l17 {}; + pma8084_l18: l18 {}; + pma8084_l19: l19 {}; + pma8084_l20: l20 {}; + pma8084_l21: l21 {}; + pma8084_l22: l22 {}; + pma8084_l23: l23 {}; + pma8084_l24: l24 {}; + pma8084_l25: l25 {}; + pma8084_l26: l26 {}; + pma8084_l27: l27 {}; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; + }; + }; + }; }; |