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-rw-r--r--arch/arm/mach-dove/cm-a510.c1
-rw-r--r--arch/arm/mach-dove/common.c43
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c1
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h2
-rw-r--r--arch/arm/mach-dove/include/mach/entry-macro.S33
-rw-r--r--arch/arm/mach-dove/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-dove/include/mach/pm.h20
-rw-r--r--arch/arm/mach-dove/irq.c100
8 files changed, 55 insertions, 147 deletions
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 0dc39cf30..b9a7c33db 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -88,6 +88,7 @@ static void __init cm_a510_init(void)
MACHINE_START(CM_A510, "Compulab CM-A510 Board")
.atag_offset = 0x100,
+ .nr_irqs = DOVE_NR_IRQS,
.init_machine = cm_a510_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 0d1a89298..0cdaa3851 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,7 @@
#include <linux/platform_data/dma-mv_xor.h>
#include <linux/platform_data/usb-ehci-orion.h>
#include <linux/platform_device.h>
+#include <linux/soc/dove/pmu.h>
#include <asm/hardware/cache-tauros2.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -375,6 +376,47 @@ void __init dove_setup_cpu_wins(void)
DOVE_SCRATCHPAD_SIZE);
}
+static struct resource orion_wdt_resource[] = {
+ DEFINE_RES_MEM(TIMER_PHYS_BASE, 0x04),
+ DEFINE_RES_MEM(RSTOUTn_MASK_PHYS, 0x04),
+};
+
+static struct platform_device orion_wdt_device = {
+ .name = "orion_wdt",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(orion_wdt_resource),
+ .resource = orion_wdt_resource,
+};
+
+static void __init __maybe_unused orion_wdt_init(void)
+{
+ platform_device_register(&orion_wdt_device);
+}
+
+static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
+ {
+ .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
+ .rst_mask = PMU_SW_RST_VIDEO_MASK,
+ .iso_mask = PMU_ISO_VIDEO_MASK,
+ .name = "vpu-domain",
+ }, {
+ .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
+ .rst_mask = PMU_SW_RST_GPU_MASK,
+ .iso_mask = PMU_ISO_GPU_MASK,
+ .name = "gpu-domain",
+ }, {
+ /* sentinel */
+ },
+};
+
+static const struct dove_pmu_initdata pmu_data __initconst = {
+ .pmc_base = DOVE_PMU_VIRT_BASE,
+ .pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
+ .irq = IRQ_DOVE_PMU,
+ .irq_domain_start = IRQ_DOVE_PMU_START,
+ .domains = pmu_domains,
+};
+
void __init dove_init(void)
{
pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -389,6 +431,7 @@ void __init dove_init(void)
dove_clk_init();
/* internal devices that every board has */
+ dove_init_pmu_legacy(&pmu_data);
dove_rtc_init();
dove_xor0_init();
dove_xor1_init();
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 76e26f949..bcb678fd2 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -94,6 +94,7 @@ static void __init dove_db_init(void)
MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
.atag_offset = 0x100,
+ .nr_irqs = DOVE_NR_IRQS,
.init_machine = dove_db_init,
.map_io = dove_map_io,
.init_early = dove_init_early,
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 0c4b35f4e..00f45458b 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -11,6 +11,8 @@
#ifndef __ASM_ARCH_DOVE_H
#define __ASM_ARCH_DOVE_H
+#include <mach/irqs.h>
+
/*
* Marvell Dove address maps.
*
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
deleted file mode 100644
index df1d44bdc..000000000
--- a/arch/arm/mach-dove/include/mach/entry-macro.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell Dove platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/bridge-regs.h>
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =IRQ_VIRT_BASE
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- @ check low interrupts
- ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
- ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
- mov \irqnr, #32
- ands \irqstat, \irqstat, \tmp
-
- @ if no low interrupts set, check high interrupts
- ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
- ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
- moveq \irqnr, #64
- andeqs \irqstat, \irqstat, \tmp
-
- @ find first active interrupt source
- clzne \irqstat, \irqstat
- subne \irqnr, \irqnr, \irqstat
- .endm
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 3f29e6bca..8ff0fa8b4 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -90,7 +90,7 @@
#define NR_PMU_IRQS 7
#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5)
-#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+#define DOVE_NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index b47f75038..d22b9b174 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -51,22 +51,14 @@
#define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY)
#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50)
-#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54)
-static inline int pmu_to_irq(int pin)
-{
- if (pin < NR_PMU_IRQS)
- return pin + IRQ_DOVE_PMU_START;
+#define PMU_SW_RST_VIDEO_MASK BIT(16)
+#define PMU_SW_RST_GPU_MASK BIT(18)
- return -EINVAL;
-}
+#define PMU_PWR_GPU_PWR_DWN_MASK BIT(2)
+#define PMU_PWR_VPU_PWR_DWN_MASK BIT(3)
-static inline int irq_to_pmu(int irq)
-{
- if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)
- return irq - IRQ_DOVE_PMU_START;
-
- return -EINVAL;
-}
+#define PMU_ISO_VIDEO_MASK BIT(0)
+#define PMU_ISO_GPU_MASK BIT(1)
#endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index bfb370335..d6627c1f7 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -7,87 +7,15 @@
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
-
-#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
-#include <linux/gpio.h>
#include <linux/io.h>
-#include <asm/mach/arch.h>
+#include <asm/exception.h>
#include <plat/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/pm.h>
#include <mach/bridge-regs.h>
#include <plat/orion-gpio.h>
#include "common.h"
-static void pmu_irq_mask(struct irq_data *d)
-{
- int pin = irq_to_pmu(d->irq);
- u32 u;
-
- u = readl(PMU_INTERRUPT_MASK);
- u &= ~(1 << (pin & 31));
- writel(u, PMU_INTERRUPT_MASK);
-}
-
-static void pmu_irq_unmask(struct irq_data *d)
-{
- int pin = irq_to_pmu(d->irq);
- u32 u;
-
- u = readl(PMU_INTERRUPT_MASK);
- u |= 1 << (pin & 31);
- writel(u, PMU_INTERRUPT_MASK);
-}
-
-static void pmu_irq_ack(struct irq_data *d)
-{
- int pin = irq_to_pmu(d->irq);
- u32 u;
-
- /*
- * The PMU mask register is not RW0C: it is RW. This means that
- * the bits take whatever value is written to them; if you write
- * a '1', you will set the interrupt.
- *
- * Unfortunately this means there is NO race free way to clear
- * these interrupts.
- *
- * So, let's structure the code so that the window is as small as
- * possible.
- */
- u = ~(1 << (pin & 31));
- u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
- writel_relaxed(u, PMU_INTERRUPT_CAUSE);
-}
-
-static struct irq_chip pmu_irq_chip = {
- .name = "pmu_irq",
- .irq_mask = pmu_irq_mask,
- .irq_unmask = pmu_irq_unmask,
- .irq_ack = pmu_irq_ack,
-};
-
-static void pmu_irq_handler(struct irq_desc *desc)
-{
- unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
- unsigned int irq;
-
- cause &= readl(PMU_INTERRUPT_MASK);
- if (cause == 0) {
- do_bad_IRQ(desc);
- return;
- }
-
- for (irq = 0; irq < NR_PMU_IRQS; irq++) {
- if (!(cause & (1 << irq)))
- continue;
- irq = pmu_to_irq(irq);
- generic_handle_irq(irq);
- }
-}
-
static int __initdata gpio0_irqs[4] = {
IRQ_DOVE_GPIO_0_7,
IRQ_DOVE_GPIO_8_15,
@@ -109,14 +37,6 @@ static int __initdata gpio2_irqs[4] = {
0,
};
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-/*
- * Compiling with both non-DT and DT support enabled, will
- * break asm irq handler used by non-DT boards. Therefore,
- * we provide a C-style irq handler even for non-DT boards,
- * if MULTI_IRQ_HANDLER is set.
- */
-
static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
static asmlinkage void
@@ -139,18 +59,13 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
return;
}
}
-#endif
void __init dove_init_irq(void)
{
- int i;
-
orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
-#ifdef CONFIG_MULTI_IRQ_HANDLER
set_handle_irq(dove_legacy_handle_irq);
-#endif
/*
* Initialize gpiolib for GPIOs 0-71.
@@ -163,17 +78,4 @@ void __init dove_init_irq(void)
orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
-
- /*
- * Mask and clear PMU interrupts
- */
- writel(0, PMU_INTERRUPT_MASK);
- writel(0, PMU_INTERRUPT_CAUSE);
-
- for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
- irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
- irq_set_status_flags(i, IRQ_LEVEL);
- irq_clear_status_flags(i, IRQ_NOREQUEST);
- }
- irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
}