diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine')
87 files changed, 664 insertions, 592 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c index 3ef01071f..8e2e24a74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c @@ -27,7 +27,6 @@ static const struct nvkm_xtensa_func g84_bsp = { - .pmc_enable = 0x04008000, .fifo_val = 0x1111, .unkd28 = 0x90044, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c index 92a9f35df..ad9f855c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -40,7 +40,6 @@ gf100_ce0 = { .code.size = sizeof(gf100_ce_code), .data.data = gf100_ce_data, .data.size = sizeof(gf100_ce_data), - .pmc_enable = 0x00000040, .init = gf100_ce_init, .intr = gt215_ce_intr, .sclass = { @@ -55,7 +54,6 @@ gf100_ce1 = { .code.size = sizeof(gf100_ce_code), .data.data = gf100_ce_data, .data.size = sizeof(gf100_ce_data), - .pmc_enable = 0x00000080, .init = gf100_ce_init, .intr = gt215_ce_intr, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index e2b944dce..9e0b53a10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -97,17 +97,5 @@ int gk104_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVKM_ENGINE_CE0) { - return nvkm_engine_new_(&gk104_ce, device, index, - 0x00000040, true, pengine); - } else - if (index == NVKM_ENGINE_CE1) { - return nvkm_engine_new_(&gk104_ce, device, index, - 0x00000080, true, pengine); - } else - if (index == NVKM_ENGINE_CE2) { - return nvkm_engine_new_(&gk104_ce, device, index, - 0x00200000, true, pengine); - } - return -ENODEV; + return nvkm_engine_new_(&gk104_ce, device, index, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c index 4c2f42919..c0df7daa8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.c @@ -39,17 +39,5 @@ int gm107_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVKM_ENGINE_CE0) { - return nvkm_engine_new_(&gm107_ce, device, index, - 0x00000040, true, pengine); - } else - if (index == NVKM_ENGINE_CE1) { - return nvkm_engine_new_(&gm107_ce, device, index, - 0x00000080, true, pengine); - } else - if (index == NVKM_ENGINE_CE2) { - return nvkm_engine_new_(&gm107_ce, device, index, - 0x00200000, true, pengine); - } - return -ENODEV; + return nvkm_engine_new_(&gm107_ce, device, index, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c index 13f07b32c..c6fa8b207 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.c @@ -38,17 +38,5 @@ int gm200_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVKM_ENGINE_CE0) { - return nvkm_engine_new_(&gm200_ce, device, index, - 0x00000040, true, pengine); - } else - if (index == NVKM_ENGINE_CE1) { - return nvkm_engine_new_(&gm200_ce, device, index, - 0x00000080, true, pengine); - } else - if (index == NVKM_ENGINE_CE2) { - return nvkm_engine_new_(&gm200_ce, device, index, - 0x00200000, true, pengine); - } - return -ENODEV; + return nvkm_engine_new_(&gm200_ce, device, index, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 402dcbcc2..63ac51a54 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -67,7 +67,6 @@ gt215_ce = { .code.size = sizeof(gt215_ce_code), .data.data = gt215_ce_data, .data.size = sizeof(gt215_ce_data), - .pmc_enable = 0x00802000, .intr = gt215_ce_intr, .sclass = { { -1, -1, GT212_DMA }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index bfd01625e..68ffb5205 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -130,6 +130,5 @@ int g84_cipher_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - return nvkm_engine_new_(&g84_cipher, device, index, - 0x00004000, true, pengine); + return nvkm_engine_new_(&g84_cipher, device, index, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 9f32c8739..4572debcb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -146,7 +146,7 @@ nv11_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv11_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -190,7 +190,7 @@ nv17_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -212,7 +212,7 @@ nv18_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -256,7 +256,7 @@ nv1f_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -278,7 +278,7 @@ nv20_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -300,7 +300,7 @@ nv25_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -322,7 +322,7 @@ nv28_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -344,7 +344,7 @@ nv2a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -366,7 +366,7 @@ nv30_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -388,7 +388,7 @@ nv31_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -411,7 +411,7 @@ nv34_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -434,7 +434,7 @@ nv35_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -456,7 +456,7 @@ nv36_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, @@ -479,7 +479,7 @@ nv40_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -505,7 +505,7 @@ nv41_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -531,7 +531,7 @@ nv42_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -557,7 +557,7 @@ nv43_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -609,7 +609,7 @@ nv45_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -661,7 +661,7 @@ nv47_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -687,7 +687,7 @@ nv49_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -739,7 +739,7 @@ nv4b_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, - .mc = nv04_mc_new, + .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, @@ -926,7 +926,7 @@ nv84_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, - .mc = nv50_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g84_pci_new, @@ -958,7 +958,7 @@ nv86_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, - .mc = nv50_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g84_pci_new, @@ -990,7 +990,7 @@ nv92_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, - .mc = nv50_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g84_pci_new, @@ -1022,7 +1022,7 @@ nv94_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = nv50_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1054,7 +1054,7 @@ nv96_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = nv50_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1118,7 +1118,7 @@ nva0_chipset = { .gpio = g94_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, - .mc = g98_mc_new, + .mc = g84_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1150,7 +1150,7 @@ nva3_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = g98_mc_new, + .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1184,7 +1184,7 @@ nva5_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = g98_mc_new, + .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1217,7 +1217,7 @@ nva8_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = g98_mc_new, + .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1314,7 +1314,7 @@ nvaf_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, - .mc = g98_mc_new, + .mc = gt215_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .pci = g94_pci_new, @@ -1676,13 +1676,14 @@ nve4_chipset = { .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, - .mc = gf100_mc_new, + .mc = gk104_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1714,13 +1715,14 @@ nve6_chipset = { .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, - .mc = gf100_mc_new, + .mc = gk104_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1752,13 +1754,14 @@ nve7_chipset = { .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, - .mc = gf100_mc_new, + .mc = gk104_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1789,6 +1792,7 @@ nvea_chipset = { .mmu = gf100_mmu_new, .pmu = gk20a_pmu_new, .timer = gk20a_timer_new, + .top = gk104_top_new, .volt = gk20a_volt_new, .ce[2] = gk104_ce_new, .dma = gf119_dma_new, @@ -1814,13 +1818,14 @@ nvf0_chipset = { .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, - .mc = gf100_mc_new, + .mc = gk104_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1851,13 +1856,14 @@ nvf1_chipset = { .iccsense = gf100_iccsense_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, - .mc = gf100_mc_new, + .mc = gk104_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1895,6 +1901,7 @@ nv106_chipset = { .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1932,6 +1939,7 @@ nv108_chipset = { .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, @@ -1969,6 +1977,41 @@ nv117_chipset = { .pmu = gm107_pmu_new, .therm = gm107_therm_new, .timer = gk20a_timer_new, + .top = gk104_top_new, + .volt = gk104_volt_new, + .ce[0] = gm107_ce_new, + .ce[2] = gm107_ce_new, + .disp = gm107_disp_new, + .dma = gf119_dma_new, + .fifo = gm107_fifo_new, + .gr = gm107_gr_new, + .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv118_chipset = { + .name = "GM108", + .bar = gf100_bar_new, + .bios = nvkm_bios_new, + .bus = gf100_bus_new, + .clk = gk104_clk_new, + .devinit = gm107_devinit_new, + .fb = gm107_fb_new, + .fuse = gm107_fuse_new, + .gpio = gk104_gpio_new, + .i2c = gf119_i2c_new, + .ibus = gk104_ibus_new, + .iccsense = gf100_iccsense_new, + .imem = nv50_instmem_new, + .ltc = gm107_ltc_new, + .mc = gk20a_mc_new, + .mmu = gf100_mmu_new, + .mxm = nv50_mxm_new, + .pci = gk104_pci_new, + .pmu = gm107_pmu_new, + .therm = gm107_therm_new, + .timer = gk20a_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gm107_ce_new, .ce[2] = gm107_ce_new, @@ -1986,7 +2029,7 @@ nv120_chipset = { .bios = nvkm_bios_new, .bus = gf100_bus_new, .devinit = gm200_devinit_new, - .fb = gm107_fb_new, + .fb = gm200_fb_new, .fuse = gm107_fuse_new, .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, @@ -2001,6 +2044,7 @@ nv120_chipset = { .pmu = gm107_pmu_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gm200_ce_new, .ce[1] = gm200_ce_new, @@ -2019,7 +2063,7 @@ nv124_chipset = { .bios = nvkm_bios_new, .bus = gf100_bus_new, .devinit = gm200_devinit_new, - .fb = gm107_fb_new, + .fb = gm200_fb_new, .fuse = gm107_fuse_new, .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, @@ -2034,6 +2078,7 @@ nv124_chipset = { .pmu = gm107_pmu_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gm200_ce_new, .ce[1] = gm200_ce_new, @@ -2052,7 +2097,7 @@ nv126_chipset = { .bios = nvkm_bios_new, .bus = gf100_bus_new, .devinit = gm200_devinit_new, - .fb = gm107_fb_new, + .fb = gm200_fb_new, .fuse = gm107_fuse_new, .gpio = gk104_gpio_new, .i2c = gm200_i2c_new, @@ -2067,6 +2112,7 @@ nv126_chipset = { .pmu = gm107_pmu_new, .secboot = gm200_secboot_new, .timer = gk20a_timer_new, + .top = gk104_top_new, .volt = gk104_volt_new, .ce[0] = gm200_ce_new, .ce[1] = gm200_ce_new, @@ -2093,6 +2139,7 @@ nv12b_chipset = { .mmu = gf100_mmu_new, .secboot = gm20b_secboot_new, .timer = gk20a_timer_new, + .top = gk104_top_new, .ce[2] = gm200_ce_new, .volt = gm20b_volt_new, .dma = gf119_dma_new, @@ -2150,6 +2197,7 @@ nvkm_device_subdev(struct nvkm_device *device, int index) _(SECBOOT , device->secboot , &device->secboot->subdev); _(THERM , device->therm , &device->therm->subdev); _(TIMER , device->timer , &device->timer->subdev); + _(TOP , device->top , &device->top->subdev); _(VOLT , device->volt , &device->volt->subdev); #undef _ default: @@ -2523,6 +2571,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x106: device->chip = &nv106_chipset; break; case 0x108: device->chip = &nv108_chipset; break; case 0x117: device->chip = &nv117_chipset; break; + case 0x118: device->chip = &nv118_chipset; break; case 0x120: device->chip = &nv120_chipset; break; case 0x124: device->chip = &nv124_chipset; break; case 0x126: device->chip = &nv126_chipset; break; @@ -2604,6 +2653,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, _(NVKM_SUBDEV_SECBOOT , secboot); _(NVKM_SUBDEV_THERM , therm); _(NVKM_SUBDEV_TIMER , timer); + _(NVKM_SUBDEV_TOP , top); _(NVKM_SUBDEV_VOLT , volt); _(NVKM_ENGINE_BSP , bsp); _(NVKM_ENGINE_CE0 , ce[0]); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index e80f6ab1c..1a06ac175 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -22,6 +22,7 @@ #include <subdev/pmu.h> #include <subdev/therm.h> #include <subdev/timer.h> +#include <subdev/top.h> #include <subdev/volt.h> #include <subdev/secboot.h> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 785fa76d0..1efe91b1e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -298,8 +298,7 @@ nvkm_disp_ctor(const struct nvkm_disp_func *func, struct nvkm_device *device, disp->func = func; disp->head.nr = heads; - ret = nvkm_engine_ctor(&nvkm_disp, device, index, 0, - true, &disp->engine); + ret = nvkm_engine_ctor(&nvkm_disp, device, index, true, &disp->engine); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 9769fc0d5..f11ebdd16 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -152,6 +152,5 @@ nvkm_dma_new_(const struct nvkm_dma_func *func, struct nvkm_device *device, return -ENOMEM; dma->func = func; - return nvkm_engine_ctor(&nvkm_dma, device, index, - 0, true, &dma->engine); + return nvkm_engine_ctor(&nvkm_dma, device, index, true, &dma->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index acc8693bb..a20b6aff7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -348,6 +348,6 @@ nvkm_falcon_new_(const struct nvkm_falcon_func *func, falcon->data.size = func->data.size; *pengine = &falcon->engine; - return nvkm_engine_ctor(&nvkm_falcon, device, index, func->pmc_enable, + return nvkm_engine_ctor(&nvkm_falcon, device, index, enable, &falcon->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index cfc7d5725..1c9682ae3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -178,6 +178,17 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, const struct nvkm_fifo_chan_oclass *sclass; int c = 0; + if (fifo->func->class_get) { + int ret = fifo->func->class_get(fifo, index, &sclass); + if (ret == 0) { + oclass->base = sclass->base; + oclass->engn = sclass; + *class = &nvkm_fifo_class; + return 0; + } + return ret; + } + while ((sclass = fifo->func->chan[c])) { if (c++ == index) { oclass->base = sclass->base; @@ -261,8 +272,7 @@ nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, fifo->nr = nr; bitmap_clear(fifo->mask, 0, fifo->nr); - ret = nvkm_engine_ctor(&nvkm_fifo, device, index, 0x00000100, - true, &fifo->engine); + ret = nvkm_engine_ctor(&nvkm_fifo, device, index, true, &fifo->engine); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 68acb36b3..743f3a189 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -25,21 +25,36 @@ #include "changk104.h" #include <core/client.h> -#include <core/enum.h> #include <core/gpuobj.h> #include <subdev/bar.h> +#include <subdev/top.h> #include <engine/sw.h> #include <nvif/class.h> -void +static int +gk104_fifo_class_get(struct nvkm_fifo *base, int index, + const struct nvkm_fifo_chan_oclass **psclass) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + int c = 0; + + while ((*psclass = fifo->func->chan[c])) { + if (c++ == index) + return 0; + } + + return c; +} + +static void gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) { struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); } -void +static void gk104_fifo_uevent_init(struct nvkm_fifo *fifo) { struct nvkm_device *device = fifo->engine.subdev.device; @@ -267,111 +282,6 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); } -static const struct nvkm_enum -gk104_fifo_fault_engine[] = { - { 0x00, "GR", NULL, NVKM_ENGINE_GR }, - { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, - { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, - { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM }, - { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO }, - { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO }, - { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO }, - { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, - { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, - { 0x13, "PERF" }, - { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, - { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, - { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, - { 0x17, "PMU" }, - { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, - { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, - {} -}; - -static const struct nvkm_enum -gk104_fifo_fault_reason[] = { - { 0x00, "PDE" }, - { 0x01, "PDE_SIZE" }, - { 0x02, "PTE" }, - { 0x03, "VA_LIMIT_VIOLATION" }, - { 0x04, "UNBOUND_INST_BLOCK" }, - { 0x05, "PRIV_VIOLATION" }, - { 0x06, "RO_VIOLATION" }, - { 0x07, "WO_VIOLATION" }, - { 0x08, "PITCH_MASK_VIOLATION" }, - { 0x09, "WORK_CREATION" }, - { 0x0a, "UNSUPPORTED_APERTURE" }, - { 0x0b, "COMPRESSION_FAILURE" }, - { 0x0c, "UNSUPPORTED_KIND" }, - { 0x0d, "REGION_VIOLATION" }, - { 0x0e, "BOTH_PTES_VALID" }, - { 0x0f, "INFO_TYPE_POISONED" }, - {} -}; - -static const struct nvkm_enum -gk104_fifo_fault_hubclient[] = { - { 0x00, "VIP" }, - { 0x01, "CE0" }, - { 0x02, "CE1" }, - { 0x03, "DNISO" }, - { 0x04, "FE" }, - { 0x05, "FECS" }, - { 0x06, "HOST" }, - { 0x07, "HOST_CPU" }, - { 0x08, "HOST_CPU_NB" }, - { 0x09, "ISO" }, - { 0x0a, "MMU" }, - { 0x0b, "MSPDEC" }, - { 0x0c, "MSPPP" }, - { 0x0d, "MSVLD" }, - { 0x0e, "NISO" }, - { 0x0f, "P2P" }, - { 0x10, "PD" }, - { 0x11, "PERF" }, - { 0x12, "PMU" }, - { 0x13, "RASTERTWOD" }, - { 0x14, "SCC" }, - { 0x15, "SCC_NB" }, - { 0x16, "SEC" }, - { 0x17, "SSYNC" }, - { 0x18, "GR_CE" }, - { 0x19, "CE2" }, - { 0x1a, "XV" }, - { 0x1b, "MMU_NB" }, - { 0x1c, "MSENC" }, - { 0x1d, "DFALCON" }, - { 0x1e, "SKED" }, - { 0x1f, "AFALCON" }, - {} -}; - -static const struct nvkm_enum -gk104_fifo_fault_gpcclient[] = { - { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, - { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, - { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, - { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, - { 0x0c, "RAST" }, - { 0x0d, "GCC" }, - { 0x0e, "GPCCS" }, - { 0x0f, "PROP_0" }, - { 0x10, "PROP_1" }, - { 0x11, "PROP_2" }, - { 0x12, "PROP_3" }, - { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, - { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, - { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, - { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, - { 0x1f, "GPM" }, - { 0x20, "LTP_UTLB_0" }, - { 0x21, "LTP_UTLB_1" }, - { 0x22, "LTP_UTLB_2" }, - { 0x23, "LTP_UTLB_3" }, - { 0x24, "GPC_RGG_UTLB" }, - {} -}; - static void gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) { @@ -390,14 +300,14 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; - char gpcid[8] = ""; + char gpcid[8] = "", en[16] = ""; - er = nvkm_enum_find(gk104_fifo_fault_reason, reason); - eu = nvkm_enum_find(gk104_fifo_fault_engine, unit); + er = nvkm_enum_find(fifo->func->fault.reason, reason); + eu = nvkm_enum_find(fifo->func->fault.engine, unit); if (hub) { - ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client); + ec = nvkm_enum_find(fifo->func->fault.hubclient, client); } else { - ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client); + ec = nvkm_enum_find(fifo->func->fault.gpcclient, client); snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); } @@ -418,13 +328,27 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) } } + if (eu == NULL) { + enum nvkm_devidx engidx = nvkm_top_fault(device->top, unit); + if (engidx < NVKM_SUBDEV_NR) { + const char *src = nvkm_subdev_name[engidx]; + char *dst = en; + do { + *dst++ = toupper(*src++); + } while(*src); + engine = nvkm_device_engine(device, engidx); + } + } else { + snprintf(en, sizeof(en), "%s", eu->name); + } + chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); nvkm_error(subdev, "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " "reason %02x [%s] on channel %d [%010llx %s]\n", write ? "write" : "read", (u64)vahi << 32 | valo, - unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", + unit, en, client, gpcid, ec ? ec->name : "", reason, er ? er->name : "", chan ? chan->chid : -1, (u64)inst << 12, chan ? chan->object.client->name : "unknown"); @@ -557,7 +481,7 @@ gk104_fifo_intr_engine(struct gk104_fifo *fifo) nvkm_fifo_uevent(&fifo->base); } -void +static void gk104_fifo_intr(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -649,7 +573,7 @@ gk104_fifo_intr(struct nvkm_fifo *base) } } -void +static void gk104_fifo_fini(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -659,13 +583,15 @@ gk104_fifo_fini(struct nvkm_fifo *base) nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); } -int +static int gk104_fifo_oneinit(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - int ret, i; + struct nvkm_top *top = device->top; + int engn, runl, pbid, ret, i, j; + enum nvkm_devidx engidx; u32 *map; /* Determine number of PBDMAs by checking valid enable bits. */ @@ -680,86 +606,26 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) for (i = 0; i < fifo->pbdma_nr; i++) map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04)); - /* Read device topology from HW. */ - for (i = 0; i < 64; i++) { - int type = -1, pbid = -1, engidx = -1; - int engn = -1, runl = -1, intr = -1, mcen = -1; - int fault = -1, j; - u32 data, addr = 0; - - do { - data = nvkm_rd32(device, 0x022700 + (i * 0x04)); - nvkm_trace(subdev, "%02x: %08x\n", i, data); - switch (data & 0x00000003) { - case 0x00000000: /* NOT_VALID */ - continue; - case 0x00000001: /* DATA */ - addr = (data & 0x00fff000); - fault = (data & 0x000000f8) >> 3; - break; - case 0x00000002: /* ENUM */ - if (data & 0x00000020) - engn = (data & 0x3c000000) >> 26; - if (data & 0x00000010) - runl = (data & 0x01e00000) >> 21; - if (data & 0x00000008) - intr = (data & 0x000f8000) >> 15; - if (data & 0x00000004) - mcen = (data & 0x00003e00) >> 9; - break; - case 0x00000003: /* ENGINE_TYPE */ - type = (data & 0x7ffffffc) >> 2; - break; - } - } while ((data & 0x80000000) && ++i < 64); - - if (!data) - continue; - + /* Determine runlist configuration from topology device info. */ + i = 0; + while ((int)(engidx = nvkm_top_engine(top, i++, &runl, &engn)) >= 0) { /* Determine which PBDMA handles requests for this engine. */ - for (j = 0; runl >= 0 && j < fifo->pbdma_nr; j++) { + for (j = 0, pbid = -1; j < fifo->pbdma_nr; j++) { if (map[j] & (1 << runl)) { pbid = j; break; } } - /* Translate engine type to NVKM engine identifier. */ - switch (type) { - case 0x00000000: engidx = NVKM_ENGINE_GR; break; - case 0x00000001: engidx = NVKM_ENGINE_CE0; break; - case 0x00000002: engidx = NVKM_ENGINE_CE1; break; - case 0x00000003: engidx = NVKM_ENGINE_CE2; break; - case 0x00000008: engidx = NVKM_ENGINE_MSPDEC; break; - case 0x00000009: engidx = NVKM_ENGINE_MSPPP; break; - case 0x0000000a: engidx = NVKM_ENGINE_MSVLD; break; - case 0x0000000b: engidx = NVKM_ENGINE_MSENC; break; - case 0x0000000c: engidx = NVKM_ENGINE_VIC; break; - case 0x0000000d: engidx = NVKM_ENGINE_SEC; break; - case 0x0000000e: engidx = NVKM_ENGINE_NVENC0; break; - case 0x0000000f: engidx = NVKM_ENGINE_NVENC1; break; - case 0x00000010: engidx = NVKM_ENGINE_NVDEC; break; - break; - default: - break; - } + nvkm_debug(subdev, "engine %2d: runlist %2d pbdma %2d\n", + engn, runl, pbid); - nvkm_debug(subdev, "%02x (%8s): engine %2d runlist %2d " - "pbdma %2d intr %2d reset %2d " - "fault %2d addr %06x\n", type, - engidx < 0 ? NULL : nvkm_subdev_name[engidx], - engn, runl, pbid, intr, mcen, fault, addr); - - /* Mark the engine as supported if everything checks out. */ - if (engn >= 0 && runl >= 0) { - fifo->engine[engn].engine = engidx < 0 ? NULL : - nvkm_device_engine(device, engidx); - fifo->engine[engn].runl = runl; - fifo->engine[engn].pbid = pbid; - fifo->engine_nr = max(fifo->engine_nr, engn + 1); - fifo->runlist[runl].engm |= 1 << engn; - fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); - } + fifo->engine[engn].engine = nvkm_device_engine(device, engidx); + fifo->engine[engn].runl = runl; + fifo->engine[engn].pbid = pbid; + fifo->engine_nr = max(fifo->engine_nr, engn + 1); + fifo->runlist[runl].engm |= 1 << engn; + fifo->runlist_nr = max(fifo->runlist_nr, runl + 1); } kfree(map); @@ -796,7 +662,7 @@ gk104_fifo_oneinit(struct nvkm_fifo *base) return 0; } -void +static void gk104_fifo_init(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -825,7 +691,7 @@ gk104_fifo_init(struct nvkm_fifo *base) nvkm_wr32(device, 0x002140, 0x7fffffff); } -void * +static void * gk104_fifo_dtor(struct nvkm_fifo *base) { struct gk104_fifo *fifo = gk104_fifo(base); @@ -842,29 +708,154 @@ gk104_fifo_dtor(struct nvkm_fifo *base) return fifo; } +static const struct nvkm_fifo_func +gk104_fifo_ = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, + .class_get = gk104_fifo_class_get, +}; + int -gk104_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, +gk104_fifo_new_(const struct gk104_fifo_func *func, struct nvkm_device *device, int index, int nr, struct nvkm_fifo **pfifo) { struct gk104_fifo *fifo; if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) return -ENOMEM; + fifo->func = func; INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work); *pfifo = &fifo->base; - return nvkm_fifo_ctor(func, device, index, nr, &fifo->base); + return nvkm_fifo_ctor(&gk104_fifo_, device, index, nr, &fifo->base); } -static const struct nvkm_fifo_func +const struct nvkm_enum +gk104_fifo_fault_engine[] = { + { 0x00, "GR", NULL, NVKM_ENGINE_GR }, + { 0x01, "DISPLAY" }, + { 0x02, "CAPTURE" }, + { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, + { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, + { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, + { 0x06, "SCHED" }, + { 0x07, "HOST0" }, + { 0x08, "HOST1" }, + { 0x09, "HOST2" }, + { 0x0a, "HOST3" }, + { 0x0b, "HOST4" }, + { 0x0c, "HOST5" }, + { 0x0d, "HOST6" }, + { 0x0e, "HOST7" }, + { 0x0f, "HOSTSR" }, + { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, + { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, + { 0x13, "PERF" }, + { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, + { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, + { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, + { 0x17, "PMU" }, + { 0x18, "PTP" }, + { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, + { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, + {} +}; + +const struct nvkm_enum +gk104_fifo_fault_reason[] = { + { 0x00, "PDE" }, + { 0x01, "PDE_SIZE" }, + { 0x02, "PTE" }, + { 0x03, "VA_LIMIT_VIOLATION" }, + { 0x04, "UNBOUND_INST_BLOCK" }, + { 0x05, "PRIV_VIOLATION" }, + { 0x06, "RO_VIOLATION" }, + { 0x07, "WO_VIOLATION" }, + { 0x08, "PITCH_MASK_VIOLATION" }, + { 0x09, "WORK_CREATION" }, + { 0x0a, "UNSUPPORTED_APERTURE" }, + { 0x0b, "COMPRESSION_FAILURE" }, + { 0x0c, "UNSUPPORTED_KIND" }, + { 0x0d, "REGION_VIOLATION" }, + { 0x0e, "BOTH_PTES_VALID" }, + { 0x0f, "INFO_TYPE_POISONED" }, + {} +}; + +const struct nvkm_enum +gk104_fifo_fault_hubclient[] = { + { 0x00, "VIP" }, + { 0x01, "CE0" }, + { 0x02, "CE1" }, + { 0x03, "DNISO" }, + { 0x04, "FE" }, + { 0x05, "FECS" }, + { 0x06, "HOST" }, + { 0x07, "HOST_CPU" }, + { 0x08, "HOST_CPU_NB" }, + { 0x09, "ISO" }, + { 0x0a, "MMU" }, + { 0x0b, "MSPDEC" }, + { 0x0c, "MSPPP" }, + { 0x0d, "MSVLD" }, + { 0x0e, "NISO" }, + { 0x0f, "P2P" }, + { 0x10, "PD" }, + { 0x11, "PERF" }, + { 0x12, "PMU" }, + { 0x13, "RASTERTWOD" }, + { 0x14, "SCC" }, + { 0x15, "SCC_NB" }, + { 0x16, "SEC" }, + { 0x17, "SSYNC" }, + { 0x18, "GR_CE" }, + { 0x19, "CE2" }, + { 0x1a, "XV" }, + { 0x1b, "MMU_NB" }, + { 0x1c, "MSENC" }, + { 0x1d, "DFALCON" }, + { 0x1e, "SKED" }, + { 0x1f, "AFALCON" }, + {} +}; + +const struct nvkm_enum +gk104_fifo_fault_gpcclient[] = { + { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, + { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, + { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, + { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, + { 0x0c, "RAST" }, + { 0x0d, "GCC" }, + { 0x0e, "GPCCS" }, + { 0x0f, "PROP_0" }, + { 0x10, "PROP_1" }, + { 0x11, "PROP_2" }, + { 0x12, "PROP_3" }, + { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, + { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, + { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, + { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, + { 0x1f, "GPM" }, + { 0x20, "LTP_UTLB_0" }, + { 0x21, "LTP_UTLB_1" }, + { 0x22, "LTP_UTLB_2" }, + { 0x23, "LTP_UTLB_3" }, + { 0x24, "GPC_RGG_UTLB" }, + {} +}; + +static const struct gk104_fifo_func gk104_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gk104_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gk104_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 9e5d00ba3..679f3ec31 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -3,10 +3,12 @@ #define gk104_fifo(p) container_of((p), struct gk104_fifo, base) #include "priv.h" +#include <core/enum.h> #include <subdev/mmu.h> struct gk104_fifo_chan; struct gk104_fifo { + const struct gk104_fifo_func *func; struct nvkm_fifo base; struct { @@ -39,15 +41,19 @@ struct gk104_fifo { } user; }; -int gk104_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, +struct gk104_fifo_func { + struct { + const struct nvkm_enum *engine; + const struct nvkm_enum *reason; + const struct nvkm_enum *hubclient; + const struct nvkm_enum *gpcclient; + } fault; + + const struct nvkm_fifo_chan_oclass *chan[]; +}; + +int gk104_fifo_new_(const struct gk104_fifo_func *, struct nvkm_device *, int index, int nr, struct nvkm_fifo **); -void *gk104_fifo_dtor(struct nvkm_fifo *); -int gk104_fifo_oneinit(struct nvkm_fifo *); -void gk104_fifo_init(struct nvkm_fifo *); -void gk104_fifo_fini(struct nvkm_fifo *); -void gk104_fifo_intr(struct nvkm_fifo *); -void gk104_fifo_uevent_init(struct nvkm_fifo *); -void gk104_fifo_uevent_fini(struct nvkm_fifo *); void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *); void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *); void gk104_fifo_runlist_commit(struct gk104_fifo *, int runl); @@ -70,4 +76,11 @@ gk104_fifo_engine_subdev(int engine) return 0; } } + +extern const struct nvkm_enum gk104_fifo_fault_engine[]; +extern const struct nvkm_enum gk104_fifo_fault_reason[]; +extern const struct nvkm_enum gk104_fifo_fault_hubclient[]; +extern const struct nvkm_enum gk104_fifo_fault_gpcclient[]; + +extern const struct nvkm_enum gm107_fifo_fault_engine[]; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c index 41307fcd4..b2f8ab7bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c @@ -24,15 +24,12 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +static const struct gk104_fifo_func gk110_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gk104_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gk110_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index ce01c1a7d..160617d37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -24,15 +24,12 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +static const struct gk104_fifo_func gk208_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gk104_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gk104_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index b47fe98f4..be9f5c16e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -22,15 +22,12 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +static const struct gk104_fifo_func gk20a_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gk104_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gk104_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c index 6d59d6579..bd1ff877a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c @@ -24,15 +24,35 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +const struct nvkm_enum +gm107_fifo_fault_engine[] = { + { 0x01, "DISPLAY" }, + { 0x02, "CAPTURE" }, + { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, + { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, + { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, + { 0x06, "SCHED" }, + { 0x07, "HOST0" }, + { 0x08, "HOST1" }, + { 0x09, "HOST2" }, + { 0x0a, "HOST3" }, + { 0x0b, "HOST4" }, + { 0x0c, "HOST5" }, + { 0x0d, "HOST6" }, + { 0x0e, "HOST7" }, + { 0x0f, "HOSTSR" }, + { 0x13, "PERF" }, + { 0x17, "PMU" }, + { 0x18, "PTP" }, + {} +}; + +static const struct gk104_fifo_func gm107_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gm107_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gk110_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c index 4bdd43078..b069f785c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c @@ -24,15 +24,12 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +static const struct gk104_fifo_func gm200_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gm107_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gm200_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c index 4c91d4aa1..2ed87c2e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c @@ -22,15 +22,12 @@ #include "gk104.h" #include "changk104.h" -static const struct nvkm_fifo_func +static const struct gk104_fifo_func gm20b_fifo = { - .dtor = gk104_fifo_dtor, - .oneinit = gk104_fifo_oneinit, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - .intr = gk104_fifo_intr, - .uevent_init = gk104_fifo_uevent_init, - .uevent_fini = gk104_fifo_uevent_fini, + .fault.engine = gm107_fifo_fault_engine, + .fault.reason = gk104_fifo_fault_reason, + .fault.hubclient = gk104_fifo_fault_hubclient, + .fault.gpcclient = gk104_fifo_fault_gpcclient, .chan = { &gm200_fifo_gpfifo_oclass, NULL diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index cb1432e9b..f6dfb37d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -7,6 +7,7 @@ int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, int index, int nr, struct nvkm_fifo *); void nvkm_fifo_uevent(struct nvkm_fifo *); +struct nvkm_fifo_chan_oclass; struct nvkm_fifo_func { void *(*dtor)(struct nvkm_fifo *); int (*oneinit)(struct nvkm_fifo *); @@ -17,6 +18,8 @@ struct nvkm_fifo_func { void (*start)(struct nvkm_fifo *, unsigned long *); void (*uevent_init)(struct nvkm_fifo *); void (*uevent_fini)(struct nvkm_fifo *); + int (*class_get)(struct nvkm_fifo *, int index, + const struct nvkm_fifo_chan_oclass **); const struct nvkm_fifo_chan_oclass *chan[]; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index 090765ff0..467065d1b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -128,9 +128,8 @@ nvkm_gr = { int nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device, - int index, u32 pmc_enable, bool enable, struct nvkm_gr *gr) + int index, bool enable, struct nvkm_gr *gr) { gr->func = func; - return nvkm_engine_ctor(&nvkm_gr, device, index, pmc_enable, - enable, &gr->engine); + return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 56f392d3d..b02d8f50e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1181,20 +1181,20 @@ gf100_grctx_generate_r418bb8(struct gf100_gr *gr) /* GPC_BROADCAST */ nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | - gr->magic_not_rop_nr); + gr->screen_tile_row_offset); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | - gr->magic_not_rop_nr | data2[0]); + gr->screen_tile_row_offset | data2[0]); nvkm_wr32(device, 0x419be4, data2[1]); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x419b00 + (i * 4), data[i]); /* UNK78xx */ nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | - gr->magic_not_rop_nr); + gr->screen_tile_row_offset); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x40780c + (i * 4), data[i]); } @@ -1238,6 +1238,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; + u32 idle_timeout; nvkm_mc_unk260(device->mc, 0); @@ -1247,7 +1248,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, grctx->tpc); gf100_gr_mmio(gr, grctx->ppc); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->bundle(info); grctx->pagepool(info); @@ -1261,7 +1262,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r406800(gr); gf100_gr_icmd(gr, grctx->icmd); - nvkm_wr32(device, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device->mc, 1); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 3c8673958..ac895edce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -81,8 +81,6 @@ void gk104_grctx_generate_bundle(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *); void gk104_grctx_generate_unkn(struct gf100_gr *); void gk104_grctx_generate_r418bb8(struct gf100_gr *); -void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *); - void gm107_grctx_generate_bundle(struct gf100_grctx *); void gm107_grctx_generate_pagepool(struct gf100_grctx *); @@ -98,7 +96,6 @@ void gm107_grctx_generate_pagepool(struct gf100_grctx *); void gm107_grctx_generate_attrib(struct gf100_grctx *); extern const struct gf100_grctx_func gm200_grctx; -void gm200_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gm200_grctx_generate_tpcid(struct gf100_gr *); void gm200_grctx_generate_405b60(struct gf100_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index 74de7a96c..f521de11a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -223,6 +223,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; + u32 idle_timeout; int i; nvkm_mc_unk260(device->mc, 0); @@ -233,7 +234,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, grctx->tpc); gf100_gr_mmio(gr, grctx->ppc); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->bundle(info); grctx->pagepool(info); @@ -250,7 +251,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); gf100_gr_icmd(gr, grctx->icmd); - nvkm_wr32(device, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device->mc, 1); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index a843e3689..9ba337778 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -924,38 +924,30 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr) /* GPC_BROADCAST */ nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | - gr->magic_not_rop_nr); + gr->screen_tile_row_offset); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | - gr->magic_not_rop_nr | data2[0]); + gr->screen_tile_row_offset | data2[0]); nvkm_wr32(device, 0x41bfe4, data2[1]); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]); /* UNK78xx */ nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | - gr->magic_not_rop_nr); + gr->screen_tile_row_offset); for (i = 0; i < 6; i++) nvkm_wr32(device, 0x40780c + (i * 4), data[i]); } void -gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr) -{ - struct nvkm_device *device = gr->base.engine.subdev.device; - const u32 fbp_count = nvkm_rd32(device, 0x120074); - nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ -} - -void gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; + u32 idle_timeout; int i; nvkm_mc_unk260(device->mc, 0); @@ -966,7 +958,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, grctx->tpc); gf100_gr_mmio(gr, grctx->ppc); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->bundle(info); grctx->pagepool(info); @@ -982,11 +974,10 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(gr); nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); gf100_gr_icmd(gr, grctx->icmd); - nvkm_wr32(device, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mc_unk260(device->mc, 1); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index ad0a6cfe7..da7c35a6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -29,15 +29,14 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; - int idle_timeout_save; + u32 idle_timeout; int i; gf100_gr_mmio(gr, gr->fuc_sw_ctx); gf100_gr_wait_idle(gr); - idle_timeout_save = nvkm_rd32(device, 0x404154); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->attrib(info); @@ -53,13 +52,11 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(gr); - nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); gf100_gr_wait_idle(gr); - nvkm_wr32(device, 0x404154, idle_timeout_save); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_wait_idle(gr); gf100_gr_mthd(gr, gr->fuc_method); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 95f59e316..6d3c5011e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -920,13 +920,15 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); + if (!(gr->ppc_mask[gpc] & (1 << ppc))) + continue; mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xf4, bo); bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; - mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs); + mmio_wr32(info, u, ((bs / 3) << 16) | bs); } } } @@ -957,6 +959,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; + u32 idle_timeout; int i; gf100_gr_mmio(gr, grctx->hub); @@ -965,7 +968,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, grctx->tpc); gf100_gr_mmio(gr, grctx->ppc); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->bundle(info); grctx->pagepool(info); @@ -984,10 +987,8 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(gr); - gf100_gr_icmd(gr, grctx->icmd); - nvkm_wr32(device, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, grctx->mthd); nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c index e586699fc..db209d33f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c @@ -33,7 +33,7 @@ gm200_grctx_generate_tpcid(struct gf100_gr *gr) struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; - for (tpc = 0, id = 0; tpc < 4; tpc++) { + for (tpc = 0, id = 0; tpc < TPC_MAX_PER_GPC; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); @@ -45,15 +45,6 @@ gm200_grctx_generate_tpcid(struct gf100_gr *gr) } } -static void -gm200_grctx_generate_rop_active_fbps(struct gf100_gr *gr) -{ - struct nvkm_device *device = gr->base.engine.subdev.device; - const u32 fbp_count = nvkm_rd32(device, 0x12006c); - nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ -} - void gm200_grctx_generate_405b60(struct gf100_gr *gr) { @@ -86,17 +77,17 @@ gm200_grctx_generate_405b60(struct gf100_gr *gr) nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]); } -void +static void gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; - u32 tmp; + u32 idle_timeout, tmp; int i; gf100_gr_mmio(gr, gr->fuc_sw_ctx); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->bundle(info); grctx->pagepool(info); @@ -113,8 +104,6 @@ gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gm200_grctx_generate_rop_active_fbps(gr); - for (tmp = 0, i = 0; i < gr->gpc_nr; i++) tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); nvkm_wr32(device, 0x4041c4, tmp); @@ -122,7 +111,7 @@ gm200_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gm200_grctx_generate_405b60(gr); gf100_gr_icmd(gr, gr->fuc_bundle); - nvkm_wr32(device, 0x404154, 0x00000800); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_mthd(gr, gr->fuc_method); nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index a8827efa9..e5702e3e0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -40,15 +40,14 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; - int idle_timeout_save; + u32 idle_timeout; int i, tmp; gf100_gr_mmio(gr, gr->fuc_sw_ctx); gf100_gr_wait_idle(gr); - idle_timeout_save = nvkm_rd32(device, 0x404154); - nvkm_wr32(device, 0x404154, 0x00000000); + idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); grctx->attrib(info); @@ -63,7 +62,6 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(gr); nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); for (tmp = 0, i = 0; i < gr->gpc_nr; i++) @@ -74,7 +72,7 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); - nvkm_wr32(device, 0x404154, idle_timeout_save); + nvkm_wr32(device, 0x404154, idle_timeout); gf100_gr_wait_idle(gr); gf100_gr_mthd(gr, gr->fuc_method); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc index dc60509f7..4984b0069 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc @@ -291,12 +291,13 @@ init: // Main program loop, very simple, sleeps until woken up by the interrupt // handler, pulls a command from the queue and executes its handler // -main: - bset $flags $p0 +wait: sleep $p0 + bset $flags $p0 +main: mov $r13 #cmd_queue call(queue_get) - bra $p1 #main + bra $p1 #wait // 0x0000-0x0003 are all context transfers cmpu b32 $r14 0x04 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h index 5f4ddfee4..8cb240b65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h @@ -370,9 +370,10 @@ uint32_t gf100_grgpc_code[] = { 0xf11f29f0, 0xf0080007, 0x02d00203, -/* 0x04bb: main */ +/* 0x04bb: wait */ 0xf404bd00, - 0x28f40031, + 0x31f40028, +/* 0x04c1: main */ 0x1cd7f000, 0xf43921f4, 0xe4b0f401, @@ -384,10 +385,10 @@ uint32_t gf100_grgpc_code[] = { 0x0018fe05, 0x05b421f5, /* 0x04eb: main_not_ctx_xfer */ - 0x94d30ef4, + 0x94d90ef4, 0xf5f010ef, 0x7e21f501, - 0xc60ef403, + 0xcc0ef403, /* 0x04f8: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h index 03381b163..550d6ba09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h @@ -397,9 +397,10 @@ uint32_t gf117_grgpc_code[] = { 0x080007f1, 0xd00203f0, 0x04bd0002, -/* 0x0508: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0508: wait */ + 0xf40028f4, +/* 0x050e: main */ + 0xd7f00031, 0x3921f424, 0xb0f401f4, 0x18f404e4, @@ -409,13 +410,13 @@ uint32_t gf117_grgpc_code[] = { 0xfd01e4b6, 0x18fe051e, 0x0121f500, - 0xd30ef406, + 0xd90ef406, /* 0x0538: main_not_ctx_xfer */ 0xf010ef94, 0x21f501f5, 0x0ef4037e, /* 0x0545: ih */ - 0xf900f9c6, + 0xf900f9cc, 0x0188fe80, 0x90f980f9, 0xb0f9a0f9, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h index 99d9b48a3..271b59d36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h @@ -397,9 +397,10 @@ uint32_t gk104_grgpc_code[] = { 0x080007f1, 0xd00203f0, 0x04bd0002, -/* 0x0508: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0508: wait */ + 0xf40028f4, +/* 0x050e: main */ + 0xd7f00031, 0x3921f424, 0xb0f401f4, 0x18f404e4, @@ -409,13 +410,13 @@ uint32_t gk104_grgpc_code[] = { 0xfd01e4b6, 0x18fe051e, 0x0121f500, - 0xd30ef406, + 0xd90ef406, /* 0x0538: main_not_ctx_xfer */ 0xf010ef94, 0x21f501f5, 0x0ef4037e, /* 0x0545: ih */ - 0xf900f9c6, + 0xf900f9cc, 0x0188fe80, 0x90f980f9, 0xb0f9a0f9, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h index f7267696c..73b4a32c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h @@ -397,9 +397,10 @@ uint32_t gk110_grgpc_code[] = { 0x300007f1, 0xd00203f0, 0x04bd0002, -/* 0x0508: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0508: wait */ + 0xf40028f4, +/* 0x050e: main */ + 0xd7f00031, 0x3921f424, 0xb0f401f4, 0x18f404e4, @@ -409,13 +410,13 @@ uint32_t gk110_grgpc_code[] = { 0xfd01e4b6, 0x18fe051e, 0x0121f500, - 0xd30ef406, + 0xd90ef406, /* 0x0538: main_not_ctx_xfer */ 0xf010ef94, 0x21f501f5, 0x0ef4037e, /* 0x0545: ih */ - 0xf900f9c6, + 0xf900f9cc, 0x0188fe80, 0x90f980f9, 0xb0f9a0f9, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h index 387d1fa3e..018169818 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h @@ -349,9 +349,10 @@ uint32_t gk208_grgpc_code[] = { 0x801f29f0, 0xf6023000, 0x04bd0002, -/* 0x0448: main */ - 0xf40031f4, - 0x240d0028, +/* 0x0448: wait */ + 0xf40028f4, +/* 0x044e: main */ + 0x240d0031, 0x0000377e, 0xb0f401f4, 0x18f404e4, @@ -362,10 +363,10 @@ uint32_t gk208_grgpc_code[] = { 0x0018fe05, 0x00051f7e, /* 0x0477: main_not_ctx_xfer */ - 0x94d40ef4, + 0x94da0ef4, 0xf5f010ef, 0x02f87e01, - 0xc70ef400, + 0xcd0ef400, /* 0x0484: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h index fa9f3c0c5..eca007f03 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgm107.fuc5.h @@ -427,9 +427,10 @@ uint32_t gm107_grgpc_code[] = { 0x1f29f024, 0x02300080, 0xbd0002f6, -/* 0x0571: main */ - 0x0031f404, - 0x0d0028f4, +/* 0x0571: wait */ + 0x0028f404, +/* 0x0577: main */ + 0x0d0031f4, 0x00377e24, 0xf401f400, 0xf404e4b0, @@ -439,13 +440,13 @@ uint32_t gm107_grgpc_code[] = { 0xfd01e4b6, 0x18fe051e, 0x06487e00, - 0xd40ef400, + 0xda0ef400, /* 0x05a0: main_not_ctx_xfer */ 0xf010ef94, 0xf87e01f5, 0x0ef40002, /* 0x05ad: ih */ - 0xf900f9c7, + 0xf900f9cd, 0x0188fe80, 0x90f980f9, 0xb0f9a0f9, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc index e3a2fb308..4d416d4f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc @@ -218,13 +218,14 @@ init: // Main program loop, very simple, sleeps until woken up by the interrupt // handler, pulls a command from the queue and executes its handler // -main: +wait: // sleep until we have something to do - bset $flags $p0 sleep $p0 + bset $flags $p0 +main: mov $r13 #cmd_queue call(queue_get) - bra $p1 #main + bra $p1 #wait // context switch, requested by GPU? cmpu b32 $r14 0x4001 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h index 397921a9a..8015b40a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h @@ -584,9 +584,10 @@ uint32_t gf100_grhub_code[] = { 0x080007f1, 0xd00203f0, 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0564: wait */ + 0xf40028f4, +/* 0x056a: main */ + 0xd7f00031, 0x3921f410, 0xb1f401f4, 0xf54001e4, @@ -650,7 +651,7 @@ uint32_t gf100_grhub_code[] = { 0x170007f1, 0xd00203f0, 0x04bd0009, - 0xff080ef5, + 0xff0e0ef5, /* 0x0660: main_not_ctx_switch */ 0xf401e4b0, 0xf2b90d1b, @@ -675,12 +676,12 @@ uint32_t gf100_grhub_code[] = { 0xf501f5f0, 0xf5037e21, /* 0x06b3: main_done */ - 0xbdfeb50e, + 0xbdfebb0e, 0x1f29f024, 0x080007f1, 0xd00203f0, 0x04bd0002, - 0xfea00ef5, + 0xfea60ef5, /* 0x06c8: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h index 50c97163d..2af90ec68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h @@ -584,9 +584,10 @@ uint32_t gf117_grhub_code[] = { 0x080007f1, 0xd00203f0, 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0564: wait */ + 0xf40028f4, +/* 0x056a: main */ + 0xd7f00031, 0x3921f410, 0xb1f401f4, 0xf54001e4, @@ -650,7 +651,7 @@ uint32_t gf117_grhub_code[] = { 0x170007f1, 0xd00203f0, 0x04bd0009, - 0xff080ef5, + 0xff0e0ef5, /* 0x0660: main_not_ctx_switch */ 0xf401e4b0, 0xf2b90d1b, @@ -675,12 +676,12 @@ uint32_t gf117_grhub_code[] = { 0xf501f5f0, 0xf5037e21, /* 0x06b3: main_done */ - 0xbdfeb50e, + 0xbdfebb0e, 0x1f29f024, 0x080007f1, 0xd00203f0, 0x04bd0002, - 0xfea00ef5, + 0xfea60ef5, /* 0x06c8: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h index 125824b39..e8b8c1c94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h @@ -584,9 +584,10 @@ uint32_t gk104_grhub_code[] = { 0x080007f1, 0xd00203f0, 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0564: wait */ + 0xf40028f4, +/* 0x056a: main */ + 0xd7f00031, 0x3921f410, 0xb1f401f4, 0xf54001e4, @@ -650,7 +651,7 @@ uint32_t gk104_grhub_code[] = { 0x170007f1, 0xd00203f0, 0x04bd0009, - 0xff080ef5, + 0xff0e0ef5, /* 0x0660: main_not_ctx_switch */ 0xf401e4b0, 0xf2b90d1b, @@ -675,12 +676,12 @@ uint32_t gk104_grhub_code[] = { 0xf501f5f0, 0xf5037e21, /* 0x06b3: main_done */ - 0xbdfeb50e, + 0xbdfebb0e, 0x1f29f024, 0x080007f1, 0xd00203f0, 0x04bd0002, - 0xfea00ef5, + 0xfea60ef5, /* 0x06c8: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h index 0a1b8c0b8..f4ed2fb6f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h @@ -584,9 +584,10 @@ uint32_t gk110_grhub_code[] = { 0x300007f1, 0xd00203f0, 0x04bd0001, -/* 0x0564: main */ - 0xf40031f4, - 0xd7f00028, +/* 0x0564: wait */ + 0xf40028f4, +/* 0x056a: main */ + 0xd7f00031, 0x3921f410, 0xb1f401f4, 0xf54001e4, @@ -650,7 +651,7 @@ uint32_t gk110_grhub_code[] = { 0x170007f1, 0xd00203f0, 0x04bd0009, - 0xff080ef5, + 0xff0e0ef5, /* 0x0660: main_not_ctx_switch */ 0xf401e4b0, 0xf2b90d1b, @@ -675,12 +676,12 @@ uint32_t gk110_grhub_code[] = { 0xf501f5f0, 0xf5037e21, /* 0x06b3: main_done */ - 0xbdfeb50e, + 0xbdfebb0e, 0x1f29f024, 0x300007f1, 0xd00203f0, 0x04bd0002, - 0xfea00ef5, + 0xfea60ef5, /* 0x06c8: ih */ 0x80f900f9, 0xf90188fe, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h index 16869d0b1..ed488973c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h @@ -531,9 +531,10 @@ uint32_t gk208_grhub_code[] = { 0x1f19f014, 0x02300080, 0xbd0001f6, -/* 0x0491: main */ - 0x0031f404, - 0x0d0028f4, +/* 0x0491: wait */ + 0x0028f404, +/* 0x0497: main */ + 0x0d0031f4, 0x00377e10, 0xf401f400, 0x4001e4b1, @@ -590,7 +591,7 @@ uint32_t gk208_grhub_code[] = { 0x09f60217, 0xf504bd00, /* 0x056b: main_not_ctx_switch */ - 0xb0ff2a0e, + 0xb0ff300e, 0x1bf401e4, 0x7ef2b20c, 0xf4000820, @@ -612,11 +613,11 @@ uint32_t gk208_grhub_code[] = { 0x7e01f5f0, 0xf50002f8, /* 0x05b7: main_done */ - 0xbdfede0e, + 0xbdfee40e, 0x1f29f024, 0x02300080, 0xbd0002f6, - 0xcc0ef504, + 0xd20ef504, /* 0x05c9: ih */ 0xf900f9fe, 0x0188fe80, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h index d6343d2a6..5c9051839 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgm107.fuc5.h @@ -531,9 +531,10 @@ uint32_t gm107_grhub_code[] = { 0x1f19f014, 0x02300080, 0xbd0001f6, -/* 0x0491: main */ - 0x0031f404, - 0x0d0028f4, +/* 0x0491: wait */ + 0x0028f404, +/* 0x0497: main */ + 0x0d0031f4, 0x00377e10, 0xf401f400, 0x4001e4b1, @@ -590,7 +591,7 @@ uint32_t gm107_grhub_code[] = { 0x09f60217, 0xf504bd00, /* 0x056b: main_not_ctx_switch */ - 0xb0ff2a0e, + 0xb0ff300e, 0x1bf401e4, 0x7ef2b20c, 0xf4000820, @@ -612,11 +613,11 @@ uint32_t gm107_grhub_code[] = { 0x7e01f5f0, 0xf50002f8, /* 0x05b7: main_done */ - 0xbdfede0e, + 0xbdfee40e, 0x1f29f024, 0x02300080, 0xbd0002f6, - 0xcc0ef504, + 0xd20ef504, /* 0x05c9: ih */ 0xf900f9fe, 0x0188fe80, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index b0c721616..ae9ab5b1a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -702,6 +702,13 @@ gf100_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +int +gf100_gr_rops(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; +} + void gf100_gr_zbc_init(struct gf100_gr *gr) { @@ -1628,32 +1635,12 @@ gf100_gr_oneinit(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; - int ret, i, j; + int i, j; nvkm_pmu_pgob(device->pmu, false); - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, - &gr->unk4188b4); - if (ret) - return ret; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, - &gr->unk4188b8); - if (ret) - return ret; - - nvkm_kmap(gr->unk4188b4); - for (i = 0; i < 0x1000; i += 4) - nvkm_wo32(gr->unk4188b4, i, 0x00000010); - nvkm_done(gr->unk4188b4); - - nvkm_kmap(gr->unk4188b8); - for (i = 0; i < 0x1000; i += 4) - nvkm_wo32(gr->unk4188b8, i, 0x00000010); - nvkm_done(gr->unk4188b8); - - gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; - gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; + gr->rop_nr = gr->func->rops(gr); + gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; for (i = 0; i < gr->gpc_nr; i++) { gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); gr->tpc_total += gr->tpc_nr[i]; @@ -1670,38 +1657,38 @@ gf100_gr_oneinit(struct nvkm_gr *base) switch (device->chipset) { case 0xc0: if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ - gr->magic_not_rop_nr = 0x07; + gr->screen_tile_row_offset = 0x07; } else if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ - gr->magic_not_rop_nr = 0x05; + gr->screen_tile_row_offset = 0x05; } else if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ - gr->magic_not_rop_nr = 0x06; + gr->screen_tile_row_offset = 0x06; } break; case 0xc3: /* 450, 4/0/0/0, 2 */ - gr->magic_not_rop_nr = 0x03; + gr->screen_tile_row_offset = 0x03; break; case 0xc4: /* 460, 3/4/0/0, 4 */ - gr->magic_not_rop_nr = 0x01; + gr->screen_tile_row_offset = 0x01; break; case 0xc1: /* 2/0/0/0, 1 */ - gr->magic_not_rop_nr = 0x01; + gr->screen_tile_row_offset = 0x01; break; case 0xc8: /* 4/4/3/4, 5 */ - gr->magic_not_rop_nr = 0x06; + gr->screen_tile_row_offset = 0x06; break; case 0xce: /* 4/4/0/0, 4 */ - gr->magic_not_rop_nr = 0x03; + gr->screen_tile_row_offset = 0x03; break; case 0xcf: /* 4/0/0/0, 3 */ - gr->magic_not_rop_nr = 0x03; + gr->screen_tile_row_offset = 0x03; break; case 0xd7: case 0xd9: /* 1/0/0/0, 1 */ case 0xea: /* gk20a */ case 0x12b: /* gm20b */ - gr->magic_not_rop_nr = 0x01; + gr->screen_tile_row_offset = 0x01; break; } @@ -1748,8 +1735,6 @@ gf100_gr_dtor(struct nvkm_gr *base) gf100_gr_dtor_init(gr->fuc_sw_ctx); gf100_gr_dtor_init(gr->fuc_sw_nonctx); - nvkm_memory_del(&gr->unk4188b8); - nvkm_memory_del(&gr->unk4188b4); return gr; } @@ -1795,7 +1780,7 @@ gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", func->fecs.ucode == NULL); - ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, + ret = nvkm_gr_ctor(&gf100_gr_, device, index, gr->firmware || func->fecs.ucode != NULL, &gr->base); if (ret) @@ -1834,6 +1819,7 @@ int gf100_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -1846,8 +1832,8 @@ gf100_gr_init(struct gf100_gr *gr) nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); gf100_gr_mmio(gr, gr->func->mmio); @@ -1870,9 +1856,9 @@ gf100_gr_init(struct gf100_gr *gr) for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | - gr->tpc_total); + gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } @@ -1965,6 +1951,7 @@ gf100_gr = { .mmio = gf100_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, + .rops = gf100_gr_rops, .grctx = &gf100_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index f0c6acb0f..2b98abdb9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -31,7 +31,8 @@ #include <subdev/mmu.h> #define GPC_MAX 32 -#define TPC_MAX (GPC_MAX * 8) +#define TPC_MAX_PER_GPC 8 +#define TPC_MAX (GPC_MAX * TPC_MAX_PER_GPC) #define ROP_BCAST(r) (0x408800 + (r)) #define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) @@ -100,15 +101,12 @@ struct gf100_gr { u8 ppc_mask[GPC_MAX]; u8 ppc_tpc_nr[GPC_MAX][4]; - struct nvkm_memory *unk4188b4; - struct nvkm_memory *unk4188b8; - struct gf100_gr_data mmio_data[4]; struct gf100_gr_mmio mmio_list[4096/8]; u32 size; u32 *data; - u8 magic_not_rop_nr; + u8 screen_tile_row_offset; }; int gf100_gr_ctor(const struct gf100_gr_func *, struct nvkm_device *, @@ -121,6 +119,8 @@ struct gf100_gr_func { void (*dtor)(struct gf100_gr *); int (*init)(struct gf100_gr *); void (*init_gpc_mmu)(struct gf100_gr *); + void (*init_rop_active_fbps)(struct gf100_gr *); + void (*init_ppc_exceptions)(struct gf100_gr *); void (*set_hww_esr_report_mask)(struct gf100_gr *); const struct gf100_gr_pack *mmio; struct { @@ -129,18 +129,23 @@ struct gf100_gr_func { struct { struct gf100_gr_ucode *ucode; } gpccs; + int (*rops)(struct gf100_gr *); int ppc_nr; const struct gf100_grctx_func *grctx; struct nvkm_sclass sclass[]; }; int gf100_gr_init(struct gf100_gr *); +int gf100_gr_rops(struct gf100_gr *); int gk104_gr_init(struct gf100_gr *); +void gk104_gr_init_rop_active_fbps(struct gf100_gr *); +void gk104_gr_init_ppc_exceptions(struct gf100_gr *); int gk20a_gr_init(struct gf100_gr *); int gm200_gr_init(struct gf100_gr *); +int gm200_gr_rops(struct gf100_gr *); #define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index 8f253e0a2..d736dcd55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -118,6 +118,7 @@ gf104_gr = { .mmio = gf104_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, + .rops = gf100_gr_rops, .grctx = &gf104_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 815a5aafa..2f0d24498 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -109,6 +109,7 @@ gf108_gr = { .mmio = gf108_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, + .rops = gf100_gr_rops, .grctx = &gf108_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index d081ee41f..d1d942eb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -90,6 +90,7 @@ gf110_gr = { .mmio = gf110_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, + .rops = gf100_gr_rops, .grctx = &gf110_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index d8e8af4d3..70335f65c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -126,6 +126,7 @@ gf117_gr = { .mmio = gf117_gr_pack_mmio, .fecs.ucode = &gf117_gr_fecs_ucode, .gpccs.ucode = &gf117_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 1, .grctx = &gf117_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 01faf9a73..8d8e4cafe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -181,6 +181,7 @@ gf119_gr = { .mmio = gf119_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, + .rops = gf100_gr_rops, .grctx = &gf119_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index abf54928a..ec22da6c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -24,6 +24,8 @@ #include "gf100.h" #include "ctxgf100.h" +#include <subdev/fb.h> + #include <nvif/class.h> /******************************************************************************* @@ -177,10 +179,35 @@ gk104_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +void +gk104_gr_init_rop_active_fbps(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 fbp_count = nvkm_rd32(device, 0x120074); + nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ +} + +void +gk104_gr_init_ppc_exceptions(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + int gpc, ppc; + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { + if (!(gr->ppc_mask[gpc] & (1 << ppc))) + continue; + nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + } + } +} + int gk104_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -193,8 +220,8 @@ gk104_gr_init(struct gf100_gr *gr) nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); gf100_gr_mmio(gr, gr->func->mmio); @@ -218,15 +245,17 @@ gk104_gr_init(struct gf100_gr *gr) for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | - gr->tpc_total); + gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); + gr->func->init_rop_active_fbps(gr); + nvkm_wr32(device, 0x400500, 0x00010001); nvkm_wr32(device, 0x400100, 0xffffffff); @@ -246,8 +275,9 @@ gk104_gr_init(struct gf100_gr *gr) nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -309,9 +339,12 @@ gk104_gr_gpccs_ucode = { static const struct gf100_gr_func gk104_gr = { .init = gk104_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk104_gr_pack_mmio, .fecs.ucode = &gk104_gr_fecs_ucode, .gpccs.ucode = &gk104_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 1, .grctx = &gk104_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index 32aa2946e..f31b171a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -183,9 +183,12 @@ gk110_gr_gpccs_ucode = { static const struct gf100_gr_func gk110_gr = { .init = gk104_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk110_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 2, .grctx = &gk110_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index 22f88afbf..d76dd1780 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -103,9 +103,12 @@ gk110b_gr_pack_mmio[] = { static const struct gf100_gr_func gk110b_gr = { .init = gk104_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk110b_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 2, .grctx = &gk110b_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index ee7554fc8..14bbe6ed0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -162,9 +162,12 @@ gk208_gr_gpccs_ucode = { static const struct gf100_gr_func gk208_gr = { .init = gk104_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gk208_gr_pack_mmio, .fecs.ucode = &gk208_gr_fecs_ucode, .gpccs.ucode = &gk208_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 1, .grctx = &gk208_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 7ffb8a626..4ca8ed151 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -239,9 +239,6 @@ gk20a_gr_init(struct gf100_gr *gr) return ret; /* MMU debug buffer */ - nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); - if (gr->func->init_gpc_mmu) gr->func->init_gpc_mmu(gr); @@ -267,7 +264,7 @@ gk20a_gr_init(struct gf100_gr *gr) for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); @@ -275,6 +272,8 @@ gk20a_gr_init(struct gf100_gr *gr) nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); + gr->func->init_rop_active_fbps(gr); + /* Enable FIFO access */ nvkm_wr32(device, 0x400500, 0x00010001); @@ -312,7 +311,9 @@ gk20a_gr_init(struct gf100_gr *gr) static const struct gf100_gr_func gk20a_gr = { .init = gk20a_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, + .rops = gf100_gr_rops, .ppc_nr = 1, .grctx = &gk20a_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 56e960212..45f965f60 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -26,6 +26,7 @@ #include <subdev/bios.h> #include <subdev/bios/P0260.h> +#include <subdev/fb.h> #include <nvif/class.h> @@ -311,17 +312,18 @@ int gm107_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; - int gpc, tpc, ppc, rop; + int gpc, tpc, rop; int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(fb->mmu_wr) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(fb->mmu_rd) >> 8); gf100_gr_mmio(gr, gr->func->mmio); @@ -347,15 +349,17 @@ gm107_gr_init(struct gf100_gr *gr) for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | - gr->tpc_total); + gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); + gr->func->init_rop_active_fbps(gr); + nvkm_wr32(device, 0x400500, 0x00010001); nvkm_wr32(device, 0x400100, 0xffffffff); @@ -373,9 +377,9 @@ gm107_gr_init(struct gf100_gr *gr) nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++) - nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -438,9 +442,12 @@ gm107_gr_gpccs_ucode = { static const struct gf100_gr_func gm107_gr = { .init = gm107_gr_init, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, .mmio = gm107_gr_pack_mmio, .fecs.ucode = &gm107_gr_fecs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode, + .rops = gf100_gr_rops, .ppc_nr = 2, .grctx = &gm107_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index 058fc1d22..4dfa4513b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c @@ -33,27 +33,45 @@ ******************************************************************************/ int +gm200_gr_rops(struct gf100_gr *gr) +{ + return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); +} + +static void +gm200_gr_init_gpc_mmu(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff); + nvkm_wr32(device, 0x418890, 0x00000000); + nvkm_wr32(device, 0x418894, 0x00000000); + + nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); + nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); + nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); +} + +static void +gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 fbp_count = nvkm_rd32(device, 0x12006c); + nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ +} + +int gm200_gr_init(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); - u32 data[TPC_MAX / 8] = {}, tmp; + u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; - int gpc, tpc, ppc, rop; + int gpc, tpc, rop; int i; - tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */ - nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff)); - nvkm_wr32(device, 0x418890, 0x00000000); - nvkm_wr32(device, 0x418894, 0x00000000); - nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(gr->unk4188b8) >> 8); - nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000); - - /*XXX: belongs in fb */ - nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); - nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); - nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000); + gr->func->init_gpc_mmu(gr); gf100_gr_mmio(gr, gr->fuc_sw_nonctx); @@ -79,9 +97,9 @@ gm200_gr_init(struct gf100_gr *gr) for (gpc = 0; gpc < gr->gpc_nr; gpc++) { nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | - gr->tpc_total); + gr->tpc_total); nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } @@ -89,6 +107,8 @@ gm200_gr_init(struct gf100_gr *gr) nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); + gr->func->init_rop_active_fbps(gr); + nvkm_wr32(device, 0x400500, 0x00010001); nvkm_wr32(device, 0x400100, 0xffffffff); nvkm_wr32(device, 0x40013c, 0xffffffff); @@ -106,9 +126,9 @@ gm200_gr_init(struct gf100_gr *gr) nvkm_wr32(device, 0x405844, 0x00ffffff); nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + gr->func->init_ppc_exceptions(gr); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) - nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); @@ -189,6 +209,10 @@ gm200_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, static const struct gf100_gr_func gm200_gr = { .init = gm200_gr_init, + .init_gpc_mmu = gm200_gr_init_gpc_mmu, + .init_rop_active_fbps = gm200_gr_init_rop_active_fbps, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, + .rops = gm200_gr_rops, .ppc_nr = 2, .grctx = &gm200_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 29732bc14..69479af1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -42,7 +42,7 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) } val = nvkm_rd32(device, 0x100c80); - val &= 0xf000087f; + val &= 0xf000187f; nvkm_wr32(device, 0x418880, val); nvkm_wr32(device, 0x418890, 0); nvkm_wr32(device, 0x418894, 0); @@ -66,7 +66,9 @@ static const struct gf100_gr_func gm20b_gr = { .init = gk20a_gr_init, .init_gpc_mmu = gm20b_gr_init_gpc_mmu, + .init_rop_active_fbps = gk104_gr_init_rop_active_fbps, .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, + .rops = gm200_gr_rops, .ppc_nr = 1, .grctx = &gm20b_grctx, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 85c5b7fea..9c2e985dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1422,6 +1422,5 @@ nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(&nv04_gr, device, index, 0x00001000, - true, &gr->base); + return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 4542867fa..4ebbfbdd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1182,7 +1182,7 @@ nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); + return nvkm_gr_ctor(func, device, index, true, &gr->base); } static const struct nvkm_gr_func diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 5caef65d3..d1dc92999 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -337,7 +337,7 @@ nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, return -ENOMEM; *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); + return nvkm_gr_ctor(func, device, index, true, &gr->base); } static const struct nvkm_gr_func diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 05a895496..5f1ad8344 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -438,7 +438,7 @@ nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, *pgr = &gr->base; INIT_LIST_HEAD(&gr->chan); - return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); + return nvkm_gr_ctor(func, device, index, true, &gr->base); } static const struct nvkm_gr_func diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index b19b912d5..fca67de43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -768,7 +768,7 @@ nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, spin_lock_init(&gr->lock); *pgr = &gr->base; - return nvkm_gr_ctor(func, device, index, 0x00201000, true, &gr->base); + return nvkm_gr_ctor(func, device, index, true, &gr->base); } static const struct nvkm_gr_func diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index a234590be..d8adcdf69 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -7,8 +7,7 @@ struct nvkm_fb_tile; struct nvkm_fifo_chan; int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, - int index, u32 pmc_enable, bool enable, - struct nvkm_gr *); + int index, bool enable, struct nvkm_gr *); bool nv04_gr_idle(struct nvkm_gr *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c index 34ff0014a..c0e11a071 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.c @@ -39,6 +39,5 @@ g84_mpeg = { int g84_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&g84_mpeg, device, index, 0x00000002, - true, pmpeg); + return nvkm_engine_new_(&g84_mpeg, device, index, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index d4d8942b1..003ac915e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -278,7 +278,7 @@ nv31_mpeg_new_(const struct nv31_mpeg_func *func, struct nvkm_device *device, mpeg->func = func; *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv31_mpeg_, device, index, 0x00000002, + return nvkm_engine_ctor(&nv31_mpeg_, device, index, true, &mpeg->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index d433cfa4a..e536f37e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -212,6 +212,5 @@ nv44_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) INIT_LIST_HEAD(&mpeg->chan); *pmpeg = &mpeg->engine; - return nvkm_engine_ctor(&nv44_mpeg, device, index, 0x00000002, - true, &mpeg->engine); + return nvkm_engine_ctor(&nv44_mpeg, device, index, true, &mpeg->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index c3a85dffc..4e528851e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -130,6 +130,5 @@ nv50_mpeg = { int nv50_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg) { - return nvkm_engine_new_(&nv50_mpeg, device, index, 0x00400002, - true, pmpeg); + return nvkm_engine_new_(&nv50_mpeg, device, index, true, pmpeg); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c index 1f1a99e92..f30cf1dcf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c @@ -35,7 +35,6 @@ g98_mspdec_init(struct nvkm_falcon *mspdec) static const struct nvkm_falcon_func g98_mspdec = { - .pmc_enable = 0x01020000, .init = g98_mspdec_init, .sclass = { { -1, -1, G98_MSPDEC }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c index 371fd6c3c..cfe1aa81b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c @@ -35,7 +35,6 @@ gf100_mspdec_init(struct nvkm_falcon *mspdec) static const struct nvkm_falcon_func gf100_mspdec = { - .pmc_enable = 0x00020000, .init = gf100_mspdec_init, .sclass = { { -1, -1, GF100_MSPDEC }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c index de804a15b..24272b492 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func gk104_mspdec = { - .pmc_enable = 0x00020000, .init = gf100_mspdec_init, .sclass = { { -1, -1, GK104_MSPDEC }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c index 835631713..cf6e59ad6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func gt215_mspdec = { - .pmc_enable = 0x01020000, .init = g98_mspdec_init, .sclass = { { -1, -1, GT212_MSPDEC }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c index 73f633ae2..c45dbf79d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c @@ -35,7 +35,6 @@ g98_msppp_init(struct nvkm_falcon *msppp) static const struct nvkm_falcon_func g98_msppp = { - .pmc_enable = 0x00400002, .init = g98_msppp_init, .sclass = { { -1, -1, G98_MSPPP }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c index c42c0c07e..803c62ab5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c @@ -35,7 +35,6 @@ gf100_msppp_init(struct nvkm_falcon *msppp) static const struct nvkm_falcon_func gf100_msppp = { - .pmc_enable = 0x00000002, .init = gf100_msppp_init, .sclass = { { -1, -1, GF100_MSPPP }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c index 00e7795f1..49cbf72ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func gt215_msppp = { - .pmc_enable = 0x00400002, .init = g98_msppp_init, .sclass = { { -1, -1, GT212_MSPPP }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c index 47e2929bf..4a2a9f049 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.c @@ -35,7 +35,6 @@ g98_msvld_init(struct nvkm_falcon *msvld) static const struct nvkm_falcon_func g98_msvld = { - .pmc_enable = 0x04008000, .init = g98_msvld_init, .sclass = { { -1, -1, G98_MSVLD }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c index 1ac581ba9..1695e532c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.c @@ -35,7 +35,6 @@ gf100_msvld_init(struct nvkm_falcon *msvld) static const struct nvkm_falcon_func gf100_msvld = { - .pmc_enable = 0x00008000, .init = gf100_msvld_init, .sclass = { { -1, -1, GF100_MSVLD }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c index 4bba16e0f..b640cd63e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func gk104_msvld = { - .pmc_enable = 0x00008000, .init = gf100_msvld_init, .sclass = { { -1, -1, GK104_MSVLD }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c index e17cb5605..201e8ef35 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func gt215_msvld = { - .pmc_enable = 0x04008000, .init = g98_msvld_init, .sclass = { { -1, -1, GT212_MSVLD }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c index 511800f6a..a0f540ef2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.c @@ -27,7 +27,6 @@ static const struct nvkm_falcon_func mcp89_msvld = { - .pmc_enable = 0x04008000, .init = g98_msvld_init, .sclass = { { -1, -1, IGT21A_MSVLD }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index f19fabef8..8616636ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -863,5 +863,5 @@ nvkm_pm_ctor(const struct nvkm_pm_func *func, struct nvkm_device *device, pm->func = func; INIT_LIST_HEAD(&pm->domains); INIT_LIST_HEAD(&pm->sources); - return nvkm_engine_ctor(&nvkm_pm, device, index, 0, true, &pm->engine); + return nvkm_engine_ctor(&nvkm_pm, device, index, true, &pm->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 995c2c5ec..6d2a7f0af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -66,7 +66,6 @@ g98_sec = { .code.size = sizeof(g98_sec_code), .data.data = g98_sec_data, .data.size = sizeof(g98_sec_data), - .pmc_enable = 0x00004000, .intr = g98_sec_intr, .sclass = { { -1, -1, G98_SEC }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c index 53c1f7e75..7be3198e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/base.c @@ -106,5 +106,5 @@ nvkm_sw_new_(const struct nvkm_sw_func *func, struct nvkm_device *device, INIT_LIST_HEAD(&sw->chan); sw->func = func; - return nvkm_engine_ctor(&nvkm_sw, device, index, 0, true, &sw->engine); + return nvkm_engine_ctor(&nvkm_sw, device, index, true, &sw->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c index 4188c77ac..7a9617878 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c @@ -27,7 +27,6 @@ static const struct nvkm_xtensa_func g84_vp = { - .pmc_enable = 0x01020000, .fifo_val = 0x111, .unkd28 = 0x9c544, .sclass = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 3692c1694..6a00ac0c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -187,6 +187,6 @@ nvkm_xtensa_new_(const struct nvkm_xtensa_func *func, xtensa->addr = addr; *pengine = &xtensa->engine; - return nvkm_engine_ctor(&nvkm_xtensa, device, index, func->pmc_enable, + return nvkm_engine_ctor(&nvkm_xtensa, device, index, enable, &xtensa->engine); } |