diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/can/rcar_can.c | 929 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx.c | 3723 | ||||
| -rw-r--r-- | drivers/net/dsa/mv88e6xxx.h | 624 | ||||
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c | 464 | ||||
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h | 310 | ||||
| -rw-r--r-- | drivers/net/wireless/broadcom/b43/phy_a.c | 595 |
6 files changed, 0 insertions, 6645 deletions
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar_can.c deleted file mode 100644 index 788459f6b..000000000 --- a/drivers/net/can/rcar_can.c +++ /dev/null @@ -1,929 +0,0 @@ -/* Renesas R-Car CAN device driver - * - * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> - * Copyright (C) 2013 Renesas Solutions Corp. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/interrupt.h> -#include <linux/errno.h> -#include <linux/netdevice.h> -#include <linux/platform_device.h> -#include <linux/can/led.h> -#include <linux/can/dev.h> -#include <linux/clk.h> -#include <linux/can/platform/rcar_can.h> -#include <linux/of.h> - -#define RCAR_CAN_DRV_NAME "rcar_can" - -/* Mailbox configuration: - * mailbox 60 - 63 - Rx FIFO mailboxes - * mailbox 56 - 59 - Tx FIFO mailboxes - * non-FIFO mailboxes are not used - */ -#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ -#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ -#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ -#define RCAR_CAN_FIFO_DEPTH 4 - -/* Mailbox registers structure */ -struct rcar_can_mbox_regs { - u32 id; /* IDE and RTR bits, SID and EID */ - u8 stub; /* Not used */ - u8 dlc; /* Data Length Code - bits [0..3] */ - u8 data[8]; /* Data Bytes */ - u8 tsh; /* Time Stamp Higher Byte */ - u8 tsl; /* Time Stamp Lower Byte */ -}; - -struct rcar_can_regs { - struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ - u32 mkr_2_9[8]; /* Mask Registers 2-9 */ - u32 fidcr[2]; /* FIFO Received ID Compare Register */ - u32 mkivlr1; /* Mask Invalid Register 1 */ - u32 mier1; /* Mailbox Interrupt Enable Register 1 */ - u32 mkr_0_1[2]; /* Mask Registers 0-1 */ - u32 mkivlr0; /* Mask Invalid Register 0*/ - u32 mier0; /* Mailbox Interrupt Enable Register 0 */ - u8 pad_440[0x3c0]; - u8 mctl[64]; /* Message Control Registers */ - u16 ctlr; /* Control Register */ - u16 str; /* Status register */ - u8 bcr[3]; /* Bit Configuration Register */ - u8 clkr; /* Clock Select Register */ - u8 rfcr; /* Receive FIFO Control Register */ - u8 rfpcr; /* Receive FIFO Pointer Control Register */ - u8 tfcr; /* Transmit FIFO Control Register */ - u8 tfpcr; /* Transmit FIFO Pointer Control Register */ - u8 eier; /* Error Interrupt Enable Register */ - u8 eifr; /* Error Interrupt Factor Judge Register */ - u8 recr; /* Receive Error Count Register */ - u8 tecr; /* Transmit Error Count Register */ - u8 ecsr; /* Error Code Store Register */ - u8 cssr; /* Channel Search Support Register */ - u8 mssr; /* Mailbox Search Status Register */ - u8 msmr; /* Mailbox Search Mode Register */ - u16 tsr; /* Time Stamp Register */ - u8 afsr; /* Acceptance Filter Support Register */ - u8 pad_857; - u8 tcr; /* Test Control Register */ - u8 pad_859[7]; - u8 ier; /* Interrupt Enable Register */ - u8 isr; /* Interrupt Status Register */ - u8 pad_862; - u8 mbsmr; /* Mailbox Search Mask Register */ -}; - -struct rcar_can_priv { - struct can_priv can; /* Must be the first member! */ - struct net_device *ndev; - struct napi_struct napi; - struct rcar_can_regs __iomem *regs; - struct clk *clk; - struct clk *can_clk; - u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; - u32 tx_head; - u32 tx_tail; - u8 clock_select; - u8 ier; -}; - -static const struct can_bittiming_const rcar_can_bittiming_const = { - .name = RCAR_CAN_DRV_NAME, - .tseg1_min = 4, - .tseg1_max = 16, - .tseg2_min = 2, - .tseg2_max = 8, - .sjw_max = 4, - .brp_min = 1, - .brp_max = 1024, - .brp_inc = 1, -}; - -/* Control Register bits */ -#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ -#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ - /* at bus-off entry */ -#define RCAR_CAN_CTLR_SLPM (1 << 10) -#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ -#define RCAR_CAN_CTLR_CANM_HALT (1 << 9) -#define RCAR_CAN_CTLR_CANM_RESET (1 << 8) -#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) -#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ -#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ -#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ -#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ - -/* Status Register bits */ -#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ - -/* FIFO Received ID Compare Registers 0 and 1 bits */ -#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ -#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ - -/* Receive FIFO Control Register bits */ -#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ -#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ - -/* Transmit FIFO Control Register bits */ -#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ - /* Number Status Bits */ -#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ - /* Message Number Status Bits */ -#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ - -#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ - /* for Rx mailboxes 0-31 */ -#define RCAR_CAN_N_RX_MKREGS2 8 - -/* Bit Configuration Register settings */ -#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) -#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) -#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) -#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) - -/* Mailbox and Mask Registers bits */ -#define RCAR_CAN_IDE (1 << 31) -#define RCAR_CAN_RTR (1 << 30) -#define RCAR_CAN_SID_SHIFT 18 - -/* Mailbox Interrupt Enable Register 1 bits */ -#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ -#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ - -/* Interrupt Enable Register bits */ -#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ -#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ - /* Enable Bit */ -#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ - /* Enable Bit */ -/* Interrupt Status Register bits */ -#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ -#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ - /* Status Bit */ -#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ - /* Status Bit */ - -/* Error Interrupt Enable Register bits */ -#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ -#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ - /* Interrupt Enable */ -#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ -#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ -#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ -#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ -#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ -#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ - -/* Error Interrupt Factor Judge Register bits */ -#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ -#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ - /* Detect Flag */ -#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ -#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ -#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ -#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ -#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ -#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ - -/* Error Code Store Register bits */ -#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ -#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ -#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ -#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ -#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ -#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ -#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ -#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ - -#define RCAR_CAN_NAPI_WEIGHT 4 -#define MAX_STR_READS 0x100 - -static void tx_failure_cleanup(struct net_device *ndev) -{ - int i; - - for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) - can_free_echo_skb(ndev, i); -} - -static void rcar_can_error(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - struct net_device_stats *stats = &ndev->stats; - struct can_frame *cf; - struct sk_buff *skb; - u8 eifr, txerr = 0, rxerr = 0; - - /* Propagate the error condition to the CAN stack */ - skb = alloc_can_err_skb(ndev, &cf); - - eifr = readb(&priv->regs->eifr); - if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { - txerr = readb(&priv->regs->tecr); - rxerr = readb(&priv->regs->recr); - if (skb) { - cf->can_id |= CAN_ERR_CRTL; - cf->data[6] = txerr; - cf->data[7] = rxerr; - } - } - if (eifr & RCAR_CAN_EIFR_BEIF) { - int rx_errors = 0, tx_errors = 0; - u8 ecsr; - - netdev_dbg(priv->ndev, "Bus error interrupt:\n"); - if (skb) - cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; - - ecsr = readb(&priv->regs->ecsr); - if (ecsr & RCAR_CAN_ECSR_ADEF) { - netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); - tx_errors++; - writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); - if (skb) - cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL; - } - if (ecsr & RCAR_CAN_ECSR_BE0F) { - netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); - tx_errors++; - writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); - if (skb) - cf->data[2] |= CAN_ERR_PROT_BIT0; - } - if (ecsr & RCAR_CAN_ECSR_BE1F) { - netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); - tx_errors++; - writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); - if (skb) - cf->data[2] |= CAN_ERR_PROT_BIT1; - } - if (ecsr & RCAR_CAN_ECSR_CEF) { - netdev_dbg(priv->ndev, "CRC Error\n"); - rx_errors++; - writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); - if (skb) - cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; - } - if (ecsr & RCAR_CAN_ECSR_AEF) { - netdev_dbg(priv->ndev, "ACK Error\n"); - tx_errors++; - writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); - if (skb) { - cf->can_id |= CAN_ERR_ACK; - cf->data[3] = CAN_ERR_PROT_LOC_ACK; - } - } - if (ecsr & RCAR_CAN_ECSR_FEF) { - netdev_dbg(priv->ndev, "Form Error\n"); - rx_errors++; - writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); - if (skb) - cf->data[2] |= CAN_ERR_PROT_FORM; - } - if (ecsr & RCAR_CAN_ECSR_SEF) { - netdev_dbg(priv->ndev, "Stuff Error\n"); - rx_errors++; - writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); - if (skb) - cf->data[2] |= CAN_ERR_PROT_STUFF; - } - - priv->can.can_stats.bus_error++; - ndev->stats.rx_errors += rx_errors; - ndev->stats.tx_errors += tx_errors; - writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); - } - if (eifr & RCAR_CAN_EIFR_EWIF) { - netdev_dbg(priv->ndev, "Error warning interrupt\n"); - priv->can.state = CAN_STATE_ERROR_WARNING; - priv->can.can_stats.error_warning++; - /* Clear interrupt condition */ - writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); - if (skb) - cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : - CAN_ERR_CRTL_RX_WARNING; - } - if (eifr & RCAR_CAN_EIFR_EPIF) { - netdev_dbg(priv->ndev, "Error passive interrupt\n"); - priv->can.state = CAN_STATE_ERROR_PASSIVE; - priv->can.can_stats.error_passive++; - /* Clear interrupt condition */ - writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); - if (skb) - cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : - CAN_ERR_CRTL_RX_PASSIVE; - } - if (eifr & RCAR_CAN_EIFR_BOEIF) { - netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); - tx_failure_cleanup(ndev); - priv->ier = RCAR_CAN_IER_ERSIE; - writeb(priv->ier, &priv->regs->ier); - priv->can.state = CAN_STATE_BUS_OFF; - /* Clear interrupt condition */ - writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); - priv->can.can_stats.bus_off++; - can_bus_off(ndev); - if (skb) - cf->can_id |= CAN_ERR_BUSOFF; - } - if (eifr & RCAR_CAN_EIFR_ORIF) { - netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); - ndev->stats.rx_over_errors++; - ndev->stats.rx_errors++; - writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); - if (skb) { - cf->can_id |= CAN_ERR_CRTL; - cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; - } - } - if (eifr & RCAR_CAN_EIFR_OLIF) { - netdev_dbg(priv->ndev, - "Overload Frame Transmission error interrupt\n"); - ndev->stats.rx_over_errors++; - ndev->stats.rx_errors++; - writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); - if (skb) { - cf->can_id |= CAN_ERR_PROT; - cf->data[2] |= CAN_ERR_PROT_OVERLOAD; - } - } - - if (skb) { - stats->rx_packets++; - stats->rx_bytes += cf->can_dlc; - netif_rx(skb); - } -} - -static void rcar_can_tx_done(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - struct net_device_stats *stats = &ndev->stats; - u8 isr; - - while (1) { - u8 unsent = readb(&priv->regs->tfcr); - - unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> - RCAR_CAN_TFCR_TFUST_SHIFT; - if (priv->tx_head - priv->tx_tail <= unsent) - break; - stats->tx_packets++; - stats->tx_bytes += priv->tx_dlc[priv->tx_tail % - RCAR_CAN_FIFO_DEPTH]; - priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; - can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); - priv->tx_tail++; - netif_wake_queue(ndev); - } - /* Clear interrupt */ - isr = readb(&priv->regs->isr); - writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); - can_led_event(ndev, CAN_LED_EVENT_TX); -} - -static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) -{ - struct net_device *ndev = dev_id; - struct rcar_can_priv *priv = netdev_priv(ndev); - u8 isr; - - isr = readb(&priv->regs->isr); - if (!(isr & priv->ier)) - return IRQ_NONE; - - if (isr & RCAR_CAN_ISR_ERSF) - rcar_can_error(ndev); - - if (isr & RCAR_CAN_ISR_TXFF) - rcar_can_tx_done(ndev); - - if (isr & RCAR_CAN_ISR_RXFF) { - if (napi_schedule_prep(&priv->napi)) { - /* Disable Rx FIFO interrupts */ - priv->ier &= ~RCAR_CAN_IER_RXFIE; - writeb(priv->ier, &priv->regs->ier); - __napi_schedule(&priv->napi); - } - } - - return IRQ_HANDLED; -} - -static void rcar_can_set_bittiming(struct net_device *dev) -{ - struct rcar_can_priv *priv = netdev_priv(dev); - struct can_bittiming *bt = &priv->can.bittiming; - u32 bcr; - - bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | - RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | - RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); - /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. - * All the registers are big-endian but they get byte-swapped on 32-bit - * read/write (but not on 8-bit, contrary to the manuals)... - */ - writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); -} - -static void rcar_can_start(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - u16 ctlr; - int i; - - /* Set controller to known mode: - * - FIFO mailbox mode - * - accept all messages - * - overrun mode - * CAN is in sleep mode after MCU hardware or software reset. - */ - ctlr = readw(&priv->regs->ctlr); - ctlr &= ~RCAR_CAN_CTLR_SLPM; - writew(ctlr, &priv->regs->ctlr); - /* Go to reset mode */ - ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; - writew(ctlr, &priv->regs->ctlr); - for (i = 0; i < MAX_STR_READS; i++) { - if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) - break; - } - rcar_can_set_bittiming(ndev); - ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ - ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ - /* at bus-off */ - ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ - ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ - writew(ctlr, &priv->regs->ctlr); - - /* Accept all SID and EID */ - writel(0, &priv->regs->mkr_2_9[6]); - writel(0, &priv->regs->mkr_2_9[7]); - /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ - writel(0, &priv->regs->mkivlr1); - /* Accept all frames */ - writel(0, &priv->regs->fidcr[0]); - writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); - /* Enable and configure FIFO mailbox interrupts */ - writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); - - priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | - RCAR_CAN_IER_TXFIE; - writeb(priv->ier, &priv->regs->ier); - - /* Accumulate error codes */ - writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); - /* Enable error interrupts */ - writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | - (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? - RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | - RCAR_CAN_EIER_OLIE, &priv->regs->eier); - priv->can.state = CAN_STATE_ERROR_ACTIVE; - - /* Go to operation mode */ - writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); - for (i = 0; i < MAX_STR_READS; i++) { - if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) - break; - } - /* Enable Rx and Tx FIFO */ - writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); - writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); -} - -static int rcar_can_open(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - int err; - - err = clk_prepare_enable(priv->clk); - if (err) { - netdev_err(ndev, - "failed to enable peripheral clock, error %d\n", - err); - goto out; - } - err = clk_prepare_enable(priv->can_clk); - if (err) { - netdev_err(ndev, "failed to enable CAN clock, error %d\n", - err); - goto out_clock; - } - err = open_candev(ndev); - if (err) { - netdev_err(ndev, "open_candev() failed, error %d\n", err); - goto out_can_clock; - } - napi_enable(&priv->napi); - err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); - if (err) { - netdev_err(ndev, "request_irq(%d) failed, error %d\n", - ndev->irq, err); - goto out_close; - } - can_led_event(ndev, CAN_LED_EVENT_OPEN); - rcar_can_start(ndev); - netif_start_queue(ndev); - return 0; -out_close: - napi_disable(&priv->napi); - close_candev(ndev); -out_can_clock: - clk_disable_unprepare(priv->can_clk); -out_clock: - clk_disable_unprepare(priv->clk); -out: - return err; -} - -static void rcar_can_stop(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - u16 ctlr; - int i; - - /* Go to (force) reset mode */ - ctlr = readw(&priv->regs->ctlr); - ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; - writew(ctlr, &priv->regs->ctlr); - for (i = 0; i < MAX_STR_READS; i++) { - if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) - break; - } - writel(0, &priv->regs->mier0); - writel(0, &priv->regs->mier1); - writeb(0, &priv->regs->ier); - writeb(0, &priv->regs->eier); - /* Go to sleep mode */ - ctlr |= RCAR_CAN_CTLR_SLPM; - writew(ctlr, &priv->regs->ctlr); - priv->can.state = CAN_STATE_STOPPED; -} - -static int rcar_can_close(struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - - netif_stop_queue(ndev); - rcar_can_stop(ndev); - free_irq(ndev->irq, ndev); - napi_disable(&priv->napi); - clk_disable_unprepare(priv->can_clk); - clk_disable_unprepare(priv->clk); - close_candev(ndev); - can_led_event(ndev, CAN_LED_EVENT_STOP); - return 0; -} - -static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, - struct net_device *ndev) -{ - struct rcar_can_priv *priv = netdev_priv(ndev); - struct can_frame *cf = (struct can_frame *)skb->data; - u32 data, i; - - if (can_dropped_invalid_skb(ndev, skb)) - return NETDEV_TX_OK; - - if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ - data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; - else /* Standard frame format */ - data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; - - if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ - data |= RCAR_CAN_RTR; - } else { - for (i = 0; i < cf->can_dlc; i++) - writeb(cf->data[i], - &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); - } - - writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); - - writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); - - priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; - can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); - priv->tx_head++; - /* Start Tx: write 0xff to the TFPCR register to increment - * the CPU-side pointer for the transmit FIFO to the next - * mailbox location - */ - writeb(0xff, &priv->regs->tfpcr); - /* Stop the queue if we've filled all FIFO entries */ - if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) - netif_stop_queue(ndev); - - return NETDEV_TX_OK; -} - -static const struct net_device_ops rcar_can_netdev_ops = { - .ndo_open = rcar_can_open, - .ndo_stop = rcar_can_close, - .ndo_start_xmit = rcar_can_start_xmit, - .ndo_change_mtu = can_change_mtu, -}; - -static void rcar_can_rx_pkt(struct rcar_can_priv *priv) -{ - struct net_device_stats *stats = &priv->ndev->stats; - struct can_frame *cf; - struct sk_buff *skb; - u32 data; - u8 dlc; - - skb = alloc_can_skb(priv->ndev, &cf); - if (!skb) { - stats->rx_dropped++; - return; - } - - data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); - if (data & RCAR_CAN_IDE) - cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; - else - cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; - - dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); - cf->can_dlc = get_can_dlc(dlc); - if (data & RCAR_CAN_RTR) { - cf->can_id |= CAN_RTR_FLAG; - } else { - for (dlc = 0; dlc < cf->can_dlc; dlc++) - cf->data[dlc] = - readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); - } - - can_led_event(priv->ndev, CAN_LED_EVENT_RX); - - stats->rx_bytes += cf->can_dlc; - stats->rx_packets++; - netif_receive_skb(skb); -} - -static int rcar_can_rx_poll(struct napi_struct *napi, int quota) -{ - struct rcar_can_priv *priv = container_of(napi, - struct rcar_can_priv, napi); - int num_pkts; - - for (num_pkts = 0; num_pkts < quota; num_pkts++) { - u8 rfcr, isr; - - isr = readb(&priv->regs->isr); - /* Clear interrupt bit */ - if (isr & RCAR_CAN_ISR_RXFF) - writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); - rfcr = readb(&priv->regs->rfcr); - if (rfcr & RCAR_CAN_RFCR_RFEST) - break; - rcar_can_rx_pkt(priv); - /* Write 0xff to the RFPCR register to increment - * the CPU-side pointer for the receive FIFO - * to the next mailbox location - */ - writeb(0xff, &priv->regs->rfpcr); - } - /* All packets processed */ - if (num_pkts < quota) { - napi_complete(napi); - priv->ier |= RCAR_CAN_IER_RXFIE; - writeb(priv->ier, &priv->regs->ier); - } - return num_pkts; -} - -static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) -{ - switch (mode) { - case CAN_MODE_START: - rcar_can_start(ndev); - netif_wake_queue(ndev); - return 0; - default: - return -EOPNOTSUPP; - } -} - -static int rcar_can_get_berr_counter(const struct net_device *dev, - struct can_berr_counter *bec) -{ - struct rcar_can_priv *priv = netdev_priv(dev); - int err; - - err = clk_prepare_enable(priv->clk); - if (err) - return err; - bec->txerr = readb(&priv->regs->tecr); - bec->rxerr = readb(&priv->regs->recr); - clk_disable_unprepare(priv->clk); - return 0; -} - -static const char * const clock_names[] = { - [CLKR_CLKP1] = "clkp1", - [CLKR_CLKP2] = "clkp2", - [CLKR_CLKEXT] = "can_clk", -}; - -static int rcar_can_probe(struct platform_device *pdev) -{ - struct rcar_can_platform_data *pdata; - struct rcar_can_priv *priv; - struct net_device *ndev; - struct resource *mem; - void __iomem *addr; - u32 clock_select = CLKR_CLKP1; - int err = -ENODEV; - int irq; - - if (pdev->dev.of_node) { - of_property_read_u32(pdev->dev.of_node, - "renesas,can-clock-select", &clock_select); - } else { - pdata = dev_get_platdata(&pdev->dev); - if (!pdata) { - dev_err(&pdev->dev, "No platform data provided!\n"); - goto fail; - } - clock_select = pdata->clock_select; - } - - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "No IRQ resource\n"); - err = irq; - goto fail; - } - - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - addr = devm_ioremap_resource(&pdev->dev, mem); - if (IS_ERR(addr)) { - err = PTR_ERR(addr); - goto fail; - } - - ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); - if (!ndev) { - dev_err(&pdev->dev, "alloc_candev() failed\n"); - err = -ENOMEM; - goto fail; - } - - priv = netdev_priv(ndev); - - priv->clk = devm_clk_get(&pdev->dev, "clkp1"); - if (IS_ERR(priv->clk)) { - err = PTR_ERR(priv->clk); - dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n", - err); - goto fail_clk; - } - - if (clock_select >= ARRAY_SIZE(clock_names)) { - err = -EINVAL; - dev_err(&pdev->dev, "invalid CAN clock selected\n"); - goto fail_clk; - } - priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); - if (IS_ERR(priv->can_clk)) { - err = PTR_ERR(priv->can_clk); - dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err); - goto fail_clk; - } - - ndev->netdev_ops = &rcar_can_netdev_ops; - ndev->irq = irq; - ndev->flags |= IFF_ECHO; - priv->ndev = ndev; - priv->regs = addr; - priv->clock_select = clock_select; - priv->can.clock.freq = clk_get_rate(priv->can_clk); - priv->can.bittiming_const = &rcar_can_bittiming_const; - priv->can.do_set_mode = rcar_can_do_set_mode; - priv->can.do_get_berr_counter = rcar_can_get_berr_counter; - priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; - platform_set_drvdata(pdev, ndev); - SET_NETDEV_DEV(ndev, &pdev->dev); - - netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, - RCAR_CAN_NAPI_WEIGHT); - err = register_candev(ndev); - if (err) { - dev_err(&pdev->dev, "register_candev() failed, error %d\n", - err); - goto fail_candev; - } - - devm_can_led_init(ndev); - - dev_info(&pdev->dev, "device registered (regs @ %p, IRQ%d)\n", - priv->regs, ndev->irq); - - return 0; -fail_candev: - netif_napi_del(&priv->napi); -fail_clk: - free_candev(ndev); -fail: - return err; -} - -static int rcar_can_remove(struct platform_device *pdev) -{ - struct net_device *ndev = platform_get_drvdata(pdev); - struct rcar_can_priv *priv = netdev_priv(ndev); - - unregister_candev(ndev); - netif_napi_del(&priv->napi); - free_candev(ndev); - return 0; -} - -static int __maybe_unused rcar_can_suspend(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct rcar_can_priv *priv = netdev_priv(ndev); - u16 ctlr; - - if (netif_running(ndev)) { - netif_stop_queue(ndev); - netif_device_detach(ndev); - } - ctlr = readw(&priv->regs->ctlr); - ctlr |= RCAR_CAN_CTLR_CANM_HALT; - writew(ctlr, &priv->regs->ctlr); - ctlr |= RCAR_CAN_CTLR_SLPM; - writew(ctlr, &priv->regs->ctlr); - priv->can.state = CAN_STATE_SLEEPING; - - clk_disable(priv->clk); - return 0; -} - -static int __maybe_unused rcar_can_resume(struct device *dev) -{ - struct net_device *ndev = dev_get_drvdata(dev); - struct rcar_can_priv *priv = netdev_priv(ndev); - u16 ctlr; - int err; - - err = clk_enable(priv->clk); - if (err) { - netdev_err(ndev, "clk_enable() failed, error %d\n", err); - return err; - } - - ctlr = readw(&priv->regs->ctlr); - ctlr &= ~RCAR_CAN_CTLR_SLPM; - writew(ctlr, &priv->regs->ctlr); - ctlr &= ~RCAR_CAN_CTLR_CANM; - writew(ctlr, &priv->regs->ctlr); - priv->can.state = CAN_STATE_ERROR_ACTIVE; - - if (netif_running(ndev)) { - netif_device_attach(ndev); - netif_start_queue(ndev); - } - return 0; -} - -static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); - -static const struct of_device_id rcar_can_of_table[] __maybe_unused = { - { .compatible = "renesas,can-r8a7778" }, - { .compatible = "renesas,can-r8a7779" }, - { .compatible = "renesas,can-r8a7790" }, - { .compatible = "renesas,can-r8a7791" }, - { .compatible = "renesas,rcar-gen1-can" }, - { .compatible = "renesas,rcar-gen2-can" }, - { .compatible = "renesas,rcar-gen3-can" }, - { } -}; -MODULE_DEVICE_TABLE(of, rcar_can_of_table); - -static struct platform_driver rcar_can_driver = { - .driver = { - .name = RCAR_CAN_DRV_NAME, - .of_match_table = of_match_ptr(rcar_can_of_table), - .pm = &rcar_can_pm_ops, - }, - .probe = rcar_can_probe, - .remove = rcar_can_remove, -}; - -module_platform_driver(rcar_can_driver); - -MODULE_AUTHOR("Cogent Embedded, Inc."); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); -MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); diff --git a/drivers/net/dsa/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx.c deleted file mode 100644 index ba9dfc942..000000000 --- a/drivers/net/dsa/mv88e6xxx.c +++ /dev/null @@ -1,3723 +0,0 @@ -/* - * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support - * Copyright (c) 2008 Marvell Semiconductor - * - * Copyright (c) 2015 CMC Electronics, Inc. - * Added support for VLAN Table Unit operations - * - * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <linux/delay.h> -#include <linux/etherdevice.h> -#include <linux/ethtool.h> -#include <linux/if_bridge.h> -#include <linux/jiffies.h> -#include <linux/list.h> -#include <linux/mdio.h> -#include <linux/module.h> -#include <linux/netdevice.h> -#include <linux/gpio/consumer.h> -#include <linux/phy.h> -#include <net/dsa.h> -#include <net/switchdev.h> -#include "mv88e6xxx.h" - -static void assert_smi_lock(struct mv88e6xxx_priv_state *ps) -{ - if (unlikely(!mutex_is_locked(&ps->smi_mutex))) { - dev_err(ps->dev, "SMI lock not held!\n"); - dump_stack(); - } -} - -/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will - * use all 32 SMI bus addresses on its SMI bus, and all switch registers - * will be directly accessible on some {device address,register address} - * pair. If the ADDR[4:0] pins are not strapped to zero, the switch - * will only respond to SMI transactions to that specific address, and - * an indirect addressing mechanism needs to be used to access its - * registers. - */ -static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) -{ - int ret; - int i; - - for (i = 0; i < 16; i++) { - ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD); - if (ret < 0) - return ret; - - if ((ret & SMI_CMD_BUSY) == 0) - return 0; - } - - return -ETIMEDOUT; -} - -static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, - int reg) -{ - int ret; - - if (sw_addr == 0) - return mdiobus_read_nested(bus, addr, reg); - - /* Wait for the bus to become free. */ - ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); - if (ret < 0) - return ret; - - /* Transmit the read command. */ - ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, - SMI_CMD_OP_22_READ | (addr << 5) | reg); - if (ret < 0) - return ret; - - /* Wait for the read command to complete. */ - ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); - if (ret < 0) - return ret; - - /* Read the data. */ - ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA); - if (ret < 0) - return ret; - - return ret & 0xffff; -} - -static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, - int addr, int reg) -{ - int ret; - - assert_smi_lock(ps); - - ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg); - if (ret < 0) - return ret; - - dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", - addr, reg, ret); - - return ret; -} - -int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg) -{ - int ret; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_reg_read(ps, addr, reg); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, - int reg, u16 val) -{ - int ret; - - if (sw_addr == 0) - return mdiobus_write_nested(bus, addr, reg, val); - - /* Wait for the bus to become free. */ - ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); - if (ret < 0) - return ret; - - /* Transmit the data to write. */ - ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val); - if (ret < 0) - return ret; - - /* Transmit the write command. */ - ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD, - SMI_CMD_OP_22_WRITE | (addr << 5) | reg); - if (ret < 0) - return ret; - - /* Wait for the write command to complete. */ - ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); - if (ret < 0) - return ret; - - return 0; -} - -static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, - int reg, u16 val) -{ - assert_smi_lock(ps); - - dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", - addr, reg, val); - - return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val); -} - -int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, - int reg, u16 val) -{ - int ret; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_reg_write(ps, addr, reg, val); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int err; - - err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01, - (addr[0] << 8) | addr[1]); - if (err) - return err; - - err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23, - (addr[2] << 8) | addr[3]); - if (err) - return err; - - return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45, - (addr[4] << 8) | addr[5]); -} - -static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - int i; - - for (i = 0; i < 6; i++) { - int j; - - /* Write the MAC address byte. */ - ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, - GLOBAL2_SWITCH_MAC_BUSY | - (i << 8) | addr[i]); - if (ret) - return ret; - - /* Wait for the write to complete. */ - for (j = 0; j < 16; j++) { - ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, - GLOBAL2_SWITCH_MAC); - if (ret < 0) - return ret; - - if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) - break; - } - if (j == 16) - return -ETIMEDOUT; - } - - return 0; -} - -int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC)) - return mv88e6xxx_set_addr_indirect(ds, addr); - else - return mv88e6xxx_set_addr_direct(ds, addr); -} - -static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr, - int regnum) -{ - if (addr >= 0) - return _mv88e6xxx_reg_read(ps, addr, regnum); - return 0xffff; -} - -static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr, - int regnum, u16 val) -{ - if (addr >= 0) - return _mv88e6xxx_reg_write(ps, addr, regnum, val); - return 0; -} - -static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps) -{ - int ret; - unsigned long timeout; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, - ret & ~GLOBAL_CONTROL_PPU_ENABLE); - if (ret) - return ret; - - timeout = jiffies + 1 * HZ; - while (time_before(jiffies, timeout)) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); - if (ret < 0) - return ret; - - usleep_range(1000, 2000); - if ((ret & GLOBAL_STATUS_PPU_MASK) != - GLOBAL_STATUS_PPU_POLLING) - return 0; - } - - return -ETIMEDOUT; -} - -static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps) -{ - int ret, err; - unsigned long timeout; - - ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); - if (ret < 0) - return ret; - - err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, - ret | GLOBAL_CONTROL_PPU_ENABLE); - if (err) - return err; - - timeout = jiffies + 1 * HZ; - while (time_before(jiffies, timeout)) { - ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); - if (ret < 0) - return ret; - - usleep_range(1000, 2000); - if ((ret & GLOBAL_STATUS_PPU_MASK) == - GLOBAL_STATUS_PPU_POLLING) - return 0; - } - - return -ETIMEDOUT; -} - -static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) -{ - struct mv88e6xxx_priv_state *ps; - - ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); - if (mutex_trylock(&ps->ppu_mutex)) { - if (mv88e6xxx_ppu_enable(ps) == 0) - ps->ppu_disabled = 0; - mutex_unlock(&ps->ppu_mutex); - } -} - -static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) -{ - struct mv88e6xxx_priv_state *ps = (void *)_ps; - - schedule_work(&ps->ppu_work); -} - -static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps) -{ - int ret; - - mutex_lock(&ps->ppu_mutex); - - /* If the PHY polling unit is enabled, disable it so that - * we can access the PHY registers. If it was already - * disabled, cancel the timer that is going to re-enable - * it. - */ - if (!ps->ppu_disabled) { - ret = mv88e6xxx_ppu_disable(ps); - if (ret < 0) { - mutex_unlock(&ps->ppu_mutex); - return ret; - } - ps->ppu_disabled = 1; - } else { - del_timer(&ps->ppu_timer); - ret = 0; - } - - return ret; -} - -static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps) -{ - /* Schedule a timer to re-enable the PHY polling unit. */ - mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); - mutex_unlock(&ps->ppu_mutex); -} - -void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps) -{ - mutex_init(&ps->ppu_mutex); - INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); - init_timer(&ps->ppu_timer); - ps->ppu_timer.data = (unsigned long)ps; - ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; -} - -static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr, - int regnum) -{ - int ret; - - ret = mv88e6xxx_ppu_access_get(ps); - if (ret >= 0) { - ret = _mv88e6xxx_reg_read(ps, addr, regnum); - mv88e6xxx_ppu_access_put(ps); - } - - return ret; -} - -static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr, - int regnum, u16 val) -{ - int ret; - - ret = mv88e6xxx_ppu_access_get(ps); - if (ret >= 0) { - ret = _mv88e6xxx_reg_write(ps, addr, regnum, val); - mv88e6xxx_ppu_access_put(ps); - } - - return ret; -} - -static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6065; -} - -static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6095; -} - -static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6097; -} - -static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6165; -} - -static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6185; -} - -static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6320; -} - -static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6351; -} - -static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->family == MV88E6XXX_FAMILY_6352; -} - -static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps) -{ - return ps->info->num_databases; -} - -static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps) -{ - /* Does the device have dedicated FID registers for ATU and VTU ops? */ - if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || - mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) - return true; - - return false; -} - -/* We expect the switch to perform auto negotiation if there is a real - * phy. However, in the case of a fixed link phy, we force the port - * settings from the fixed link settings. - */ -static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, - struct phy_device *phydev) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - u32 reg; - int ret; - - if (!phy_is_pseudo_fixed_link(phydev)) - return; - - mutex_lock(&ps->smi_mutex); - - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); - if (ret < 0) - goto out; - - reg = ret & ~(PORT_PCS_CTRL_LINK_UP | - PORT_PCS_CTRL_FORCE_LINK | - PORT_PCS_CTRL_DUPLEX_FULL | - PORT_PCS_CTRL_FORCE_DUPLEX | - PORT_PCS_CTRL_UNFORCED); - - reg |= PORT_PCS_CTRL_FORCE_LINK; - if (phydev->link) - reg |= PORT_PCS_CTRL_LINK_UP; - - if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100) - goto out; - - switch (phydev->speed) { - case SPEED_1000: - reg |= PORT_PCS_CTRL_1000; - break; - case SPEED_100: - reg |= PORT_PCS_CTRL_100; - break; - case SPEED_10: - reg |= PORT_PCS_CTRL_10; - break; - default: - pr_info("Unknown speed"); - goto out; - } - - reg |= PORT_PCS_CTRL_FORCE_DUPLEX; - if (phydev->duplex == DUPLEX_FULL) - reg |= PORT_PCS_CTRL_DUPLEX_FULL; - - if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) && - (port >= ps->info->num_ports - 2)) { - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) - reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) - reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) - reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | - PORT_PCS_CTRL_RGMII_DELAY_TXCLK); - } - _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg); - -out: - mutex_unlock(&ps->smi_mutex); -} - -static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps) -{ - int ret; - int i; - - for (i = 0; i < 10; i++) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP); - if ((ret & GLOBAL_STATS_OP_BUSY) == 0) - return 0; - } - - return -ETIMEDOUT; -} - -static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps, - int port) -{ - int ret; - - if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) - port = (port + 1) << 5; - - /* Snapshot the hardware statistics counters for this port. */ - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, - GLOBAL_STATS_OP_CAPTURE_PORT | - GLOBAL_STATS_OP_HIST_RX_TX | port); - if (ret < 0) - return ret; - - /* Wait for the snapshotting to complete. */ - ret = _mv88e6xxx_stats_wait(ps); - if (ret < 0) - return ret; - - return 0; -} - -static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps, - int stat, u32 *val) -{ - u32 _val; - int ret; - - *val = 0; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, - GLOBAL_STATS_OP_READ_CAPTURED | - GLOBAL_STATS_OP_HIST_RX_TX | stat); - if (ret < 0) - return; - - ret = _mv88e6xxx_stats_wait(ps); - if (ret < 0) - return; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); - if (ret < 0) - return; - - _val = ret << 16; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); - if (ret < 0) - return; - - *val = _val | ret; -} - -static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { - { "in_good_octets", 8, 0x00, BANK0, }, - { "in_bad_octets", 4, 0x02, BANK0, }, - { "in_unicast", 4, 0x04, BANK0, }, - { "in_broadcasts", 4, 0x06, BANK0, }, - { "in_multicasts", 4, 0x07, BANK0, }, - { "in_pause", 4, 0x16, BANK0, }, - { "in_undersize", 4, 0x18, BANK0, }, - { "in_fragments", 4, 0x19, BANK0, }, - { "in_oversize", 4, 0x1a, BANK0, }, - { "in_jabber", 4, 0x1b, BANK0, }, - { "in_rx_error", 4, 0x1c, BANK0, }, - { "in_fcs_error", 4, 0x1d, BANK0, }, - { "out_octets", 8, 0x0e, BANK0, }, - { "out_unicast", 4, 0x10, BANK0, }, - { "out_broadcasts", 4, 0x13, BANK0, }, - { "out_multicasts", 4, 0x12, BANK0, }, - { "out_pause", 4, 0x15, BANK0, }, - { "excessive", 4, 0x11, BANK0, }, - { "collisions", 4, 0x1e, BANK0, }, - { "deferred", 4, 0x05, BANK0, }, - { "single", 4, 0x14, BANK0, }, - { "multiple", 4, 0x17, BANK0, }, - { "out_fcs_error", 4, 0x03, BANK0, }, - { "late", 4, 0x1f, BANK0, }, - { "hist_64bytes", 4, 0x08, BANK0, }, - { "hist_65_127bytes", 4, 0x09, BANK0, }, - { "hist_128_255bytes", 4, 0x0a, BANK0, }, - { "hist_256_511bytes", 4, 0x0b, BANK0, }, - { "hist_512_1023bytes", 4, 0x0c, BANK0, }, - { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, - { "sw_in_discards", 4, 0x10, PORT, }, - { "sw_in_filtered", 2, 0x12, PORT, }, - { "sw_out_filtered", 2, 0x13, PORT, }, - { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, - { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, -}; - -static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_hw_stat *stat) -{ - switch (stat->type) { - case BANK0: - return true; - case BANK1: - return mv88e6xxx_6320_family(ps); - case PORT: - return mv88e6xxx_6095_family(ps) || - mv88e6xxx_6185_family(ps) || - mv88e6xxx_6097_family(ps) || - mv88e6xxx_6165_family(ps) || - mv88e6xxx_6351_family(ps) || - mv88e6xxx_6352_family(ps); - } - return false; -} - -static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_hw_stat *s, - int port) -{ - u32 low; - u32 high = 0; - int ret; - u64 value; - - switch (s->type) { - case PORT: - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg); - if (ret < 0) - return UINT64_MAX; - - low = ret; - if (s->sizeof_stat == 4) { - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), - s->reg + 1); - if (ret < 0) - return UINT64_MAX; - high = ret; - } - break; - case BANK0: - case BANK1: - _mv88e6xxx_stats_read(ps, s->reg, &low); - if (s->sizeof_stat == 8) - _mv88e6xxx_stats_read(ps, s->reg + 1, &high); - } - value = (((u64)high) << 16) | low; - return value; -} - -static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, - uint8_t *data) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_hw_stat *stat; - int i, j; - - for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { - stat = &mv88e6xxx_hw_stats[i]; - if (mv88e6xxx_has_stat(ps, stat)) { - memcpy(data + j * ETH_GSTRING_LEN, stat->string, - ETH_GSTRING_LEN); - j++; - } - } -} - -static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_hw_stat *stat; - int i, j; - - for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { - stat = &mv88e6xxx_hw_stats[i]; - if (mv88e6xxx_has_stat(ps, stat)) - j++; - } - return j; -} - -static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, - uint64_t *data) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_hw_stat *stat; - int ret; - int i, j; - - mutex_lock(&ps->smi_mutex); - - ret = _mv88e6xxx_stats_snapshot(ps, port); - if (ret < 0) { - mutex_unlock(&ps->smi_mutex); - return; - } - for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { - stat = &mv88e6xxx_hw_stats[i]; - if (mv88e6xxx_has_stat(ps, stat)) { - data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port); - j++; - } - } - - mutex_unlock(&ps->smi_mutex); -} - -static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) -{ - return 32 * sizeof(u16); -} - -static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, - struct ethtool_regs *regs, void *_p) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - u16 *p = _p; - int i; - - regs->version = 0; - - memset(p, 0xff, 32 * sizeof(u16)); - - mutex_lock(&ps->smi_mutex); - - for (i = 0; i < 32; i++) { - int ret; - - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i); - if (ret >= 0) - p[i] = ret; - } - - mutex_unlock(&ps->smi_mutex); -} - -static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset, - u16 mask) -{ - unsigned long timeout = jiffies + HZ / 10; - - while (time_before(jiffies, timeout)) { - int ret; - - ret = _mv88e6xxx_reg_read(ps, reg, offset); - if (ret < 0) - return ret; - if (!(ret & mask)) - return 0; - - usleep_range(1000, 2000); - } - return -ETIMEDOUT; -} - -static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, - int offset, u16 mask) -{ - int ret; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_wait(ps, reg, offset, mask); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps) -{ - return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, - GLOBAL2_SMI_OP_BUSY); -} - -static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, - GLOBAL2_EEPROM_OP_LOAD); -} - -static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, - GLOBAL2_EEPROM_OP_BUSY); -} - -static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - mutex_lock(&ps->eeprom_mutex); - - ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, - GLOBAL2_EEPROM_OP_READ | - (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); - if (ret < 0) - goto error; - - ret = mv88e6xxx_eeprom_busy_wait(ds); - if (ret < 0) - goto error; - - ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA); -error: - mutex_unlock(&ps->eeprom_mutex); - return ret; -} - -static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) - return ps->eeprom_len; - - return 0; -} - -static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, - struct ethtool_eeprom *eeprom, u8 *data) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int offset; - int len; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) - return -EOPNOTSUPP; - - offset = eeprom->offset; - len = eeprom->len; - eeprom->len = 0; - - eeprom->magic = 0xc3ec4951; - - ret = mv88e6xxx_eeprom_load_wait(ds); - if (ret < 0) - return ret; - - if (offset & 1) { - int word; - - word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); - if (word < 0) - return word; - - *data++ = (word >> 8) & 0xff; - - offset++; - len--; - eeprom->len++; - } - - while (len >= 2) { - int word; - - word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); - if (word < 0) - return word; - - *data++ = word & 0xff; - *data++ = (word >> 8) & 0xff; - - offset += 2; - len -= 2; - eeprom->len += 2; - } - - if (len) { - int word; - - word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); - if (word < 0) - return word; - - *data++ = word & 0xff; - - offset++; - len--; - eeprom->len++; - } - - return 0; -} - -static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP); - if (ret < 0) - return ret; - - if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN)) - return -EROFS; - - return 0; -} - -static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr, - u16 data) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - mutex_lock(&ps->eeprom_mutex); - - ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); - if (ret < 0) - goto error; - - ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, - GLOBAL2_EEPROM_OP_WRITE | - (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); - if (ret < 0) - goto error; - - ret = mv88e6xxx_eeprom_busy_wait(ds); -error: - mutex_unlock(&ps->eeprom_mutex); - return ret; -} - -static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, - struct ethtool_eeprom *eeprom, u8 *data) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int offset; - int ret; - int len; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) - return -EOPNOTSUPP; - - if (eeprom->magic != 0xc3ec4951) - return -EINVAL; - - ret = mv88e6xxx_eeprom_is_readonly(ds); - if (ret) - return ret; - - offset = eeprom->offset; - len = eeprom->len; - eeprom->len = 0; - - ret = mv88e6xxx_eeprom_load_wait(ds); - if (ret < 0) - return ret; - - if (offset & 1) { - int word; - - word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); - if (word < 0) - return word; - - word = (*data++ << 8) | (word & 0xff); - - ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); - if (ret < 0) - return ret; - - offset++; - len--; - eeprom->len++; - } - - while (len >= 2) { - int word; - - word = *data++; - word |= *data++ << 8; - - ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); - if (ret < 0) - return ret; - - offset += 2; - len -= 2; - eeprom->len += 2; - } - - if (len) { - int word; - - word = mv88e6xxx_read_eeprom_word(ds, offset >> 1); - if (word < 0) - return word; - - word = (word & 0xff00) | *data++; - - ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word); - if (ret < 0) - return ret; - - offset++; - len--; - eeprom->len++; - } - - return 0; -} - -static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps) -{ - return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP, - GLOBAL_ATU_OP_BUSY); -} - -static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps, - int addr, int regnum) -{ - int ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, - GLOBAL2_SMI_OP_22_READ | (addr << 5) | - regnum); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_phy_wait(ps); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA); - - return ret; -} - -static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps, - int addr, int regnum, u16 val) -{ - int ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, - GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | - regnum); - - return _mv88e6xxx_phy_wait(ps); -} - -static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, - struct ethtool_eee *e) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int reg; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - reg = _mv88e6xxx_phy_read_indirect(ps, port, 16); - if (reg < 0) - goto out; - - e->eee_enabled = !!(reg & 0x0200); - e->tx_lpi_enabled = !!(reg & 0x0100); - - reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); - if (reg < 0) - goto out; - - e->eee_active = !!(reg & PORT_STATUS_EEE); - reg = 0; - -out: - mutex_unlock(&ps->smi_mutex); - return reg; -} - -static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, - struct phy_device *phydev, struct ethtool_eee *e) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int reg; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - ret = _mv88e6xxx_phy_read_indirect(ps, port, 16); - if (ret < 0) - goto out; - - reg = ret & ~0x0300; - if (e->eee_enabled) - reg |= 0x0200; - if (e->tx_lpi_enabled) - reg |= 0x0100; - - ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg); -out: - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd) -{ - int ret; - - if (mv88e6xxx_has_fid_reg(ps)) { - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid); - if (ret < 0) - return ret; - } else if (mv88e6xxx_num_databases(ps) == 256) { - /* ATU DBNum[7:4] are located in ATU Control 15:12 */ - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, - (ret & 0xfff) | - ((fid << 8) & 0xf000)); - if (ret < 0) - return ret; - - /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ - cmd |= fid & 0xf; - } - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd); - if (ret < 0) - return ret; - - return _mv88e6xxx_atu_wait(ps); -} - -static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_atu_entry *entry) -{ - u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; - - if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { - unsigned int mask, shift; - - if (entry->trunk) { - data |= GLOBAL_ATU_DATA_TRUNK; - mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; - shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; - } else { - mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; - shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; - } - - data |= (entry->portv_trunkid << shift) & mask; - } - - return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data); -} - -static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_atu_entry *entry, - bool static_too) -{ - int op; - int err; - - err = _mv88e6xxx_atu_wait(ps); - if (err) - return err; - - err = _mv88e6xxx_atu_data_write(ps, entry); - if (err) - return err; - - if (entry->fid) { - op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : - GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; - } else { - op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : - GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; - } - - return _mv88e6xxx_atu_cmd(ps, entry->fid, op); -} - -static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps, - u16 fid, bool static_too) -{ - struct mv88e6xxx_atu_entry entry = { - .fid = fid, - .state = 0, /* EntryState bits must be 0 */ - }; - - return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); -} - -static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid, - int from_port, int to_port, bool static_too) -{ - struct mv88e6xxx_atu_entry entry = { - .trunk = false, - .fid = fid, - }; - - /* EntryState bits must be 0xF */ - entry.state = GLOBAL_ATU_DATA_STATE_MASK; - - /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ - entry.portv_trunkid = (to_port & 0x0f) << 4; - entry.portv_trunkid |= from_port & 0x0f; - - return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); -} - -static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid, - int port, bool static_too) -{ - /* Destination port 0xF means remove the entries */ - return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too); -} - -static const char * const mv88e6xxx_port_state_names[] = { - [PORT_CONTROL_STATE_DISABLED] = "Disabled", - [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", - [PORT_CONTROL_STATE_LEARNING] = "Learning", - [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", -}; - -static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port, - u8 state) -{ - struct dsa_switch *ds = ps->ds; - int reg, ret = 0; - u8 oldstate; - - reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL); - if (reg < 0) - return reg; - - oldstate = reg & PORT_CONTROL_STATE_MASK; - - if (oldstate != state) { - /* Flush forwarding database if we're moving a port - * from Learning or Forwarding state to Disabled or - * Blocking or Listening state. - */ - if ((oldstate == PORT_CONTROL_STATE_LEARNING || - oldstate == PORT_CONTROL_STATE_FORWARDING) - && (state == PORT_CONTROL_STATE_DISABLED || - state == PORT_CONTROL_STATE_BLOCKING)) { - ret = _mv88e6xxx_atu_remove(ps, 0, port, false); - if (ret) - return ret; - } - - reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL, - reg); - if (ret) - return ret; - - netdev_dbg(ds->ports[port], "PortState %s (was %s)\n", - mv88e6xxx_port_state_names[state], - mv88e6xxx_port_state_names[oldstate]); - } - - return ret; -} - -static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps, - int port) -{ - struct net_device *bridge = ps->ports[port].bridge_dev; - const u16 mask = (1 << ps->info->num_ports) - 1; - struct dsa_switch *ds = ps->ds; - u16 output_ports = 0; - int reg; - int i; - - /* allow CPU port or DSA link(s) to send frames to every port */ - if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { - output_ports = mask; - } else { - for (i = 0; i < ps->info->num_ports; ++i) { - /* allow sending frames to every group member */ - if (bridge && ps->ports[i].bridge_dev == bridge) - output_ports |= BIT(i); - - /* allow sending frames to CPU port and DSA link(s) */ - if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) - output_ports |= BIT(i); - } - } - - /* prevent frames from going back out of the port they came in on */ - output_ports &= ~BIT(port); - - reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); - if (reg < 0) - return reg; - - reg &= ~mask; - reg |= output_ports & mask; - - return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg); -} - -static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, - u8 state) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int stp_state; - int err; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE)) - return; - - switch (state) { - case BR_STATE_DISABLED: - stp_state = PORT_CONTROL_STATE_DISABLED; - break; - case BR_STATE_BLOCKING: - case BR_STATE_LISTENING: - stp_state = PORT_CONTROL_STATE_BLOCKING; - break; - case BR_STATE_LEARNING: - stp_state = PORT_CONTROL_STATE_LEARNING; - break; - case BR_STATE_FORWARDING: - default: - stp_state = PORT_CONTROL_STATE_FORWARDING; - break; - } - - mutex_lock(&ps->smi_mutex); - err = _mv88e6xxx_port_state(ps, port, stp_state); - mutex_unlock(&ps->smi_mutex); - - if (err) - netdev_err(ds->ports[port], "failed to update state to %s\n", - mv88e6xxx_port_state_names[stp_state]); -} - -static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port, - u16 *new, u16 *old) -{ - struct dsa_switch *ds = ps->ds; - u16 pvid; - int ret; - - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN); - if (ret < 0) - return ret; - - pvid = ret & PORT_DEFAULT_VLAN_MASK; - - if (new) { - ret &= ~PORT_DEFAULT_VLAN_MASK; - ret |= *new & PORT_DEFAULT_VLAN_MASK; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_DEFAULT_VLAN, ret); - if (ret < 0) - return ret; - - netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new, - pvid); - } - - if (old) - *old = pvid; - - return 0; -} - -static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps, - int port, u16 *pvid) -{ - return _mv88e6xxx_port_pvid(ps, port, NULL, pvid); -} - -static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps, - int port, u16 pvid) -{ - return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL); -} - -static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps) -{ - return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP, - GLOBAL_VTU_OP_BUSY); -} - -static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op) -{ - int ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op); - if (ret < 0) - return ret; - - return _mv88e6xxx_vtu_wait(ps); -} - -static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps) -{ - int ret; - - ret = _mv88e6xxx_vtu_wait(ps); - if (ret < 0) - return ret; - - return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL); -} - -static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry, - unsigned int nibble_offset) -{ - u16 regs[3]; - int i; - int ret; - - for (i = 0; i < 3; ++i) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, - GLOBAL_VTU_DATA_0_3 + i); - if (ret < 0) - return ret; - - regs[i] = ret; - } - - for (i = 0; i < ps->info->num_ports; ++i) { - unsigned int shift = (i % 4) * 4 + nibble_offset; - u16 reg = regs[i / 4]; - - entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; - } - - return 0; -} - -static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0); -} - -static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2); -} - -static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry, - unsigned int nibble_offset) -{ - u16 regs[3] = { 0 }; - int i; - int ret; - - for (i = 0; i < ps->info->num_ports; ++i) { - unsigned int shift = (i % 4) * 4 + nibble_offset; - u8 data = entry->data[i]; - - regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; - } - - for (i = 0; i < 3; ++i) { - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, - GLOBAL_VTU_DATA_0_3 + i, regs[i]); - if (ret < 0) - return ret; - } - - return 0; -} - -static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0); -} - -static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2); -} - -static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid) -{ - return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, - vid & GLOBAL_VTU_VID_MASK); -} - -static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - struct mv88e6xxx_vtu_stu_entry next = { 0 }; - int ret; - - ret = _mv88e6xxx_vtu_wait(ps); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); - if (ret < 0) - return ret; - - next.vid = ret & GLOBAL_VTU_VID_MASK; - next.valid = !!(ret & GLOBAL_VTU_VID_VALID); - - if (next.valid) { - ret = mv88e6xxx_vtu_data_read(ps, &next); - if (ret < 0) - return ret; - - if (mv88e6xxx_has_fid_reg(ps)) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, - GLOBAL_VTU_FID); - if (ret < 0) - return ret; - - next.fid = ret & GLOBAL_VTU_FID_MASK; - } else if (mv88e6xxx_num_databases(ps) == 256) { - /* VTU DBNum[7:4] are located in VTU Operation 11:8, and - * VTU DBNum[3:0] are located in VTU Operation 3:0 - */ - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, - GLOBAL_VTU_OP); - if (ret < 0) - return ret; - - next.fid = (ret & 0xf00) >> 4; - next.fid |= ret & 0xf; - } - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, - GLOBAL_VTU_SID); - if (ret < 0) - return ret; - - next.sid = ret & GLOBAL_VTU_SID_MASK; - } - } - - *entry = next; - return 0; -} - -static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, - struct switchdev_obj_port_vlan *vlan, - int (*cb)(struct switchdev_obj *obj)) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_vtu_stu_entry next; - u16 pvid; - int err; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); - if (err) - goto unlock; - - err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); - if (err) - goto unlock; - - do { - err = _mv88e6xxx_vtu_getnext(ps, &next); - if (err) - break; - - if (!next.valid) - break; - - if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) - continue; - - /* reinit and dump this VLAN obj */ - vlan->vid_begin = vlan->vid_end = next.vid; - vlan->flags = 0; - - if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) - vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; - - if (next.vid == pvid) - vlan->flags |= BRIDGE_VLAN_INFO_PVID; - - err = cb(&vlan->obj); - if (err) - break; - } while (next.vid < GLOBAL_VTU_VID_MASK); - -unlock: - mutex_unlock(&ps->smi_mutex); - - return err; -} - -static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; - u16 reg = 0; - int ret; - - ret = _mv88e6xxx_vtu_wait(ps); - if (ret < 0) - return ret; - - if (!entry->valid) - goto loadpurge; - - /* Write port member tags */ - ret = mv88e6xxx_vtu_data_write(ps, entry); - if (ret < 0) - return ret; - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { - reg = entry->sid & GLOBAL_VTU_SID_MASK; - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); - if (ret < 0) - return ret; - } - - if (mv88e6xxx_has_fid_reg(ps)) { - reg = entry->fid & GLOBAL_VTU_FID_MASK; - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg); - if (ret < 0) - return ret; - } else if (mv88e6xxx_num_databases(ps) == 256) { - /* VTU DBNum[7:4] are located in VTU Operation 11:8, and - * VTU DBNum[3:0] are located in VTU Operation 3:0 - */ - op |= (entry->fid & 0xf0) << 8; - op |= entry->fid & 0xf; - } - - reg = GLOBAL_VTU_VID_VALID; -loadpurge: - reg |= entry->vid & GLOBAL_VTU_VID_MASK; - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); - if (ret < 0) - return ret; - - return _mv88e6xxx_vtu_cmd(ps, op); -} - -static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - struct mv88e6xxx_vtu_stu_entry next = { 0 }; - int ret; - - ret = _mv88e6xxx_vtu_wait(ps); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, - sid & GLOBAL_VTU_SID_MASK); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID); - if (ret < 0) - return ret; - - next.sid = ret & GLOBAL_VTU_SID_MASK; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); - if (ret < 0) - return ret; - - next.valid = !!(ret & GLOBAL_VTU_VID_VALID); - - if (next.valid) { - ret = mv88e6xxx_stu_data_read(ps, &next); - if (ret < 0) - return ret; - } - - *entry = next; - return 0; -} - -static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - u16 reg = 0; - int ret; - - ret = _mv88e6xxx_vtu_wait(ps); - if (ret < 0) - return ret; - - if (!entry->valid) - goto loadpurge; - - /* Write port states */ - ret = mv88e6xxx_stu_data_write(ps, entry); - if (ret < 0) - return ret; - - reg = GLOBAL_VTU_VID_VALID; -loadpurge: - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); - if (ret < 0) - return ret; - - reg = entry->sid & GLOBAL_VTU_SID_MASK; - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); - if (ret < 0) - return ret; - - return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE); -} - -static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port, - u16 *new, u16 *old) -{ - struct dsa_switch *ds = ps->ds; - u16 upper_mask; - u16 fid; - int ret; - - if (mv88e6xxx_num_databases(ps) == 4096) - upper_mask = 0xff; - else if (mv88e6xxx_num_databases(ps) == 256) - upper_mask = 0xf; - else - return -EOPNOTSUPP; - - /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); - if (ret < 0) - return ret; - - fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; - - if (new) { - ret &= ~PORT_BASE_VLAN_FID_3_0_MASK; - ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, - ret); - if (ret < 0) - return ret; - } - - /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1); - if (ret < 0) - return ret; - - fid |= (ret & upper_mask) << 4; - - if (new) { - ret &= ~upper_mask; - ret |= (*new >> 4) & upper_mask; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, - ret); - if (ret < 0) - return ret; - - netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid); - } - - if (old) - *old = fid; - - return 0; -} - -static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps, - int port, u16 *fid) -{ - return _mv88e6xxx_port_fid(ps, port, NULL, fid); -} - -static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps, - int port, u16 fid) -{ - return _mv88e6xxx_port_fid(ps, port, &fid, NULL); -} - -static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid) -{ - DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); - struct mv88e6xxx_vtu_stu_entry vlan; - int i, err; - - bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); - - /* Set every FID bit used by the (un)bridged ports */ - for (i = 0; i < ps->info->num_ports; ++i) { - err = _mv88e6xxx_port_fid_get(ps, i, fid); - if (err) - return err; - - set_bit(*fid, fid_bitmap); - } - - /* Set every FID bit used by the VLAN entries */ - err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); - if (err) - return err; - - do { - err = _mv88e6xxx_vtu_getnext(ps, &vlan); - if (err) - return err; - - if (!vlan.valid) - break; - - set_bit(vlan.fid, fid_bitmap); - } while (vlan.vid < GLOBAL_VTU_VID_MASK); - - /* The reset value 0x000 is used to indicate that multiple address - * databases are not needed. Return the next positive available. - */ - *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); - if (unlikely(*fid >= mv88e6xxx_num_databases(ps))) - return -ENOSPC; - - /* Clear the database */ - return _mv88e6xxx_atu_flush(ps, *fid, true); -} - -static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid, - struct mv88e6xxx_vtu_stu_entry *entry) -{ - struct dsa_switch *ds = ps->ds; - struct mv88e6xxx_vtu_stu_entry vlan = { - .valid = true, - .vid = vid, - }; - int i, err; - - err = _mv88e6xxx_fid_new(ps, &vlan.fid); - if (err) - return err; - - /* exclude all ports except the CPU and DSA ports */ - for (i = 0; i < ps->info->num_ports; ++i) - vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) - ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED - : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; - - if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || - mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) { - struct mv88e6xxx_vtu_stu_entry vstp; - - /* Adding a VTU entry requires a valid STU entry. As VSTP is not - * implemented, only one STU entry is needed to cover all VTU - * entries. Thus, validate the SID 0. - */ - vlan.sid = 0; - err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp); - if (err) - return err; - - if (vstp.sid != vlan.sid || !vstp.valid) { - memset(&vstp, 0, sizeof(vstp)); - vstp.valid = true; - vstp.sid = vlan.sid; - - err = _mv88e6xxx_stu_loadpurge(ps, &vstp); - if (err) - return err; - } - } - - *entry = vlan; - return 0; -} - -static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid, - struct mv88e6xxx_vtu_stu_entry *entry, bool creat) -{ - int err; - - if (!vid) - return -EINVAL; - - err = _mv88e6xxx_vtu_vid_write(ps, vid - 1); - if (err) - return err; - - err = _mv88e6xxx_vtu_getnext(ps, entry); - if (err) - return err; - - if (entry->vid != vid || !entry->valid) { - if (!creat) - return -EOPNOTSUPP; - /* -ENOENT would've been more appropriate, but switchdev expects - * -EOPNOTSUPP to inform bridge about an eventual software VLAN. - */ - - err = _mv88e6xxx_vtu_new(ps, vid, entry); - } - - return err; -} - -static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, - u16 vid_begin, u16 vid_end) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_vtu_stu_entry vlan; - int i, err; - - if (!vid_begin) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1); - if (err) - goto unlock; - - do { - err = _mv88e6xxx_vtu_getnext(ps, &vlan); - if (err) - goto unlock; - - if (!vlan.valid) - break; - - if (vlan.vid > vid_end) - break; - - for (i = 0; i < ps->info->num_ports; ++i) { - if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) - continue; - - if (vlan.data[i] == - GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) - continue; - - if (ps->ports[i].bridge_dev == - ps->ports[port].bridge_dev) - break; /* same bridge, check next VLAN */ - - netdev_warn(ds->ports[port], - "hardware VLAN %d already used by %s\n", - vlan.vid, - netdev_name(ps->ports[i].bridge_dev)); - err = -EOPNOTSUPP; - goto unlock; - } - } while (vlan.vid < vid_end); - -unlock: - mutex_unlock(&ps->smi_mutex); - - return err; -} - -static const char * const mv88e6xxx_port_8021q_mode_names[] = { - [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", - [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", - [PORT_CONTROL_2_8021Q_CHECK] = "Check", - [PORT_CONTROL_2_8021Q_SECURE] = "Secure", -}; - -static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, - bool vlan_filtering) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : - PORT_CONTROL_2_8021Q_DISABLED; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2); - if (ret < 0) - goto unlock; - - old = ret & PORT_CONTROL_2_8021Q_MASK; - - if (new != old) { - ret &= ~PORT_CONTROL_2_8021Q_MASK; - ret |= new & PORT_CONTROL_2_8021Q_MASK; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2, - ret); - if (ret < 0) - goto unlock; - - netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n", - mv88e6xxx_port_8021q_mode_names[new], - mv88e6xxx_port_8021q_mode_names[old]); - } - - ret = 0; -unlock: - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan, - struct switchdev_trans *trans) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int err; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) - return -EOPNOTSUPP; - - /* If the requested port doesn't belong to the same bridge as the VLAN - * members, do not support it (yet) and fallback to software VLAN. - */ - err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, - vlan->vid_end); - if (err) - return err; - - /* We don't need any dynamic resource from the kernel (yet), - * so skip the prepare phase. - */ - return 0; -} - -static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port, - u16 vid, bool untagged) -{ - struct mv88e6xxx_vtu_stu_entry vlan; - int err; - - err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true); - if (err) - return err; - - vlan.data[port] = untagged ? - GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : - GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; - - return _mv88e6xxx_vtu_loadpurge(ps, &vlan); -} - -static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan, - struct switchdev_trans *trans) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; - bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; - u16 vid; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) - return; - - mutex_lock(&ps->smi_mutex); - - for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) - if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged)) - netdev_err(ds->ports[port], "failed to add VLAN %d%c\n", - vid, untagged ? 'u' : 't'); - - if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end)) - netdev_err(ds->ports[port], "failed to set PVID %d\n", - vlan->vid_end); - - mutex_unlock(&ps->smi_mutex); -} - -static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps, - int port, u16 vid) -{ - struct dsa_switch *ds = ps->ds; - struct mv88e6xxx_vtu_stu_entry vlan; - int i, err; - - err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); - if (err) - return err; - - /* Tell switchdev if this VLAN is handled in software */ - if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) - return -EOPNOTSUPP; - - vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; - - /* keep the VLAN unless all ports are excluded */ - vlan.valid = false; - for (i = 0; i < ps->info->num_ports; ++i) { - if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) - continue; - - if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { - vlan.valid = true; - break; - } - } - - err = _mv88e6xxx_vtu_loadpurge(ps, &vlan); - if (err) - return err; - - return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false); -} - -static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_vlan *vlan) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - u16 pvid, vid; - int err = 0; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); - if (err) - goto unlock; - - for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { - err = _mv88e6xxx_port_vlan_del(ps, port, vid); - if (err) - goto unlock; - - if (vid == pvid) { - err = _mv88e6xxx_port_pvid_set(ps, port, 0); - if (err) - goto unlock; - } - } - -unlock: - mutex_unlock(&ps->smi_mutex); - - return err; -} - -static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps, - const unsigned char *addr) -{ - int i, ret; - - for (i = 0; i < 3; i++) { - ret = _mv88e6xxx_reg_write( - ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, - (addr[i * 2] << 8) | addr[i * 2 + 1]); - if (ret < 0) - return ret; - } - - return 0; -} - -static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps, - unsigned char *addr) -{ - int i, ret; - - for (i = 0; i < 3; i++) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, - GLOBAL_ATU_MAC_01 + i); - if (ret < 0) - return ret; - addr[i * 2] = ret >> 8; - addr[i * 2 + 1] = ret & 0xff; - } - - return 0; -} - -static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps, - struct mv88e6xxx_atu_entry *entry) -{ - int ret; - - ret = _mv88e6xxx_atu_wait(ps); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_atu_mac_write(ps, entry->mac); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_atu_data_write(ps, entry); - if (ret < 0) - return ret; - - return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB); -} - -static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port, - const unsigned char *addr, u16 vid, - u8 state) -{ - struct mv88e6xxx_atu_entry entry = { 0 }; - struct mv88e6xxx_vtu_stu_entry vlan; - int err; - - /* Null VLAN ID corresponds to the port private database */ - if (vid == 0) - err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid); - else - err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); - if (err) - return err; - - entry.fid = vlan.fid; - entry.state = state; - ether_addr_copy(entry.mac, addr); - if (state != GLOBAL_ATU_DATA_STATE_UNUSED) { - entry.trunk = false; - entry.portv_trunkid = BIT(port); - } - - return _mv88e6xxx_atu_load(ps, &entry); -} - -static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_fdb *fdb, - struct switchdev_trans *trans) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) - return -EOPNOTSUPP; - - /* We don't need any dynamic resource from the kernel (yet), - * so skip the prepare phase. - */ - return 0; -} - -static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_fdb *fdb, - struct switchdev_trans *trans) -{ - int state = is_multicast_ether_addr(fdb->addr) ? - GLOBAL_ATU_DATA_STATE_MC_STATIC : - GLOBAL_ATU_DATA_STATE_UC_STATIC; - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) - return; - - mutex_lock(&ps->smi_mutex); - if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state)) - netdev_err(ds->ports[port], "failed to load MAC address\n"); - mutex_unlock(&ps->smi_mutex); -} - -static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, - const struct switchdev_obj_port_fdb *fdb) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, - GLOBAL_ATU_DATA_STATE_UNUSED); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid, - struct mv88e6xxx_atu_entry *entry) -{ - struct mv88e6xxx_atu_entry next = { 0 }; - int ret; - - next.fid = fid; - - ret = _mv88e6xxx_atu_wait(ps); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_atu_mac_read(ps, next.mac); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA); - if (ret < 0) - return ret; - - next.state = ret & GLOBAL_ATU_DATA_STATE_MASK; - if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { - unsigned int mask, shift; - - if (ret & GLOBAL_ATU_DATA_TRUNK) { - next.trunk = true; - mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; - shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; - } else { - next.trunk = false; - mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; - shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; - } - - next.portv_trunkid = (ret & mask) >> shift; - } - - *entry = next; - return 0; -} - -static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps, - u16 fid, u16 vid, int port, - struct switchdev_obj_port_fdb *fdb, - int (*cb)(struct switchdev_obj *obj)) -{ - struct mv88e6xxx_atu_entry addr = { - .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, - }; - int err; - - err = _mv88e6xxx_atu_mac_write(ps, addr.mac); - if (err) - return err; - - do { - err = _mv88e6xxx_atu_getnext(ps, fid, &addr); - if (err) - break; - - if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) - break; - - if (!addr.trunk && addr.portv_trunkid & BIT(port)) { - bool is_static = addr.state == - (is_multicast_ether_addr(addr.mac) ? - GLOBAL_ATU_DATA_STATE_MC_STATIC : - GLOBAL_ATU_DATA_STATE_UC_STATIC); - - fdb->vid = vid; - ether_addr_copy(fdb->addr, addr.mac); - fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; - - err = cb(&fdb->obj); - if (err) - break; - } - } while (!is_broadcast_ether_addr(addr.mac)); - - return err; -} - -static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, - struct switchdev_obj_port_fdb *fdb, - int (*cb)(struct switchdev_obj *obj)) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct mv88e6xxx_vtu_stu_entry vlan = { - .vid = GLOBAL_VTU_VID_MASK, /* all ones */ - }; - u16 fid; - int err; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - /* Dump port's default Filtering Information Database (VLAN ID 0) */ - err = _mv88e6xxx_port_fid_get(ps, port, &fid); - if (err) - goto unlock; - - err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb); - if (err) - goto unlock; - - /* Dump VLANs' Filtering Information Databases */ - err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid); - if (err) - goto unlock; - - do { - err = _mv88e6xxx_vtu_getnext(ps, &vlan); - if (err) - break; - - if (!vlan.valid) - break; - - err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port, - fdb, cb); - if (err) - break; - } while (vlan.vid < GLOBAL_VTU_VID_MASK); - -unlock: - mutex_unlock(&ps->smi_mutex); - - return err; -} - -static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, - struct net_device *bridge) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int i, err = 0; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) - return -EOPNOTSUPP; - - mutex_lock(&ps->smi_mutex); - - /* Assign the bridge and remap each port's VLANTable */ - ps->ports[port].bridge_dev = bridge; - - for (i = 0; i < ps->info->num_ports; ++i) { - if (ps->ports[i].bridge_dev == bridge) { - err = _mv88e6xxx_port_based_vlan_map(ps, i); - if (err) - break; - } - } - - mutex_unlock(&ps->smi_mutex); - - return err; -} - -static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - struct net_device *bridge = ps->ports[port].bridge_dev; - int i; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) - return; - - mutex_lock(&ps->smi_mutex); - - /* Unassign the bridge and remap each port's VLANTable */ - ps->ports[port].bridge_dev = NULL; - - for (i = 0; i < ps->info->num_ports; ++i) - if (i == port || ps->ports[i].bridge_dev == bridge) - if (_mv88e6xxx_port_based_vlan_map(ps, i)) - netdev_warn(ds->ports[i], "failed to remap\n"); - - mutex_unlock(&ps->smi_mutex); -} - -static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps, - int port, int page, int reg, int val) -{ - int ret; - - ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page); - if (ret < 0) - goto restore_page_0; - - ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val); -restore_page_0: - _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0); - - return ret; -} - -static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps, - int port, int page, int reg) -{ - int ret; - - ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page); - if (ret < 0) - goto restore_page_0; - - ret = _mv88e6xxx_phy_read_indirect(ps, port, reg); -restore_page_0: - _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0); - - return ret; -} - -static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps) -{ - bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE); - u16 is_reset = (ppu_active ? 0x8800 : 0xc800); - struct gpio_desc *gpiod = ps->reset; - unsigned long timeout; - int ret; - int i; - - /* Set all ports to the disabled state. */ - for (i = 0; i < ps->info->num_ports; i++) { - ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL); - if (ret < 0) - return ret; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL, - ret & 0xfffc); - if (ret) - return ret; - } - - /* Wait for transmit queues to drain. */ - usleep_range(2000, 4000); - - /* If there is a gpio connected to the reset pin, toggle it */ - if (gpiod) { - gpiod_set_value_cansleep(gpiod, 1); - usleep_range(10000, 20000); - gpiod_set_value_cansleep(gpiod, 0); - usleep_range(10000, 20000); - } - - /* Reset the switch. Keep the PPU active if requested. The PPU - * needs to be active to support indirect phy register access - * through global registers 0x18 and 0x19. - */ - if (ppu_active) - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000); - else - ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400); - if (ret) - return ret; - - /* Wait up to one second for reset to complete. */ - timeout = jiffies + 1 * HZ; - while (time_before(jiffies, timeout)) { - ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00); - if (ret < 0) - return ret; - - if ((ret & is_reset) == is_reset) - break; - usleep_range(1000, 2000); - } - if (time_after(jiffies, timeout)) - ret = -ETIMEDOUT; - else - ret = 0; - - return ret; -} - -static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps) -{ - int ret; - - ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES, - MII_BMCR); - if (ret < 0) - return ret; - - if (ret & BMCR_PDOWN) { - ret &= ~BMCR_PDOWN; - ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES, - PAGE_FIBER_SERDES, MII_BMCR, - ret); - } - - return ret; -} - -static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port) -{ - struct dsa_switch *ds = ps->ds; - int ret; - u16 reg; - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || - mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) { - /* MAC Forcing register: don't force link, speed, - * duplex or flow control state to any particular - * values on physical ports, but force the CPU port - * and all DSA ports to their maximum bandwidth and - * full duplex. - */ - reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); - if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { - reg &= ~PORT_PCS_CTRL_UNFORCED; - reg |= PORT_PCS_CTRL_FORCE_LINK | - PORT_PCS_CTRL_LINK_UP | - PORT_PCS_CTRL_DUPLEX_FULL | - PORT_PCS_CTRL_FORCE_DUPLEX; - if (mv88e6xxx_6065_family(ps)) - reg |= PORT_PCS_CTRL_100; - else - reg |= PORT_PCS_CTRL_1000; - } else { - reg |= PORT_PCS_CTRL_UNFORCED; - } - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_PCS_CTRL, reg); - if (ret) - return ret; - } - - /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, - * disable Header mode, enable IGMP/MLD snooping, disable VLAN - * tunneling, determine priority by looking at 802.1p and IP - * priority fields (IP prio has precedence), and set STP state - * to Forwarding. - * - * If this is the CPU link, use DSA or EDSA tagging depending - * on which tagging mode was configured. - * - * If this is a link to another switch, use DSA tagging mode. - * - * If this is the upstream port for this switch, enable - * forwarding of unknown unicasts and multicasts. - */ - reg = 0; - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || - mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) - reg = PORT_CONTROL_IGMP_MLD_SNOOP | - PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | - PORT_CONTROL_STATE_FORWARDING; - if (dsa_is_cpu_port(ds, port)) { - if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) - reg |= PORT_CONTROL_DSA_TAG; - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6320_family(ps)) { - if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) - reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA; - else - reg |= PORT_CONTROL_FRAME_MODE_DSA; - reg |= PORT_CONTROL_FORWARD_UNKNOWN | - PORT_CONTROL_FORWARD_UNKNOWN_MC; - } - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || - mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) { - if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA) - reg |= PORT_CONTROL_EGRESS_ADD_TAG; - } - } - if (dsa_is_dsa_port(ds, port)) { - if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) - reg |= PORT_CONTROL_DSA_TAG; - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6320_family(ps)) { - reg |= PORT_CONTROL_FRAME_MODE_DSA; - } - - if (port == dsa_upstream_port(ds)) - reg |= PORT_CONTROL_FORWARD_UNKNOWN | - PORT_CONTROL_FORWARD_UNKNOWN_MC; - } - if (reg) { - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_CONTROL, reg); - if (ret) - return ret; - } - - /* If this port is connected to a SerDes, make sure the SerDes is not - * powered down. - */ - if (mv88e6xxx_6352_family(ps)) { - ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); - if (ret < 0) - return ret; - ret &= PORT_STATUS_CMODE_MASK; - if ((ret == PORT_STATUS_CMODE_100BASE_X) || - (ret == PORT_STATUS_CMODE_1000BASE_X) || - (ret == PORT_STATUS_CMODE_SGMII)) { - ret = mv88e6xxx_power_on_serdes(ps); - if (ret < 0) - return ret; - } - } - - /* Port Control 2: don't force a good FCS, set the maximum frame size to - * 10240 bytes, disable 802.1q tags checking, don't discard tagged or - * untagged frames on this port, do a destination address lookup on all - * received packets as usual, disable ARP mirroring and don't send a - * copy of all transmitted/received frames on this port to the CPU. - */ - reg = 0; - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) || - mv88e6xxx_6185_family(ps)) - reg = PORT_CONTROL_2_MAP_DA; - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps)) - reg |= PORT_CONTROL_2_JUMBO_10240; - - if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) { - /* Set the upstream port this port should use */ - reg |= dsa_upstream_port(ds); - /* enable forwarding of unknown multicast addresses to - * the upstream port - */ - if (port == dsa_upstream_port(ds)) - reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; - } - - reg |= PORT_CONTROL_2_8021Q_DISABLED; - - if (reg) { - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_CONTROL_2, reg); - if (ret) - return ret; - } - - /* Port Association Vector: when learning source addresses - * of packets, add the address to the address database using - * a port bitmap that has only the bit for this port set and - * the other bits clear. - */ - reg = 1 << port; - /* Disable learning for CPU port */ - if (dsa_is_cpu_port(ds, port)) - reg = 0; - - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg); - if (ret) - return ret; - - /* Egress rate control 2: disable egress rate control. */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2, - 0x0000); - if (ret) - return ret; - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6320_family(ps)) { - /* Do not limit the period of time that this port can - * be paused for by the remote end or the period of - * time that this port can pause the remote end. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_PAUSE_CTRL, 0x0000); - if (ret) - return ret; - - /* Port ATU control: disable limiting the number of - * address database entries that this port is allowed - * to use. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_ATU_CONTROL, 0x0000); - /* Priority Override: disable DA, SA and VTU priority - * override. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_PRI_OVERRIDE, 0x0000); - if (ret) - return ret; - - /* Port Ethertype: use the Ethertype DSA Ethertype - * value. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_ETH_TYPE, ETH_P_EDSA); - if (ret) - return ret; - /* Tag Remap: use an identity 802.1p prio -> switch - * prio mapping. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_TAG_REGMAP_0123, 0x3210); - if (ret) - return ret; - - /* Tag Remap 2: use an identity 802.1p prio -> switch - * prio mapping. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_TAG_REGMAP_4567, 0x7654); - if (ret) - return ret; - } - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || - mv88e6xxx_6320_family(ps)) { - /* Rate Control: disable ingress rate limiting. */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), - PORT_RATE_CONTROL, 0x0001); - if (ret) - return ret; - } - - /* Port Control 1: disable trunking, disable sending - * learning messages to this port. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000); - if (ret) - return ret; - - /* Port based VLAN map: give each port the same default address - * database, and allow bidirectional communication between the - * CPU and DSA port(s), and the other ports. - */ - ret = _mv88e6xxx_port_fid_set(ps, port, 0); - if (ret) - return ret; - - ret = _mv88e6xxx_port_based_vlan_map(ps, port); - if (ret) - return ret; - - /* Default VLAN ID and priority: don't set a default VLAN - * ID, and set the default packet priority to zero. - */ - ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN, - 0x0000); - if (ret) - return ret; - - return 0; -} - -static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps) -{ - struct dsa_switch *ds = ps->ds; - u32 upstream_port = dsa_upstream_port(ds); - u16 reg; - int err; - int i; - - /* Enable the PHY Polling Unit if present, don't discard any packets, - * and mask all interrupt sources. - */ - reg = 0; - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) || - mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE)) - reg |= GLOBAL_CONTROL_PPU_ENABLE; - - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg); - if (err) - return err; - - /* Configure the upstream port, and configure it as the port to which - * ingress and egress and ARP monitor frames are to be sent. - */ - reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | - upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | - upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); - if (err) - return err; - - /* Disable remote management, and set the switch's DSA device number. */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2, - GLOBAL_CONTROL_2_MULTIPLE_CASCADE | - (ds->index & 0x1f)); - if (err) - return err; - - /* Set the default address aging time to 5 minutes, and - * enable address learn messages to be sent to all message - * ports. - */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, - 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); - if (err) - return err; - - /* Configure the IP ToS mapping registers. */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); - if (err) - return err; - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); - if (err) - return err; - - /* Configure the IEEE 802.1p priority mapping register. */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); - if (err) - return err; - - /* Send all frames with destination addresses matching - * 01:80:c2:00:00:0x to the CPU port. - */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); - if (err) - return err; - - /* Ignore removed tag data on doubly tagged packets, disable - * flow control messages, force flow control priority to the - * highest, and send all special multicast frames to the CPU - * port at the highest priority. - */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, - 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | - GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); - if (err) - return err; - - /* Program the DSA routing table. */ - for (i = 0; i < 32; i++) { - int nexthop = 0x1f; - - if (ps->ds->cd->rtable && - i != ps->ds->index && i < ps->ds->dst->pd->nr_chips) - nexthop = ps->ds->cd->rtable[i] & 0x1f; - - err = _mv88e6xxx_reg_write( - ps, REG_GLOBAL2, - GLOBAL2_DEVICE_MAPPING, - GLOBAL2_DEVICE_MAPPING_UPDATE | - (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop); - if (err) - return err; - } - - /* Clear all trunk masks. */ - for (i = 0; i < 8; i++) { - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, - 0x8000 | - (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | - ((1 << ps->info->num_ports) - 1)); - if (err) - return err; - } - - /* Clear all trunk mappings. */ - for (i = 0; i < 16; i++) { - err = _mv88e6xxx_reg_write( - ps, REG_GLOBAL2, - GLOBAL2_TRUNK_MAPPING, - GLOBAL2_TRUNK_MAPPING_UPDATE | - (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); - if (err) - return err; - } - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6320_family(ps)) { - /* Send all frames with destination addresses matching - * 01:80:c2:00:00:2x to the CPU port. - */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, - GLOBAL2_MGMT_EN_2X, 0xffff); - if (err) - return err; - - /* Initialise cross-chip port VLAN table to reset - * defaults. - */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, - GLOBAL2_PVT_ADDR, 0x9000); - if (err) - return err; - - /* Clear the priority override table. */ - for (i = 0; i < 16; i++) { - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, - GLOBAL2_PRIO_OVERRIDE, - 0x8000 | (i << 8)); - if (err) - return err; - } - } - - if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || - mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || - mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || - mv88e6xxx_6320_family(ps)) { - /* Disable ingress rate limiting by resetting all - * ingress rate limit registers to their initial - * state. - */ - for (i = 0; i < ps->info->num_ports; i++) { - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, - GLOBAL2_INGRESS_OP, - 0x9000 | (i << 8)); - if (err) - return err; - } - } - - /* Clear the statistics counters for all ports */ - err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, - GLOBAL_STATS_OP_FLUSH_ALL); - if (err) - return err; - - /* Wait for the flush to complete. */ - err = _mv88e6xxx_stats_wait(ps); - if (err) - return err; - - /* Clear all ATU entries */ - err = _mv88e6xxx_atu_flush(ps, 0, true); - if (err) - return err; - - /* Clear all the VTU and STU entries */ - err = _mv88e6xxx_vtu_stu_flush(ps); - if (err < 0) - return err; - - return err; -} - -static int mv88e6xxx_setup(struct dsa_switch *ds) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int err; - int i; - - ps->ds = ds; - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) - mutex_init(&ps->eeprom_mutex); - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) - mv88e6xxx_ppu_state_init(ps); - - mutex_lock(&ps->smi_mutex); - - err = mv88e6xxx_switch_reset(ps); - if (err) - goto unlock; - - err = mv88e6xxx_setup_global(ps); - if (err) - goto unlock; - - for (i = 0; i < ps->info->num_ports; i++) { - err = mv88e6xxx_setup_port(ps, i); - if (err) - goto unlock; - } - -unlock: - mutex_unlock(&ps->smi_mutex); - - return err; -} - -int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_phy_page_read(ps, port, page, reg); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, - int reg, int val) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - - mutex_lock(&ps->smi_mutex); - ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val); - mutex_unlock(&ps->smi_mutex); - - return ret; -} - -static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps, - int port) -{ - if (port >= 0 && port < ps->info->num_ports) - return port; - return -EINVAL; -} - -static int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int addr = mv88e6xxx_port_to_phy_addr(ps, port); - int ret; - - if (addr < 0) - return 0xffff; - - mutex_lock(&ps->smi_mutex); - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) - ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum); - else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) - ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum); - else - ret = _mv88e6xxx_phy_read(ps, addr, regnum); - - mutex_unlock(&ps->smi_mutex); - return ret; -} - -static int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, - u16 val) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int addr = mv88e6xxx_port_to_phy_addr(ps, port); - int ret; - - if (addr < 0) - return 0xffff; - - mutex_lock(&ps->smi_mutex); - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) - ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val); - else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) - ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val); - else - ret = _mv88e6xxx_phy_write(ps, addr, regnum, val); - - mutex_unlock(&ps->smi_mutex); - return ret; -} - -#ifdef CONFIG_NET_DSA_HWMON - -static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int ret; - int val; - - *temp = 0; - - mutex_lock(&ps->smi_mutex); - - ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6); - if (ret < 0) - goto error; - - /* Enable temperature sensor */ - ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a); - if (ret < 0) - goto error; - - ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5)); - if (ret < 0) - goto error; - - /* Wait for temperature to stabilize */ - usleep_range(10000, 12000); - - val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a); - if (val < 0) { - ret = val; - goto error; - } - - /* Disable temperature sensor */ - ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5)); - if (ret < 0) - goto error; - - *temp = ((val & 0x1f) - 5) * 5; - -error: - _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0); - mutex_unlock(&ps->smi_mutex); - return ret; -} - -static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; - int ret; - - *temp = 0; - - ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27); - if (ret < 0) - return ret; - - *temp = (ret & 0xff) - 25; - - return 0; -} - -static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP)) - return -EOPNOTSUPP; - - if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) - return mv88e63xx_get_temp(ds, temp); - - return mv88e61xx_get_temp(ds, temp); -} - -static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) - return -EOPNOTSUPP; - - *temp = 0; - - ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); - if (ret < 0) - return ret; - - *temp = (((ret >> 8) & 0x1f) * 5) - 25; - - return 0; -} - -static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) - return -EOPNOTSUPP; - - ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); - if (ret < 0) - return ret; - temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); - return mv88e6xxx_phy_page_write(ds, phy, 6, 26, - (ret & 0xe0ff) | (temp << 8)); -} - -static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) -{ - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; - int ret; - - if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) - return -EOPNOTSUPP; - - *alarm = false; - - ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26); - if (ret < 0) - return ret; - - *alarm = !!(ret & 0x40); - - return 0; -} -#endif /* CONFIG_NET_DSA_HWMON */ - -static const struct mv88e6xxx_info mv88e6xxx_table[] = { - [MV88E6085] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, - .family = MV88E6XXX_FAMILY_6097, - .name = "Marvell 88E6085", - .num_databases = 4096, - .num_ports = 10, - .flags = MV88E6XXX_FLAGS_FAMILY_6097, - }, - - [MV88E6095] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, - .family = MV88E6XXX_FAMILY_6095, - .name = "Marvell 88E6095/88E6095F", - .num_databases = 256, - .num_ports = 11, - .flags = MV88E6XXX_FLAGS_FAMILY_6095, - }, - - [MV88E6123] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, - .family = MV88E6XXX_FAMILY_6165, - .name = "Marvell 88E6123", - .num_databases = 4096, - .num_ports = 3, - .flags = MV88E6XXX_FLAGS_FAMILY_6165, - }, - - [MV88E6131] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, - .family = MV88E6XXX_FAMILY_6185, - .name = "Marvell 88E6131", - .num_databases = 256, - .num_ports = 8, - .flags = MV88E6XXX_FLAGS_FAMILY_6185, - }, - - [MV88E6161] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, - .family = MV88E6XXX_FAMILY_6165, - .name = "Marvell 88E6161", - .num_databases = 4096, - .num_ports = 6, - .flags = MV88E6XXX_FLAGS_FAMILY_6165, - }, - - [MV88E6165] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, - .family = MV88E6XXX_FAMILY_6165, - .name = "Marvell 88E6165", - .num_databases = 4096, - .num_ports = 6, - .flags = MV88E6XXX_FLAGS_FAMILY_6165, - }, - - [MV88E6171] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, - .family = MV88E6XXX_FAMILY_6351, - .name = "Marvell 88E6171", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6351, - }, - - [MV88E6172] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, - .family = MV88E6XXX_FAMILY_6352, - .name = "Marvell 88E6172", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6352, - }, - - [MV88E6175] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, - .family = MV88E6XXX_FAMILY_6351, - .name = "Marvell 88E6175", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6351, - }, - - [MV88E6176] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, - .family = MV88E6XXX_FAMILY_6352, - .name = "Marvell 88E6176", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6352, - }, - - [MV88E6185] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, - .family = MV88E6XXX_FAMILY_6185, - .name = "Marvell 88E6185", - .num_databases = 256, - .num_ports = 10, - .flags = MV88E6XXX_FLAGS_FAMILY_6185, - }, - - [MV88E6240] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, - .family = MV88E6XXX_FAMILY_6352, - .name = "Marvell 88E6240", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6352, - }, - - [MV88E6320] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, - .family = MV88E6XXX_FAMILY_6320, - .name = "Marvell 88E6320", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6320, - }, - - [MV88E6321] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, - .family = MV88E6XXX_FAMILY_6320, - .name = "Marvell 88E6321", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6320, - }, - - [MV88E6350] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, - .family = MV88E6XXX_FAMILY_6351, - .name = "Marvell 88E6350", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6351, - }, - - [MV88E6351] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, - .family = MV88E6XXX_FAMILY_6351, - .name = "Marvell 88E6351", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6351, - }, - - [MV88E6352] = { - .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, - .family = MV88E6XXX_FAMILY_6352, - .name = "Marvell 88E6352", - .num_databases = 4096, - .num_ports = 7, - .flags = MV88E6XXX_FLAGS_FAMILY_6352, - }, -}; - -static const struct mv88e6xxx_info * -mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table, - unsigned int num) -{ - int i; - - for (i = 0; i < num; ++i) - if (table[i].prod_num == prod_num) - return &table[i]; - - return NULL; -} - -static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, - struct device *host_dev, int sw_addr, - void **priv) -{ - const struct mv88e6xxx_info *info; - struct mv88e6xxx_priv_state *ps; - struct mii_bus *bus; - const char *name; - int id, prod_num, rev; - - bus = dsa_host_dev_to_mii_bus(host_dev); - if (!bus) - return NULL; - - id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID); - if (id < 0) - return NULL; - - prod_num = (id & 0xfff0) >> 4; - rev = id & 0x000f; - - info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table, - ARRAY_SIZE(mv88e6xxx_table)); - if (!info) - return NULL; - - name = info->name; - - ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL); - if (!ps) - return NULL; - - ps->bus = bus; - ps->sw_addr = sw_addr; - ps->info = info; - mutex_init(&ps->smi_mutex); - - *priv = ps; - - dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n", - prod_num, name, rev); - - return name; -} - -struct dsa_switch_driver mv88e6xxx_switch_driver = { - .tag_protocol = DSA_TAG_PROTO_EDSA, - .probe = mv88e6xxx_drv_probe, - .setup = mv88e6xxx_setup, - .set_addr = mv88e6xxx_set_addr, - .phy_read = mv88e6xxx_phy_read, - .phy_write = mv88e6xxx_phy_write, - .adjust_link = mv88e6xxx_adjust_link, - .get_strings = mv88e6xxx_get_strings, - .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, - .get_sset_count = mv88e6xxx_get_sset_count, - .set_eee = mv88e6xxx_set_eee, - .get_eee = mv88e6xxx_get_eee, -#ifdef CONFIG_NET_DSA_HWMON - .get_temp = mv88e6xxx_get_temp, - .get_temp_limit = mv88e6xxx_get_temp_limit, - .set_temp_limit = mv88e6xxx_set_temp_limit, - .get_temp_alarm = mv88e6xxx_get_temp_alarm, -#endif - .get_eeprom_len = mv88e6xxx_get_eeprom_len, - .get_eeprom = mv88e6xxx_get_eeprom, - .set_eeprom = mv88e6xxx_set_eeprom, - .get_regs_len = mv88e6xxx_get_regs_len, - .get_regs = mv88e6xxx_get_regs, - .port_bridge_join = mv88e6xxx_port_bridge_join, - .port_bridge_leave = mv88e6xxx_port_bridge_leave, - .port_stp_state_set = mv88e6xxx_port_stp_state_set, - .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, - .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, - .port_vlan_add = mv88e6xxx_port_vlan_add, - .port_vlan_del = mv88e6xxx_port_vlan_del, - .port_vlan_dump = mv88e6xxx_port_vlan_dump, - .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, - .port_fdb_add = mv88e6xxx_port_fdb_add, - .port_fdb_del = mv88e6xxx_port_fdb_del, - .port_fdb_dump = mv88e6xxx_port_fdb_dump, -}; - -int mv88e6xxx_probe(struct mdio_device *mdiodev) -{ - struct device *dev = &mdiodev->dev; - struct device_node *np = dev->of_node; - struct mv88e6xxx_priv_state *ps; - int id, prod_num, rev; - struct dsa_switch *ds; - u32 eeprom_len; - int err; - - ds = devm_kzalloc(dev, sizeof(*ds) + sizeof(*ps), GFP_KERNEL); - if (!ds) - return -ENOMEM; - - ps = (struct mv88e6xxx_priv_state *)(ds + 1); - ds->priv = ps; - ds->dev = dev; - ps->dev = dev; - ps->ds = ds; - ps->bus = mdiodev->bus; - ps->sw_addr = mdiodev->addr; - mutex_init(&ps->smi_mutex); - - get_device(&ps->bus->dev); - - ds->drv = &mv88e6xxx_switch_driver; - - id = mv88e6xxx_reg_read(ps, REG_PORT(0), PORT_SWITCH_ID); - if (id < 0) - return id; - - prod_num = (id & 0xfff0) >> 4; - rev = id & 0x000f; - - ps->info = mv88e6xxx_lookup_info(prod_num, mv88e6xxx_table, - ARRAY_SIZE(mv88e6xxx_table)); - if (!ps->info) - return -ENODEV; - - ps->reset = devm_gpiod_get(&mdiodev->dev, "reset", GPIOD_ASIS); - if (IS_ERR(ps->reset)) { - err = PTR_ERR(ps->reset); - if (err == -ENOENT) { - /* Optional, so not an error */ - ps->reset = NULL; - } else { - return err; - } - } - - if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) && - !of_property_read_u32(np, "eeprom-length", &eeprom_len)) - ps->eeprom_len = eeprom_len; - - dev_set_drvdata(dev, ds); - - dev_info(dev, "switch 0x%x probed: %s, revision %u\n", - prod_num, ps->info->name, rev); - - return 0; -} - -static void mv88e6xxx_remove(struct mdio_device *mdiodev) -{ - struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); - struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); - - put_device(&ps->bus->dev); -} - -static const struct of_device_id mv88e6xxx_of_match[] = { - { .compatible = "marvell,mv88e6085" }, - { /* sentinel */ }, -}; - -MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); - -static struct mdio_driver mv88e6xxx_driver = { - .probe = mv88e6xxx_probe, - .remove = mv88e6xxx_remove, - .mdiodrv.driver = { - .name = "mv88e6085", - .of_match_table = mv88e6xxx_of_match, - }, -}; - -static int __init mv88e6xxx_init(void) -{ - register_switch_driver(&mv88e6xxx_switch_driver); - return mdio_driver_register(&mv88e6xxx_driver); -} -module_init(mv88e6xxx_init); - -static void __exit mv88e6xxx_cleanup(void) -{ - mdio_driver_unregister(&mv88e6xxx_driver); - unregister_switch_driver(&mv88e6xxx_switch_driver); -} -module_exit(mv88e6xxx_cleanup); - -MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); -MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); -MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx.h deleted file mode 100644 index 36d0e1504..000000000 --- a/drivers/net/dsa/mv88e6xxx.h +++ /dev/null @@ -1,624 +0,0 @@ -/* - * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support - * Copyright (c) 2008 Marvell Semiconductor - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __MV88E6XXX_H -#define __MV88E6XXX_H - -#include <linux/if_vlan.h> -#include <linux/gpio/consumer.h> - -#ifndef UINT64_MAX -#define UINT64_MAX (u64)(~((u64)0)) -#endif - -#define SMI_CMD 0x00 -#define SMI_CMD_BUSY BIT(15) -#define SMI_CMD_CLAUSE_22 BIT(12) -#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) -#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) -#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) -#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) -#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) -#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) -#define SMI_DATA 0x01 - -/* Fiber/SERDES Registers are located at SMI address F, page 1 */ -#define REG_FIBER_SERDES 0x0f -#define PAGE_FIBER_SERDES 0x01 - -#define REG_PORT(p) (0x10 + (p)) -#define PORT_STATUS 0x00 -#define PORT_STATUS_PAUSE_EN BIT(15) -#define PORT_STATUS_MY_PAUSE BIT(14) -#define PORT_STATUS_HD_FLOW BIT(13) -#define PORT_STATUS_PHY_DETECT BIT(12) -#define PORT_STATUS_LINK BIT(11) -#define PORT_STATUS_DUPLEX BIT(10) -#define PORT_STATUS_SPEED_MASK 0x0300 -#define PORT_STATUS_SPEED_10 0x0000 -#define PORT_STATUS_SPEED_100 0x0100 -#define PORT_STATUS_SPEED_1000 0x0200 -#define PORT_STATUS_EEE BIT(6) /* 6352 */ -#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ -#define PORT_STATUS_MGMII BIT(6) /* 6185 */ -#define PORT_STATUS_TX_PAUSED BIT(5) -#define PORT_STATUS_FLOW_CTRL BIT(4) -#define PORT_STATUS_CMODE_MASK 0x0f -#define PORT_STATUS_CMODE_100BASE_X 0x8 -#define PORT_STATUS_CMODE_1000BASE_X 0x9 -#define PORT_STATUS_CMODE_SGMII 0xa -#define PORT_PCS_CTRL 0x01 -#define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) -#define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) -#define PORT_PCS_CTRL_FC BIT(7) -#define PORT_PCS_CTRL_FORCE_FC BIT(6) -#define PORT_PCS_CTRL_LINK_UP BIT(5) -#define PORT_PCS_CTRL_FORCE_LINK BIT(4) -#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) -#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) -#define PORT_PCS_CTRL_10 0x00 -#define PORT_PCS_CTRL_100 0x01 -#define PORT_PCS_CTRL_1000 0x02 -#define PORT_PCS_CTRL_UNFORCED 0x03 -#define PORT_PAUSE_CTRL 0x02 -#define PORT_SWITCH_ID 0x03 -#define PORT_SWITCH_ID_PROD_NUM_6085 0x04a -#define PORT_SWITCH_ID_PROD_NUM_6095 0x095 -#define PORT_SWITCH_ID_PROD_NUM_6131 0x106 -#define PORT_SWITCH_ID_PROD_NUM_6320 0x115 -#define PORT_SWITCH_ID_PROD_NUM_6123 0x121 -#define PORT_SWITCH_ID_PROD_NUM_6161 0x161 -#define PORT_SWITCH_ID_PROD_NUM_6165 0x165 -#define PORT_SWITCH_ID_PROD_NUM_6171 0x171 -#define PORT_SWITCH_ID_PROD_NUM_6172 0x172 -#define PORT_SWITCH_ID_PROD_NUM_6175 0x175 -#define PORT_SWITCH_ID_PROD_NUM_6176 0x176 -#define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7 -#define PORT_SWITCH_ID_PROD_NUM_6240 0x240 -#define PORT_SWITCH_ID_PROD_NUM_6321 0x310 -#define PORT_SWITCH_ID_PROD_NUM_6352 0x352 -#define PORT_SWITCH_ID_PROD_NUM_6350 0x371 -#define PORT_SWITCH_ID_PROD_NUM_6351 0x375 -#define PORT_CONTROL 0x04 -#define PORT_CONTROL_USE_CORE_TAG BIT(15) -#define PORT_CONTROL_DROP_ON_LOCK BIT(14) -#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) -#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) -#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) -#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) -#define PORT_CONTROL_HEADER BIT(11) -#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) -#define PORT_CONTROL_DOUBLE_TAG BIT(9) -#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) -#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) -#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) -#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) -#define PORT_CONTROL_DSA_TAG BIT(8) -#define PORT_CONTROL_VLAN_TUNNEL BIT(7) -#define PORT_CONTROL_TAG_IF_BOTH BIT(6) -#define PORT_CONTROL_USE_IP BIT(5) -#define PORT_CONTROL_USE_TAG BIT(4) -#define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) -#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) -#define PORT_CONTROL_STATE_MASK 0x03 -#define PORT_CONTROL_STATE_DISABLED 0x00 -#define PORT_CONTROL_STATE_BLOCKING 0x01 -#define PORT_CONTROL_STATE_LEARNING 0x02 -#define PORT_CONTROL_STATE_FORWARDING 0x03 -#define PORT_CONTROL_1 0x05 -#define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) -#define PORT_BASE_VLAN 0x06 -#define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) -#define PORT_DEFAULT_VLAN 0x07 -#define PORT_DEFAULT_VLAN_MASK 0xfff -#define PORT_CONTROL_2 0x08 -#define PORT_CONTROL_2_IGNORE_FCS BIT(15) -#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) -#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) -#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) -#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) -#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) -#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) -#define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) -#define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) -#define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) -#define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) -#define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) -#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) -#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) -#define PORT_CONTROL_2_MAP_DA BIT(7) -#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) -#define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) -#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) -#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) -#define PORT_RATE_CONTROL 0x09 -#define PORT_RATE_CONTROL_2 0x0a -#define PORT_ASSOC_VECTOR 0x0b -#define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) -#define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) -#define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) -#define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) -#define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) -#define PORT_ATU_CONTROL 0x0c -#define PORT_PRI_OVERRIDE 0x0d -#define PORT_ETH_TYPE 0x0f -#define PORT_IN_DISCARD_LO 0x10 -#define PORT_IN_DISCARD_HI 0x11 -#define PORT_IN_FILTERED 0x12 -#define PORT_OUT_FILTERED 0x13 -#define PORT_TAG_REGMAP_0123 0x18 -#define PORT_TAG_REGMAP_4567 0x19 - -#define REG_GLOBAL 0x1b -#define GLOBAL_STATUS 0x00 -#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ -/* Two bits for 6165, 6185 etc */ -#define GLOBAL_STATUS_PPU_MASK (0x3 << 14) -#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) -#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) -#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) -#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) -#define GLOBAL_MAC_01 0x01 -#define GLOBAL_MAC_23 0x02 -#define GLOBAL_MAC_45 0x03 -#define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */ -#define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */ -#define GLOBAL_VTU_FID_MASK 0xfff -#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ -#define GLOBAL_VTU_SID_MASK 0x3f -#define GLOBAL_CONTROL 0x04 -#define GLOBAL_CONTROL_SW_RESET BIT(15) -#define GLOBAL_CONTROL_PPU_ENABLE BIT(14) -#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ -#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ -#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ -#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ -#define GLOBAL_CONTROL_DEVICE_EN BIT(7) -#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) -#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) -#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) -#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) -#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) -#define GLOBAL_CONTROL_TCAM_EN BIT(1) -#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) -#define GLOBAL_VTU_OP 0x05 -#define GLOBAL_VTU_OP_BUSY BIT(15) -#define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) -#define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) -#define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) -#define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) -#define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) -#define GLOBAL_VTU_VID 0x06 -#define GLOBAL_VTU_VID_MASK 0xfff -#define GLOBAL_VTU_VID_VALID BIT(12) -#define GLOBAL_VTU_DATA_0_3 0x07 -#define GLOBAL_VTU_DATA_4_7 0x08 -#define GLOBAL_VTU_DATA_8_11 0x09 -#define GLOBAL_VTU_STU_DATA_MASK 0x03 -#define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 -#define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 -#define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 -#define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 -#define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 -#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 -#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 -#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 -#define GLOBAL_ATU_CONTROL 0x0a -#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) -#define GLOBAL_ATU_OP 0x0b -#define GLOBAL_ATU_OP_BUSY BIT(15) -#define GLOBAL_ATU_OP_NOP (0 << 12) -#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) -#define GLOBAL_ATU_DATA 0x0c -#define GLOBAL_ATU_DATA_TRUNK BIT(15) -#define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 -#define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 -#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 -#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 -#define GLOBAL_ATU_DATA_STATE_MASK 0x0f -#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 -#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d -#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e -#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f -#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 -#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 -#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e -#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f -#define GLOBAL_ATU_MAC_01 0x0d -#define GLOBAL_ATU_MAC_23 0x0e -#define GLOBAL_ATU_MAC_45 0x0f -#define GLOBAL_IP_PRI_0 0x10 -#define GLOBAL_IP_PRI_1 0x11 -#define GLOBAL_IP_PRI_2 0x12 -#define GLOBAL_IP_PRI_3 0x13 -#define GLOBAL_IP_PRI_4 0x14 -#define GLOBAL_IP_PRI_5 0x15 -#define GLOBAL_IP_PRI_6 0x16 -#define GLOBAL_IP_PRI_7 0x17 -#define GLOBAL_IEEE_PRI 0x18 -#define GLOBAL_CORE_TAG_TYPE 0x19 -#define GLOBAL_MONITOR_CONTROL 0x1a -#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 -#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 -#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 -#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 -#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) -#define GLOBAL_CONTROL_2 0x1c -#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 -#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 - -#define GLOBAL_STATS_OP 0x1d -#define GLOBAL_STATS_OP_BUSY BIT(15) -#define GLOBAL_STATS_OP_NOP (0 << 12) -#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) -#define GLOBAL_STATS_OP_BANK_1 BIT(9) -#define GLOBAL_STATS_COUNTER_32 0x1e -#define GLOBAL_STATS_COUNTER_01 0x1f - -#define REG_GLOBAL2 0x1c -#define GLOBAL2_INT_SOURCE 0x00 -#define GLOBAL2_INT_MASK 0x01 -#define GLOBAL2_MGMT_EN_2X 0x02 -#define GLOBAL2_MGMT_EN_0X 0x03 -#define GLOBAL2_FLOW_CONTROL 0x04 -#define GLOBAL2_SWITCH_MGMT 0x05 -#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) -#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) -#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) -#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) -#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) -#define GLOBAL2_DEVICE_MAPPING 0x06 -#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) -#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 -#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f -#define GLOBAL2_TRUNK_MASK 0x07 -#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) -#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 -#define GLOBAL2_TRUNK_MAPPING 0x08 -#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) -#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 -#define GLOBAL2_INGRESS_OP 0x09 -#define GLOBAL2_INGRESS_DATA 0x0a -#define GLOBAL2_PVT_ADDR 0x0b -#define GLOBAL2_PVT_DATA 0x0c -#define GLOBAL2_SWITCH_MAC 0x0d -#define GLOBAL2_SWITCH_MAC_BUSY BIT(15) -#define GLOBAL2_ATU_STATS 0x0e -#define GLOBAL2_PRIO_OVERRIDE 0x0f -#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) -#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 -#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) -#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 -#define GLOBAL2_EEPROM_OP 0x14 -#define GLOBAL2_EEPROM_OP_BUSY BIT(15) -#define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY) -#define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY) -#define GLOBAL2_EEPROM_OP_LOAD BIT(11) -#define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10) -#define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff -#define GLOBAL2_EEPROM_DATA 0x15 -#define GLOBAL2_PTP_AVB_OP 0x16 -#define GLOBAL2_PTP_AVB_DATA 0x17 -#define GLOBAL2_SMI_OP 0x18 -#define GLOBAL2_SMI_OP_BUSY BIT(15) -#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) -#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ - GLOBAL2_SMI_OP_CLAUSE_22) -#define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ - GLOBAL2_SMI_OP_CLAUSE_22) -#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) -#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) -#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) -#define GLOBAL2_SMI_DATA 0x19 -#define GLOBAL2_SCRATCH_MISC 0x1a -#define GLOBAL2_SCRATCH_BUSY BIT(15) -#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 -#define GLOBAL2_SCRATCH_VALUE_MASK 0xff -#define GLOBAL2_WDOG_CONTROL 0x1b -#define GLOBAL2_QOS_WEIGHT 0x1c -#define GLOBAL2_MISC 0x1d - -#define MV88E6XXX_N_FID 4096 - -/* List of supported models */ -enum mv88e6xxx_model { - MV88E6085, - MV88E6095, - MV88E6123, - MV88E6131, - MV88E6161, - MV88E6165, - MV88E6171, - MV88E6172, - MV88E6175, - MV88E6176, - MV88E6185, - MV88E6240, - MV88E6320, - MV88E6321, - MV88E6350, - MV88E6351, - MV88E6352, -}; - -enum mv88e6xxx_family { - MV88E6XXX_FAMILY_NONE, - MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */ - MV88E6XXX_FAMILY_6095, /* 6092 6095 */ - MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */ - MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */ - MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */ - MV88E6XXX_FAMILY_6320, /* 6320 6321 */ - MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */ - MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */ -}; - -enum mv88e6xxx_cap { - /* Address Translation Unit. - * The ATU is used to lookup and learn MAC addresses. See GLOBAL_ATU_OP. - */ - MV88E6XXX_CAP_ATU, - - /* Energy Efficient Ethernet. - */ - MV88E6XXX_CAP_EEE, - - /* EEPROM Command and Data registers. - * See GLOBAL2_EEPROM_OP and GLOBAL2_EEPROM_DATA. - */ - MV88E6XXX_CAP_EEPROM, - - /* Port State Filtering for 802.1D Spanning Tree. - * See PORT_CONTROL_STATE_* values in the PORT_CONTROL register. - */ - MV88E6XXX_CAP_PORTSTATE, - - /* PHY Polling Unit. - * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING. - */ - MV88E6XXX_CAP_PPU, - MV88E6XXX_CAP_PPU_ACTIVE, - - /* SMI PHY Command and Data registers. - * This requires an indirect access to PHY registers through - * GLOBAL2_SMI_OP, otherwise direct access to PHY registers is done. - */ - MV88E6XXX_CAP_SMI_PHY, - - /* Per VLAN Spanning Tree Unit (STU). - * The Port State database, if present, is accessed through VTU - * operations and dedicated SID registers. See GLOBAL_VTU_SID. - */ - MV88E6XXX_CAP_STU, - - /* Switch MAC/WoL/WoF register. - * This requires an indirect access to set the switch MAC address - * through GLOBAL2_SWITCH_MAC, otherwise GLOBAL_MAC_01, GLOBAL_MAC_23, - * and GLOBAL_MAC_45 are used with a direct access. - */ - MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF, - - /* Internal temperature sensor. - * Available from any enabled port's PHY register 26, page 6. - */ - MV88E6XXX_CAP_TEMP, - MV88E6XXX_CAP_TEMP_LIMIT, - - /* In-chip Port Based VLANs. - * Each port VLANTable register (see PORT_BASE_VLAN) is used to restrict - * the output (or egress) ports to which it is allowed to send frames. - */ - MV88E6XXX_CAP_VLANTABLE, - - /* VLAN Table Unit. - * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP. - */ - MV88E6XXX_CAP_VTU, -}; - -/* Bitmask of capabilities */ -#define MV88E6XXX_FLAG_ATU BIT(MV88E6XXX_CAP_ATU) -#define MV88E6XXX_FLAG_EEE BIT(MV88E6XXX_CAP_EEE) -#define MV88E6XXX_FLAG_EEPROM BIT(MV88E6XXX_CAP_EEPROM) -#define MV88E6XXX_FLAG_PORTSTATE BIT(MV88E6XXX_CAP_PORTSTATE) -#define MV88E6XXX_FLAG_PPU BIT(MV88E6XXX_CAP_PPU) -#define MV88E6XXX_FLAG_PPU_ACTIVE BIT(MV88E6XXX_CAP_PPU_ACTIVE) -#define MV88E6XXX_FLAG_SMI_PHY BIT(MV88E6XXX_CAP_SMI_PHY) -#define MV88E6XXX_FLAG_STU BIT(MV88E6XXX_CAP_STU) -#define MV88E6XXX_FLAG_SWITCH_MAC BIT(MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF) -#define MV88E6XXX_FLAG_TEMP BIT(MV88E6XXX_CAP_TEMP) -#define MV88E6XXX_FLAG_TEMP_LIMIT BIT(MV88E6XXX_CAP_TEMP_LIMIT) -#define MV88E6XXX_FLAG_VLANTABLE BIT(MV88E6XXX_CAP_VLANTABLE) -#define MV88E6XXX_FLAG_VTU BIT(MV88E6XXX_CAP_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6095 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_PPU | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6097 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_PPU | \ - MV88E6XXX_FLAG_STU | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6165 \ - (MV88E6XXX_FLAG_STU | \ - MV88E6XXX_FLAG_SWITCH_MAC | \ - MV88E6XXX_FLAG_TEMP | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6185 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_PPU | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6320 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_EEE | \ - MV88E6XXX_FLAG_EEPROM | \ - MV88E6XXX_FLAG_PORTSTATE | \ - MV88E6XXX_FLAG_PPU_ACTIVE | \ - MV88E6XXX_FLAG_SMI_PHY | \ - MV88E6XXX_FLAG_SWITCH_MAC | \ - MV88E6XXX_FLAG_TEMP | \ - MV88E6XXX_FLAG_TEMP_LIMIT | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6351 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_PORTSTATE | \ - MV88E6XXX_FLAG_PPU_ACTIVE | \ - MV88E6XXX_FLAG_SMI_PHY | \ - MV88E6XXX_FLAG_STU | \ - MV88E6XXX_FLAG_SWITCH_MAC | \ - MV88E6XXX_FLAG_TEMP | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -#define MV88E6XXX_FLAGS_FAMILY_6352 \ - (MV88E6XXX_FLAG_ATU | \ - MV88E6XXX_FLAG_EEE | \ - MV88E6XXX_FLAG_EEPROM | \ - MV88E6XXX_FLAG_PORTSTATE | \ - MV88E6XXX_FLAG_PPU_ACTIVE | \ - MV88E6XXX_FLAG_SMI_PHY | \ - MV88E6XXX_FLAG_STU | \ - MV88E6XXX_FLAG_SWITCH_MAC | \ - MV88E6XXX_FLAG_TEMP | \ - MV88E6XXX_FLAG_TEMP_LIMIT | \ - MV88E6XXX_FLAG_VLANTABLE | \ - MV88E6XXX_FLAG_VTU) - -struct mv88e6xxx_info { - enum mv88e6xxx_family family; - u16 prod_num; - const char *name; - unsigned int num_databases; - unsigned int num_ports; - unsigned long flags; -}; - -struct mv88e6xxx_atu_entry { - u16 fid; - u8 state; - bool trunk; - u16 portv_trunkid; - u8 mac[ETH_ALEN]; -}; - -struct mv88e6xxx_vtu_stu_entry { - /* VTU only */ - u16 vid; - u16 fid; - - /* VTU and STU */ - u8 sid; - bool valid; - u8 data[DSA_MAX_PORTS]; -}; - -struct mv88e6xxx_priv_port { - struct net_device *bridge_dev; -}; - -struct mv88e6xxx_priv_state { - const struct mv88e6xxx_info *info; - - /* The dsa_switch this private structure is related to */ - struct dsa_switch *ds; - - /* The device this structure is associated to */ - struct device *dev; - - /* When using multi-chip addressing, this mutex protects - * access to the indirect access registers. (In single-chip - * mode, this mutex is effectively useless.) - */ - struct mutex smi_mutex; - - /* The MII bus and the address on the bus that is used to - * communication with the switch - */ - struct mii_bus *bus; - int sw_addr; - - /* Handles automatic disabling and re-enabling of the PHY - * polling unit. - */ - struct mutex ppu_mutex; - int ppu_disabled; - struct work_struct ppu_work; - struct timer_list ppu_timer; - - /* This mutex serialises access to the statistics unit. - * Hold this mutex over snapshot + dump sequences. - */ - struct mutex stats_mutex; - - /* This mutex serializes phy access for chips with - * indirect phy addressing. It is unused for chips - * with direct phy access. - */ - struct mutex phy_mutex; - - /* This mutex serializes eeprom access for chips with - * eeprom support. - */ - struct mutex eeprom_mutex; - - struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS]; - - /* A switch may have a GPIO line tied to its reset pin. Parse - * this from the device tree, and use it before performing - * switch soft reset. - */ - struct gpio_desc *reset; - - /* set to size of eeprom if supported by the switch */ - int eeprom_len; -}; - -enum stat_type { - BANK0, - BANK1, - PORT, -}; - -struct mv88e6xxx_hw_stat { - char string[ETH_GSTRING_LEN]; - int sizeof_stat; - int reg; - enum stat_type type; -}; - -static inline bool mv88e6xxx_has(struct mv88e6xxx_priv_state *ps, - unsigned long flags) -{ - return (ps->info->flags & flags) == flags; -} - -#endif diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c deleted file mode 100644 index d88a7a7b2..000000000 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * cxgb4_ppm.c: Chelsio common library for T4/T5 iSCSI PagePod Manager - * - * Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Written by: Karen Xie (kxie@chelsio.com) - */ - -#include <linux/kernel.h> -#include <linux/version.h> -#include <linux/module.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <linux/debugfs.h> -#include <linux/export.h> -#include <linux/list.h> -#include <linux/skbuff.h> -#include <linux/pci.h> -#include <linux/scatterlist.h> - -#include "cxgb4_ppm.h" - -/* Direct Data Placement - - * Directly place the iSCSI Data-In or Data-Out PDU's payload into - * pre-posted final destination host-memory buffers based on the - * Initiator Task Tag (ITT) in Data-In or Target Task Tag (TTT) - * in Data-Out PDUs. The host memory address is programmed into - * h/w in the format of pagepod entries. The location of the - * pagepod entry is encoded into ddp tag which is used as the base - * for ITT/TTT. - */ - -/* Direct-Data Placement page size adjustment - */ -int cxgbi_ppm_find_page_index(struct cxgbi_ppm *ppm, unsigned long pgsz) -{ - struct cxgbi_tag_format *tformat = &ppm->tformat; - int i; - - for (i = 0; i < DDP_PGIDX_MAX; i++) { - if (pgsz == 1UL << (DDP_PGSZ_BASE_SHIFT + - tformat->pgsz_order[i])) { - pr_debug("%s: %s ppm, pgsz %lu -> idx %d.\n", - __func__, ppm->ndev->name, pgsz, i); - return i; - } - } - pr_info("ippm: ddp page size %lu not supported.\n", pgsz); - return DDP_PGIDX_MAX; -} - -/* DDP setup & teardown - */ -static int ppm_find_unused_entries(unsigned long *bmap, - unsigned int max_ppods, - unsigned int start, - unsigned int nr, - unsigned int align_mask) -{ - unsigned long i; - - i = bitmap_find_next_zero_area(bmap, max_ppods, start, nr, align_mask); - - if (unlikely(i >= max_ppods) && (start > nr)) - i = bitmap_find_next_zero_area(bmap, max_ppods, 0, start - 1, - align_mask); - if (unlikely(i >= max_ppods)) - return -ENOSPC; - - bitmap_set(bmap, i, nr); - return (int)i; -} - -static void ppm_mark_entries(struct cxgbi_ppm *ppm, int i, int count, - unsigned long caller_data) -{ - struct cxgbi_ppod_data *pdata = ppm->ppod_data + i; - - pdata->caller_data = caller_data; - pdata->npods = count; - - if (pdata->color == ((1 << PPOD_IDX_SHIFT) - 1)) - pdata->color = 0; - else - pdata->color++; -} - -static int ppm_get_cpu_entries(struct cxgbi_ppm *ppm, unsigned int count, - unsigned long caller_data) -{ - struct cxgbi_ppm_pool *pool; - unsigned int cpu; - int i; - - cpu = get_cpu(); - pool = per_cpu_ptr(ppm->pool, cpu); - spin_lock_bh(&pool->lock); - put_cpu(); - - i = ppm_find_unused_entries(pool->bmap, ppm->pool_index_max, - pool->next, count, 0); - if (i < 0) { - pool->next = 0; - spin_unlock_bh(&pool->lock); - return -ENOSPC; - } - - pool->next = i + count; - if (pool->next >= ppm->pool_index_max) - pool->next = 0; - - spin_unlock_bh(&pool->lock); - - pr_debug("%s: cpu %u, idx %d + %d (%d), next %u.\n", - __func__, cpu, i, count, i + cpu * ppm->pool_index_max, - pool->next); - - i += cpu * ppm->pool_index_max; - ppm_mark_entries(ppm, i, count, caller_data); - - return i; -} - -static int ppm_get_entries(struct cxgbi_ppm *ppm, unsigned int count, - unsigned long caller_data) -{ - int i; - - spin_lock_bh(&ppm->map_lock); - i = ppm_find_unused_entries(ppm->ppod_bmap, ppm->bmap_index_max, - ppm->next, count, 0); - if (i < 0) { - ppm->next = 0; - spin_unlock_bh(&ppm->map_lock); - pr_debug("ippm: NO suitable entries %u available.\n", - count); - return -ENOSPC; - } - - ppm->next = i + count; - if (ppm->next >= ppm->bmap_index_max) - ppm->next = 0; - - spin_unlock_bh(&ppm->map_lock); - - pr_debug("%s: idx %d + %d (%d), next %u, caller_data 0x%lx.\n", - __func__, i, count, i + ppm->pool_rsvd, ppm->next, - caller_data); - - i += ppm->pool_rsvd; - ppm_mark_entries(ppm, i, count, caller_data); - - return i; -} - -static void ppm_unmark_entries(struct cxgbi_ppm *ppm, int i, int count) -{ - pr_debug("%s: idx %d + %d.\n", __func__, i, count); - - if (i < ppm->pool_rsvd) { - unsigned int cpu; - struct cxgbi_ppm_pool *pool; - - cpu = i / ppm->pool_index_max; - i %= ppm->pool_index_max; - - pool = per_cpu_ptr(ppm->pool, cpu); - spin_lock_bh(&pool->lock); - bitmap_clear(pool->bmap, i, count); - - if (i < pool->next) - pool->next = i; - spin_unlock_bh(&pool->lock); - - pr_debug("%s: cpu %u, idx %d, next %u.\n", - __func__, cpu, i, pool->next); - } else { - spin_lock_bh(&ppm->map_lock); - - i -= ppm->pool_rsvd; - bitmap_clear(ppm->ppod_bmap, i, count); - - if (i < ppm->next) - ppm->next = i; - spin_unlock_bh(&ppm->map_lock); - - pr_debug("%s: idx %d, next %u.\n", __func__, i, ppm->next); - } -} - -void cxgbi_ppm_ppod_release(struct cxgbi_ppm *ppm, u32 idx) -{ - struct cxgbi_ppod_data *pdata; - - if (idx >= ppm->ppmax) { - pr_warn("ippm: idx too big %u > %u.\n", idx, ppm->ppmax); - return; - } - - pdata = ppm->ppod_data + idx; - if (!pdata->npods) { - pr_warn("ippm: idx %u, npods 0.\n", idx); - return; - } - - pr_debug("release idx %u, npods %u.\n", idx, pdata->npods); - ppm_unmark_entries(ppm, idx, pdata->npods); -} -EXPORT_SYMBOL(cxgbi_ppm_ppod_release); - -int cxgbi_ppm_ppods_reserve(struct cxgbi_ppm *ppm, unsigned short nr_pages, - u32 per_tag_pg_idx, u32 *ppod_idx, - u32 *ddp_tag, unsigned long caller_data) -{ - struct cxgbi_ppod_data *pdata; - unsigned int npods; - int idx = -1; - unsigned int hwidx; - u32 tag; - - npods = (nr_pages + PPOD_PAGES_MAX - 1) >> PPOD_PAGES_SHIFT; - if (!npods) { - pr_warn("%s: pages %u -> npods %u, full.\n", - __func__, nr_pages, npods); - return -EINVAL; - } - - /* grab from cpu pool first */ - idx = ppm_get_cpu_entries(ppm, npods, caller_data); - /* try the general pool */ - if (idx < 0) - idx = ppm_get_entries(ppm, npods, caller_data); - if (idx < 0) { - pr_debug("ippm: pages %u, nospc %u, nxt %u, 0x%lx.\n", - nr_pages, npods, ppm->next, caller_data); - return idx; - } - - pdata = ppm->ppod_data + idx; - hwidx = ppm->base_idx + idx; - - tag = cxgbi_ppm_make_ddp_tag(hwidx, pdata->color); - - if (per_tag_pg_idx) - tag |= (per_tag_pg_idx << 30) & 0xC0000000; - - *ppod_idx = idx; - *ddp_tag = tag; - - pr_debug("ippm: sg %u, tag 0x%x(%u,%u), data 0x%lx.\n", - nr_pages, tag, idx, npods, caller_data); - - return npods; -} -EXPORT_SYMBOL(cxgbi_ppm_ppods_reserve); - -void cxgbi_ppm_make_ppod_hdr(struct cxgbi_ppm *ppm, u32 tag, - unsigned int tid, unsigned int offset, - unsigned int length, - struct cxgbi_pagepod_hdr *hdr) -{ - /* The ddp tag in pagepod should be with bit 31:30 set to 0. - * The ddp Tag on the wire should be with non-zero 31:30 to the peer - */ - tag &= 0x3FFFFFFF; - - hdr->vld_tid = htonl(PPOD_VALID_FLAG | PPOD_TID(tid)); - - hdr->rsvd = 0; - hdr->pgsz_tag_clr = htonl(tag & ppm->tformat.idx_clr_mask); - hdr->max_offset = htonl(length); - hdr->page_offset = htonl(offset); - - pr_debug("ippm: tag 0x%x, tid 0x%x, xfer %u, off %u.\n", - tag, tid, length, offset); -} -EXPORT_SYMBOL(cxgbi_ppm_make_ppod_hdr); - -static void ppm_free(struct cxgbi_ppm *ppm) -{ - vfree(ppm); -} - -static void ppm_destroy(struct kref *kref) -{ - struct cxgbi_ppm *ppm = container_of(kref, - struct cxgbi_ppm, - refcnt); - pr_info("ippm: kref 0, destroy %s ppm 0x%p.\n", - ppm->ndev->name, ppm); - - *ppm->ppm_pp = NULL; - - free_percpu(ppm->pool); - ppm_free(ppm); -} - -int cxgbi_ppm_release(struct cxgbi_ppm *ppm) -{ - if (ppm) { - int rv; - - rv = kref_put(&ppm->refcnt, ppm_destroy); - return rv; - } - return 1; -} - -static struct cxgbi_ppm_pool *ppm_alloc_cpu_pool(unsigned int *total, - unsigned int *pcpu_ppmax) -{ - struct cxgbi_ppm_pool *pools; - unsigned int ppmax = (*total) / num_possible_cpus(); - unsigned int max = (PCPU_MIN_UNIT_SIZE - sizeof(*pools)) << 3; - unsigned int bmap; - unsigned int alloc_sz; - unsigned int count = 0; - unsigned int cpu; - - /* make sure per cpu pool fits into PCPU_MIN_UNIT_SIZE */ - if (ppmax > max) - ppmax = max; - - /* pool size must be multiple of unsigned long */ - bmap = BITS_TO_LONGS(ppmax); - ppmax = (bmap * sizeof(unsigned long)) << 3; - - alloc_sz = sizeof(*pools) + sizeof(unsigned long) * bmap; - pools = __alloc_percpu(alloc_sz, __alignof__(struct cxgbi_ppm_pool)); - - if (!pools) - return NULL; - - for_each_possible_cpu(cpu) { - struct cxgbi_ppm_pool *ppool = per_cpu_ptr(pools, cpu); - - memset(ppool, 0, alloc_sz); - spin_lock_init(&ppool->lock); - count += ppmax; - } - - *total = count; - *pcpu_ppmax = ppmax; - - return pools; -} - -int cxgbi_ppm_init(void **ppm_pp, struct net_device *ndev, - struct pci_dev *pdev, void *lldev, - struct cxgbi_tag_format *tformat, - unsigned int ppmax, - unsigned int llimit, - unsigned int start, - unsigned int reserve_factor) -{ - struct cxgbi_ppm *ppm = (struct cxgbi_ppm *)(*ppm_pp); - struct cxgbi_ppm_pool *pool = NULL; - unsigned int ppmax_pool = 0; - unsigned int pool_index_max = 0; - unsigned int alloc_sz; - unsigned int ppod_bmap_size; - - if (ppm) { - pr_info("ippm: %s, ppm 0x%p,0x%p already initialized, %u/%u.\n", - ndev->name, ppm_pp, ppm, ppm->ppmax, ppmax); - kref_get(&ppm->refcnt); - return 1; - } - - if (reserve_factor) { - ppmax_pool = ppmax / reserve_factor; - pool = ppm_alloc_cpu_pool(&ppmax_pool, &pool_index_max); - - pr_debug("%s: ppmax %u, cpu total %u, per cpu %u.\n", - ndev->name, ppmax, ppmax_pool, pool_index_max); - } - - ppod_bmap_size = BITS_TO_LONGS(ppmax - ppmax_pool); - alloc_sz = sizeof(struct cxgbi_ppm) + - ppmax * (sizeof(struct cxgbi_ppod_data)) + - ppod_bmap_size * sizeof(unsigned long); - - ppm = vmalloc(alloc_sz); - if (!ppm) - goto release_ppm_pool; - - memset(ppm, 0, alloc_sz); - - ppm->ppod_bmap = (unsigned long *)(&ppm->ppod_data[ppmax]); - - if ((ppod_bmap_size >> 3) > (ppmax - ppmax_pool)) { - unsigned int start = ppmax - ppmax_pool; - unsigned int end = ppod_bmap_size >> 3; - - bitmap_set(ppm->ppod_bmap, ppmax, end - start); - pr_info("%s: %u - %u < %u * 8, mask extra bits %u, %u.\n", - __func__, ppmax, ppmax_pool, ppod_bmap_size, start, - end); - } - - spin_lock_init(&ppm->map_lock); - kref_init(&ppm->refcnt); - - memcpy(&ppm->tformat, tformat, sizeof(struct cxgbi_tag_format)); - - ppm->ppm_pp = ppm_pp; - ppm->ndev = ndev; - ppm->pdev = pdev; - ppm->lldev = lldev; - ppm->ppmax = ppmax; - ppm->next = 0; - ppm->llimit = llimit; - ppm->base_idx = start > llimit ? - (start - llimit + 1) >> PPOD_SIZE_SHIFT : 0; - ppm->bmap_index_max = ppmax - ppmax_pool; - - ppm->pool = pool; - ppm->pool_rsvd = ppmax_pool; - ppm->pool_index_max = pool_index_max; - - /* check one more time */ - if (*ppm_pp) { - ppm_free(ppm); - ppm = (struct cxgbi_ppm *)(*ppm_pp); - - pr_info("ippm: %s, ppm 0x%p,0x%p already initialized, %u/%u.\n", - ndev->name, ppm_pp, *ppm_pp, ppm->ppmax, ppmax); - - kref_get(&ppm->refcnt); - return 1; - } - *ppm_pp = ppm; - - ppm->tformat.pgsz_idx_dflt = cxgbi_ppm_find_page_index(ppm, PAGE_SIZE); - - pr_info("ippm %s: ppm 0x%p, 0x%p, base %u/%u, pg %lu,%u, rsvd %u,%u.\n", - ndev->name, ppm_pp, ppm, ppm->base_idx, ppm->ppmax, PAGE_SIZE, - ppm->tformat.pgsz_idx_dflt, ppm->pool_rsvd, - ppm->pool_index_max); - - return 0; - -release_ppm_pool: - free_percpu(pool); - return -ENOMEM; -} -EXPORT_SYMBOL(cxgbi_ppm_init); - -unsigned int cxgbi_tagmask_set(unsigned int ppmax) -{ - unsigned int bits = fls(ppmax); - - if (bits > PPOD_IDX_MAX_SIZE) - bits = PPOD_IDX_MAX_SIZE; - - pr_info("ippm: ppmax %u/0x%x -> bits %u, tagmask 0x%x.\n", - ppmax, ppmax, bits, 1 << (bits + PPOD_IDX_SHIFT)); - - return 1 << (bits + PPOD_IDX_SHIFT); -} diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h deleted file mode 100644 index d48732673..000000000 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_ppm.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * cxgb4_ppm.h: Chelsio common library for T4/T5 iSCSI ddp operation - * - * Copyright (c) 2016 Chelsio Communications, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Written by: Karen Xie (kxie@chelsio.com) - */ - -#ifndef __CXGB4PPM_H__ -#define __CXGB4PPM_H__ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <linux/debugfs.h> -#include <linux/list.h> -#include <linux/netdevice.h> -#include <linux/scatterlist.h> -#include <linux/skbuff.h> -#include <linux/vmalloc.h> -#include <linux/bitmap.h> - -struct cxgbi_pagepod_hdr { - u32 vld_tid; - u32 pgsz_tag_clr; - u32 max_offset; - u32 page_offset; - u64 rsvd; -}; - -#define PPOD_PAGES_MAX 4 -struct cxgbi_pagepod { - struct cxgbi_pagepod_hdr hdr; - u64 addr[PPOD_PAGES_MAX + 1]; -}; - -/* ddp tag format - * for a 32-bit tag: - * bit # - * 31 ..... ..... 0 - * X Y...Y Z...Z, where - * ^ ^^^^^ ^^^^ - * | | |____ when ddp bit = 0: color bits - * | | - * | |____ when ddp bit = 0: idx into the ddp memory region - * | - * |____ ddp bit: 0 - ddp tag, 1 - non-ddp tag - * - * [page selector:2] [sw/free bits] [0] [idx] [color:6] - */ - -#define DDP_PGIDX_MAX 4 -#define DDP_PGSZ_BASE_SHIFT 12 /* base page 4K */ - -struct cxgbi_task_tag_info { - unsigned char flags; -#define CXGBI_PPOD_INFO_FLAG_VALID 0x1 -#define CXGBI_PPOD_INFO_FLAG_MAPPED 0x2 - unsigned char cid; - unsigned short pg_shift; - unsigned int npods; - unsigned int idx; - unsigned int tag; - struct cxgbi_pagepod_hdr hdr; - int nents; - int nr_pages; - struct scatterlist *sgl; -}; - -struct cxgbi_tag_format { - unsigned char pgsz_order[DDP_PGIDX_MAX]; - unsigned char pgsz_idx_dflt; - unsigned char free_bits:4; - unsigned char color_bits:4; - unsigned char idx_bits; - unsigned char rsvd_bits; - unsigned int no_ddp_mask; - unsigned int idx_mask; - unsigned int color_mask; - unsigned int idx_clr_mask; - unsigned int rsvd_mask; -}; - -struct cxgbi_ppod_data { - unsigned char pg_idx:2; - unsigned char color:6; - unsigned char chan_id; - unsigned short npods; - unsigned long caller_data; -}; - -/* per cpu ppm pool */ -struct cxgbi_ppm_pool { - unsigned int base; /* base index */ - unsigned int next; /* next possible free index */ - spinlock_t lock; /* ppm pool lock */ - unsigned long bmap[0]; -} ____cacheline_aligned_in_smp; - -struct cxgbi_ppm { - struct kref refcnt; - struct net_device *ndev; /* net_device, 1st port */ - struct pci_dev *pdev; - void *lldev; - void **ppm_pp; - struct cxgbi_tag_format tformat; - unsigned int ppmax; - unsigned int llimit; - unsigned int base_idx; - - unsigned int pool_rsvd; - unsigned int pool_index_max; - struct cxgbi_ppm_pool __percpu *pool; - /* map lock */ - spinlock_t map_lock; /* ppm map lock */ - unsigned int bmap_index_max; - unsigned int next; - unsigned long *ppod_bmap; - struct cxgbi_ppod_data ppod_data[0]; -}; - -#define DDP_THRESHOLD 512 - -#define PPOD_PAGES_SHIFT 2 /* 4 pages per pod */ - -#define IPPOD_SIZE sizeof(struct cxgbi_pagepod) /* 64 */ -#define PPOD_SIZE_SHIFT 6 - -/* page pods are allocated in groups of this size (must be power of 2) */ -#define PPOD_CLUSTER_SIZE 16U - -#define ULPMEM_DSGL_MAX_NPPODS 16 /* 1024/PPOD_SIZE */ -#define ULPMEM_IDATA_MAX_NPPODS 3 /* (PPOD_SIZE * 3 + ulptx hdr) < 256B */ -#define PCIE_MEMWIN_MAX_NPPODS 16 /* 1024/PPOD_SIZE */ - -#define PPOD_COLOR_SHIFT 0 -#define PPOD_COLOR(x) ((x) << PPOD_COLOR_SHIFT) - -#define PPOD_IDX_SHIFT 6 -#define PPOD_IDX_MAX_SIZE 24 - -#define PPOD_TID_SHIFT 0 -#define PPOD_TID(x) ((x) << PPOD_TID_SHIFT) - -#define PPOD_TAG_SHIFT 6 -#define PPOD_TAG(x) ((x) << PPOD_TAG_SHIFT) - -#define PPOD_VALID_SHIFT 24 -#define PPOD_VALID(x) ((x) << PPOD_VALID_SHIFT) -#define PPOD_VALID_FLAG PPOD_VALID(1U) - -#define PPOD_PI_EXTRACT_CTL_SHIFT 31 -#define PPOD_PI_EXTRACT_CTL(x) ((x) << PPOD_PI_EXTRACT_CTL_SHIFT) -#define PPOD_PI_EXTRACT_CTL_FLAG V_PPOD_PI_EXTRACT_CTL(1U) - -#define PPOD_PI_TYPE_SHIFT 29 -#define PPOD_PI_TYPE_MASK 0x3 -#define PPOD_PI_TYPE(x) ((x) << PPOD_PI_TYPE_SHIFT) - -#define PPOD_PI_CHECK_CTL_SHIFT 27 -#define PPOD_PI_CHECK_CTL_MASK 0x3 -#define PPOD_PI_CHECK_CTL(x) ((x) << PPOD_PI_CHECK_CTL_SHIFT) - -#define PPOD_PI_REPORT_CTL_SHIFT 25 -#define PPOD_PI_REPORT_CTL_MASK 0x3 -#define PPOD_PI_REPORT_CTL(x) ((x) << PPOD_PI_REPORT_CTL_SHIFT) - -static inline int cxgbi_ppm_is_ddp_tag(struct cxgbi_ppm *ppm, u32 tag) -{ - return !(tag & ppm->tformat.no_ddp_mask); -} - -static inline int cxgbi_ppm_sw_tag_is_usable(struct cxgbi_ppm *ppm, - u32 tag) -{ - /* the sw tag must be using <= 31 bits */ - return !(tag & 0x80000000U); -} - -static inline int cxgbi_ppm_make_non_ddp_tag(struct cxgbi_ppm *ppm, - u32 sw_tag, - u32 *final_tag) -{ - struct cxgbi_tag_format *tformat = &ppm->tformat; - - if (!cxgbi_ppm_sw_tag_is_usable(ppm, sw_tag)) { - pr_info("sw_tag 0x%x NOT usable.\n", sw_tag); - return -EINVAL; - } - - if (!sw_tag) { - *final_tag = tformat->no_ddp_mask; - } else { - unsigned int shift = tformat->idx_bits + tformat->color_bits; - u32 lower = sw_tag & tformat->idx_clr_mask; - u32 upper = (sw_tag >> shift) << (shift + 1); - - *final_tag = upper | tformat->no_ddp_mask | lower; - } - return 0; -} - -static inline u32 cxgbi_ppm_decode_non_ddp_tag(struct cxgbi_ppm *ppm, - u32 tag) -{ - struct cxgbi_tag_format *tformat = &ppm->tformat; - unsigned int shift = tformat->idx_bits + tformat->color_bits; - u32 lower = tag & tformat->idx_clr_mask; - u32 upper = (tag >> tformat->rsvd_bits) << shift; - - return upper | lower; -} - -static inline u32 cxgbi_ppm_ddp_tag_get_idx(struct cxgbi_ppm *ppm, - u32 ddp_tag) -{ - u32 hw_idx = (ddp_tag >> PPOD_IDX_SHIFT) & - ppm->tformat.idx_mask; - - return hw_idx - ppm->base_idx; -} - -static inline u32 cxgbi_ppm_make_ddp_tag(unsigned int hw_idx, - unsigned char color) -{ - return (hw_idx << PPOD_IDX_SHIFT) | ((u32)color); -} - -static inline unsigned long -cxgbi_ppm_get_tag_caller_data(struct cxgbi_ppm *ppm, - u32 ddp_tag) -{ - u32 idx = cxgbi_ppm_ddp_tag_get_idx(ppm, ddp_tag); - - return ppm->ppod_data[idx].caller_data; -} - -/* sw bits are the free bits */ -static inline int cxgbi_ppm_ddp_tag_update_sw_bits(struct cxgbi_ppm *ppm, - u32 val, u32 orig_tag, - u32 *final_tag) -{ - struct cxgbi_tag_format *tformat = &ppm->tformat; - u32 v = val >> tformat->free_bits; - - if (v) { - pr_info("sw_bits 0x%x too large, avail bits %u.\n", - val, tformat->free_bits); - return -EINVAL; - } - if (!cxgbi_ppm_is_ddp_tag(ppm, orig_tag)) - return -EINVAL; - - *final_tag = (val << tformat->rsvd_bits) | - (orig_tag & ppm->tformat.rsvd_mask); - return 0; -} - -static inline void cxgbi_ppm_ppod_clear(struct cxgbi_pagepod *ppod) -{ - ppod->hdr.vld_tid = 0U; -} - -static inline void cxgbi_tagmask_check(unsigned int tagmask, - struct cxgbi_tag_format *tformat) -{ - unsigned int bits = fls(tagmask); - - /* reserve top most 2 bits for page selector */ - tformat->free_bits = 32 - 2 - bits; - tformat->rsvd_bits = bits; - tformat->color_bits = PPOD_IDX_SHIFT; - tformat->idx_bits = bits - 1 - PPOD_IDX_SHIFT; - tformat->no_ddp_mask = 1 << (bits - 1); - tformat->idx_mask = (1 << tformat->idx_bits) - 1; - tformat->color_mask = (1 << PPOD_IDX_SHIFT) - 1; - tformat->idx_clr_mask = (1 << (bits - 1)) - 1; - tformat->rsvd_mask = (1 << bits) - 1; - - pr_info("ippm: tagmask 0x%x, rsvd %u=%u+%u+1, mask 0x%x,0x%x, " - "pg %u,%u,%u,%u.\n", - tagmask, tformat->rsvd_bits, tformat->idx_bits, - tformat->color_bits, tformat->no_ddp_mask, tformat->rsvd_mask, - tformat->pgsz_order[0], tformat->pgsz_order[1], - tformat->pgsz_order[2], tformat->pgsz_order[3]); -} - -int cxgbi_ppm_find_page_index(struct cxgbi_ppm *ppm, unsigned long pgsz); -void cxgbi_ppm_make_ppod_hdr(struct cxgbi_ppm *ppm, u32 tag, - unsigned int tid, unsigned int offset, - unsigned int length, - struct cxgbi_pagepod_hdr *hdr); -void cxgbi_ppm_ppod_release(struct cxgbi_ppm *, u32 idx); -int cxgbi_ppm_ppods_reserve(struct cxgbi_ppm *, unsigned short nr_pages, - u32 per_tag_pg_idx, u32 *ppod_idx, u32 *ddp_tag, - unsigned long caller_data); -int cxgbi_ppm_init(void **ppm_pp, struct net_device *, struct pci_dev *, - void *lldev, struct cxgbi_tag_format *, - unsigned int ppmax, unsigned int llimit, - unsigned int start, - unsigned int reserve_factor); -int cxgbi_ppm_release(struct cxgbi_ppm *ppm); -void cxgbi_tagmask_check(unsigned int tagmask, struct cxgbi_tag_format *); -unsigned int cxgbi_tagmask_set(unsigned int ppmax); - -#endif /*__CXGB4PPM_H__*/ diff --git a/drivers/net/wireless/broadcom/b43/phy_a.c b/drivers/net/wireless/broadcom/b43/phy_a.c deleted file mode 100644 index 99c036f5e..000000000 --- a/drivers/net/wireless/broadcom/b43/phy_a.c +++ /dev/null @@ -1,595 +0,0 @@ -/* - - Broadcom B43 wireless driver - IEEE 802.11a PHY driver - - Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, - Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> - Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> - Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> - Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to - the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, - Boston, MA 02110-1301, USA. - -*/ - -#include <linux/slab.h> - -#include "b43.h" -#include "phy_a.h" -#include "phy_common.h" -#include "wa.h" -#include "tables.h" -#include "main.h" - - -/* Get the freq, as it has to be written to the device. */ -static inline u16 channel2freq_a(u8 channel) -{ - B43_WARN_ON(channel > 200); - - return (5000 + 5 * channel); -} - -static inline u16 freq_r3A_value(u16 frequency) -{ - u16 value; - - if (frequency < 5091) - value = 0x0040; - else if (frequency < 5321) - value = 0x0000; - else if (frequency < 5806) - value = 0x0080; - else - value = 0x0040; - - return value; -} - -#if 0 -/* This function converts a TSSI value to dBm in Q5.2 */ -static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - s8 dbm = 0; - s32 tmp; - - tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi); - tmp += 0x80; - tmp = clamp_val(tmp, 0x00, 0xFF); - dbm = aphy->tssi2dbm[tmp]; - //TODO: There's a FIXME on the specs - - return dbm; -} -#endif - -static void b43_radio_set_tx_iq(struct b43_wldev *dev) -{ - static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 }; - static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A }; - u16 tmp = b43_radio_read16(dev, 0x001E); - int i, j; - - for (i = 0; i < 5; i++) { - for (j = 0; j < 5; j++) { - if (tmp == (data_high[i] << 4 | data_low[j])) { - b43_phy_write(dev, 0x0069, - (i - j) << 8 | 0x00C0); - return; - } - } - } -} - -static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel) -{ - u16 freq, r8, tmp; - - freq = channel2freq_a(channel); - - r8 = b43_radio_read16(dev, 0x0008); - b43_write16(dev, 0x03F0, freq); - b43_radio_write16(dev, 0x0008, r8); - - //TODO: write max channel TX power? to Radio 0x2D - tmp = b43_radio_read16(dev, 0x002E); - tmp &= 0x0080; - //TODO: OR tmp with the Power out estimation for this channel? - b43_radio_write16(dev, 0x002E, tmp); - - if (freq >= 4920 && freq <= 5500) { - /* - * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F; - * = (freq * 0.025862069 - */ - r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */ - } - b43_radio_write16(dev, 0x0007, (r8 << 4) | r8); - b43_radio_write16(dev, 0x0020, (r8 << 4) | r8); - b43_radio_write16(dev, 0x0021, (r8 << 4) | r8); - b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4)); - b43_radio_write16(dev, 0x002A, (r8 << 4)); - b43_radio_write16(dev, 0x002B, (r8 << 4)); - b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4)); - b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0); - b43_radio_write16(dev, 0x0035, 0x00AA); - b43_radio_write16(dev, 0x0036, 0x0085); - b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq)); - b43_radio_mask(dev, 0x003D, 0x00FF); - b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080); - b43_radio_mask(dev, 0x0035, 0xFFEF); - b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010); - b43_radio_set_tx_iq(dev); - //TODO: TSSI2dbm workaround -//FIXME b43_phy_xmitpower(dev); -} - -static void b43_radio_init2060(struct b43_wldev *dev) -{ - b43_radio_write16(dev, 0x0004, 0x00C0); - b43_radio_write16(dev, 0x0005, 0x0008); - b43_radio_write16(dev, 0x0009, 0x0040); - b43_radio_write16(dev, 0x0005, 0x00AA); - b43_radio_write16(dev, 0x0032, 0x008F); - b43_radio_write16(dev, 0x0006, 0x008F); - b43_radio_write16(dev, 0x0034, 0x008F); - b43_radio_write16(dev, 0x002C, 0x0007); - b43_radio_write16(dev, 0x0082, 0x0080); - b43_radio_write16(dev, 0x0080, 0x0000); - b43_radio_write16(dev, 0x003F, 0x00DA); - b43_radio_mask(dev, 0x0005, ~0x0008); - b43_radio_mask(dev, 0x0081, ~0x0010); - b43_radio_mask(dev, 0x0081, ~0x0020); - b43_radio_mask(dev, 0x0081, ~0x0020); - msleep(1); /* delay 400usec */ - - b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010); - msleep(1); /* delay 400usec */ - - b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008); - b43_radio_mask(dev, 0x0085, ~0x0010); - b43_radio_mask(dev, 0x0005, ~0x0008); - b43_radio_mask(dev, 0x0081, ~0x0040); - b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040); - b43_radio_write16(dev, 0x0005, - (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008); - b43_phy_write(dev, 0x0063, 0xDDC6); - b43_phy_write(dev, 0x0069, 0x07BE); - b43_phy_write(dev, 0x006A, 0x0000); - - aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev)); - - msleep(1); -} - -static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable) -{ - int i; - - if (dev->phy.rev < 3) { - if (enable) - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) { - b43_ofdmtab_write16(dev, - B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8); - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, 0xFFF8); - } - else - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) { - b43_ofdmtab_write16(dev, - B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]); - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]); - } - } else { - if (enable) - for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, 0x0820); - else - for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++) - b43_ofdmtab_write16(dev, - B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]); - } -} - -static void b43_phy_ww(struct b43_wldev *dev) -{ - u16 b, curr_s, best_s = 0xFFFF; - int i; - - b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN); - b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000); - b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300); - b43_radio_set(dev, 0x0009, 0x0080); - b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002); - b43_wa_initgains(dev); - b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5); - b = b43_phy_read(dev, B43_PHY_PWRDOWN); - b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005); - b43_radio_set(dev, 0x0004, 0x0004); - for (i = 0x10; i <= 0x20; i++) { - b43_radio_write16(dev, 0x0013, i); - curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF; - if (!curr_s) { - best_s = 0x0000; - break; - } else if (curr_s >= 0x0080) - curr_s = 0x0100 - curr_s; - if (curr_s < best_s) - best_s = curr_s; - } - b43_phy_write(dev, B43_PHY_PWRDOWN, b); - b43_radio_mask(dev, 0x0004, 0xFFFB); - b43_radio_write16(dev, 0x0013, best_s); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC); - b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80); - b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00); - b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0); - b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0); - b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF); - b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053); - b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120); - b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000); - b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017); - for (i = 0; i < 6; i++) - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011); - b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013); - b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030); - b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); -} - -static void hardware_pctl_init_aphy(struct b43_wldev *dev) -{ - //TODO -} - -void b43_phy_inita(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - - /* This lowlevel A-PHY init is also called from G-PHY init. - * So we must not access phy->a, if called from G-PHY code. - */ - B43_WARN_ON((phy->type != B43_PHYTYPE_A) && - (phy->type != B43_PHYTYPE_G)); - - might_sleep(); - - if (phy->rev >= 6) { - if (phy->type == B43_PHYTYPE_A) - b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000); - if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) - b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); - else - b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); - } - - b43_wa_all(dev); - - if (phy->type == B43_PHYTYPE_A) { - if (phy->gmode && (phy->rev < 3)) - b43_phy_set(dev, 0x0034, 0x0001); - b43_phy_rssiagc(dev, 0); - - b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN); - - b43_radio_init2060(dev); - - if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && - ((dev->dev->board_type == SSB_BOARD_BU4306) || - (dev->dev->board_type == SSB_BOARD_BU4309))) { - ; //TODO: A PHY LO - } - - if (phy->rev >= 3) - b43_phy_ww(dev); - - hardware_pctl_init_aphy(dev); - - //TODO: radar detection - } - - if ((phy->type == B43_PHYTYPE_G) && - (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)) { - b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); - } -} - -/* Initialise the TSSI->dBm lookup table */ -static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - s16 pab0, pab1, pab2; - - pab0 = (s16) (dev->dev->bus_sprom->pa1b0); - pab1 = (s16) (dev->dev->bus_sprom->pa1b1); - pab2 = (s16) (dev->dev->bus_sprom->pa1b2); - - if (pab0 != 0 && pab1 != 0 && pab2 != 0 && - pab0 != -1 && pab1 != -1 && pab2 != -1) { - /* The pabX values are set in SPROM. Use them. */ - if ((s8) dev->dev->bus_sprom->itssi_a != 0 && - (s8) dev->dev->bus_sprom->itssi_a != -1) - aphy->tgt_idle_tssi = - (s8) (dev->dev->bus_sprom->itssi_a); - else - aphy->tgt_idle_tssi = 62; - aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, - pab1, pab2); - if (!aphy->tssi2dbm) - return -ENOMEM; - } else { - /* pabX values not set in SPROM, - * but APHY needs a generated table. */ - aphy->tssi2dbm = NULL; - b43err(dev->wl, "Could not generate tssi2dBm " - "table (wrong SPROM info)!\n"); - return -ENODEV; - } - - return 0; -} - -static int b43_aphy_op_allocate(struct b43_wldev *dev) -{ - struct b43_phy_a *aphy; - int err; - - aphy = kzalloc(sizeof(*aphy), GFP_KERNEL); - if (!aphy) - return -ENOMEM; - dev->phy.a = aphy; - - err = b43_aphy_init_tssi2dbm_table(dev); - if (err) - goto err_free_aphy; - - return 0; - -err_free_aphy: - kfree(aphy); - dev->phy.a = NULL; - - return err; -} - -static void b43_aphy_op_prepare_structs(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - const void *tssi2dbm; - int tgt_idle_tssi; - - /* tssi2dbm table is constant, so it is initialized at alloc time. - * Save a copy of the pointer. */ - tssi2dbm = aphy->tssi2dbm; - tgt_idle_tssi = aphy->tgt_idle_tssi; - - /* Zero out the whole PHY structure. */ - memset(aphy, 0, sizeof(*aphy)); - - aphy->tssi2dbm = tssi2dbm; - aphy->tgt_idle_tssi = tgt_idle_tssi; - - //TODO init struct b43_phy_a - -} - -static void b43_aphy_op_free(struct b43_wldev *dev) -{ - struct b43_phy *phy = &dev->phy; - struct b43_phy_a *aphy = phy->a; - - kfree(aphy->tssi2dbm); - aphy->tssi2dbm = NULL; - - kfree(aphy); - dev->phy.a = NULL; -} - -static int b43_aphy_op_init(struct b43_wldev *dev) -{ - b43_phy_inita(dev); - - return 0; -} - -static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset) -{ - /* OFDM registers are base-registers for the A-PHY. */ - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { - offset &= ~B43_PHYROUTE; - offset |= B43_PHYROUTE_BASE; - } - -#if B43_DEBUG - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { - /* Ext-G registers are only available on G-PHYs */ - b43err(dev->wl, "Invalid EXT-G PHY access at " - "0x%04X on A-PHY\n", offset); - dump_stack(); - } - if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) { - /* N-BMODE registers are only available on N-PHYs */ - b43err(dev->wl, "Invalid N-BMODE PHY access at " - "0x%04X on A-PHY\n", offset); - dump_stack(); - } -#endif /* B43_DEBUG */ - - return offset; -} - -static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg) -{ - reg = adjust_phyreg(dev, reg); - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - return b43_read16(dev, B43_MMIO_PHY_DATA); -} - -static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - reg = adjust_phyreg(dev, reg); - b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); - b43_write16(dev, B43_MMIO_PHY_DATA, value); -} - -static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - /* A-PHY needs 0x40 for read access */ - reg |= 0x40; - - b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); - return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); -} - -static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) -{ - /* Register 1 is a 32-bit register. */ - B43_WARN_ON(reg == 1); - - b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); - b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); -} - -static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev) -{ - return (dev->phy.rev >= 5); -} - -static void b43_aphy_op_software_rfkill(struct b43_wldev *dev, - bool blocked) -{ - struct b43_phy *phy = &dev->phy; - - if (!blocked) { - if (phy->radio_on) - return; - b43_radio_write16(dev, 0x0004, 0x00C0); - b43_radio_write16(dev, 0x0005, 0x0008); - b43_phy_mask(dev, 0x0010, 0xFFF7); - b43_phy_mask(dev, 0x0011, 0xFFF7); - b43_radio_init2060(dev); - } else { - b43_radio_write16(dev, 0x0004, 0x00FF); - b43_radio_write16(dev, 0x0005, 0x00FB); - b43_phy_set(dev, 0x0010, 0x0008); - b43_phy_set(dev, 0x0011, 0x0008); - } -} - -static int b43_aphy_op_switch_channel(struct b43_wldev *dev, - unsigned int new_channel) -{ - if (new_channel > 200) - return -EINVAL; - aphy_channel_switch(dev, new_channel); - - return 0; -} - -static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev) -{ - return 36; /* Default to channel 36 */ -} - -static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) -{//TODO - struct b43_phy *phy = &dev->phy; - u16 tmp; - int autodiv = 0; - - if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1) - autodiv = 1; - - b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); - - b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, - (autodiv ? B43_ANTENNA_AUTO1 : antenna) << - B43_PHY_BBANDCFG_RXANT_SHIFT); - - if (autodiv) { - tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); - if (antenna == B43_ANTENNA_AUTO1) - tmp &= ~B43_PHY_ANTDWELL_AUTODIV1; - else - tmp |= B43_PHY_ANTDWELL_AUTODIV1; - b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); - } - if (phy->rev < 3) - b43_phy_maskset(dev, B43_PHY_ANTDWELL, 0xFF00, 0x24); - else { - b43_phy_set(dev, B43_PHY_OFDM61, 0x10); - if (phy->rev == 3) { - b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x1D); - b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); - } else { - b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x3A); - b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); - } - } - - b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); -} - -static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev) -{//TODO -} - -static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev, - bool ignore_tssi) -{//TODO - return B43_TXPWR_RES_DONE; -} - -static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev) -{//TODO -} - -static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev) -{//TODO -} - -static const struct b43_phy_operations b43_phyops_a = { - .allocate = b43_aphy_op_allocate, - .free = b43_aphy_op_free, - .prepare_structs = b43_aphy_op_prepare_structs, - .init = b43_aphy_op_init, - .phy_read = b43_aphy_op_read, - .phy_write = b43_aphy_op_write, - .radio_read = b43_aphy_op_radio_read, - .radio_write = b43_aphy_op_radio_write, - .supports_hwpctl = b43_aphy_op_supports_hwpctl, - .software_rfkill = b43_aphy_op_software_rfkill, - .switch_analog = b43_phyop_switch_analog_generic, - .switch_channel = b43_aphy_op_switch_channel, - .get_default_chan = b43_aphy_op_get_default_chan, - .set_rx_antenna = b43_aphy_op_set_rx_antenna, - .recalc_txpower = b43_aphy_op_recalc_txpower, - .adjust_txpower = b43_aphy_op_adjust_txpower, - .pwork_15sec = b43_aphy_op_pwork_15sec, - .pwork_60sec = b43_aphy_op_pwork_60sec, -}; |