diff options
Diffstat (limited to 'drivers/pinctrl/mediatek')
| -rw-r--r-- | drivers/pinctrl/mediatek/Kconfig | 13 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/Makefile | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt6397.c | 77 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8127.c | 358 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8135.c | 13 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mt8173.c | 377 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 164 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 75 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h | 424 | ||||
| -rw-r--r-- | drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h | 1318 |
10 files changed, 2559 insertions, 262 deletions
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 6b3551cad..02f6f92df 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -15,6 +15,12 @@ config PINCTRL_MT8135 default MACH_MT8135 select PINCTRL_MTK_COMMON +config PINCTRL_MT8127 + bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127 + depends on OF + default MACH_MT8127 + select PINCTRL_MTK_COMMON + # For ARMv8 SoCs config PINCTRL_MT8173 bool "Mediatek MT8173 pin control" @@ -23,4 +29,11 @@ config PINCTRL_MT8173 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_COMMON +# For PMIC +config PINCTRL_MT6397 + bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397 + depends on OF + default MFD_MT6397 + select PINCTRL_MTK_COMMON + endif diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index d8606a217..eb923d64d 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,4 +3,6 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o +obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o +obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c new file mode 100644 index 000000000..f9751ae28 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/mfd/mt6397/core.h> + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6397.h" + +#define MT6397_PIN_REG_BASE 0xc000 + +static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { + .pins = mtk_pins_mt6397, + .npins = ARRAY_SIZE(mtk_pins_mt6397), + .dir_offset = (MT6397_PIN_REG_BASE + 0x000), + .ies_offset = MTK_PINCTRL_NOT_SUPPORT, + .smt_offset = MTK_PINCTRL_NOT_SUPPORT, + .pullen_offset = (MT6397_PIN_REG_BASE + 0x020), + .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040), + .dout_offset = (MT6397_PIN_REG_BASE + 0x080), + .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), + .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), + .type1_start = 41, + .type1_end = 41, + .port_shf = 3, + .port_mask = 0x3, + .port_align = 2, +}; + +static int mt6397_pinctrl_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6397; + + mt6397 = dev_get_drvdata(pdev->dev.parent); + return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap); +} + +static const struct of_device_id mt6397_pctrl_match[] = { + { .compatible = "mediatek,mt6397-pinctrl", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt6397_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt6397_pinctrl_probe, + .driver = { + .name = "mediatek-mt6397-pinctrl", + .of_match_table = mt6397_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver"); +MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c new file mode 100644 index 000000000..b317b0b66 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com> + * Yingjoe Chen <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/regmap.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8127.h" + +static const struct mtk_drv_group_desc mt8127_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8127_pin_drv[] = { + MTK_PIN_DRV_GRP(0, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(1, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(2, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(3, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(4, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(5, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(6, 0xb00, 0, 1), + MTK_PIN_DRV_GRP(7, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(8, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(9, 0xb00, 12, 1), + MTK_PIN_DRV_GRP(10, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(11, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(12, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(13, 0xb00, 8, 1), + MTK_PIN_DRV_GRP(14, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(15, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(16, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(17, 0xb10, 4, 0), + MTK_PIN_DRV_GRP(18, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(19, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(20, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(21, 0xb10, 8, 0), + MTK_PIN_DRV_GRP(22, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(23, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(24, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(25, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(26, 0xb20, 0, 0), + MTK_PIN_DRV_GRP(27, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(28, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(29, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(30, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(31, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(32, 0xb20, 4, 0), + MTK_PIN_DRV_GRP(33, 0xb30, 4, 1), + MTK_PIN_DRV_GRP(34, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(35, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(36, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(37, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(38, 0xb30, 8, 1), + MTK_PIN_DRV_GRP(39, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(40, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(41, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(42, 0xb30, 12, 1), + MTK_PIN_DRV_GRP(43, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(44, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(45, 0xb40, 12, 0), + MTK_PIN_DRV_GRP(46, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(47, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(48, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(49, 0xb50, 0, 2), + MTK_PIN_DRV_GRP(50, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(51, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(52, 0xb70, 0, 1), + MTK_PIN_DRV_GRP(53, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(54, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(55, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(56, 0xb50, 12, 1), + MTK_PIN_DRV_GRP(59, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(60, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(61, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(62, 0xb40, 0, 1), + MTK_PIN_DRV_GRP(63, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(64, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(65, 0xb40, 4, 1), + MTK_PIN_DRV_GRP(66, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(67, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(68, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(69, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(70, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(71, 0xb40, 8, 1), + MTK_PIN_DRV_GRP(72, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(73, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(74, 0xb50, 4, 1), + MTK_PIN_DRV_GRP(79, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(80, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(81, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(82, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(83, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(84, 0xb50, 8, 1), + MTK_PIN_DRV_GRP(85, 0xce0, 0, 2), + MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2), + MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2), + MTK_PIN_DRV_GRP(117, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(118, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(119, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(120, 0xb60, 12, 1), + MTK_PIN_DRV_GRP(121, 0xc80, 0, 2), + MTK_PIN_DRV_GRP(122, 0xc70, 0, 2), + MTK_PIN_DRV_GRP(123, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(124, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(125, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(126, 0xc90, 0, 2), + MTK_PIN_DRV_GRP(127, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(128, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(129, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(130, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(131, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(132, 0xc10, 0, 2), + MTK_PIN_DRV_GRP(133, 0xc00, 0, 2), + MTK_PIN_DRV_GRP(134, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(135, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(136, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(137, 0xc20, 0, 2), + MTK_PIN_DRV_GRP(142, 0xb50, 0, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */ + MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */ + MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */ + MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */ + MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */ + MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */ + MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */ + MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */ + MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */ + MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */ + MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */ + MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */ + MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */ + MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */ + MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */ + MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */ + MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */ + MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */ + MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */ + MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */ + MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */ + MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */ + MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */ + MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */ + MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */ + MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */ +}; + +static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd, + ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0); +} + +static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4), + MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4), + MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4), + MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13), +}; + +static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11), + MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10), + MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11), + MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12), + MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13), + MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10), + MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15), + MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11), + MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11), + MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3), + MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7), + MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11), + MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15), + MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7), + MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11), + MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11), + MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3), + MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7), + MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11), + MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15), + MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15), + MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11), + MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7), + MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3), + MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3), + MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11), + MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11), + MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15), + MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11), + MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7), + MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3), + MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), +}; + +static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set, + ARRAY_SIZE(mt8127_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set, + ARRAY_SIZE(mt8127_smt_set), pin, align, value); + return -EINVAL; +} + + +static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { + .pins = mtk_pins_mt8127, + .npins = ARRAY_SIZE(mtk_pins_mt8127), + .grp_desc = mt8127_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp), + .pin_drv_grp = mt8127_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv), + .spec_pull_set = mt8127_spec_pull_set, + .spec_ies_smt_set = mt8127_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0100, + .pullsel_offset = 0x0200, + .dout_offset = 0x0400, + .din_offset = 0x0500, + .pinmux_offset = 0x0600, + .type1_start = 143, + .type1_end = 143, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .eint_offsets = { + .name = "mt8127_eint", + .stat = 0x000, + .ack = 0x040, + .mask = 0x080, + .mask_set = 0x0c0, + .mask_clr = 0x100, + .sens = 0x140, + .sens_set = 0x180, + .sens_clr = 0x1c0, + .soft = 0x200, + .soft_set = 0x240, + .soft_clr = 0x280, + .pol = 0x300, + .pol_set = 0x340, + .pol_clr = 0x380, + .dom_en = 0x400, + .dbnc_ctrl = 0x500, + .dbnc_set = 0x600, + .dbnc_clr = 0x700, + .port_mask = 7, + .ports = 6, + }, + .ap_num = 143, + .db_cnt = 16, +}; + +static int mt8127_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL); +} + +static const struct of_device_id mt8127_pctrl_match[] = { + { .compatible = "mediatek,mt8127-pinctrl", }, + { } +}; +MODULE_DEVICE_TABLE(of, mt8127_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt8127_pinctrl_probe, + .driver = { + .name = "mediatek-mt8127-pinctrl", + .of_match_table = mt8127_pctrl_match, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} + +module_init(mtk_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver"); +MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index f1e1e187c..404f11785 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -32,12 +32,12 @@ #define R1_BASE2 0x250 struct mtk_spec_pull_set { - unsigned int pin; - unsigned int pupd_offset; + unsigned char pin; unsigned char pupd_bit; - unsigned int r0_offset; + unsigned short pupd_offset; + unsigned short r0_offset; + unsigned short r1_offset; unsigned char r0_bit; - unsigned int r1_offset; unsigned char r1_bit; }; @@ -305,7 +305,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .pullen_offset = 0x0200, .smt_offset = 0x0300, .pullsel_offset = 0x0400, - .invser_offset = 0x0600, .dout_offset = 0x0800, .din_offset = 0x0A00, .pinmux_offset = 0x0C00, @@ -314,7 +313,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, - .chip_type = MTK_CHIP_TYPE_BASE, .eint_offsets = { .name = "mt8135_eint", .stat = 0x000, @@ -344,7 +342,7 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { static int mt8135_pinctrl_probe(struct platform_device *pdev) { - return mtk_pctrl_init(pdev, &mt8135_pinctrl_data); + return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL); } static const struct of_device_id mt8135_pctrl_match[] = { @@ -359,7 +357,6 @@ static struct platform_driver mtk_pinctrl_driver = { .probe = mt8135_pinctrl_probe, .driver = { .name = "mediatek-mt8135-pinctrl", - .owner = THIS_MODULE, .of_match_table = mt8135_pctrl_match, }, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 412ea8483..d0c811d5f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -18,6 +18,7 @@ #include <linux/of_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> +#include <linux/pinctrl/pinconf-generic.h> #include <dt-bindings/pinctrl/mt65xx.h> #include "pinctrl-mtk-common.h" @@ -25,228 +26,172 @@ #define DRV_BASE 0xb00 -/** - * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. - * @start: The start pin number of those special pins. - * @end: The end pin number of those special pins. - * @offset: The offset of special setting register. - * @bit: The bit of special setting register. - */ -struct mtk_pin_ies_smt_set { - unsigned int start; - unsigned int end; - unsigned int offset; - unsigned char bit; +static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */ + MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */ + MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */ + MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */ + MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */ + MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */ + + MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */ + MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */ + MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */ + MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */ + MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */ + MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */ + MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */ + MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */ + MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */ + MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */ + MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */ + MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */ + + MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */ + MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ + MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ + MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ + MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ + MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */ + + MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ + MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ + MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ + MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ + MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */ + MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */ + + MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ + MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ + MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ + MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ + MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */ + MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ }; -#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ - { \ - .start = _start, \ - .end = _end, \ - .bit = _bit, \ - .offset = _offset, \ - } - -/** - * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting. - * @pin: The pin number. - * @offset: The offset of special pull up/down setting register. - * @pupd_bit: The pull up/down bit in this register. - * @r0_bit: The r0 bit of pull resistor. - * @r1_bit: The r1 bit of pull resistor. - */ -struct mtk_pin_spec_pupd_set { - unsigned int pin; - unsigned int offset; - unsigned char pupd_bit; - unsigned char r1_bit; - unsigned char r0_bit; -}; - -#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \ - { \ - .pin = _pin, \ - .offset = _offset, \ - .pupd_bit = _pupd, \ - .r1_bit = _r1, \ - .r0_bit = _r0, \ - } - -static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = { - MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */ - MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */ - MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */ - MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */ - MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */ - MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */ - - MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */ - MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */ - MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */ - MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */ - MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */ - MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */ - MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */ - MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */ - MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */ - MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */ - MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */ - MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */ - - MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */ - MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */ - MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */ - MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */ - MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */ - MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */ - - MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */ - MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */ - MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */ - MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */ - MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */ - MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */ - - MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */ - MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */ - MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */ - MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */ - MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */ - MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ -}; - -static int spec_pull_set(struct regmap *regmap, unsigned int pin, +static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, unsigned char align, bool isup, unsigned int r1r0) { - unsigned int i; - unsigned int reg_pupd, reg_set, reg_rst; - unsigned int bit_pupd, bit_r0, bit_r1; - const struct mtk_pin_spec_pupd_set *spec_pupd_pin; - bool find = false; - - for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) { - if (pin == mt8173_spec_pupd[i].pin) { - find = true; - break; - } - } - - if (!find) - return -EINVAL; - - spec_pupd_pin = mt8173_spec_pupd + i; - reg_set = spec_pupd_pin->offset + align; - reg_rst = spec_pupd_pin->offset + (align << 1); - - if (isup) - reg_pupd = reg_rst; - else - reg_pupd = reg_set; - - bit_pupd = BIT(spec_pupd_pin->pupd_bit); - regmap_write(regmap, reg_pupd, bit_pupd); - - bit_r0 = BIT(spec_pupd_pin->r0_bit); - bit_r1 = BIT(spec_pupd_pin->r1_bit); - - switch (r1r0) { - case MTK_PUPD_SET_R1R0_00: - regmap_write(regmap, reg_rst, bit_r0); - regmap_write(regmap, reg_rst, bit_r1); - break; - case MTK_PUPD_SET_R1R0_01: - regmap_write(regmap, reg_set, bit_r0); - regmap_write(regmap, reg_rst, bit_r1); - break; - case MTK_PUPD_SET_R1R0_10: - regmap_write(regmap, reg_rst, bit_r0); - regmap_write(regmap, reg_set, bit_r1); - break; - case MTK_PUPD_SET_R1R0_11: - regmap_write(regmap, reg_set, bit_r0); - regmap_write(regmap, reg_set, bit_r1); - break; - default: - return -EINVAL; - } - - return 0; + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, + ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); } -static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { - MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), - MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), - MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), - MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), - MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), - MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), - MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), - MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), - MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), - MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), - MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), - MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), - MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), - MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), - MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), - MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), - MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), - MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), - MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), - MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), - MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), - MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), - MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), - MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), - MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), - MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), - MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), - MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), - MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), - MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), - MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), - MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), - MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), - MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), - MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), - MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), - MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), - MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), - MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), - MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), - MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), - MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), - MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), - MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), - MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), - MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) +static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10), + MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2), + MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3), + MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13), + MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13), + MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13), + MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7), + MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0), + MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11), + MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12), + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13), + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13), + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13), + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13), + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13), + MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14), + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13), + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13), + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0), + MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1), + MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13), + MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14), + MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15), + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13), + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13), + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13), + MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4), + MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1), + MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2), + MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5), + MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6), + MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8), + MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9), + MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8), + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) }; -static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value) -{ - unsigned int i, reg_addr, bit; - bool find = false; - - for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { - if (pin >= mt8173_ies_smt_set[i].start && - pin <= mt8173_ies_smt_set[i].end) { - find = true; - break; - } - } - - if (!find) - return -EINVAL; - - if (value) - reg_addr = mt8173_ies_smt_set[i].offset + align; - else - reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); +static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3), + MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14), + MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14), + MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14), + MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14), + MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4), + MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5), + MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7), + MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14), + MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14), + MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14), + MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14), + MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14), + MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14), + MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14), + MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14), + MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14), + MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14), + MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14), + MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14), + MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4), + MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8), + MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9), + MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8), + MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) +}; - bit = BIT(mt8173_ies_smt_set[i].bit); - regmap_write(regmap, reg_addr, bit); - return 0; +static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, + ARRAY_SIZE(mt8173_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, + ARRAY_SIZE(mt8173_smt_set), pin, align, value); + return -EINVAL; } static const struct mtk_drv_group_desc mt8173_drv_grp[] = { @@ -382,8 +327,8 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), .pin_drv_grp = mt8173_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), - .spec_pull_set = spec_pull_set, - .spec_ies_smt_set = spec_ies_smt_set, + .spec_pull_set = mt8173_spec_pull_set, + .spec_ies_smt_set = mt8173_ies_smt_set, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, @@ -424,7 +369,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { static int mt8173_pinctrl_probe(struct platform_device *pdev) { - return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); + return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL); } static const struct of_device_id mt8173_pctrl_match[] = { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 474812e2b..ad1ea1695 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); } -static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, - int value, enum pin_config_param param) +static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, + int value, enum pin_config_param arg) { unsigned int reg_addr, offset; unsigned int bit; - int ret; + + /** + * Due to some soc are not support ies/smt config, add this special + * control to handle it. + */ + if (!pctl->devdata->spec_ies_smt_set && + pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT && + arg == PIN_CONFIG_INPUT_ENABLE) + return -EINVAL; + + if (!pctl->devdata->spec_ies_smt_set && + pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT && + arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return -EINVAL; /* * Due to some pins are irregular, their input enable and smt - * control register are discontinuous, but they are mapping together. - * So we need this special handle. + * control register are discontinuous, so we need this special handle. */ if (pctl->devdata->spec_ies_smt_set) { - ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, value); - if (!ret) - return; + return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), + pin, pctl->devdata->port_align, value, arg); } bit = BIT(pin & 0xf); - if (param == PIN_CONFIG_INPUT_ENABLE) + if (arg == PIN_CONFIG_INPUT_ENABLE) offset = pctl->devdata->ies_offset; else offset = pctl->devdata->smt_offset; @@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); + return 0; +} + +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, + unsigned int pin, unsigned char align, int value) +{ + unsigned int i, reg_addr, bit; + + for (i = 0; i < info_num; i++) { + if (pin >= ies_smt_infos[i].start && + pin <= ies_smt_infos[i].end) { + break; + } + } + + if (i == info_num) + return -EINVAL; + + if (value) + reg_addr = ies_smt_infos[i].offset + align; + else + reg_addr = ies_smt_infos[i].offset + (align << 1); + + bit = BIT(ies_smt_infos[i].bit); + regmap_write(regmap, reg_addr, bit); + return 0; } static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( @@ -186,6 +223,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, return -EINVAL; } +int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, + unsigned int info_num, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + unsigned int i; + unsigned int reg_pupd, reg_set, reg_rst; + unsigned int bit_pupd, bit_r0, bit_r1; + const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; + bool find = false; + + for (i = 0; i < info_num; i++) { + if (pin == pupd_infos[i].pin) { + find = true; + break; + } + } + + if (!find) + return -EINVAL; + + spec_pupd_pin = pupd_infos + i; + reg_set = spec_pupd_pin->offset + align; + reg_rst = spec_pupd_pin->offset + (align << 1); + + if (isup) + reg_pupd = reg_rst; + else + reg_pupd = reg_set; + + bit_pupd = BIT(spec_pupd_pin->pupd_bit); + regmap_write(regmap, reg_pupd, bit_pupd); + + bit_r0 = BIT(spec_pupd_pin->r0_bit); + bit_r1 = BIT(spec_pupd_pin->r1_bit); + + switch (r1r0) { + case MTK_PUPD_SET_R1R0_00: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_01: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_rst, bit_r1); + break; + case MTK_PUPD_SET_R1R0_10: + regmap_write(regmap, reg_rst, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + case MTK_PUPD_SET_R1R0_11: + regmap_write(regmap, reg_set, bit_r0); + regmap_write(regmap, reg_set, bit_r1); + break; + default: + return -EINVAL; + } + + return 0; +} + static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, unsigned int pin, bool enable, bool isup, unsigned int arg) { @@ -235,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param, enum pin_config_param arg) { + int ret = 0; struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); switch (param) { case PIN_CONFIG_BIAS_DISABLE: - mtk_pconf_set_pull_select(pctl, pin, false, false, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg); break; case PIN_CONFIG_BIAS_PULL_UP: - mtk_pconf_set_pull_select(pctl, pin, true, true, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg); break; case PIN_CONFIG_BIAS_PULL_DOWN: - mtk_pconf_set_pull_select(pctl, pin, true, false, arg); + ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg); break; case PIN_CONFIG_INPUT_ENABLE: - mtk_pconf_set_ies_smt(pctl, pin, arg, param); + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_OUTPUT: mtk_gpio_set(pctl->chip, pin, arg); - mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); + ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - mtk_pconf_set_ies_smt(pctl, pin, arg, param); + ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param); break; case PIN_CONFIG_DRIVE_STRENGTH: - mtk_pconf_set_driving(pctl, pin, arg); + ret = mtk_pconf_set_driving(pctl, pin, arg); break; default: - return -EINVAL; + ret = -EINVAL; } - return 0; + return ret; } static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, @@ -283,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, { struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct mtk_pinctrl_group *g = &pctl->groups[group]; - int i; + int i, ret; for (i = 0; i < num_configs; i++) { - mtk_pconf_parse_conf(pctldev, g->pin, + ret = mtk_pconf_parse_conf(pctldev, g->pin, pinconf_to_config_param(configs[i]), pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; g->config = configs[i]; } @@ -1109,7 +1209,8 @@ static struct pinctrl_desc mtk_pctrl_desc = { }; int mtk_pctrl_init(struct platform_device *pdev, - const struct mtk_pinctrl_devdata *data) + const struct mtk_pinctrl_devdata *data, + struct regmap *regmap) { struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; @@ -1135,6 +1236,11 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->regmap1 = syscon_node_to_regmap(node); if (IS_ERR(pctl->regmap1)) return PTR_ERR(pctl->regmap1); + } else if (regmap) { + pctl->regmap1 = regmap; + } else { + dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); + return -EINVAL; } /* Only 8135 has two base addr, other SoCs have only one. */ @@ -1165,9 +1271,9 @@ int mtk_pctrl_init(struct platform_device *pdev, mtk_pctrl_desc.npins = pctl->devdata->npins; pctl->dev = &pdev->dev; pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); - if (!pctl->pctl_dev) { + if (IS_ERR(pctl->pctl_dev)) { dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return -EINVAL; + return PTR_ERR(pctl->pctl_dev); } pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); @@ -1176,11 +1282,11 @@ int mtk_pctrl_init(struct platform_device *pdev, goto pctrl_error; } - pctl->chip = &mtk_gpio_chip; + *pctl->chip = mtk_gpio_chip; pctl->chip->ngpio = pctl->devdata->npins; pctl->chip->label = dev_name(&pdev->dev); pctl->chip->dev = &pdev->dev; - pctl->chip->base = 0; + pctl->chip->base = -1; ret = gpiochip_add(pctl->chip); if (ret) { @@ -1196,6 +1302,9 @@ int mtk_pctrl_init(struct platform_device *pdev, goto chip_error; } + if (!of_property_read_bool(np, "interrupt-controller")) + return 0; + /* Get EINT register base from dts. */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -1242,8 +1351,7 @@ int mtk_pctrl_init(struct platform_device *pdev, set_irq_flags(virq, IRQF_VALID); }; - irq_set_chained_handler(irq, mtk_eint_irq_handler); - irq_set_handler_data(irq, pctl); + irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); set_irq_flags(irq, IRQF_VALID); return 0; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 375771db9..30213e514 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -17,16 +17,17 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> +#include <linux/pinctrl/pinconf-generic.h> #define NO_EINT_SUPPORT 255 -#define MTK_CHIP_TYPE_BASE 0 -#define MTK_CHIP_TYPE_PMIC 1 #define MT_EDGE_SENSITIVE 0 #define MT_LEVEL_SENSITIVE 1 #define EINT_DBNC_SET_DBNC_BITS 4 #define EINT_DBNC_RST_BIT (0x1 << 1) #define EINT_DBNC_SET_EN (0x1 << 0) +#define MTK_PINCTRL_NOT_SUPPORT (0xffff) + struct mtk_desc_function { const char *name; unsigned char muxval; @@ -39,7 +40,6 @@ struct mtk_desc_eint { struct mtk_desc_pin { struct pinctrl_pin_desc pin; - const char *chip; const struct mtk_desc_eint eint; const struct mtk_desc_function *functions; }; @@ -47,7 +47,6 @@ struct mtk_desc_pin { #define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ { \ .pin = _pin, \ - .chip = _chip, \ .eint = _eint, \ .functions = (struct mtk_desc_function[]){ \ __VA_ARGS__, { } }, \ @@ -107,8 +106,8 @@ struct mtk_drv_group_desc { * @grp: The group for this pin belongs to. */ struct mtk_pin_drv_grp { - unsigned int pin; - unsigned int offset; + unsigned short pin; + unsigned short offset; unsigned char bit; unsigned char grp; }; @@ -121,6 +120,54 @@ struct mtk_pin_drv_grp { .grp = _grp, \ } +/** + * struct mtk_pin_spec_pupd_set_samereg + * - For special pins' pull up/down setting which resides in same register + * @pin: The pin number. + * @offset: The offset of special pull up/down setting register. + * @pupd_bit: The pull up/down bit in this register. + * @r0_bit: The r0 bit of pull resistor. + * @r1_bit: The r1 bit of pull resistor. + */ +struct mtk_pin_spec_pupd_set_samereg { + unsigned short pin; + unsigned short offset; + unsigned char pupd_bit; + unsigned char r1_bit; + unsigned char r0_bit; +}; + +#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ + { \ + .pin = _pin, \ + .offset = _offset, \ + .pupd_bit = _pupd, \ + .r1_bit = _r1, \ + .r0_bit = _r0, \ + } + +/** + * struct mtk_pin_ies_set - For special pins' ies and smt setting. + * @start: The start pin number of those special pins. + * @end: The end pin number of those special pins. + * @offset: The offset of special setting register. + * @bit: The bit of special setting register. + */ +struct mtk_pin_ies_smt_set { + unsigned short start; + unsigned short end; + unsigned short offset; + unsigned char bit; +}; + +#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ + { \ + .start = _start, \ + .end = _end, \ + .bit = _bit, \ + .offset = _offset, \ + } + struct mtk_eint_offsets { const char *name; unsigned int stat; @@ -186,14 +233,13 @@ struct mtk_pinctrl_devdata { int (*spec_pull_set)(struct regmap *reg, unsigned int pin, unsigned char align, bool isup, unsigned int arg); int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, - unsigned char align, int value); + unsigned char align, int value, enum pin_config_param arg); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; unsigned int pullen_offset; unsigned int pullsel_offset; unsigned int drv_offset; - unsigned int invser_offset; unsigned int dout_offset; unsigned int din_offset; unsigned int pinmux_offset; @@ -202,7 +248,6 @@ struct mtk_pinctrl_devdata { unsigned char port_shf; unsigned char port_mask; unsigned char port_align; - unsigned char chip_type; struct mtk_eint_offsets eint_offsets; unsigned int ap_num; unsigned int db_cnt; @@ -224,6 +269,16 @@ struct mtk_pinctrl { }; int mtk_pctrl_init(struct platform_device *pdev, - const struct mtk_pinctrl_devdata *data); + const struct mtk_pinctrl_devdata *data, + struct regmap *regmap); + +int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, + const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, + unsigned int info_num, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0); + +int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, + const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, + unsigned int pin, unsigned char align, int value); #endif /* __PINCTRL_MTK_COMMON_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h new file mode 100644 index 000000000..4eb98ddb4 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h @@ -0,0 +1,424 @@ +#ifndef __PINCTRL_MTK_MT6397_H +#define __PINCTRL_MTK_MT6397_H + +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6397[] = { + MTK_PIN( + PINCTRL_PIN(0, "INT"), + "N2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "INT") + ), + MTK_PIN( + PINCTRL_PIN(1, "SRCVOLTEN"), + "M4", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SRCVOLTEN"), + MTK_FUNCTION(6, "TEST_CK1") + ), + MTK_PIN( + PINCTRL_PIN(2, "SRCLKEN_PERI"), + "M2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SRCLKEN_PERI"), + MTK_FUNCTION(6, "TEST_CK2") + ), + MTK_PIN( + PINCTRL_PIN(3, "RTC_32K1V8"), + "K3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "RTC_32K1V8"), + MTK_FUNCTION(6, "TEST_CK3") + ), + MTK_PIN( + PINCTRL_PIN(4, "WRAP_EVENT"), + "J2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "WRAP_EVENT") + ), + MTK_PIN( + PINCTRL_PIN(5, "SPI_CLK"), + "L4", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI_CLK") + ), + MTK_PIN( + PINCTRL_PIN(6, "SPI_CSN"), + "J3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI_CSN") + ), + MTK_PIN( + PINCTRL_PIN(7, "SPI_MOSI"), + "J1", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(8, "SPI_MISO"), + "L3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SPI_MISO") + ), + MTK_PIN( + PINCTRL_PIN(9, "AUD_CLK_MOSI"), + "H2", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(6, "TEST_IN0"), + MTK_FUNCTION(7, "TEST_OUT0") + ), + MTK_PIN( + PINCTRL_PIN(10, "AUD_DAT_MISO"), + "H3", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "AUD_MISO"), + MTK_FUNCTION(6, "TEST_IN1"), + MTK_FUNCTION(7, "TEST_OUT1") + ), + MTK_PIN( + PINCTRL_PIN(11, "AUD_DAT_MOSI"), + "H1", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "AUD_MOSI"), + MTK_FUNCTION(6, "TEST_IN2"), + MTK_FUNCTION(7, "TEST_OUT2") + ), + MTK_PIN( + PINCTRL_PIN(12, "COL0"), + "F3", "mt6397", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "COL0_USBDL"), + MTK_FUNCTION(2, "EINT10_1X"), + MTK_FUNCTION(3, "PWM1_3X"), + MTK_FUNCTION(6, "TEST_IN3"), + MTK_FUNCTION(7, "TEST_OUT3") + ), + MTK_PIN( + PINCTRL_PIN(13, "COL1"), + "G8", "mt6397", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "COL1"), + MTK_FUNCTION(2, "EINT11_1X"), + MTK_FUNCTION(3, "SCL0_2X"), + MTK_FUNCTION(6, "TEST_IN4"), + MTK_FUNCTION(7, "TEST_OUT4") + ), + MTK_PIN( + PINCTRL_PIN(14, "COL2"), + "H4", "mt6397", + MTK_EINT_FUNCTION(2, 12), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "COL2"), + MTK_FUNCTION(2, "EINT12_1X"), + MTK_FUNCTION(3, "SDA0_2X"), + MTK_FUNCTION(6, "TEST_IN5"), + MTK_FUNCTION(7, "TEST_OUT5") + ), + MTK_PIN( + PINCTRL_PIN(15, "COL3"), + "G2", "mt6397", + MTK_EINT_FUNCTION(2, 13), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "COL3"), + MTK_FUNCTION(2, "EINT13_1X"), + MTK_FUNCTION(3, "SCL1_2X"), + MTK_FUNCTION(6, "TEST_IN6"), + MTK_FUNCTION(7, "TEST_OUT6") + ), + MTK_PIN( + PINCTRL_PIN(16, "COL4"), + "F2", "mt6397", + MTK_EINT_FUNCTION(2, 14), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "COL4"), + MTK_FUNCTION(2, "EINT14_1X"), + MTK_FUNCTION(3, "SDA1_2X"), + MTK_FUNCTION(6, "TEST_IN7"), + MTK_FUNCTION(7, "TEST_OUT7") + ), + MTK_PIN( + PINCTRL_PIN(17, "COL5"), + "G7", "mt6397", + MTK_EINT_FUNCTION(2, 15), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "COL5"), + MTK_FUNCTION(2, "EINT15_1X"), + MTK_FUNCTION(3, "SCL2_2X"), + MTK_FUNCTION(6, "TEST_IN8"), + MTK_FUNCTION(7, "TEST_OUT8") + ), + MTK_PIN( + PINCTRL_PIN(18, "COL6"), + "J6", "mt6397", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "COL6"), + MTK_FUNCTION(2, "EINT16_1X"), + MTK_FUNCTION(3, "SDA2_2X"), + MTK_FUNCTION(4, "GPIO32K_0"), + MTK_FUNCTION(5, "GPIO26M_0"), + MTK_FUNCTION(6, "TEST_IN9"), + MTK_FUNCTION(7, "TEST_OUT9") + ), + MTK_PIN( + PINCTRL_PIN(19, "COL7"), + "J5", "mt6397", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "COL7"), + MTK_FUNCTION(2, "EINT17_1X"), + MTK_FUNCTION(3, "PWM2_3X"), + MTK_FUNCTION(4, "GPIO32K_1"), + MTK_FUNCTION(5, "GPIO26M_1"), + MTK_FUNCTION(6, "TEST_IN10"), + MTK_FUNCTION(7, "TEST_OUT10") + ), + MTK_PIN( + PINCTRL_PIN(20, "ROW0"), + "L7", "mt6397", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "ROW0"), + MTK_FUNCTION(2, "EINT18_1X"), + MTK_FUNCTION(3, "SCL0_3X"), + MTK_FUNCTION(6, "TEST_IN11"), + MTK_FUNCTION(7, "TEST_OUT11") + ), + MTK_PIN( + PINCTRL_PIN(21, "ROW1"), + "P1", "mt6397", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "ROW1"), + MTK_FUNCTION(2, "EINT19_1X"), + MTK_FUNCTION(3, "SDA0_3X"), + MTK_FUNCTION(4, "AUD_TSTCK"), + MTK_FUNCTION(6, "TEST_IN12"), + MTK_FUNCTION(7, "TEST_OUT12") + ), + MTK_PIN( + PINCTRL_PIN(22, "ROW2"), + "J8", "mt6397", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "ROW2"), + MTK_FUNCTION(2, "EINT20_1X"), + MTK_FUNCTION(3, "SCL1_3X"), + MTK_FUNCTION(6, "TEST_IN13"), + MTK_FUNCTION(7, "TEST_OUT13") + ), + MTK_PIN( + PINCTRL_PIN(23, "ROW3"), + "J7", "mt6397", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "ROW3"), + MTK_FUNCTION(2, "EINT21_1X"), + MTK_FUNCTION(3, "SDA1_3X"), + MTK_FUNCTION(6, "TEST_IN14"), + MTK_FUNCTION(7, "TEST_OUT14") + ), + MTK_PIN( + PINCTRL_PIN(24, "ROW4"), + "L5", "mt6397", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "ROW4"), + MTK_FUNCTION(2, "EINT22_1X"), + MTK_FUNCTION(3, "SCL2_3X"), + MTK_FUNCTION(6, "TEST_IN15"), + MTK_FUNCTION(7, "TEST_OUT15") + ), + MTK_PIN( + PINCTRL_PIN(25, "ROW5"), + "N6", "mt6397", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "ROW5"), + MTK_FUNCTION(2, "EINT23_1X"), + MTK_FUNCTION(3, "SDA2_3X"), + MTK_FUNCTION(6, "TEST_IN16"), + MTK_FUNCTION(7, "TEST_OUT16") + ), + MTK_PIN( + PINCTRL_PIN(26, "ROW6"), + "L6", "mt6397", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "ROW6"), + MTK_FUNCTION(2, "EINT24_1X"), + MTK_FUNCTION(3, "PWM3_3X"), + MTK_FUNCTION(4, "GPIO32K_2"), + MTK_FUNCTION(5, "GPIO26M_2"), + MTK_FUNCTION(6, "TEST_IN17"), + MTK_FUNCTION(7, "TEST_OUT17") + ), + MTK_PIN( + PINCTRL_PIN(27, "ROW7"), + "P2", "mt6397", + MTK_EINT_FUNCTION(2, 3), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "ROW7"), + MTK_FUNCTION(2, "EINT3_1X"), + MTK_FUNCTION(3, "CBUS"), + MTK_FUNCTION(4, "GPIO32K_3"), + MTK_FUNCTION(5, "GPIO26M_3"), + MTK_FUNCTION(6, "TEST_IN18"), + MTK_FUNCTION(7, "TEST_OUT18") + ), + MTK_PIN( + PINCTRL_PIN(28, "PWM1(VMSEL1)"), + "J4", "mt6397", + MTK_EINT_FUNCTION(2, 4), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT4_1X"), + MTK_FUNCTION(4, "GPIO32K_4"), + MTK_FUNCTION(5, "GPIO26M_4"), + MTK_FUNCTION(6, "TEST_IN19"), + MTK_FUNCTION(7, "TEST_OUT19") + ), + MTK_PIN( + PINCTRL_PIN(29, "PWM2(VMSEL2)"), + "N5", "mt6397", + MTK_EINT_FUNCTION(2, 5), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT5_1X"), + MTK_FUNCTION(4, "GPIO32K_5"), + MTK_FUNCTION(5, "GPIO26M_5"), + MTK_FUNCTION(6, "TEST_IN20"), + MTK_FUNCTION(7, "TEST_OUT20") + ), + MTK_PIN( + PINCTRL_PIN(30, "PWM3(PWM)"), + "R3", "mt6397", + MTK_EINT_FUNCTION(2, 6), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT6_1X"), + MTK_FUNCTION(3, "COL0"), + MTK_FUNCTION(4, "GPIO32K_6"), + MTK_FUNCTION(5, "GPIO26M_6"), + MTK_FUNCTION(6, "TEST_IN21"), + MTK_FUNCTION(7, "TEST_OUT21") + ), + MTK_PIN( + PINCTRL_PIN(31, "SCL0"), + "N1", "mt6397", + MTK_EINT_FUNCTION(2, 7), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT7_1X"), + MTK_FUNCTION(3, "PWM1_2X"), + MTK_FUNCTION(6, "TEST_IN22"), + MTK_FUNCTION(7, "TEST_OUT22") + ), + MTK_PIN( + PINCTRL_PIN(32, "SDA0"), + "N3", "mt6397", + MTK_EINT_FUNCTION(2, 8), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT8_1X"), + MTK_FUNCTION(6, "TEST_IN23"), + MTK_FUNCTION(7, "TEST_OUT23") + ), + MTK_PIN( + PINCTRL_PIN(33, "SCL1"), + "T1", "mt6397", + MTK_EINT_FUNCTION(2, 9), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT9_1X"), + MTK_FUNCTION(3, "PWM2_2X"), + MTK_FUNCTION(6, "TEST_IN24"), + MTK_FUNCTION(7, "TEST_OUT24") + ), + MTK_PIN( + PINCTRL_PIN(34, "SDA1"), + "T2", "mt6397", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT0_1X"), + MTK_FUNCTION(6, "TEST_IN25"), + MTK_FUNCTION(7, "TEST_OUT25") + ), + MTK_PIN( + PINCTRL_PIN(35, "SCL2"), + "T3", "mt6397", + MTK_EINT_FUNCTION(2, 1), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT1_1X"), + MTK_FUNCTION(3, "PWM3_2X"), + MTK_FUNCTION(6, "TEST_IN26"), + MTK_FUNCTION(7, "TEST_OUT26") + ), + MTK_PIN( + PINCTRL_PIN(36, "SDA2"), + "U2", "mt6397", + MTK_EINT_FUNCTION(2, 2), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT2_1X"), + MTK_FUNCTION(6, "TEST_IN27"), + MTK_FUNCTION(7, "TEST_OUT27") + ), + MTK_PIN( + PINCTRL_PIN(37, "HDMISD"), + "H6", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "HDMISD"), + MTK_FUNCTION(6, "TEST_IN28"), + MTK_FUNCTION(7, "TEST_OUT28") + ), + MTK_PIN( + PINCTRL_PIN(38, "HDMISCK"), + "H5", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "HDMISCK"), + MTK_FUNCTION(6, "TEST_IN29"), + MTK_FUNCTION(7, "TEST_OUT29") + ), + MTK_PIN( + PINCTRL_PIN(39, "HTPLG"), + "H7", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "HTPLG"), + MTK_FUNCTION(6, "TEST_IN30"), + MTK_FUNCTION(7, "TEST_OUT30") + ), + MTK_PIN( + PINCTRL_PIN(40, "CEC"), + "J9", "mt6397", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "CEC"), + MTK_FUNCTION(6, "TEST_IN31"), + MTK_FUNCTION(7, "TEST_OUT31") + ), +}; + +#endif /* __PINCTRL_MTK_MT6397_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h new file mode 100644 index 000000000..212559c14 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h @@ -0,0 +1,1318 @@ +#ifndef __PINCTRL_MTK_MT8127_H +#define __PINCTRL_MTK_MT8127_H + +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8127[] = { + MTK_PIN( + PINCTRL_PIN(0, "PWRAP_SPI0_MI"), + "P22", "mt8127", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "PWRAP_SPIDI") + ), + MTK_PIN( + PINCTRL_PIN(1, "PWRAP_SPI0_MO"), + "M22", "mt8127", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "PWRAP_SPIDO") + ), + MTK_PIN( + PINCTRL_PIN(2, "PWRAP_INT"), + "L23", "mt8127", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO2") + ), + MTK_PIN( + PINCTRL_PIN(3, "PWRAP_SPI0_CK"), + "N23", "mt8127", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "PWRAP_SPICK_I") + ), + MTK_PIN( + PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), + "N22", "mt8127", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I") + ), + MTK_PIN( + PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), + "L19", "mt8127", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "PWRAP_SPICK2_I"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "VDEC_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[0]") + ), + MTK_PIN( + PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), + "M23", "mt8127", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "MM_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[1]") + ), + MTK_PIN( + PINCTRL_PIN(7, "AUD_CLK_MOSI"), + "K23", "mt8127", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "AUD_CLK"), + MTK_FUNCTION(2, "ADC_CK") + ), + MTK_PIN( + PINCTRL_PIN(8, "AUD_DAT_MISO"), + "K24", "mt8127", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "AUD_MISO"), + MTK_FUNCTION(2, "ADC_DAT_IN"), + MTK_FUNCTION(3, "AUD_MOSI") + ), + MTK_PIN( + PINCTRL_PIN(9, "AUD_DAT_MOSI"), + "K22", "mt8127", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "AUD_MOSI"), + MTK_FUNCTION(2, "ADC_WS"), + MTK_FUNCTION(3, "AUD_MISO") + ), + MTK_PIN( + PINCTRL_PIN(10, "RTC32K_CK"), + "R21", "mt8127", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(11, "WATCHDOG"), + "P24", "mt8127", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + PINCTRL_PIN(12, "SRCLKENA"), + "R22", "mt8127", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "SRCLKENA") + ), + MTK_PIN( + PINCTRL_PIN(13, "SRCLKENAI"), + "P23", "mt8127", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN( + PINCTRL_PIN(14, "URXD2"), + "U19", "mt8127", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(5, "SRCCLKENAI2"), + MTK_FUNCTION(6, "KROW4") + ), + MTK_PIN( + PINCTRL_PIN(15, "UTXD2"), + "U20", "mt8127", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_HSYNC"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(6, "KROW5") + ), + MTK_PIN( + PINCTRL_PIN(16, "URXD3"), + "U18", "mt8127", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "DPI_DE"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "KROW6") + ), + MTK_PIN( + PINCTRL_PIN(17, "UTXD3"), + "R18", "mt8127", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "DPI_VSYNC"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "KROW7") + ), + MTK_PIN( + PINCTRL_PIN(18, "PCM_CLK"), + "U22", "mt8127", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "PCM_CLK0"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "I2SIN1_BCK0"), + MTK_FUNCTION(4, "I2SOUT_BCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "IR"), + MTK_FUNCTION(7, "DBG_MON_A[0]") + ), + MTK_PIN( + PINCTRL_PIN(19, "PCM_SYNC"), + "U23", "mt8127", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "I2SOUT_LRCK"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(6, "EXT_COL"), + MTK_FUNCTION(7, "DBG_MON_A[1]") + ), + MTK_PIN( + PINCTRL_PIN(20, "PCM_RX"), + "V22", "mt8127", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "PCM_RX"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2SIN1_DATA_IN"), + MTK_FUNCTION(4, "PCM_TX"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "EXT_MDIO"), + MTK_FUNCTION(7, "DBG_MON_A[2]") + ), + MTK_PIN( + PINCTRL_PIN(21, "PCM_TX"), + "U21", "mt8127", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "PCM_TX"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "PCM_RX"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "EXT_MDC"), + MTK_FUNCTION(7, "DBG_MON_A[3]") + ), + MTK_PIN( + PINCTRL_PIN(22, "EINT0"), + "AB19", "mt8127", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "DPI_CK"), + MTK_FUNCTION(4, "EXT_TXD0"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "DBG_MON_A[4]") + ), + MTK_PIN( + PINCTRL_PIN(23, "EINT1"), + "AA21", "mt8127", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "DPI_D12"), + MTK_FUNCTION(4, "EXT_TXD1"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[5]") + ), + MTK_PIN( + PINCTRL_PIN(24, "EINT2"), + "AA19", "mt8127", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D13"), + MTK_FUNCTION(4, "EXT_TXD2"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "KCOL4"), + MTK_FUNCTION(7, "DBG_MON_A[6]") + ), + MTK_PIN( + PINCTRL_PIN(25, "EINT3"), + "Y19", "mt8127", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D14"), + MTK_FUNCTION(3, "SPI_MI"), + MTK_FUNCTION(4, "EXT_TXD3"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "KCOL5"), + MTK_FUNCTION(7, "DBG_MON_A[7]") + ), + MTK_PIN( + PINCTRL_PIN(26, "EINT4"), + "V21", "mt8127", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D15"), + MTK_FUNCTION(3, "SPI_MO"), + MTK_FUNCTION(4, "EXT_TXC"), + MTK_FUNCTION(5, "CONN_MCU_TCK0"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(7, "DBG_MON_A[8]") + ), + MTK_PIN( + PINCTRL_PIN(27, "EINT5"), + "AB22", "mt8127", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D16"), + MTK_FUNCTION(3, "SPI_CS"), + MTK_FUNCTION(4, "EXT_RXER"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "KCOL6"), + MTK_FUNCTION(7, "DBG_MON_A[9]") + ), + MTK_PIN( + PINCTRL_PIN(28, "EINT6"), + "AA23", "mt8127", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D17"), + MTK_FUNCTION(3, "SPI_CK"), + MTK_FUNCTION(4, "EXT_RXC"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "KCOL7"), + MTK_FUNCTION(7, "DBG_MON_A[10]") + ), + MTK_PIN( + PINCTRL_PIN(29, "EINT7"), + "Y23", "mt8127", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "UCTS3"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "EXT_RXDV"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(7, "DBG_MON_A[11]") + ), + MTK_PIN( + PINCTRL_PIN(30, "EINT8"), + "Y24", "mt8127", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "URTS3"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "EXT_RXD0"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "DPI_D7"), + MTK_FUNCTION(7, "DBG_MON_B[2]") + ), + MTK_PIN( + PINCTRL_PIN(31, "EINT9"), + "W23", "mt8127", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "SDA2"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD1"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "DPI_D8"), + MTK_FUNCTION(7, "DBG_MON_B[3]") + ), + MTK_PIN( + PINCTRL_PIN(32, "EINT10"), + "W24", "mt8127", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "SCL2"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD2"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "DPI_D9"), + MTK_FUNCTION(7, "DBG_MON_B[4]") + ), + MTK_PIN( + PINCTRL_PIN(33, "KPROW0"), + "AB24", "mt8127", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "KROW0"), + MTK_FUNCTION(4, "IMG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A[12]") + ), + MTK_PIN( + PINCTRL_PIN(34, "KPROW1"), + "AC24", "mt8127", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "KROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "MFG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[5]") + ), + MTK_PIN( + PINCTRL_PIN(35, "KPROW2"), + "AD24", "mt8127", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "KROW2"), + MTK_FUNCTION(2, "DRV_VBUS"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[6]") + ), + MTK_PIN( + PINCTRL_PIN(36, "KPCOL0"), + "AB23", "mt8127", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "KCOL0"), + MTK_FUNCTION(7, "DBG_MON_A[13]") + ), + MTK_PIN( + PINCTRL_PIN(37, "KPCOL1"), + "AC22", "mt8127", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "KCOL1"), + MTK_FUNCTION(7, "DBG_MON_B[7]") + ), + MTK_PIN( + PINCTRL_PIN(38, "KPCOL2"), + "AC23", "mt8127", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "KCOL2"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_B[8]") + ), + MTK_PIN( + PINCTRL_PIN(39, "JTMS"), + "V18", "mt8127", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC") + ), + MTK_PIN( + PINCTRL_PIN(40, "JTCK"), + "AA18", "mt8127", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK1"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC") + ), + MTK_PIN( + PINCTRL_PIN(41, "JTDI"), + "W18", "mt8127", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI") + ), + MTK_PIN( + PINCTRL_PIN(42, "JTDO"), + "Y18", "mt8127", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO") + ), + MTK_PIN( + PINCTRL_PIN(43, "EINT11"), + "W22", "mt8127", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "KROW3"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "DPI_D10"), + MTK_FUNCTION(6, "EXT_RXD3"), + MTK_FUNCTION(7, "DBG_MON_B[9]") + ), + MTK_PIN( + PINCTRL_PIN(44, "EINT12"), + "V23", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "KCOL3"), + MTK_FUNCTION(4, "ANT_SEL4"), + MTK_FUNCTION(5, "DPI_D11"), + MTK_FUNCTION(6, "EXT_TXEN"), + MTK_FUNCTION(7, "DBG_MON_B[10]") + ), + MTK_PIN( + PINCTRL_PIN(45, "EINT13"), + "Y21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(4, "ANT_SEL5"), + MTK_FUNCTION(5, "DPI_D0"), + MTK_FUNCTION(6, "SPDIF"), + MTK_FUNCTION(7, "DBG_MON_B[11]") + ), + MTK_PIN( + PINCTRL_PIN(46, "EINT14"), + "F23", "mt8127", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(2, "DAC_DAT_OUT"), + MTK_FUNCTION(4, "ANT_SEL1"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "DBG_MON_A[14]") + ), + MTK_PIN( + PINCTRL_PIN(47, "EINT15"), + "G23", "mt8127", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(2, "DAC_WS"), + MTK_FUNCTION(4, "ANT_SEL2"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "NCEB1"), + MTK_FUNCTION(7, "DBG_MON_A[15]") + ), + MTK_PIN( + PINCTRL_PIN(48, "EINT16"), + "H23", "mt8127", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(2, "DAC_CK"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "NCEB0"), + MTK_FUNCTION(7, "DBG_MON_A[16]") + ), + MTK_PIN( + PINCTRL_PIN(49, "EINT17"), + "J22", "mt8127", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "UCTS0"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "NREB"), + MTK_FUNCTION(7, "DBG_MON_A[17]") + ), + MTK_PIN( + PINCTRL_PIN(50, "EINT18"), + "AD20", "mt8127", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "URTS0"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "I2SOUT_LRCK"), + MTK_FUNCTION(4, "DRV_VBUS"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[12]") + ), + MTK_PIN( + PINCTRL_PIN(51, "EINT19"), + "AC21", "mt8127", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(3, "I2SOUT_BCK"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[13]") + ), + MTK_PIN( + PINCTRL_PIN(52, "EINT20"), + "V20", "mt8127", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "PCM_TX"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[14]") + ), + MTK_PIN( + PINCTRL_PIN(53, "SPI_CS"), + "AD19", "mt8127", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SPI_CS"), + MTK_FUNCTION(3, "I2SIN1_DATA_IN"), + MTK_FUNCTION(4, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[15]") + ), + MTK_PIN( + PINCTRL_PIN(54, "SPI_CK"), + "AC18", "mt8127", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SPI_CK"), + MTK_FUNCTION(3, "I2SIN1_LRCK"), + MTK_FUNCTION(4, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[16]") + ), + MTK_PIN( + PINCTRL_PIN(55, "SPI_MI"), + "AC19", "mt8127", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SPI_MI"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "I2SIN1_BCK1"), + MTK_FUNCTION(4, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[17]") + ), + MTK_PIN( + PINCTRL_PIN(56, "SPI_MO"), + "AD18", "mt8127", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SPI_MO"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(7, "DBG_MON_B[18]") + ), + MTK_PIN( + PINCTRL_PIN(57, "SDA1"), + "AE23", "mt8127", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SDA1") + ), + MTK_PIN( + PINCTRL_PIN(58, "SCL1"), + "AD23", "mt8127", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SCL1") + ), + MTK_PIN( + PINCTRL_PIN(59, "DISP_PWM"), + "AC20", "mt8127", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(7, "DBG_MON_A[18]") + ), + MTK_PIN( + PINCTRL_PIN(60, "WB_RSTB"), + "AD7", "mt8127", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "WB_RSTB"), + MTK_FUNCTION(7, "DBG_MON_A[19]") + ), + MTK_PIN( + PINCTRL_PIN(61, "F2W_DATA"), + "Y10", "mt8127", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "F2W_DATA"), + MTK_FUNCTION(7, "DBG_MON_A[20]") + ), + MTK_PIN( + PINCTRL_PIN(62, "F2W_CLK"), + "W10", "mt8127", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "F2W_CK"), + MTK_FUNCTION(7, "DBG_MON_A[21]") + ), + MTK_PIN( + PINCTRL_PIN(63, "WB_SCLK"), + "AB7", "mt8127", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "WB_SCLK"), + MTK_FUNCTION(7, "DBG_MON_A[22]") + ), + MTK_PIN( + PINCTRL_PIN(64, "WB_SDATA"), + "AA7", "mt8127", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "WB_SDATA"), + MTK_FUNCTION(7, "DBG_MON_A[23]") + ), + MTK_PIN( + PINCTRL_PIN(65, "WB_SEN"), + "Y7", "mt8127", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "WB_SEN"), + MTK_FUNCTION(7, "DBG_MON_A[24]") + ), + MTK_PIN( + PINCTRL_PIN(66, "WB_CRTL0"), + "AA1", "mt8127", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "WB_CRTL0"), + MTK_FUNCTION(2, "DFD_NTRST_XI"), + MTK_FUNCTION(7, "DBG_MON_A[25]") + ), + MTK_PIN( + PINCTRL_PIN(67, "WB_CRTL1"), + "AA2", "mt8127", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "WB_CRTL1"), + MTK_FUNCTION(2, "DFD_TMS_XI"), + MTK_FUNCTION(7, "DBG_MON_A[26]") + ), + MTK_PIN( + PINCTRL_PIN(68, "WB_CRTL2"), + "Y1", "mt8127", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "WB_CRTL2"), + MTK_FUNCTION(2, "DFD_TCK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[27]") + ), + MTK_PIN( + PINCTRL_PIN(69, "WB_CRTL3"), + "Y2", "mt8127", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "WB_CRTL3"), + MTK_FUNCTION(2, "DFD_TDI_XI"), + MTK_FUNCTION(7, "DBG_MON_A[28]") + ), + MTK_PIN( + PINCTRL_PIN(70, "WB_CRTL4"), + "Y3", "mt8127", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "WB_CRTL4"), + MTK_FUNCTION(2, "DFD_TDO"), + MTK_FUNCTION(7, "DBG_MON_A[29]") + ), + MTK_PIN( + PINCTRL_PIN(71, "WB_CRTL5"), + "Y4", "mt8127", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "WB_CRTL5"), + MTK_FUNCTION(7, "DBG_MON_A[30]") + ), + MTK_PIN( + PINCTRL_PIN(72, "I2S_DATA_IN"), + "K21", "mt8127", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "I2SIN1_DATA_IN"), + MTK_FUNCTION(2, "PCM_RX"), + MTK_FUNCTION(3, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PWM0"), + MTK_FUNCTION(6, "ADC_CK"), + MTK_FUNCTION(7, "DBG_MON_B[19]") + ), + MTK_PIN( + PINCTRL_PIN(73, "I2S_LRCK"), + "L21", "mt8127", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "I2SIN1_LRCK"), + MTK_FUNCTION(2, "PCM_SYNC"), + MTK_FUNCTION(3, "I2SOUT_LRCK"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "ADC_DAT_IN"), + MTK_FUNCTION(7, "DBG_MON_B[20]") + ), + MTK_PIN( + PINCTRL_PIN(74, "I2S_BCK"), + "L20", "mt8127", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "I2SIN1_BCK2"), + MTK_FUNCTION(2, "PCM_CLK1"), + MTK_FUNCTION(3, "I2SOUT_BCK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "ADC_WS"), + MTK_FUNCTION(7, "DBG_MON_B[21]") + ), + MTK_PIN( + PINCTRL_PIN(75, "SDA0"), + "W3", "mt8127", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SDA0") + ), + MTK_PIN( + PINCTRL_PIN(76, "SCL0"), + "W4", "mt8127", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "SCL0") + ), + MTK_PIN( + PINCTRL_PIN(77, "SDA2"), + "K19", "mt8127", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "PWM1") + ), + MTK_PIN( + PINCTRL_PIN(78, "SCL2"), + "K20", "mt8127", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "PWM2") + ), + MTK_PIN( + PINCTRL_PIN(79, "URXD0"), + "K18", "mt8127", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(80, "UTXD0"), + "K17", "mt8127", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0") + ), + MTK_PIN( + PINCTRL_PIN(81, "URXD1"), + "L17", "mt8127", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1") + ), + MTK_PIN( + PINCTRL_PIN(82, "UTXD1"), + "L18", "mt8127", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1") + ), + MTK_PIN( + PINCTRL_PIN(83, "LCM_RST"), + "W5", "mt8127", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "VDAC_CK_XI"), + MTK_FUNCTION(7, "DBG_MON_A[31]") + ), + MTK_PIN( + PINCTRL_PIN(84, "DSI_TE"), + "W6", "mt8127", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A[32]") + ), + MTK_PIN( + PINCTRL_PIN(85, "MSDC2_CMD"), + "U7", "mt8127", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(6, "I2SOUT_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[22]") + ), + MTK_PIN( + PINCTRL_PIN(86, "MSDC2_CLK"), + "T8", "mt8127", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(6, "I2SOUT_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[23]") + ), + MTK_PIN( + PINCTRL_PIN(87, "MSDC2_DAT0"), + "V3", "mt8127", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "ANT_SEL2"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "I2SOUT_DATA_OUT"), + MTK_FUNCTION(7, "DBG_MON_B[24]") + ), + MTK_PIN( + PINCTRL_PIN(88, "MSDC2_DAT1"), + "V4", "mt8127", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "PWM1"), + MTK_FUNCTION(7, "DBG_MON_B[25]") + ), + MTK_PIN( + PINCTRL_PIN(89, "MSDC2_DAT2"), + "U5", "mt8127", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(3, "SDA2"), + MTK_FUNCTION(5, "UTXD1"), + MTK_FUNCTION(6, "PWM2"), + MTK_FUNCTION(7, "DBG_MON_B[26]") + ), + MTK_PIN( + PINCTRL_PIN(90, "MSDC2_DAT3"), + "U6", "mt8127", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(3, "SCL2"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "URXD1"), + MTK_FUNCTION(6, "PWM3"), + MTK_FUNCTION(7, "DBG_MON_B[27]") + ), + MTK_PIN( + PINCTRL_PIN(91, "TDN3"), + "U2", "mt8127", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPI91"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + PINCTRL_PIN(92, "TDP3"), + "U1", "mt8127", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPI92"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + PINCTRL_PIN(93, "TDN2"), + "T2", "mt8127", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPI93"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + PINCTRL_PIN(94, "TDP2"), + "T1", "mt8127", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPI94"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + PINCTRL_PIN(95, "TCN"), + "R5", "mt8127", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPI95"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + PINCTRL_PIN(96, "TCP"), + "R4", "mt8127", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPI96"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + PINCTRL_PIN(97, "TDN1"), + "R3", "mt8127", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPI97"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + PINCTRL_PIN(98, "TDP1"), + "R2", "mt8127", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPI98"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + PINCTRL_PIN(99, "TDN0"), + "P3", "mt8127", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPI99"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + PINCTRL_PIN(100, "TDP0"), + "P2", "mt8127", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPI100"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + PINCTRL_PIN(101, "RDN0"), + "K1", "mt8127", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPI101"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + PINCTRL_PIN(102, "RDP0"), + "K2", "mt8127", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPI102"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + PINCTRL_PIN(103, "RDN1"), + "L2", "mt8127", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPI103"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + PINCTRL_PIN(104, "RDP1"), + "L3", "mt8127", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPI104"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + PINCTRL_PIN(105, "RCN"), + "M4", "mt8127", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPI105"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + PINCTRL_PIN(106, "RCP"), + "M5", "mt8127", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPI106"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + PINCTRL_PIN(107, "RDN2"), + "M2", "mt8127", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPI107"), + MTK_FUNCTION(1, "RDN2"), + MTK_FUNCTION(2, "CMDAT8") + ), + MTK_PIN( + PINCTRL_PIN(108, "RDP2"), + "M3", "mt8127", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPI108"), + MTK_FUNCTION(1, "RDP2"), + MTK_FUNCTION(2, "CMDAT9") + ), + MTK_PIN( + PINCTRL_PIN(109, "RDN3"), + "N2", "mt8127", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPI109"), + MTK_FUNCTION(1, "RDN3"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + PINCTRL_PIN(110, "RDP3"), + "N3", "mt8127", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPI110"), + MTK_FUNCTION(1, "RDP3"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + PINCTRL_PIN(111, "RCN_A"), + "J5", "mt8127", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPI111"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + PINCTRL_PIN(112, "RCP_A"), + "J4", "mt8127", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPI112"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + PINCTRL_PIN(113, "RDN1_A"), + "J2", "mt8127", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPI113"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT2"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(114, "RDP1_A"), + "J3", "mt8127", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPI114"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT3"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(115, "RDN0_A"), + "H2", "mt8127", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPI115"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC") + ), + MTK_PIN( + PINCTRL_PIN(116, "RDP0_A"), + "H3", "mt8127", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPI116"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC") + ), + MTK_PIN( + PINCTRL_PIN(117, "CMDAT0"), + "G5", "mt8127", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "ANT_SEL2"), + MTK_FUNCTION(7, "DBG_MON_B[28]") + ), + MTK_PIN( + PINCTRL_PIN(118, "CMDAT1"), + "G4", "mt8127", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(7, "DBG_MON_B[29]") + ), + MTK_PIN( + PINCTRL_PIN(119, "CMMCLK"), + "F3", "mt8127", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(3, "ANT_SEL4"), + MTK_FUNCTION(7, "DBG_MON_B[30]") + ), + MTK_PIN( + PINCTRL_PIN(120, "CMPCLK"), + "G6", "mt8127", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "ANT_SEL5"), + MTK_FUNCTION(7, "DBG_MON_B[31]") + ), + MTK_PIN( + PINCTRL_PIN(121, "MSDC1_CMD"), + "E3", "mt8127", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC1_CMD") + ), + MTK_PIN( + PINCTRL_PIN(122, "MSDC1_CLK"), + "D1", "mt8127", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC1_CLK") + ), + MTK_PIN( + PINCTRL_PIN(123, "MSDC1_DAT0"), + "D2", "mt8127", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC1_DAT0") + ), + MTK_PIN( + PINCTRL_PIN(124, "MSDC1_DAT1"), + "D3", "mt8127", + MTK_EINT_FUNCTION(0, 125), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC1_DAT1") + ), + MTK_PIN( + PINCTRL_PIN(125, "MSDC1_DAT2"), + "F2", "mt8127", + MTK_EINT_FUNCTION(0, 126), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC1_DAT2") + ), + MTK_PIN( + PINCTRL_PIN(126, "MSDC1_DAT3"), + "E2", "mt8127", + MTK_EINT_FUNCTION(0, 127), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MSDC1_DAT3") + ), + MTK_PIN( + PINCTRL_PIN(127, "MSDC0_DAT7"), + "C23", "mt8127", + MTK_EINT_FUNCTION(0, 128), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(4, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(128, "MSDC0_DAT6"), + "C24", "mt8127", + MTK_EINT_FUNCTION(0, 129), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(4, "NLD6") + ), + MTK_PIN( + PINCTRL_PIN(129, "MSDC0_DAT5"), + "D22", "mt8127", + MTK_EINT_FUNCTION(0, 130), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(4, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(130, "MSDC0_DAT4"), + "D24", "mt8127", + MTK_EINT_FUNCTION(0, 131), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(4, "NLD3") + ), + MTK_PIN( + PINCTRL_PIN(131, "MSDC0_RSTB"), + "F24", "mt8127", + MTK_EINT_FUNCTION(0, 132), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(4, "NLD0") + ), + MTK_PIN( + PINCTRL_PIN(132, "MSDC0_CMD"), + "G20", "mt8127", + MTK_EINT_FUNCTION(0, 133), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(4, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(133, "MSDC0_CLK"), + "G21", "mt8127", + MTK_EINT_FUNCTION(0, 134), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(4, "NWEB") + ), + MTK_PIN( + PINCTRL_PIN(134, "MSDC0_DAT3"), + "D23", "mt8127", + MTK_EINT_FUNCTION(0, 135), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(4, "NLD1") + ), + MTK_PIN( + PINCTRL_PIN(135, "MSDC0_DAT2"), + "E22", "mt8127", + MTK_EINT_FUNCTION(0, 136), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(4, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(136, "MSDC0_DAT1"), + "E23", "mt8127", + MTK_EINT_FUNCTION(0, 137), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(4, "NLD8") + ), + MTK_PIN( + PINCTRL_PIN(137, "MSDC0_DAT0"), + "F22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(5, "NLD2") + ), + MTK_PIN( + PINCTRL_PIN(138, "CEC"), + "AE21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CEC") + ), + MTK_PIN( + PINCTRL_PIN(139, "HTPLG"), + "AD21", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "HTPLG") + ), + MTK_PIN( + PINCTRL_PIN(140, "HDMISCK"), + "AE22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "HDMISCK") + ), + MTK_PIN( + PINCTRL_PIN(141, "HDMISD"), + "AD22", "mt8127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "HDMISD") + ), + MTK_PIN( + PINCTRL_PIN(142, "EINT21"), + "J23", "mt8127", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(7, "DBG_MON_B[32]") + ), +}; + +#endif /* __PINCTRL_MTK_MT8127_H */ |