diff options
Diffstat (limited to 'drivers/staging/emxx_udc')
-rw-r--r-- | drivers/staging/emxx_udc/emxx_udc.c | 24 | ||||
-rw-r--r-- | drivers/staging/emxx_udc/emxx_udc.h | 40 |
2 files changed, 32 insertions, 32 deletions
diff --git a/drivers/staging/emxx_udc/emxx_udc.c b/drivers/staging/emxx_udc/emxx_udc.c index e8cacaecf..3bd91758b 100644 --- a/drivers/staging/emxx_udc/emxx_udc.c +++ b/drivers/staging/emxx_udc/emxx_udc.c @@ -418,9 +418,9 @@ static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) { struct fc_regs *preg = udc->p_regs; - _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum-1].EP_DCR1, DCR1_EPn_REQEN); + _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPn_REQEN); mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */ - _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum-1].EP_DMA_CTRL, EPn_DMA_EN); + _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPn_DMA_EN); } /*-------------------------------------------------------------------------*/ @@ -909,7 +909,7 @@ static int _nbu2ss_epn_out_pio( /* Copy of every four bytes */ for (i = 0; i < iWordLength; i++) { pBuf32->dw = - _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ); + _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); pBuf32++; } result = iWordLength * sizeof(u32); @@ -919,7 +919,7 @@ static int _nbu2ss_epn_out_pio( if (data > 0) { /*---------------------------------------------------------*/ /* Copy of fraction byte */ - Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ); + Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); for (i = 0 ; i < data ; i++) pBuf32->byte.DATA[i] = Temp32.byte.DATA[i]; result += data; @@ -1128,7 +1128,7 @@ static int _nbu2ss_epn_in_pio( if (iWordLength > 0) { for (i = 0; i < iWordLength; i++) { _nbu2ss_writel( - &preg->EP_REGS[ep->epnum-1].EP_WRITE + &preg->EP_REGS[ep->epnum - 1].EP_WRITE , pBuf32->dw ); @@ -1290,7 +1290,7 @@ static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) if (ep->epnum > 0) { length = _nbu2ss_readl( - &ep->udc->p_regs->EP_REGS[ep->epnum-1].EP_LEN_DCNT); + &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT); length &= EPn_LDATA; if (length < ep->ep.maxpacket) @@ -1463,7 +1463,7 @@ static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) bit_data = EP0_STL; } else { - data = _nbu2ss_readl(&preg->EP_REGS[epnum-1].EP_CONTROL); + data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL); if ((data & EPn_EN) == 0) return -1; @@ -1558,7 +1558,7 @@ static void _nbu2ss_epn_set_stall( ; limit_cnt++) { regdata = _nbu2ss_readl( - &preg->EP_REGS[ep->epnum-1].EP_STATUS); + &preg->EP_REGS[ep->epnum - 1].EP_STATUS); if ((regdata & EPn_IN_DATA) == 0) break; @@ -1983,7 +1983,7 @@ static inline void _nbu2ss_epn_in_int( if (req->zero && ((req->req.actual % ep->ep.maxpacket) == 0)) { status = - _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_STATUS); + _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS); if ((status & EPn_IN_FULL) == 0) { /*-----------------------------------------*/ @@ -2894,7 +2894,7 @@ static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA; } else { - data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_LEN_DCNT) + data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT) & EPn_LDATA; } @@ -3051,7 +3051,7 @@ static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active) } /*-------------------------------------------------------------------------*/ -static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned mA) +static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned int mA) { struct nbu2ss_udc *udc; unsigned long flags; @@ -3101,7 +3101,7 @@ static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on) /*-------------------------------------------------------------------------*/ static int nbu2ss_gad_ioctl( struct usb_gadget *pgadget, - unsigned code, + unsigned int code, unsigned long param) { return 0; diff --git a/drivers/staging/emxx_udc/emxx_udc.h b/drivers/staging/emxx_udc/emxx_udc.h index 4a2cc38de..39769e3a8 100644 --- a/drivers/staging/emxx_udc/emxx_udc.h +++ b/drivers/staging/emxx_udc/emxx_udc.h @@ -97,7 +97,7 @@ #define BIT30 0x40000000 #define BIT31 0x80000000 -#define TEST_FORCE_ENABLE (BIT18+BIT16) +#define TEST_FORCE_ENABLE (BIT18 + BIT16) #define INT_SEL BIT10 #define CONSTFS BIT09 @@ -125,15 +125,15 @@ /*------- (0x0008) USB Address Register */ #define USB_ADDR 0x007F0000 #define SOF_STATUS BIT15 -#define UFRAME (BIT14+BIT13+BIT12) +#define UFRAME (BIT14 + BIT13 + BIT12) #define FRAME 0x000007FF #define USB_ADRS_SHIFT 16 /*------- (0x000C) UTMI Characteristic 1 Register */ -#define SQUSET (BIT07+BIT06+BIT05+BIT04) +#define SQUSET (BIT07 + BIT06 + BIT05 + BIT04) -#define USB_SQUSET (BIT06+BIT05+BIT04) +#define USB_SQUSET (BIT06 + BIT05 + BIT04) /*------- (0x0010) TEST Control Register */ #define FORCEHS BIT02 @@ -196,7 +196,7 @@ #define RSUM_EN BIT01 #define USB_INT_EN_BIT \ - (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN) + (EP0_EN | SPEED_MODE_EN | USB_RST_EN | SPND_EN | RSUM_EN) /*------- (0x0028) EP0 Control Register */ #define EP0_STGSEL BIT18 @@ -205,9 +205,9 @@ #define EP0_PIDCLR BIT09 #define EP0_BCLR BIT08 #define EP0_DEND BIT07 -#define EP0_DW (BIT06+BIT05) +#define EP0_DW (BIT06 + BIT05) #define EP0_DW4 0 -#define EP0_DW3 (BIT06+BIT05) +#define EP0_DW3 (BIT06 + BIT05) #define EP0_DW2 BIT06 #define EP0_DW1 BIT05 @@ -238,7 +238,7 @@ #define STG_START_INT BIT01 #define SETUP_INT BIT00 -#define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF) +#define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF) /*------- (0x0030) EP0 Interrupt Enable Register */ #define EP0_PERR_NAK_EN BIT16 @@ -256,7 +256,7 @@ #define SETUP_EN BIT00 #define EP0_INT_EN_BIT \ - (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN) + (EP0_OUT_OR_EN | EP0_OUT_EN | EP0_IN_EN | STG_END_EN | SETUP_EN) /*------- (0x0034) EP0 Length Register */ #define EP0_LDATA 0x0000007F @@ -270,7 +270,7 @@ #define EPn_BUF_SINGLE BIT30 #define EPn_DIR0 BIT26 -#define EPn_MODE (BIT25+BIT24) +#define EPn_MODE (BIT25 + BIT24) #define EPn_BULK 0 #define EPn_INTERRUPT BIT24 #define EPn_ISO BIT25 @@ -283,9 +283,9 @@ #define EPn_BCLR BIT09 #define EPn_CBCLR BIT08 #define EPn_DEND BIT07 -#define EPn_DW (BIT06+BIT05) +#define EPn_DW (BIT06 + BIT05) #define EPn_DW4 0 -#define EPn_DW3 (BIT06+BIT05) +#define EPn_DW3 (BIT06 + BIT05) #define EPn_DW2 BIT06 #define EPn_DW1 BIT05 @@ -324,7 +324,7 @@ #define EPn_IN_EMPTY BIT00 /* R */ #define EPn_INT_EN \ - (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT) + (EPn_OUT_END_INT | EPn_OUT_INT | EPn_IN_END_INT | EPn_IN_INT) /*------- (0x0048:) EPn Interrupt Enable Register */ #define EPn_OUT_END_EN BIT23 /* RW */ @@ -368,7 +368,7 @@ #define ARBITER_CTR BIT31 /* RW */ #define MCYCLE_RST BIT12 /* RW */ -#define ENDIAN_CTR (BIT09+BIT08) /* RW */ +#define ENDIAN_CTR (BIT09 + BIT08) /* RW */ #define ENDIAN_BYTE_SWAP BIT09 #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR @@ -376,7 +376,7 @@ #define HTRANS_MODE BIT04 /* RW */ #define WBURST_TYPE BIT02 /* RW */ -#define BURST_TYPE (BIT01+BIT00) /* RW */ +#define BURST_TYPE (BIT01 + BIT00) /* RW */ #define BURST_MAX_16 0 #define BURST_MAX_8 BIT00 #define BURST_MAX_4 BIT01 @@ -412,7 +412,7 @@ #define EPC_RST BIT00 /* RW */ /*------- (0x1014) USBF_EPTEST Register */ -#define LINESTATE (BIT09+BIT08) /* R */ +#define LINESTATE (BIT09 + BIT08) /* R */ #define DM_LEVEL BIT09 /* R */ #define DP_LEVEL BIT08 /* R */ @@ -485,7 +485,7 @@ struct fc_regs { struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ - u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */ + u8 Reserved220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ u32 AHBSCTR; /* (0x1000) AHBSCTR */ u32 AHBMCTR; /* (0x1004) AHBMCTR */ @@ -494,16 +494,16 @@ struct fc_regs { u32 EPCTR; /* (0x1010) EPCTR */ u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ - u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */ + u8 Reserved1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ u32 USBSSVER; /* (0x1020) USBSSVER */ u32 USBSSCONF; /* (0x1024) USBSSCONF */ - u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */ + u8 Reserved1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ - u8 Reserved1200[0x1000-0x200]; /* Reserved */ + u8 Reserved1200[0x1000 - 0x200]; /* Reserved */ } __aligned(32); #define EP0_PACKETSIZE 64 |