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path: root/drivers/staging/sm750fb/ddk750_chip.c
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Diffstat (limited to 'drivers/staging/sm750fb/ddk750_chip.c')
-rw-r--r--drivers/staging/sm750fb/ddk750_chip.c132
1 files changed, 70 insertions, 62 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 0331d3445..95f7cae3c 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -1,3 +1,4 @@
+#include <linux/kernel.h>
#include <linux/sizes.h>
#include "ddk750_help.h"
@@ -5,6 +6,10 @@
#include "ddk750_chip.h"
#include "ddk750_power.h"
+/* n / d + 1 / 2 = (2n + d) / 2d */
+#define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom)))
+#define MHz(x) ((x) * 1000000)
+
logical_chip_type_t getChipType(void)
{
unsigned short physicalID;
@@ -36,10 +41,10 @@ static unsigned int get_mxclk_freq(void)
return MHz(130);
pll_reg = PEEK32(MXCLK_PLL_CTRL);
- M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M);
- N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N);
- OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD);
- POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD);
+ M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
+ N = (pll_reg & PLL_CTRL_N_MASK) >> PLL_CTRL_M_SHIFT;
+ OD = (pll_reg & PLL_CTRL_OD_MASK) >> PLL_CTRL_OD_SHIFT;
+ POD = (pll_reg & PLL_CTRL_POD_MASK) >> PLL_CTRL_POD_SHIFT;
return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
}
@@ -79,7 +84,7 @@ static void setChipClock(unsigned int frequency)
static void setMemoryClock(unsigned int frequency)
{
- unsigned int ulReg, divisor;
+ unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
@@ -95,24 +100,24 @@ static void setMemoryClock(unsigned int frequency)
divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
- ulReg = PEEK32(CURRENT_GATE);
+ reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_M2XCLK_MASK;
switch (divisor) {
default:
case 1:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
+ reg |= CURRENT_GATE_M2XCLK_DIV_1;
break;
case 2:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2);
+ reg |= CURRENT_GATE_M2XCLK_DIV_2;
break;
case 3:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3);
+ reg |= CURRENT_GATE_M2XCLK_DIV_3;
break;
case 4:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4);
+ reg |= CURRENT_GATE_M2XCLK_DIV_4;
break;
}
- setCurrentGate(ulReg);
+ setCurrentGate(reg);
}
}
@@ -126,7 +131,7 @@ static void setMemoryClock(unsigned int frequency)
*/
static void setMasterClock(unsigned int frequency)
{
- unsigned int ulReg, divisor;
+ unsigned int reg, divisor;
/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
if (getChipType() == SM750LE)
@@ -142,24 +147,24 @@ static void setMasterClock(unsigned int frequency)
divisor = roundedDiv(get_mxclk_freq(), frequency);
/* Set the corresponding divisor in the register. */
- ulReg = PEEK32(CURRENT_GATE);
+ reg = PEEK32(CURRENT_GATE) & ~CURRENT_GATE_MCLK_MASK;
switch (divisor) {
default:
case 3:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
+ reg |= CURRENT_GATE_MCLK_DIV_3;
break;
case 4:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
+ reg |= CURRENT_GATE_MCLK_DIV_4;
break;
case 6:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
+ reg |= CURRENT_GATE_MCLK_DIV_6;
break;
case 8:
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
+ reg |= CURRENT_GATE_MCLK_DIV_8;
break;
}
- setCurrentGate(ulReg);
+ setCurrentGate(reg);
}
}
@@ -174,11 +179,11 @@ unsigned int ddk750_getVMSize(void)
/* for 750,always use power mode0*/
reg = PEEK32(MODE0_GATE);
- reg = FIELD_SET(reg, MODE0_GATE, GPIO, ON);
+ reg |= MODE0_GATE_GPIO;
POKE32(MODE0_GATE, reg);
/* get frame buffer size from GPIO */
- reg = FIELD_GET(PEEK32(MISC_CTRL), MISC_CTRL, LOCALMEM_SIZE);
+ reg = PEEK32(MISC_CTRL) & MISC_CTRL_LOCALMEM_SIZE_MASK;
switch (reg) {
case MISC_CTRL_LOCALMEM_SIZE_8M:
data = SZ_8M; break; /* 8 Mega byte */
@@ -197,24 +202,22 @@ unsigned int ddk750_getVMSize(void)
int ddk750_initHw(initchip_param_t *pInitParam)
{
- unsigned int ulReg;
+ unsigned int reg;
if (pInitParam->powerMode != 0)
pInitParam->powerMode = 0;
setPowerMode(pInitParam->powerMode);
/* Enable display power gate & LOCALMEM power gate*/
- ulReg = PEEK32(CURRENT_GATE);
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, DISPLAY, ON);
- ulReg = FIELD_SET(ulReg, CURRENT_GATE, LOCALMEM, ON);
- setCurrentGate(ulReg);
+ reg = PEEK32(CURRENT_GATE);
+ reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
+ setCurrentGate(reg);
if (getChipType() != SM750LE) {
/* set panel pll and graphic mode via mmio_88 */
- ulReg = PEEK32(VGA_CONFIGURATION);
- ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, PLL, PANEL);
- ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, MODE, GRAPHIC);
- POKE32(VGA_CONFIGURATION, ulReg);
+ reg = PEEK32(VGA_CONFIGURATION);
+ reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
+ POKE32(VGA_CONFIGURATION, reg);
} else {
#if defined(__i386__) || defined(__x86_64__)
/* set graphic mode via IO method */
@@ -238,36 +241,36 @@ int ddk750_initHw(initchip_param_t *pInitParam)
The memory should be resetted after changing the MXCLK.
*/
if (pInitParam->resetMemory == 1) {
- ulReg = PEEK32(MISC_CTRL);
- ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET);
- POKE32(MISC_CTRL, ulReg);
+ reg = PEEK32(MISC_CTRL);
+ reg &= ~MISC_CTRL_LOCALMEM_RESET;
+ POKE32(MISC_CTRL, reg);
- ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, NORMAL);
- POKE32(MISC_CTRL, ulReg);
+ reg |= MISC_CTRL_LOCALMEM_RESET;
+ POKE32(MISC_CTRL, reg);
}
if (pInitParam->setAllEngOff == 1) {
enable2DEngine(0);
/* Disable Overlay, if a former application left it on */
- ulReg = PEEK32(VIDEO_DISPLAY_CTRL);
- ulReg = FIELD_SET(ulReg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(VIDEO_DISPLAY_CTRL, ulReg);
+ reg = PEEK32(VIDEO_DISPLAY_CTRL);
+ reg &= ~DISPLAY_CTRL_PLANE;
+ POKE32(VIDEO_DISPLAY_CTRL, reg);
/* Disable video alpha, if a former application left it on */
- ulReg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
- ulReg = FIELD_SET(ulReg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(VIDEO_ALPHA_DISPLAY_CTRL, ulReg);
+ reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
+ reg &= ~DISPLAY_CTRL_PLANE;
+ POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
/* Disable alpha plane, if a former application left it on */
- ulReg = PEEK32(ALPHA_DISPLAY_CTRL);
- ulReg = FIELD_SET(ulReg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(ALPHA_DISPLAY_CTRL, ulReg);
+ reg = PEEK32(ALPHA_DISPLAY_CTRL);
+ reg &= ~DISPLAY_CTRL_PLANE;
+ POKE32(ALPHA_DISPLAY_CTRL, reg);
/* Disable DMA Channel, if a former application left it on */
- ulReg = PEEK32(DMA_ABORT_INTERRUPT);
- ulReg = FIELD_SET(ulReg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT);
- POKE32(DMA_ABORT_INTERRUPT, ulReg);
+ reg = PEEK32(DMA_ABORT_INTERRUPT);
+ reg |= DMA_ABORT_INTERRUPT_ABORT_1;
+ POKE32(DMA_ABORT_INTERRUPT, reg);
/* Disable DMA Power, if a former application left it on */
enableDMA(0);
@@ -337,7 +340,7 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
unsigned int diff;
tmpClock = pll->inputFreq * M / N / X;
- diff = absDiff(tmpClock, request_orig);
+ diff = abs(tmpClock - request_orig);
if (diff < mini_diff) {
pll->M = M;
pll->N = N;
@@ -356,24 +359,29 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
unsigned int formatPllReg(pll_value_t *pPLL)
{
- unsigned int ulPllReg = 0;
-
- /* Note that all PLL's have the same format. Here, we just use Panel PLL parameter
- to work out the bit fields in the register.
- On returning a 32 bit number, the value can be applied to any PLL in the calling function.
- */
- ulPllReg =
- FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF)
- | FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON)
- | FIELD_SET(0, PANEL_PLL_CTRL, INPUT, OSC)
#ifndef VALIDATION_CHIP
- | FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
+ unsigned int POD = pPLL->POD;
+#endif
+ unsigned int OD = pPLL->OD;
+ unsigned int M = pPLL->M;
+ unsigned int N = pPLL->N;
+ unsigned int reg = 0;
+
+ /*
+ * Note that all PLL's have the same format. Here, we just use
+ * Panel PLL parameter to work out the bit fields in the
+ * register. On returning a 32 bit number, the value can be
+ * applied to any PLL in the calling function.
+ */
+ reg = PLL_CTRL_POWER |
+#ifndef VALIDATION_CHIP
+ ((POD << PLL_CTRL_POD_SHIFT) & PLL_CTRL_POD_MASK) |
#endif
- | FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
- | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
- | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
+ ((OD << PLL_CTRL_OD_SHIFT) & PLL_CTRL_OD_MASK) |
+ ((N << PLL_CTRL_N_SHIFT) & PLL_CTRL_N_MASK) |
+ ((M << PLL_CTRL_M_SHIFT) & PLL_CTRL_M_MASK);
- return ulPllReg;
+ return reg;
}
generated by cgit v1.2.3-54-g00ecf (git 2.45.2) at 2024-07-04 06:47:32 +0000