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-rw-r--r--include/dt-bindings/clock/alphascale,asm9260.h97
-rw-r--r--include/dt-bindings/clock/at91.h22
-rw-r--r--include/dt-bindings/clock/bcm21664.h62
-rw-r--r--include/dt-bindings/clock/bcm281xx.h77
-rw-r--r--include/dt-bindings/clock/berlin2.h45
-rw-r--r--include/dt-bindings/clock/berlin2q.h31
-rw-r--r--include/dt-bindings/clock/clps711x-clock.h27
-rw-r--r--include/dt-bindings/clock/efm32-cmu.h42
-rw-r--r--include/dt-bindings/clock/exynos-audss-clk.h26
-rw-r--r--include/dt-bindings/clock/exynos3250.h346
-rw-r--r--include/dt-bindings/clock/exynos4.h274
-rw-r--r--include/dt-bindings/clock/exynos4415.h360
-rw-r--r--include/dt-bindings/clock/exynos5250.h179
-rw-r--r--include/dt-bindings/clock/exynos5260-clk.h469
-rw-r--r--include/dt-bindings/clock/exynos5410.h33
-rw-r--r--include/dt-bindings/clock/exynos5420.h220
-rw-r--r--include/dt-bindings/clock/exynos5433.h1403
-rw-r--r--include/dt-bindings/clock/exynos5440.h42
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h172
-rw-r--r--include/dt-bindings/clock/hi3620-clock.h157
-rw-r--r--include/dt-bindings/clock/hip04-clock.h35
-rw-r--r--include/dt-bindings/clock/hix5hd2-clock.h85
-rw-r--r--include/dt-bindings/clock/imx1-clock.h40
-rw-r--r--include/dt-bindings/clock/imx21-clock.h80
-rw-r--r--include/dt-bindings/clock/imx27-clock.h108
-rw-r--r--include/dt-bindings/clock/imx5-clock.h206
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h256
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h179
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h279
-rw-r--r--include/dt-bindings/clock/lsi,axm5516-clks.h36
-rw-r--r--include/dt-bindings/clock/marvell,mmp2.h74
-rw-r--r--include/dt-bindings/clock/marvell,pxa168.h57
-rw-r--r--include/dt-bindings/clock/marvell,pxa910.h54
-rw-r--r--include/dt-bindings/clock/maxim,max77686.h23
-rw-r--r--include/dt-bindings/clock/maxim,max77802.h22
-rw-r--r--include/dt-bindings/clock/mpc512x-clock.h76
-rw-r--r--include/dt-bindings/clock/pistachio-clk.h183
-rw-r--r--include/dt-bindings/clock/pxa-clock.h77
-rw-r--r--include/dt-bindings/clock/qcom,gcc-apq8084.h351
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h293
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8660.h276
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8916.h156
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8960.h323
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8974.h324
-rw-r--r--include/dt-bindings/clock/qcom,lcc-ipq806x.h30
-rw-r--r--include/dt-bindings/clock/qcom,lcc-msm8960.h50
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-apq8084.h183
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8960.h145
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8974.h161
-rw-r--r--include/dt-bindings/clock/r7s72100-clock.h41
-rw-r--r--include/dt-bindings/clock/r8a73a4-clock.h62
-rw-r--r--include/dt-bindings/clock/r8a7740-clock.h78
-rw-r--r--include/dt-bindings/clock/r8a7778-clock.h71
-rw-r--r--include/dt-bindings/clock/r8a7779-clock.h64
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h154
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h157
-rw-r--r--include/dt-bindings/clock/r8a7794-clock.h106
-rw-r--r--include/dt-bindings/clock/rk3066a-cru.h35
-rw-r--r--include/dt-bindings/clock/rk3188-cru-common.h250
-rw-r--r--include/dt-bindings/clock/rk3188-cru.h51
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h378
-rw-r--r--include/dt-bindings/clock/rockchip,rk808.h11
-rw-r--r--include/dt-bindings/clock/s3c2410.h62
-rw-r--r--include/dt-bindings/clock/s3c2412.h73
-rw-r--r--include/dt-bindings/clock/s3c2443.h92
-rw-r--r--include/dt-bindings/clock/s5pv210-audss.h34
-rw-r--r--include/dt-bindings/clock/s5pv210.h239
-rw-r--r--include/dt-bindings/clock/samsung,s3c64xx-clock.h178
-rw-r--r--include/dt-bindings/clock/sh73a0-clock.h82
-rw-r--r--include/dt-bindings/clock/stih407-clks.h86
-rw-r--r--include/dt-bindings/clock/stih410-clks.h25
-rw-r--r--include/dt-bindings/clock/stih415-clks.h16
-rw-r--r--include/dt-bindings/clock/stih416-clks.h16
-rw-r--r--include/dt-bindings/clock/stih418-clks.h34
-rw-r--r--include/dt-bindings/clock/tegra114-car.h343
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h345
-rw-r--r--include/dt-bindings/clock/tegra124-car.h19
-rw-r--r--include/dt-bindings/clock/tegra20-car.h158
-rw-r--r--include/dt-bindings/clock/tegra30-car.h273
-rw-r--r--include/dt-bindings/clock/vf610-clock.h198
80 files changed, 11977 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/alphascale,asm9260.h b/include/dt-bindings/clock/alphascale,asm9260.h
new file mode 100644
index 000000000..04e8db27d
--- /dev/null
+++ b/include/dt-bindings/clock/alphascale,asm9260.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ASM9260_H
+#define _DT_BINDINGS_CLK_ASM9260_H
+
+/* ahb gate */
+#define CLKID_AHB_ROM 0
+#define CLKID_AHB_RAM 1
+#define CLKID_AHB_GPIO 2
+#define CLKID_AHB_MAC 3
+#define CLKID_AHB_EMI 4
+#define CLKID_AHB_USB0 5
+#define CLKID_AHB_USB1 6
+#define CLKID_AHB_DMA0 7
+#define CLKID_AHB_DMA1 8
+#define CLKID_AHB_UART0 9
+#define CLKID_AHB_UART1 10
+#define CLKID_AHB_UART2 11
+#define CLKID_AHB_UART3 12
+#define CLKID_AHB_UART4 13
+#define CLKID_AHB_UART5 14
+#define CLKID_AHB_UART6 15
+#define CLKID_AHB_UART7 16
+#define CLKID_AHB_UART8 17
+#define CLKID_AHB_UART9 18
+#define CLKID_AHB_I2S0 19
+#define CLKID_AHB_I2C0 20
+#define CLKID_AHB_I2C1 21
+#define CLKID_AHB_SSP0 22
+#define CLKID_AHB_IOCONFIG 23
+#define CLKID_AHB_WDT 24
+#define CLKID_AHB_CAN0 25
+#define CLKID_AHB_CAN1 26
+#define CLKID_AHB_MPWM 27
+#define CLKID_AHB_SPI0 28
+#define CLKID_AHB_SPI1 29
+#define CLKID_AHB_QEI 30
+#define CLKID_AHB_QUADSPI0 31
+#define CLKID_AHB_CAMIF 32
+#define CLKID_AHB_LCDIF 33
+#define CLKID_AHB_TIMER0 34
+#define CLKID_AHB_TIMER1 35
+#define CLKID_AHB_TIMER2 36
+#define CLKID_AHB_TIMER3 37
+#define CLKID_AHB_IRQ 38
+#define CLKID_AHB_RTC 39
+#define CLKID_AHB_NAND 40
+#define CLKID_AHB_ADC0 41
+#define CLKID_AHB_LED 42
+#define CLKID_AHB_DAC0 43
+#define CLKID_AHB_LCD 44
+#define CLKID_AHB_I2S1 45
+#define CLKID_AHB_MAC1 46
+
+/* devider */
+#define CLKID_SYS_CPU 47
+#define CLKID_SYS_AHB 48
+#define CLKID_SYS_I2S0M 49
+#define CLKID_SYS_I2S0S 50
+#define CLKID_SYS_I2S1M 51
+#define CLKID_SYS_I2S1S 52
+#define CLKID_SYS_UART0 53
+#define CLKID_SYS_UART1 54
+#define CLKID_SYS_UART2 55
+#define CLKID_SYS_UART3 56
+#define CLKID_SYS_UART4 56
+#define CLKID_SYS_UART5 57
+#define CLKID_SYS_UART6 58
+#define CLKID_SYS_UART7 59
+#define CLKID_SYS_UART8 60
+#define CLKID_SYS_UART9 61
+#define CLKID_SYS_SPI0 62
+#define CLKID_SYS_SPI1 63
+#define CLKID_SYS_QUADSPI 64
+#define CLKID_SYS_SSP0 65
+#define CLKID_SYS_NAND 66
+#define CLKID_SYS_TRACE 67
+#define CLKID_SYS_CAMM 68
+#define CLKID_SYS_WDT 69
+#define CLKID_SYS_CLKOUT 70
+#define CLKID_SYS_MAC 71
+#define CLKID_SYS_LCD 72
+#define CLKID_SYS_ADCANA 73
+
+#define MAX_CLKS 74
+#endif
diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
new file mode 100644
index 000000000..0b4cb999a
--- /dev/null
+++ b/include/dt-bindings/clock/at91.h
@@ -0,0 +1,22 @@
+/*
+ * This header provides constants for AT91 pmc status.
+ *
+ * The constants defined in this header are being used in dts.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AT91_H
+#define _DT_BINDINGS_CLK_AT91_H
+
+#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
+#define AT91_PMC_LOCKA 1 /* PLLA Lock */
+#define AT91_PMC_LOCKB 2 /* PLLB Lock */
+#define AT91_PMC_MCKRDY 3 /* Master Clock */
+#define AT91_PMC_LOCKU 6 /* UPLL Lock */
+#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
+#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
+#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
+#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
+
+#endif
diff --git a/include/dt-bindings/clock/bcm21664.h b/include/dt-bindings/clock/bcm21664.h
new file mode 100644
index 000000000..5a7f0e475
--- /dev/null
+++ b/include/dt-bindings/clock/bcm21664.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM21664_H
+#define _CLOCK_BCM21664_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM21664 family SoCs.
+ */
+
+/* bcm21664 CCU device tree "compatible" strings */
+#define BCM21664_DT_ROOT_CCU_COMPAT "brcm,bcm21664-root-ccu"
+#define BCM21664_DT_AON_CCU_COMPAT "brcm,bcm21664-aon-ccu"
+#define BCM21664_DT_MASTER_CCU_COMPAT "brcm,bcm21664-master-ccu"
+#define BCM21664_DT_SLAVE_CCU_COMPAT "brcm,bcm21664-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM21664_ROOT_CCU_FRAC_1M 0
+#define BCM21664_ROOT_CCU_CLOCK_COUNT 1
+
+/* aon CCU clock ids */
+
+#define BCM21664_AON_CCU_HUB_TIMER 0
+#define BCM21664_AON_CCU_CLOCK_COUNT 1
+
+/* master CCU clock ids */
+
+#define BCM21664_MASTER_CCU_SDIO1 0
+#define BCM21664_MASTER_CCU_SDIO2 1
+#define BCM21664_MASTER_CCU_SDIO3 2
+#define BCM21664_MASTER_CCU_SDIO4 3
+#define BCM21664_MASTER_CCU_SDIO1_SLEEP 4
+#define BCM21664_MASTER_CCU_SDIO2_SLEEP 5
+#define BCM21664_MASTER_CCU_SDIO3_SLEEP 6
+#define BCM21664_MASTER_CCU_SDIO4_SLEEP 7
+#define BCM21664_MASTER_CCU_CLOCK_COUNT 8
+
+/* slave CCU clock ids */
+
+#define BCM21664_SLAVE_CCU_UARTB 0
+#define BCM21664_SLAVE_CCU_UARTB2 1
+#define BCM21664_SLAVE_CCU_UARTB3 2
+#define BCM21664_SLAVE_CCU_BSC1 3
+#define BCM21664_SLAVE_CCU_BSC2 4
+#define BCM21664_SLAVE_CCU_BSC3 5
+#define BCM21664_SLAVE_CCU_BSC4 6
+#define BCM21664_SLAVE_CCU_CLOCK_COUNT 7
+
+#endif /* _CLOCK_BCM21664_H */
diff --git a/include/dt-bindings/clock/bcm281xx.h b/include/dt-bindings/clock/bcm281xx.h
new file mode 100644
index 000000000..a763460cf
--- /dev/null
+++ b/include/dt-bindings/clock/bcm281xx.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ * Copyright 2013 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CLOCK_BCM281XX_H
+#define _CLOCK_BCM281XX_H
+
+/*
+ * This file defines the values used to specify clocks provided by
+ * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
+ */
+
+/*
+ * These are the bcm281xx CCU device tree "compatible" strings.
+ * We're stuck with using "bcm11351" in the string because wild
+ * cards aren't allowed, and that name was the first one defined
+ * in this family of devices.
+ */
+#define BCM281XX_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
+#define BCM281XX_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
+#define BCM281XX_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
+#define BCM281XX_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
+#define BCM281XX_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
+
+/* root CCU clock ids */
+
+#define BCM281XX_ROOT_CCU_FRAC_1M 0
+#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1
+
+/* aon CCU clock ids */
+
+#define BCM281XX_AON_CCU_HUB_TIMER 0
+#define BCM281XX_AON_CCU_PMU_BSC 1
+#define BCM281XX_AON_CCU_PMU_BSC_VAR 2
+#define BCM281XX_AON_CCU_CLOCK_COUNT 3
+
+/* hub CCU clock ids */
+
+#define BCM281XX_HUB_CCU_TMON_1M 0
+#define BCM281XX_HUB_CCU_CLOCK_COUNT 1
+
+/* master CCU clock ids */
+
+#define BCM281XX_MASTER_CCU_SDIO1 0
+#define BCM281XX_MASTER_CCU_SDIO2 1
+#define BCM281XX_MASTER_CCU_SDIO3 2
+#define BCM281XX_MASTER_CCU_SDIO4 3
+#define BCM281XX_MASTER_CCU_USB_IC 4
+#define BCM281XX_MASTER_CCU_HSIC2_48M 5
+#define BCM281XX_MASTER_CCU_HSIC2_12M 6
+#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7
+
+/* slave CCU clock ids */
+
+#define BCM281XX_SLAVE_CCU_UARTB 0
+#define BCM281XX_SLAVE_CCU_UARTB2 1
+#define BCM281XX_SLAVE_CCU_UARTB3 2
+#define BCM281XX_SLAVE_CCU_UARTB4 3
+#define BCM281XX_SLAVE_CCU_SSP0 4
+#define BCM281XX_SLAVE_CCU_SSP2 5
+#define BCM281XX_SLAVE_CCU_BSC1 6
+#define BCM281XX_SLAVE_CCU_BSC2 7
+#define BCM281XX_SLAVE_CCU_BSC3 8
+#define BCM281XX_SLAVE_CCU_PWM 9
+#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10
+
+#endif /* _CLOCK_BCM281XX_H */
diff --git a/include/dt-bindings/clock/berlin2.h b/include/dt-bindings/clock/berlin2.h
new file mode 100644
index 000000000..0c3080017
--- /dev/null
+++ b/include/dt-bindings/clock/berlin2.h
@@ -0,0 +1,45 @@
+/*
+ * Berlin2 BG2/BG2CD clock tree IDs
+ */
+
+#define CLKID_SYS 0
+#define CLKID_CPU 1
+#define CLKID_DRMFIGO 2
+#define CLKID_CFG 3
+#define CLKID_GFX 4
+#define CLKID_ZSP 5
+#define CLKID_PERIF 6
+#define CLKID_PCUBE 7
+#define CLKID_VSCOPE 8
+#define CLKID_NFC_ECC 9
+#define CLKID_VPP 10
+#define CLKID_APP 11
+#define CLKID_AUDIO0 12
+#define CLKID_AUDIO2 13
+#define CLKID_AUDIO3 14
+#define CLKID_AUDIO1 15
+#define CLKID_GFX3D_CORE 16
+#define CLKID_GFX3D_SYS 17
+#define CLKID_ARC 18
+#define CLKID_VIP 19
+#define CLKID_SDIO0XIN 20
+#define CLKID_SDIO1XIN 21
+#define CLKID_GFX3D_EXTRA 22
+#define CLKID_GC360 23
+#define CLKID_SDIO_DLLMST 24
+#define CLKID_GETH0 25
+#define CLKID_GETH1 26
+#define CLKID_SATA 27
+#define CLKID_AHBAPB 28
+#define CLKID_USB0 29
+#define CLKID_USB1 30
+#define CLKID_PBRIDGE 31
+#define CLKID_SDIO0 32
+#define CLKID_SDIO1 33
+#define CLKID_NFC 34
+#define CLKID_SMEMC 35
+#define CLKID_AUDIOHD 36
+#define CLKID_VIDEO0 37
+#define CLKID_VIDEO1 38
+#define CLKID_VIDEO2 39
+#define CLKID_TWD 40
diff --git a/include/dt-bindings/clock/berlin2q.h b/include/dt-bindings/clock/berlin2q.h
new file mode 100644
index 000000000..287fc3b4a
--- /dev/null
+++ b/include/dt-bindings/clock/berlin2q.h
@@ -0,0 +1,31 @@
+/*
+ * Berlin2 BG2Q clock tree IDs
+ */
+
+#define CLKID_SYS 0
+#define CLKID_DRMFIGO 1
+#define CLKID_CFG 2
+#define CLKID_GFX2D 3
+#define CLKID_ZSP 4
+#define CLKID_PERIF 5
+#define CLKID_PCUBE 6
+#define CLKID_VSCOPE 7
+#define CLKID_NFC_ECC 8
+#define CLKID_VPP 9
+#define CLKID_APP 10
+#define CLKID_SDIO0XIN 11
+#define CLKID_SDIO1XIN 12
+#define CLKID_GFX2DAXI 13
+#define CLKID_GETH0 14
+#define CLKID_SATA 15
+#define CLKID_AHBAPB 16
+#define CLKID_USB0 17
+#define CLKID_USB1 18
+#define CLKID_USB2 19
+#define CLKID_USB3 20
+#define CLKID_PBRIDGE 21
+#define CLKID_SDIO 22
+#define CLKID_NFC 23
+#define CLKID_SMEMC 24
+#define CLKID_PCIE 25
+#define CLKID_TWD 26
diff --git a/include/dt-bindings/clock/clps711x-clock.h b/include/dt-bindings/clock/clps711x-clock.h
new file mode 100644
index 000000000..0c4c80b63
--- /dev/null
+++ b/include/dt-bindings/clock/clps711x-clock.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
+#define __DT_BINDINGS_CLOCK_CLPS711X_H
+
+#define CLPS711X_CLK_DUMMY 0
+#define CLPS711X_CLK_CPU 1
+#define CLPS711X_CLK_BUS 2
+#define CLPS711X_CLK_PLL 3
+#define CLPS711X_CLK_TIMERREF 4
+#define CLPS711X_CLK_TIMER1 5
+#define CLPS711X_CLK_TIMER2 6
+#define CLPS711X_CLK_PWM 7
+#define CLPS711X_CLK_SPIREF 8
+#define CLPS711X_CLK_SPI 9
+#define CLPS711X_CLK_UART 10
+#define CLPS711X_CLK_TICK 11
+#define CLPS711X_CLK_MAX 12
+
+#endif
diff --git a/include/dt-bindings/clock/efm32-cmu.h b/include/dt-bindings/clock/efm32-cmu.h
new file mode 100644
index 000000000..b21b91e73
--- /dev/null
+++ b/include/dt-bindings/clock/efm32-cmu.h
@@ -0,0 +1,42 @@
+#ifndef __DT_BINDINGS_CLOCK_EFM32_CMU_H
+#define __DT_BINDINGS_CLOCK_EFM32_CMU_H
+
+#define clk_HFXO 0
+#define clk_HFRCO 1
+#define clk_LFXO 2
+#define clk_LFRCO 3
+#define clk_ULFRCO 4
+#define clk_AUXHFRCO 5
+#define clk_HFCLKNODIV 6
+#define clk_HFCLK 7
+#define clk_HFPERCLK 8
+#define clk_HFCORECLK 9
+#define clk_LFACLK 10
+#define clk_LFBCLK 11
+#define clk_WDOGCLK 12
+#define clk_HFCORECLKDMA 13
+#define clk_HFCORECLKAES 14
+#define clk_HFCORECLKUSBC 15
+#define clk_HFCORECLKUSB 16
+#define clk_HFCORECLKLE 17
+#define clk_HFCORECLKEBI 18
+#define clk_HFPERCLKUSART0 19
+#define clk_HFPERCLKUSART1 20
+#define clk_HFPERCLKUSART2 21
+#define clk_HFPERCLKUART0 22
+#define clk_HFPERCLKUART1 23
+#define clk_HFPERCLKTIMER0 24
+#define clk_HFPERCLKTIMER1 25
+#define clk_HFPERCLKTIMER2 26
+#define clk_HFPERCLKTIMER3 27
+#define clk_HFPERCLKACMP0 28
+#define clk_HFPERCLKACMP1 29
+#define clk_HFPERCLKI2C0 30
+#define clk_HFPERCLKI2C1 31
+#define clk_HFPERCLKGPIO 32
+#define clk_HFPERCLKVCMP 33
+#define clk_HFPERCLKPRS 34
+#define clk_HFPERCLKADC0 35
+#define clk_HFPERCLKDAC0 36
+
+#endif /* __DT_BINDINGS_CLOCK_EFM32_CMU_H */
diff --git a/include/dt-bindings/clock/exynos-audss-clk.h b/include/dt-bindings/clock/exynos-audss-clk.h
new file mode 100644
index 000000000..0ae6f5a75
--- /dev/null
+++ b/include/dt-bindings/clock/exynos-audss-clk.h
@@ -0,0 +1,26 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS 0
+#define EXYNOS_MOUT_I2S 1
+#define EXYNOS_DOUT_SRP 2
+#define EXYNOS_DOUT_AUD_BUS 3
+#define EXYNOS_DOUT_I2S 4
+#define EXYNOS_SRP_CLK 5
+#define EXYNOS_I2S_BUS 6
+#define EXYNOS_SCLK_I2S 7
+#define EXYNOS_PCM_BUS 8
+#define EXYNOS_SCLK_PCM 9
+#define EXYNOS_ADMA 10
+
+#define EXYNOS_AUDSS_MAX_CLKS 11
+
+#endif
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
new file mode 100644
index 000000000..aab088d30
--- /dev/null
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Tomasz Figa <t.figa@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos3250 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL 1
+#define CLK_FIN_PLL 2
+#define CLK_FOUT_APLL 3
+#define CLK_FOUT_VPLL 4
+#define CLK_FOUT_UPLL 5
+#define CLK_FOUT_MPLL 6
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L 16
+#define CLK_MOUT_GDL 17
+#define CLK_MOUT_MPLL_USER_R 18
+#define CLK_MOUT_GDR 19
+#define CLK_MOUT_EBI 20
+#define CLK_MOUT_ACLK_200 21
+#define CLK_MOUT_ACLK_160 22
+#define CLK_MOUT_ACLK_100 23
+#define CLK_MOUT_ACLK_266_1 24
+#define CLK_MOUT_ACLK_266_0 25
+#define CLK_MOUT_ACLK_266 26
+#define CLK_MOUT_VPLL 27
+#define CLK_MOUT_EPLL_USER 28
+#define CLK_MOUT_EBI_1 29
+#define CLK_MOUT_UPLL 30
+#define CLK_MOUT_ACLK_400_MCUISP_SUB 31
+#define CLK_MOUT_MPLL 32
+#define CLK_MOUT_ACLK_400_MCUISP 33
+#define CLK_MOUT_VPLLSRC 34
+#define CLK_MOUT_CAM1 35
+#define CLK_MOUT_CAM_BLK 36
+#define CLK_MOUT_MFC 37
+#define CLK_MOUT_MFC_1 38
+#define CLK_MOUT_MFC_0 39
+#define CLK_MOUT_G3D 40
+#define CLK_MOUT_G3D_1 41
+#define CLK_MOUT_G3D_0 42
+#define CLK_MOUT_MIPI0 43
+#define CLK_MOUT_FIMD0 44
+#define CLK_MOUT_UART_ISP 45
+#define CLK_MOUT_SPI1_ISP 46
+#define CLK_MOUT_SPI0_ISP 47
+#define CLK_MOUT_TSADC 48
+#define CLK_MOUT_MMC1 49
+#define CLK_MOUT_MMC0 50
+#define CLK_MOUT_UART1 51
+#define CLK_MOUT_UART0 52
+#define CLK_MOUT_SPI1 53
+#define CLK_MOUT_SPI0 54
+#define CLK_MOUT_AUDIO 55
+#define CLK_MOUT_MPLL_USER_C 56
+#define CLK_MOUT_HPM 57
+#define CLK_MOUT_CORE 58
+#define CLK_MOUT_APLL 59
+#define CLK_MOUT_ACLK_266_SUB 60
+
+/* Dividers */
+#define CLK_DIV_GPL 64
+#define CLK_DIV_GDL 65
+#define CLK_DIV_GPR 66
+#define CLK_DIV_GDR 67
+#define CLK_DIV_MPLL_PRE 68
+#define CLK_DIV_ACLK_400_MCUISP 69
+#define CLK_DIV_EBI 70
+#define CLK_DIV_ACLK_200 71
+#define CLK_DIV_ACLK_160 72
+#define CLK_DIV_ACLK_100 73
+#define CLK_DIV_ACLK_266 74
+#define CLK_DIV_CAM1 75
+#define CLK_DIV_CAM_BLK 76
+#define CLK_DIV_MFC 77
+#define CLK_DIV_G3D 78
+#define CLK_DIV_MIPI0_PRE 79
+#define CLK_DIV_MIPI0 80
+#define CLK_DIV_FIMD0 81
+#define CLK_DIV_UART_ISP 82
+#define CLK_DIV_SPI1_ISP_PRE 83
+#define CLK_DIV_SPI1_ISP 84
+#define CLK_DIV_SPI0_ISP_PRE 85
+#define CLK_DIV_SPI0_ISP 86
+#define CLK_DIV_TSADC_PRE 87
+#define CLK_DIV_TSADC 88
+#define CLK_DIV_MMC1_PRE 89
+#define CLK_DIV_MMC1 90
+#define CLK_DIV_MMC0_PRE 91
+#define CLK_DIV_MMC0 92
+#define CLK_DIV_UART1 93
+#define CLK_DIV_UART0 94
+#define CLK_DIV_SPI1_PRE 95
+#define CLK_DIV_SPI1 96
+#define CLK_DIV_SPI0_PRE 97
+#define CLK_DIV_SPI0 98
+#define CLK_DIV_PCM 99
+#define CLK_DIV_AUDIO 100
+#define CLK_DIV_I2S 101
+#define CLK_DIV_CORE2 102
+#define CLK_DIV_APLL 103
+#define CLK_DIV_PCLK_DBG 104
+#define CLK_DIV_ATB 105
+#define CLK_DIV_COREM 106
+#define CLK_DIV_CORE 107
+#define CLK_DIV_HPM 108
+#define CLK_DIV_COPY 109
+
+/* Gates */
+#define CLK_ASYNC_G3D 128
+#define CLK_ASYNC_MFCL 129
+#define CLK_PPMULEFT 130
+#define CLK_GPIO_LEFT 131
+#define CLK_ASYNC_ISPMX 132
+#define CLK_ASYNC_FSYSD 133
+#define CLK_ASYNC_LCD0X 134
+#define CLK_ASYNC_CAMX 135
+#define CLK_PPMURIGHT 136
+#define CLK_GPIO_RIGHT 137
+#define CLK_MONOCNT 138
+#define CLK_TZPC6 139
+#define CLK_PROVISIONKEY1 140
+#define CLK_PROVISIONKEY0 141
+#define CLK_CMU_ISPPART 142
+#define CLK_TMU_APBIF 143
+#define CLK_KEYIF 144
+#define CLK_RTC 145
+#define CLK_WDT 146
+#define CLK_MCT 147
+#define CLK_SECKEY 148
+#define CLK_TZPC5 149
+#define CLK_TZPC4 150
+#define CLK_TZPC3 151
+#define CLK_TZPC2 152
+#define CLK_TZPC1 153
+#define CLK_TZPC0 154
+#define CLK_CMU_COREPART 155
+#define CLK_CMU_TOPPART 156
+#define CLK_PMU_APBIF 157
+#define CLK_SYSREG 158
+#define CLK_CHIP_ID 159
+#define CLK_QEJPEG 160
+#define CLK_PIXELASYNCM1 161
+#define CLK_PIXELASYNCM0 162
+#define CLK_PPMUCAMIF 163
+#define CLK_QEM2MSCALER 164
+#define CLK_QEGSCALER1 165
+#define CLK_QEGSCALER0 166
+#define CLK_SMMUJPEG 167
+#define CLK_SMMUM2M2SCALER 168
+#define CLK_SMMUGSCALER1 169
+#define CLK_SMMUGSCALER0 170
+#define CLK_JPEG 171
+#define CLK_M2MSCALER 172
+#define CLK_GSCALER1 173
+#define CLK_GSCALER0 174
+#define CLK_QEMFC 175
+#define CLK_PPMUMFC_L 176
+#define CLK_SMMUMFC_L 177
+#define CLK_MFC 178
+#define CLK_SMMUG3D 179
+#define CLK_QEG3D 180
+#define CLK_PPMUG3D 181
+#define CLK_G3D 182
+#define CLK_QE_CH1_LCD 183
+#define CLK_QE_CH0_LCD 184
+#define CLK_PPMULCD0 185
+#define CLK_SMMUFIMD0 186
+#define CLK_DSIM0 187
+#define CLK_FIMD0 188
+#define CLK_CAM1 189
+#define CLK_UART_ISP_TOP 190
+#define CLK_SPI1_ISP_TOP 191
+#define CLK_SPI0_ISP_TOP 192
+#define CLK_TSADC 193
+#define CLK_PPMUFILE 194
+#define CLK_USBOTG 195
+#define CLK_USBHOST 196
+#define CLK_SROMC 197
+#define CLK_SDMMC1 198
+#define CLK_SDMMC0 199
+#define CLK_PDMA1 200
+#define CLK_PDMA0 201
+#define CLK_PWM 202
+#define CLK_PCM 203
+#define CLK_I2S 204
+#define CLK_SPI1 205
+#define CLK_SPI0 206
+#define CLK_I2C7 207
+#define CLK_I2C6 208
+#define CLK_I2C5 209
+#define CLK_I2C4 210
+#define CLK_I2C3 211
+#define CLK_I2C2 212
+#define CLK_I2C1 213
+#define CLK_I2C0 214
+#define CLK_UART1 215
+#define CLK_UART0 216
+#define CLK_BLOCK_LCD 217
+#define CLK_BLOCK_G3D 218
+#define CLK_BLOCK_MFC 219
+#define CLK_BLOCK_CAM 220
+#define CLK_SMIES 221
+
+/* Special clocks */
+#define CLK_SCLK_JPEG 224
+#define CLK_SCLK_M2MSCALER 225
+#define CLK_SCLK_GSCALER1 226
+#define CLK_SCLK_GSCALER0 227
+#define CLK_SCLK_MFC 228
+#define CLK_SCLK_G3D 229
+#define CLK_SCLK_MIPIDPHY2L 230
+#define CLK_SCLK_MIPI0 231
+#define CLK_SCLK_FIMD0 232
+#define CLK_SCLK_CAM1 233
+#define CLK_SCLK_UART_ISP 234
+#define CLK_SCLK_SPI1_ISP 235
+#define CLK_SCLK_SPI0_ISP 236
+#define CLK_SCLK_UPLL 237
+#define CLK_SCLK_TSADC 238
+#define CLK_SCLK_EBI 239
+#define CLK_SCLK_MMC1 240
+#define CLK_SCLK_MMC0 241
+#define CLK_SCLK_I2S 242
+#define CLK_SCLK_PCM 243
+#define CLK_SCLK_SPI1 244
+#define CLK_SCLK_SPI0 245
+#define CLK_SCLK_UART1 246
+#define CLK_SCLK_UART0 247
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS 248
+
+/*
+ * CMU DMC
+ */
+
+#define CLK_FOUT_BPLL 1
+#define CLK_FOUT_EPLL 2
+
+/* Muxes */
+#define CLK_MOUT_MPLL_MIF 8
+#define CLK_MOUT_BPLL 9
+#define CLK_MOUT_DPHY 10
+#define CLK_MOUT_DMC_BUS 11
+#define CLK_MOUT_EPLL 12
+
+/* Dividers */
+#define CLK_DIV_DMC 16
+#define CLK_DIV_DPHY 17
+#define CLK_DIV_DMC_PRE 18
+#define CLK_DIV_DMCP 19
+#define CLK_DIV_DMCD 20
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_DMC 21
+
+/*
+ * CMU ISP
+ */
+
+/* Dividers */
+
+#define CLK_DIV_ISP1 1
+#define CLK_DIV_ISP0 2
+#define CLK_DIV_MCUISP1 3
+#define CLK_DIV_MCUISP0 4
+#define CLK_DIV_MPWM 5
+
+/* Gates */
+
+#define CLK_UART_ISP 8
+#define CLK_WDT_ISP 9
+#define CLK_PWM_ISP 10
+#define CLK_I2C1_ISP 11
+#define CLK_I2C0_ISP 12
+#define CLK_MPWM_ISP 13
+#define CLK_MCUCTL_ISP 14
+#define CLK_PPMUISPX 15
+#define CLK_PPMUISPMX 16
+#define CLK_QE_LITE1 17
+#define CLK_QE_LITE0 18
+#define CLK_QE_FD 19
+#define CLK_QE_DRC 20
+#define CLK_QE_ISP 21
+#define CLK_CSIS1 22
+#define CLK_SMMU_LITE1 23
+#define CLK_SMMU_LITE0 24
+#define CLK_SMMU_FD 25
+#define CLK_SMMU_DRC 26
+#define CLK_SMMU_ISP 27
+#define CLK_GICISP 28
+#define CLK_CSIS0 29
+#define CLK_MCUISP 30
+#define CLK_LITE1 31
+#define CLK_LITE0 32
+#define CLK_FD 33
+#define CLK_DRC 34
+#define CLK_ISP 35
+#define CLK_QE_ISPCX 36
+#define CLK_QE_SCALERP 37
+#define CLK_QE_SCALERC 38
+#define CLK_SMMU_SCALERP 39
+#define CLK_SMMU_SCALERC 40
+#define CLK_SCALERP 41
+#define CLK_SCALERC 42
+#define CLK_SPI1_ISP 43
+#define CLK_SPI0_ISP 44
+#define CLK_SMMU_ISPCX 45
+#define CLK_ASYNCAXIM 46
+#define CLK_SCLK_MPWM_ISP 47
+
+/*
+ * Total number of clocks of CMU_ISP.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define NR_CLKS_ISP 48
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
new file mode 100644
index 000000000..c4b1676ea
--- /dev/null
+++ b/include/dt-bindings/clock/exynos4.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos4 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_4_H
+
+/* core clocks */
+#define CLK_XXTI 1
+#define CLK_XUSBXTI 2
+#define CLK_FIN_PLL 3
+#define CLK_FOUT_APLL 4
+#define CLK_FOUT_MPLL 5
+#define CLK_FOUT_EPLL 6
+#define CLK_FOUT_VPLL 7
+#define CLK_SCLK_APLL 8
+#define CLK_SCLK_MPLL 9
+#define CLK_SCLK_EPLL 10
+#define CLK_SCLK_VPLL 11
+#define CLK_ARM_CLK 12
+#define CLK_ACLK200 13
+#define CLK_ACLK100 14
+#define CLK_ACLK160 15
+#define CLK_ACLK133 16
+#define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
+#define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
+#define CLK_MOUT_CORE 19
+#define CLK_MOUT_APLL 20
+#define CLK_SCLK_HDMIPHY 22
+#define CLK_OUT_DMC 23
+#define CLK_OUT_TOP 24
+#define CLK_OUT_LEFTBUS 25
+#define CLK_OUT_RIGHTBUS 26
+#define CLK_OUT_CPU 27
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_FIMC0 128
+#define CLK_SCLK_FIMC1 129
+#define CLK_SCLK_FIMC2 130
+#define CLK_SCLK_FIMC3 131
+#define CLK_SCLK_CAM0 132
+#define CLK_SCLK_CAM1 133
+#define CLK_SCLK_CSIS0 134
+#define CLK_SCLK_CSIS1 135
+#define CLK_SCLK_HDMI 136
+#define CLK_SCLK_MIXER 137
+#define CLK_SCLK_DAC 138
+#define CLK_SCLK_PIXEL 139
+#define CLK_SCLK_FIMD0 140
+#define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
+#define CLK_SCLK_MDNIE_PWM0 142
+#define CLK_SCLK_MIPI0 143
+#define CLK_SCLK_AUDIO0 144
+#define CLK_SCLK_MMC0 145
+#define CLK_SCLK_MMC1 146
+#define CLK_SCLK_MMC2 147
+#define CLK_SCLK_MMC3 148
+#define CLK_SCLK_MMC4 149
+#define CLK_SCLK_SATA 150 /* Exynos4210 only */
+#define CLK_SCLK_UART0 151
+#define CLK_SCLK_UART1 152
+#define CLK_SCLK_UART2 153
+#define CLK_SCLK_UART3 154
+#define CLK_SCLK_UART4 155
+#define CLK_SCLK_AUDIO1 156
+#define CLK_SCLK_AUDIO2 157
+#define CLK_SCLK_SPDIF 158
+#define CLK_SCLK_SPI0 159
+#define CLK_SCLK_SPI1 160
+#define CLK_SCLK_SPI2 161
+#define CLK_SCLK_SLIMBUS 162
+#define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
+#define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
+#define CLK_SCLK_PCM1 165
+#define CLK_SCLK_PCM2 166
+#define CLK_SCLK_I2S1 167
+#define CLK_SCLK_I2S2 168
+#define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
+#define CLK_SCLK_MFC 170
+#define CLK_SCLK_PCM0 171
+#define CLK_SCLK_G3D 172
+#define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
+#define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
+#define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
+#define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
+#define CLK_SCLK_FIMG2D 177
+
+/* gate clocks */
+#define CLK_FIMC0 256
+#define CLK_FIMC1 257
+#define CLK_FIMC2 258
+#define CLK_FIMC3 259
+#define CLK_CSIS0 260
+#define CLK_CSIS1 261
+#define CLK_JPEG 262
+#define CLK_SMMU_FIMC0 263
+#define CLK_SMMU_FIMC1 264
+#define CLK_SMMU_FIMC2 265
+#define CLK_SMMU_FIMC3 266
+#define CLK_SMMU_JPEG 267
+#define CLK_VP 268
+#define CLK_MIXER 269
+#define CLK_TVENC 270 /* Exynos4210 only */
+#define CLK_HDMI 271
+#define CLK_SMMU_TV 272
+#define CLK_MFC 273
+#define CLK_SMMU_MFCL 274
+#define CLK_SMMU_MFCR 275
+#define CLK_G3D 276
+#define CLK_G2D 277
+#define CLK_ROTATOR 278
+#define CLK_MDMA 279
+#define CLK_SMMU_G2D 280
+#define CLK_SMMU_ROTATOR 281
+#define CLK_SMMU_MDMA 282
+#define CLK_FIMD0 283
+#define CLK_MIE0 284
+#define CLK_MDNIE0 285 /* Exynos4412 only */
+#define CLK_DSIM0 286
+#define CLK_SMMU_FIMD0 287
+#define CLK_FIMD1 288 /* Exynos4210 only */
+#define CLK_MIE1 289 /* Exynos4210 only */
+#define CLK_DSIM1 290 /* Exynos4210 only */
+#define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
+#define CLK_PDMA0 292
+#define CLK_PDMA1 293
+#define CLK_PCIE_PHY 294
+#define CLK_SATA_PHY 295 /* Exynos4210 only */
+#define CLK_TSI 296
+#define CLK_SDMMC0 297
+#define CLK_SDMMC1 298
+#define CLK_SDMMC2 299
+#define CLK_SDMMC3 300
+#define CLK_SDMMC4 301
+#define CLK_SATA 302 /* Exynos4210 only */
+#define CLK_SROMC 303
+#define CLK_USB_HOST 304
+#define CLK_USB_DEVICE 305
+#define CLK_PCIE 306
+#define CLK_ONENAND 307
+#define CLK_NFCON 308
+#define CLK_SMMU_PCIE 309
+#define CLK_GPS 310
+#define CLK_SMMU_GPS 311
+#define CLK_UART0 312
+#define CLK_UART1 313
+#define CLK_UART2 314
+#define CLK_UART3 315
+#define CLK_UART4 316
+#define CLK_I2C0 317
+#define CLK_I2C1 318
+#define CLK_I2C2 319
+#define CLK_I2C3 320
+#define CLK_I2C4 321
+#define CLK_I2C5 322
+#define CLK_I2C6 323
+#define CLK_I2C7 324
+#define CLK_I2C_HDMI 325
+#define CLK_TSADC 326
+#define CLK_SPI0 327
+#define CLK_SPI1 328
+#define CLK_SPI2 329
+#define CLK_I2S1 330
+#define CLK_I2S2 331
+#define CLK_PCM0 332
+#define CLK_I2S0 333
+#define CLK_PCM1 334
+#define CLK_PCM2 335
+#define CLK_PWM 336
+#define CLK_SLIMBUS 337
+#define CLK_SPDIF 338
+#define CLK_AC97 339
+#define CLK_MODEMIF 340
+#define CLK_CHIPID 341
+#define CLK_SYSREG 342
+#define CLK_HDMI_CEC 343
+#define CLK_MCT 344
+#define CLK_WDT 345
+#define CLK_RTC 346
+#define CLK_KEYIF 347
+#define CLK_AUDSS 348
+#define CLK_MIPI_HSI 349 /* Exynos4210 only */
+#define CLK_PIXELASYNCM0 351
+#define CLK_PIXELASYNCM1 352
+#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
+#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
+#define CLK_PPMUISPX 355 /* Exynos4x12 only */
+#define CLK_PPMUISPMX 356 /* Exynos4x12 only */
+#define CLK_FIMC_ISP 357 /* Exynos4x12 only */
+#define CLK_FIMC_DRC 358 /* Exynos4x12 only */
+#define CLK_FIMC_FD 359 /* Exynos4x12 only */
+#define CLK_MCUISP 360 /* Exynos4x12 only */
+#define CLK_GICISP 361 /* Exynos4x12 only */
+#define CLK_SMMU_ISP 362 /* Exynos4x12 only */
+#define CLK_SMMU_DRC 363 /* Exynos4x12 only */
+#define CLK_SMMU_FD 364 /* Exynos4x12 only */
+#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
+#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
+#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
+#define CLK_MPWM_ISP 368 /* Exynos4x12 only */
+#define CLK_I2C0_ISP 369 /* Exynos4x12 only */
+#define CLK_I2C1_ISP 370 /* Exynos4x12 only */
+#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
+#define CLK_PWM_ISP 372 /* Exynos4x12 only */
+#define CLK_WDT_ISP 373 /* Exynos4x12 only */
+#define CLK_UART_ISP 374 /* Exynos4x12 only */
+#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
+#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
+#define CLK_SPI0_ISP 377 /* Exynos4x12 only */
+#define CLK_SPI1_ISP 378 /* Exynos4x12 only */
+#define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
+#define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
+#define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
+#define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
+#define CLK_TMU_APBIF 383
+
+/* mux clocks */
+#define CLK_MOUT_FIMC0 384
+#define CLK_MOUT_FIMC1 385
+#define CLK_MOUT_FIMC2 386
+#define CLK_MOUT_FIMC3 387
+#define CLK_MOUT_CAM0 388
+#define CLK_MOUT_CAM1 389
+#define CLK_MOUT_CSIS0 390
+#define CLK_MOUT_CSIS1 391
+#define CLK_MOUT_G3D0 392
+#define CLK_MOUT_G3D1 393
+#define CLK_MOUT_G3D 394
+#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
+#define CLK_MOUT_HDMI 396
+#define CLK_MOUT_MIXER 397
+
+/* gate clocks - ppmu */
+#define CLK_PPMULEFT 400
+#define CLK_PPMURIGHT 401
+#define CLK_PPMUCAMIF 402
+#define CLK_PPMUTV 403
+#define CLK_PPMUMFC_L 404
+#define CLK_PPMUMFC_R 405
+#define CLK_PPMUG3D 406
+#define CLK_PPMUIMAGE 407
+#define CLK_PPMULCD0 408
+#define CLK_PPMULCD1 409 /* Exynos4210 only */
+#define CLK_PPMUFILE 410
+#define CLK_PPMUGPS 411
+#define CLK_PPMUDMC0 412
+#define CLK_PPMUDMC1 413
+#define CLK_PPMUCPU 414
+#define CLK_PPMUACP 415
+
+/* div clocks */
+#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
+#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
+#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
+#define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
+#define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
+#define CLK_DIV_ACP 456
+#define CLK_DIV_DMC 457
+#define CLK_DIV_C2C 458 /* Exynos4x12 only */
+#define CLK_DIV_GDL 459
+#define CLK_DIV_GDR 460
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS 461
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos4415.h b/include/dt-bindings/clock/exynos4415.h
new file mode 100644
index 000000000..7eed55100
--- /dev/null
+++ b/include/dt-bindings/clock/exynos4415.h
@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung Exynos4415 clock controllers.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/*
+ * Main CMU
+ */
+
+#define CLK_OSCSEL 1
+#define CLK_FIN_PLL 2
+#define CLK_FOUT_APLL 3
+#define CLK_FOUT_MPLL 4
+#define CLK_FOUT_EPLL 5
+#define CLK_FOUT_G3D_PLL 6
+#define CLK_FOUT_ISP_PLL 7
+#define CLK_FOUT_DISP_PLL 8
+
+/* Muxes */
+#define CLK_MOUT_MPLL_USER_L 16
+#define CLK_MOUT_GDL 17
+#define CLK_MOUT_MPLL_USER_R 18
+#define CLK_MOUT_GDR 19
+#define CLK_MOUT_EBI 20
+#define CLK_MOUT_ACLK_200 21
+#define CLK_MOUT_ACLK_160 22
+#define CLK_MOUT_ACLK_100 23
+#define CLK_MOUT_ACLK_266 24
+#define CLK_MOUT_G3D_PLL 25
+#define CLK_MOUT_EPLL 26
+#define CLK_MOUT_EBI_1 27
+#define CLK_MOUT_ISP_PLL 28
+#define CLK_MOUT_DISP_PLL 29
+#define CLK_MOUT_MPLL_USER_T 30
+#define CLK_MOUT_ACLK_400_MCUISP 31
+#define CLK_MOUT_G3D_PLLSRC 32
+#define CLK_MOUT_CSIS1 33
+#define CLK_MOUT_CSIS0 34
+#define CLK_MOUT_CAM1 35
+#define CLK_MOUT_FIMC3_LCLK 36
+#define CLK_MOUT_FIMC2_LCLK 37
+#define CLK_MOUT_FIMC1_LCLK 38
+#define CLK_MOUT_FIMC0_LCLK 39
+#define CLK_MOUT_MFC 40
+#define CLK_MOUT_MFC_1 41
+#define CLK_MOUT_MFC_0 42
+#define CLK_MOUT_G3D 43
+#define CLK_MOUT_G3D_1 44
+#define CLK_MOUT_G3D_0 45
+#define CLK_MOUT_MIPI0 46
+#define CLK_MOUT_FIMD0 47
+#define CLK_MOUT_TSADC_ISP 48
+#define CLK_MOUT_UART_ISP 49
+#define CLK_MOUT_SPI1_ISP 50
+#define CLK_MOUT_SPI0_ISP 51
+#define CLK_MOUT_PWM_ISP 52
+#define CLK_MOUT_AUDIO0 53
+#define CLK_MOUT_TSADC 54
+#define CLK_MOUT_MMC2 55
+#define CLK_MOUT_MMC1 56
+#define CLK_MOUT_MMC0 57
+#define CLK_MOUT_UART3 58
+#define CLK_MOUT_UART2 59
+#define CLK_MOUT_UART1 60
+#define CLK_MOUT_UART0 61
+#define CLK_MOUT_SPI2 62
+#define CLK_MOUT_SPI1 63
+#define CLK_MOUT_SPI0 64
+#define CLK_MOUT_SPDIF 65
+#define CLK_MOUT_AUDIO2 66
+#define CLK_MOUT_AUDIO1 67
+#define CLK_MOUT_MPLL_USER_C 68
+#define CLK_MOUT_HPM 69
+#define CLK_MOUT_CORE 70
+#define CLK_MOUT_APLL 71
+#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
+#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
+#define CLK_MOUT_JPEG 74
+#define CLK_MOUT_JPEG1 75
+#define CLK_MOUT_JPEG0 76
+#define CLK_MOUT_ACLK_ISP0_300 77
+#define CLK_MOUT_ACLK_ISP0_400 78
+#define CLK_MOUT_ACLK_ISP0_300_USER 79
+#define CLK_MOUT_ACLK_ISP1_300 80
+#define CLK_MOUT_ACLK_ISP1_300_USER 81
+#define CLK_MOUT_HDMI 82
+
+/* Dividers */
+#define CLK_DIV_GPL 90
+#define CLK_DIV_GDL 91
+#define CLK_DIV_GPR 92
+#define CLK_DIV_GDR 93
+#define CLK_DIV_ACLK_400_MCUISP 94
+#define CLK_DIV_EBI 95
+#define CLK_DIV_ACLK_200 96
+#define CLK_DIV_ACLK_160 97
+#define CLK_DIV_ACLK_100 98
+#define CLK_DIV_ACLK_266 99
+#define CLK_DIV_CSIS1 100
+#define CLK_DIV_CSIS0 101
+#define CLK_DIV_CAM1 102
+#define CLK_DIV_FIMC3_LCLK 103
+#define CLK_DIV_FIMC2_LCLK 104
+#define CLK_DIV_FIMC1_LCLK 105
+#define CLK_DIV_FIMC0_LCLK 106
+#define CLK_DIV_TV_BLK 107
+#define CLK_DIV_MFC 108
+#define CLK_DIV_G3D 109
+#define CLK_DIV_MIPI0_PRE 110
+#define CLK_DIV_MIPI0 111
+#define CLK_DIV_FIMD0 112
+#define CLK_DIV_UART_ISP 113
+#define CLK_DIV_SPI1_ISP_PRE 114
+#define CLK_DIV_SPI1_ISP 115
+#define CLK_DIV_SPI0_ISP_PRE 116
+#define CLK_DIV_SPI0_ISP 117
+#define CLK_DIV_PWM_ISP 118
+#define CLK_DIV_PCM0 119
+#define CLK_DIV_AUDIO0 120
+#define CLK_DIV_TSADC_PRE 121
+#define CLK_DIV_TSADC 122
+#define CLK_DIV_MMC1_PRE 123
+#define CLK_DIV_MMC1 124
+#define CLK_DIV_MMC0_PRE 125
+#define CLK_DIV_MMC0 126
+#define CLK_DIV_MMC2_PRE 127
+#define CLK_DIV_MMC2 128
+#define CLK_DIV_UART3 129
+#define CLK_DIV_UART2 130
+#define CLK_DIV_UART1 131
+#define CLK_DIV_UART0 132
+#define CLK_DIV_SPI1_PRE 133
+#define CLK_DIV_SPI1 134
+#define CLK_DIV_SPI0_PRE 135
+#define CLK_DIV_SPI0 136
+#define CLK_DIV_SPI2_PRE 137
+#define CLK_DIV_SPI2 138
+#define CLK_DIV_PCM2 139
+#define CLK_DIV_AUDIO2 140
+#define CLK_DIV_PCM1 141
+#define CLK_DIV_AUDIO1 142
+#define CLK_DIV_I2S1 143
+#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
+#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
+#define CLK_DIV_JPEG 146
+#define CLK_DIV_CORE2 147
+#define CLK_DIV_APLL 148
+#define CLK_DIV_PCLK_DBG 149
+#define CLK_DIV_ATB 150
+#define CLK_DIV_PERIPH 151
+#define CLK_DIV_COREM1 152
+#define CLK_DIV_COREM0 153
+#define CLK_DIV_CORE 154
+#define CLK_DIV_HPM 155
+#define CLK_DIV_COPY 156
+
+/* Gates */
+#define CLK_ASYNC_G3D 180
+#define CLK_ASYNC_MFCL 181
+#define CLK_ASYNC_TVX 182
+#define CLK_PPMULEFT 183
+#define CLK_GPIO_LEFT 184
+#define CLK_PPMUIMAGE 185
+#define CLK_QEMDMA2 186
+#define CLK_QEROTATOR 187
+#define CLK_SMMUMDMA2 188
+#define CLK_SMMUROTATOR 189
+#define CLK_MDMA2 190
+#define CLK_ROTATOR 191
+#define CLK_ASYNC_ISPMX 192
+#define CLK_ASYNC_MAUDIOX 193
+#define CLK_ASYNC_MFCR 194
+#define CLK_ASYNC_FSYSD 195
+#define CLK_ASYNC_LCD0X 196
+#define CLK_ASYNC_CAMX 197
+#define CLK_PPMURIGHT 198
+#define CLK_GPIO_RIGHT 199
+#define CLK_ANTIRBK_APBIF 200
+#define CLK_EFUSE_WRITER_APBIF 201
+#define CLK_MONOCNT 202
+#define CLK_TZPC6 203
+#define CLK_PROVISIONKEY1 204
+#define CLK_PROVISIONKEY0 205
+#define CLK_CMU_ISPPART 206
+#define CLK_TMU_APBIF 207
+#define CLK_KEYIF 208
+#define CLK_RTC 209
+#define CLK_WDT 210
+#define CLK_MCT 211
+#define CLK_SECKEY 212
+#define CLK_HDMI_CEC 213
+#define CLK_TZPC5 214
+#define CLK_TZPC4 215
+#define CLK_TZPC3 216
+#define CLK_TZPC2 217
+#define CLK_TZPC1 218
+#define CLK_TZPC0 219
+#define CLK_CMU_COREPART 220
+#define CLK_CMU_TOPPART 221
+#define CLK_PMU_APBIF 222
+#define CLK_SYSREG 223
+#define CLK_CHIP_ID 224
+#define CLK_SMMUFIMC_LITE2 225
+#define CLK_FIMC_LITE2 226
+#define CLK_PIXELASYNCM1 227
+#define CLK_PIXELASYNCM0 228
+#define CLK_PPMUCAMIF 229
+#define CLK_SMMUJPEG 230
+#define CLK_SMMUFIMC3 231
+#define CLK_SMMUFIMC2 232
+#define CLK_SMMUFIMC1 233
+#define CLK_SMMUFIMC0 234
+#define CLK_JPEG 235
+#define CLK_CSIS1 236
+#define CLK_CSIS0 237
+#define CLK_FIMC3 238
+#define CLK_FIMC2 239
+#define CLK_FIMC1 240
+#define CLK_FIMC0 241
+#define CLK_PPMUTV 242
+#define CLK_SMMUTV 243
+#define CLK_HDMI 244
+#define CLK_MIXER 245
+#define CLK_VP 246
+#define CLK_PPMUMFC_R 247
+#define CLK_PPMUMFC_L 248
+#define CLK_SMMUMFC_R 249
+#define CLK_SMMUMFC_L 250
+#define CLK_MFC 251
+#define CLK_PPMUG3D 252
+#define CLK_G3D 253
+#define CLK_PPMULCD0 254
+#define CLK_SMMUFIMD0 255
+#define CLK_DSIM0 256
+#define CLK_SMIES 257
+#define CLK_MIE0 258
+#define CLK_FIMD0 259
+#define CLK_TSADC 260
+#define CLK_PPMUFILE 261
+#define CLK_NFCON 262
+#define CLK_USBDEVICE 263
+#define CLK_USBHOST 264
+#define CLK_SROMC 265
+#define CLK_SDMMC2 266
+#define CLK_SDMMC1 267
+#define CLK_SDMMC0 268
+#define CLK_PDMA1 269
+#define CLK_PDMA0 270
+#define CLK_SPDIF 271
+#define CLK_PWM 272
+#define CLK_PCM2 273
+#define CLK_PCM1 274
+#define CLK_I2S1 275
+#define CLK_SPI2 276
+#define CLK_SPI1 277
+#define CLK_SPI0 278
+#define CLK_I2CHDMI 279
+#define CLK_I2C7 280
+#define CLK_I2C6 281
+#define CLK_I2C5 282
+#define CLK_I2C4 283
+#define CLK_I2C3 284
+#define CLK_I2C2 285
+#define CLK_I2C1 286
+#define CLK_I2C0 287
+#define CLK_UART3 288
+#define CLK_UART2 289
+#define CLK_UART1 290
+#define CLK_UART0 291
+
+/* Special clocks */
+#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
+#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
+#define CLK_SCLK_JPEG 332
+#define CLK_SCLK_CSIS1 333
+#define CLK_SCLK_CSIS0 334
+#define CLK_SCLK_CAM1 335
+#define CLK_SCLK_FIMC3_LCLK 336
+#define CLK_SCLK_FIMC2_LCLK 337
+#define CLK_SCLK_FIMC1_LCLK 338
+#define CLK_SCLK_FIMC0_LCLK 339
+#define CLK_SCLK_PIXEL 340
+#define CLK_SCLK_HDMI 341
+#define CLK_SCLK_MIXER 342
+#define CLK_SCLK_MFC 343
+#define CLK_SCLK_G3D 344
+#define CLK_SCLK_MIPIDPHY4L 345
+#define CLK_SCLK_MIPI0 346
+#define CLK_SCLK_MDNIE0 347
+#define CLK_SCLK_FIMD0 348
+#define CLK_SCLK_PCM0 349
+#define CLK_SCLK_AUDIO0 350
+#define CLK_SCLK_TSADC 351
+#define CLK_SCLK_EBI 352
+#define CLK_SCLK_MMC2 353
+#define CLK_SCLK_MMC1 354
+#define CLK_SCLK_MMC0 355
+#define CLK_SCLK_I2S 356
+#define CLK_SCLK_PCM2 357
+#define CLK_SCLK_PCM1 358
+#define CLK_SCLK_AUDIO2 359
+#define CLK_SCLK_AUDIO1 360
+#define CLK_SCLK_SPDIF 361
+#define CLK_SCLK_SPI2 362
+#define CLK_SCLK_SPI1 363
+#define CLK_SCLK_SPI0 364
+#define CLK_SCLK_UART3 365
+#define CLK_SCLK_UART2 366
+#define CLK_SCLK_UART1 367
+#define CLK_SCLK_UART0 368
+#define CLK_SCLK_HDMIPHY 369
+
+/*
+ * Total number of clocks of main CMU.
+ * NOTE: Must be equal to last clock ID increased by one.
+ */
+#define CLK_NR_CLKS 370
+
+/*
+ * CMU DMC
+ */
+#define CLK_DMC_FOUT_MPLL 1
+#define CLK_DMC_FOUT_BPLL 2
+
+#define CLK_DMC_MOUT_MPLL 3
+#define CLK_DMC_MOUT_BPLL 4
+#define CLK_DMC_MOUT_DPHY 5
+#define CLK_DMC_MOUT_DMC_BUS 6
+
+#define CLK_DMC_DIV_DMC 7
+#define CLK_DMC_DIV_DPHY 8
+#define CLK_DMC_DIV_DMC_PRE 9
+#define CLK_DMC_DIV_DMCP 10
+#define CLK_DMC_DIV_DMCD 11
+#define CLK_DMC_DIV_MPLL_PRE 12
+
+/*
+ * Total number of clocks of CMU_DMC.
+ * NOTE: Must be equal to highest clock ID increased by one.
+ */
+#define NR_CLKS_DMC 13
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
new file mode 100644
index 000000000..4273891dc
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5250 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_MPLL 3
+#define CLK_FOUT_BPLL 4
+#define CLK_FOUT_GPLL 5
+#define CLK_FOUT_CPLL 6
+#define CLK_FOUT_EPLL 7
+#define CLK_FOUT_VPLL 8
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_CAM_BAYER 128
+#define CLK_SCLK_CAM0 129
+#define CLK_SCLK_CAM1 130
+#define CLK_SCLK_GSCL_WA 131
+#define CLK_SCLK_GSCL_WB 132
+#define CLK_SCLK_FIMD1 133
+#define CLK_SCLK_MIPI1 134
+#define CLK_SCLK_DP 135
+#define CLK_SCLK_HDMI 136
+#define CLK_SCLK_PIXEL 137
+#define CLK_SCLK_AUDIO0 138
+#define CLK_SCLK_MMC0 139
+#define CLK_SCLK_MMC1 140
+#define CLK_SCLK_MMC2 141
+#define CLK_SCLK_MMC3 142
+#define CLK_SCLK_SATA 143
+#define CLK_SCLK_USB3 144
+#define CLK_SCLK_JPEG 145
+#define CLK_SCLK_UART0 146
+#define CLK_SCLK_UART1 147
+#define CLK_SCLK_UART2 148
+#define CLK_SCLK_UART3 149
+#define CLK_SCLK_PWM 150
+#define CLK_SCLK_AUDIO1 151
+#define CLK_SCLK_AUDIO2 152
+#define CLK_SCLK_SPDIF 153
+#define CLK_SCLK_SPI0 154
+#define CLK_SCLK_SPI1 155
+#define CLK_SCLK_SPI2 156
+#define CLK_DIV_I2S1 157
+#define CLK_DIV_I2S2 158
+#define CLK_SCLK_HDMIPHY 159
+#define CLK_DIV_PCM0 160
+
+/* gate clocks */
+#define CLK_GSCL0 256
+#define CLK_GSCL1 257
+#define CLK_GSCL2 258
+#define CLK_GSCL3 259
+#define CLK_GSCL_WA 260
+#define CLK_GSCL_WB 261
+#define CLK_SMMU_GSCL0 262
+#define CLK_SMMU_GSCL1 263
+#define CLK_SMMU_GSCL2 264
+#define CLK_SMMU_GSCL3 265
+#define CLK_MFC 266
+#define CLK_SMMU_MFCL 267
+#define CLK_SMMU_MFCR 268
+#define CLK_ROTATOR 269
+#define CLK_JPEG 270
+#define CLK_MDMA1 271
+#define CLK_SMMU_ROTATOR 272
+#define CLK_SMMU_JPEG 273
+#define CLK_SMMU_MDMA1 274
+#define CLK_PDMA0 275
+#define CLK_PDMA1 276
+#define CLK_SATA 277
+#define CLK_USBOTG 278
+#define CLK_MIPI_HSI 279
+#define CLK_SDMMC0 280
+#define CLK_SDMMC1 281
+#define CLK_SDMMC2 282
+#define CLK_SDMMC3 283
+#define CLK_SROMC 284
+#define CLK_USB2 285
+#define CLK_USB3 286
+#define CLK_SATA_PHYCTRL 287
+#define CLK_SATA_PHYI2C 288
+#define CLK_UART0 289
+#define CLK_UART1 290
+#define CLK_UART2 291
+#define CLK_UART3 292
+#define CLK_UART4 293
+#define CLK_I2C0 294
+#define CLK_I2C1 295
+#define CLK_I2C2 296
+#define CLK_I2C3 297
+#define CLK_I2C4 298
+#define CLK_I2C5 299
+#define CLK_I2C6 300
+#define CLK_I2C7 301
+#define CLK_I2C_HDMI 302
+#define CLK_ADC 303
+#define CLK_SPI0 304
+#define CLK_SPI1 305
+#define CLK_SPI2 306
+#define CLK_I2S1 307
+#define CLK_I2S2 308
+#define CLK_PCM1 309
+#define CLK_PCM2 310
+#define CLK_PWM 311
+#define CLK_SPDIF 312
+#define CLK_AC97 313
+#define CLK_HSI2C0 314
+#define CLK_HSI2C1 315
+#define CLK_HSI2C2 316
+#define CLK_HSI2C3 317
+#define CLK_CHIPID 318
+#define CLK_SYSREG 319
+#define CLK_PMU 320
+#define CLK_CMU_TOP 321
+#define CLK_CMU_CORE 322
+#define CLK_CMU_MEM 323
+#define CLK_TZPC0 324
+#define CLK_TZPC1 325
+#define CLK_TZPC2 326
+#define CLK_TZPC3 327
+#define CLK_TZPC4 328
+#define CLK_TZPC5 329
+#define CLK_TZPC6 330
+#define CLK_TZPC7 331
+#define CLK_TZPC8 332
+#define CLK_TZPC9 333
+#define CLK_HDMI_CEC 334
+#define CLK_MCT 335
+#define CLK_WDT 336
+#define CLK_RTC 337
+#define CLK_TMU 338
+#define CLK_FIMD1 339
+#define CLK_MIE1 340
+#define CLK_DSIM0 341
+#define CLK_DP 342
+#define CLK_MIXER 343
+#define CLK_HDMI 344
+#define CLK_G2D 345
+#define CLK_MDMA0 346
+#define CLK_SMMU_MDMA0 347
+#define CLK_SSS 348
+#define CLK_G3D 349
+#define CLK_SMMU_TV 350
+#define CLK_SMMU_FIMD1 351
+#define CLK_SMMU_2D 352
+#define CLK_SMMU_FIMC_ISP 353
+#define CLK_SMMU_FIMC_DRC 354
+#define CLK_SMMU_FIMC_SCC 355
+#define CLK_SMMU_FIMC_SCP 356
+#define CLK_SMMU_FIMC_FD 357
+#define CLK_SMMU_FIMC_MCU 358
+#define CLK_SMMU_FIMC_ODC 359
+#define CLK_SMMU_FIMC_DIS0 360
+#define CLK_SMMU_FIMC_DIS1 361
+#define CLK_SMMU_FIMC_3DNR 362
+#define CLK_SMMU_FIMC_LITE0 363
+#define CLK_SMMU_FIMC_LITE1 364
+#define CLK_CAMIF_TOP 365
+
+/* mux clocks */
+#define CLK_MOUT_HDMI 1024
+#define CLK_MOUT_GPLL 1025
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS 1026
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
new file mode 100644
index 000000000..a4bac9a17
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -0,0 +1,469 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Rahul Sharma <rahul.sharma@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Provides Constants for Exynos5260 clocks.
+*/
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS5260_H
+#define _DT_BINDINGS_CLK_EXYNOS5260_H
+
+/* Clock names: <cmu><type><IP> */
+
+/* List Of Clocks For CMU_TOP */
+
+#define TOP_FOUT_DISP_PLL 1
+#define TOP_FOUT_AUD_PLL 2
+#define TOP_MOUT_AUDTOP_PLL_USER 3
+#define TOP_MOUT_AUD_PLL 4
+#define TOP_MOUT_DISP_PLL 5
+#define TOP_MOUT_BUSTOP_PLL_USER 6
+#define TOP_MOUT_MEMTOP_PLL_USER 7
+#define TOP_MOUT_MEDIATOP_PLL_USER 8
+#define TOP_MOUT_DISP_DISP_333 9
+#define TOP_MOUT_ACLK_DISP_333 10
+#define TOP_MOUT_DISP_DISP_222 11
+#define TOP_MOUT_ACLK_DISP_222 12
+#define TOP_MOUT_DISP_MEDIA_PIXEL 13
+#define TOP_MOUT_FIMD1 14
+#define TOP_MOUT_SCLK_PERI_SPI0_CLK 15
+#define TOP_MOUT_SCLK_PERI_SPI1_CLK 16
+#define TOP_MOUT_SCLK_PERI_SPI2_CLK 17
+#define TOP_MOUT_SCLK_PERI_UART0_UCLK 18
+#define TOP_MOUT_SCLK_PERI_UART2_UCLK 19
+#define TOP_MOUT_SCLK_PERI_UART1_UCLK 20
+#define TOP_MOUT_BUS4_BUSTOP_100 21
+#define TOP_MOUT_BUS4_BUSTOP_400 22
+#define TOP_MOUT_BUS3_BUSTOP_100 23
+#define TOP_MOUT_BUS3_BUSTOP_400 24
+#define TOP_MOUT_BUS2_BUSTOP_400 25
+#define TOP_MOUT_BUS2_BUSTOP_100 26
+#define TOP_MOUT_BUS1_BUSTOP_100 27
+#define TOP_MOUT_BUS1_BUSTOP_400 28
+#define TOP_MOUT_SCLK_FSYS_USB 29
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A 30
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A 31
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A 32
+#define TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B 33
+#define TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B 34
+#define TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B 35
+#define TOP_MOUT_ACLK_ISP1_266 36
+#define TOP_MOUT_ISP1_MEDIA_266 37
+#define TOP_MOUT_ACLK_ISP1_400 38
+#define TOP_MOUT_ISP1_MEDIA_400 39
+#define TOP_MOUT_SCLK_ISP1_SPI0 40
+#define TOP_MOUT_SCLK_ISP1_SPI1 41
+#define TOP_MOUT_SCLK_ISP1_UART 42
+#define TOP_MOUT_SCLK_ISP1_SENSOR2 43
+#define TOP_MOUT_SCLK_ISP1_SENSOR1 44
+#define TOP_MOUT_SCLK_ISP1_SENSOR0 45
+#define TOP_MOUT_ACLK_MFC_333 46
+#define TOP_MOUT_MFC_BUSTOP_333 47
+#define TOP_MOUT_ACLK_G2D_333 48
+#define TOP_MOUT_G2D_BUSTOP_333 49
+#define TOP_MOUT_ACLK_GSCL_FIMC 50
+#define TOP_MOUT_GSCL_BUSTOP_FIMC 51
+#define TOP_MOUT_ACLK_GSCL_333 52
+#define TOP_MOUT_GSCL_BUSTOP_333 53
+#define TOP_MOUT_ACLK_GSCL_400 54
+#define TOP_MOUT_M2M_MEDIATOP_400 55
+#define TOP_DOUT_ACLK_MFC_333 56
+#define TOP_DOUT_ACLK_G2D_333 57
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_A 58
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_A 59
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_A 60
+#define TOP_DOUT_ACLK_GSCL_FIMC 61
+#define TOP_DOUT_ACLK_GSCL_400 62
+#define TOP_DOUT_ACLK_GSCL_333 63
+#define TOP_DOUT_SCLK_ISP1_SPI0_B 64
+#define TOP_DOUT_SCLK_ISP1_SPI0_A 65
+#define TOP_DOUT_ACLK_ISP1_400 66
+#define TOP_DOUT_ACLK_ISP1_266 67
+#define TOP_DOUT_SCLK_ISP1_UART 68
+#define TOP_DOUT_SCLK_ISP1_SPI1_B 69
+#define TOP_DOUT_SCLK_ISP1_SPI1_A 70
+#define TOP_DOUT_SCLK_ISP1_SENSOR2_B 71
+#define TOP_DOUT_SCLK_ISP1_SENSOR1_B 72
+#define TOP_DOUT_SCLK_ISP1_SENSOR0_B 73
+#define TOP_DOUTTOP__SCLK_HPM_TARGETCLK 74
+#define TOP_DOUT_SCLK_DISP_PIXEL 75
+#define TOP_DOUT_ACLK_DISP_222 76
+#define TOP_DOUT_ACLK_DISP_333 77
+#define TOP_DOUT_ACLK_BUS4_100 78
+#define TOP_DOUT_ACLK_BUS4_400 79
+#define TOP_DOUT_ACLK_BUS3_100 80
+#define TOP_DOUT_ACLK_BUS3_400 81
+#define TOP_DOUT_ACLK_BUS2_100 82
+#define TOP_DOUT_ACLK_BUS2_400 83
+#define TOP_DOUT_ACLK_BUS1_100 84
+#define TOP_DOUT_ACLK_BUS1_400 85
+#define TOP_DOUT_SCLK_PERI_SPI1_B 86
+#define TOP_DOUT_SCLK_PERI_SPI1_A 87
+#define TOP_DOUT_SCLK_PERI_SPI0_B 88
+#define TOP_DOUT_SCLK_PERI_SPI0_A 89
+#define TOP_DOUT_SCLK_PERI_UART0 90
+#define TOP_DOUT_SCLK_PERI_UART2 91
+#define TOP_DOUT_SCLK_PERI_UART1 92
+#define TOP_DOUT_SCLK_PERI_SPI2_B 93
+#define TOP_DOUT_SCLK_PERI_SPI2_A 94
+#define TOP_DOUT_ACLK_PERI_AUD 95
+#define TOP_DOUT_ACLK_PERI_66 96
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B 97
+#define TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A 98
+#define TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK 99
+#define TOP_DOUT_ACLK_FSYS_200 100
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B 101
+#define TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A 102
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B 103
+#define TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A 104
+#define TOP_SCLK_FIMD1 105
+#define TOP_SCLK_MMC2 106
+#define TOP_SCLK_MMC1 107
+#define TOP_SCLK_MMC0 108
+#define PHYCLK_DPTX_PHY_CH3_TXD_CLK 109
+#define PHYCLK_DPTX_PHY_CH2_TXD_CLK 110
+#define PHYCLK_DPTX_PHY_CH1_TXD_CLK 111
+#define PHYCLK_DPTX_PHY_CH0_TXD_CLK 112
+#define phyclk_hdmi_phy_tmds_clko 113
+#define PHYCLK_HDMI_PHY_PIXEL_CLKO 114
+#define PHYCLK_HDMI_LINK_O_TMDS_CLKHI 115
+#define PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS 116
+#define PHYCLK_DPTX_PHY_O_REF_CLK_24M 117
+#define PHYCLK_DPTX_PHY_CLK_DIV2 118
+#define PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0 119
+#define PHYCLK_USBHOST20_PHY_PHYCLOCK 120
+#define PHYCLK_USBHOST20_PHY_FREECLK 121
+#define PHYCLK_USBHOST20_PHY_CLK48MOHCI 122
+#define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 123
+#define PHYCLK_USBDRD30_UDRD30_PHYCLOCK 124
+#define TOP_NR_CLK 125
+
+
+/* List Of Clocks For CMU_EGL */
+
+#define EGL_FOUT_EGL_PLL 1
+#define EGL_FOUT_EGL_DPLL 2
+#define EGL_MOUT_EGL_B 3
+#define EGL_MOUT_EGL_PLL 4
+#define EGL_DOUT_EGL_PLL 5
+#define EGL_DOUT_EGL_PCLK_DBG 6
+#define EGL_DOUT_EGL_ATCLK 7
+#define EGL_DOUT_PCLK_EGL 8
+#define EGL_DOUT_ACLK_EGL 9
+#define EGL_DOUT_EGL2 10
+#define EGL_DOUT_EGL1 11
+#define EGL_NR_CLK 12
+
+
+/* List Of Clocks For CMU_KFC */
+
+#define KFC_FOUT_KFC_PLL 1
+#define KFC_MOUT_KFC_PLL 2
+#define KFC_MOUT_KFC 3
+#define KFC_DOUT_KFC_PLL 4
+#define KFC_DOUT_PCLK_KFC 5
+#define KFC_DOUT_ACLK_KFC 6
+#define KFC_DOUT_KFC_PCLK_DBG 7
+#define KFC_DOUT_KFC_ATCLK 8
+#define KFC_DOUT_KFC2 9
+#define KFC_DOUT_KFC1 10
+#define KFC_NR_CLK 11
+
+
+/* List Of Clocks For CMU_MIF */
+
+#define MIF_FOUT_MEM_PLL 1
+#define MIF_FOUT_MEDIA_PLL 2
+#define MIF_FOUT_BUS_PLL 3
+#define MIF_MOUT_CLK2X_PHY 4
+#define MIF_MOUT_MIF_DREX2X 5
+#define MIF_MOUT_CLKM_PHY 6
+#define MIF_MOUT_MIF_DREX 7
+#define MIF_MOUT_MEDIA_PLL 8
+#define MIF_MOUT_BUS_PLL 9
+#define MIF_MOUT_MEM_PLL 10
+#define MIF_DOUT_ACLK_BUS_100 11
+#define MIF_DOUT_ACLK_BUS_200 12
+#define MIF_DOUT_ACLK_MIF_466 13
+#define MIF_DOUT_CLK2X_PHY 14
+#define MIF_DOUT_CLKM_PHY 15
+#define MIF_DOUT_BUS_PLL 16
+#define MIF_DOUT_MEM_PLL 17
+#define MIF_DOUT_MEDIA_PLL 18
+#define MIF_CLK_LPDDR3PHY_WRAP1 19
+#define MIF_CLK_LPDDR3PHY_WRAP0 20
+#define MIF_CLK_MONOCNT 21
+#define MIF_CLK_MIF_RTC 22
+#define MIF_CLK_DREX1 23
+#define MIF_CLK_DREX0 24
+#define MIF_CLK_INTMEM 25
+#define MIF_SCLK_LPDDR3PHY_WRAP_U1 26
+#define MIF_SCLK_LPDDR3PHY_WRAP_U0 27
+#define MIF_NR_CLK 28
+
+
+/* List Of Clocks For CMU_G3D */
+
+#define G3D_FOUT_G3D_PLL 1
+#define G3D_MOUT_G3D_PLL 2
+#define G3D_DOUT_PCLK_G3D 3
+#define G3D_DOUT_ACLK_G3D 4
+#define G3D_CLK_G3D_HPM 5
+#define G3D_CLK_G3D 6
+#define G3D_NR_CLK 7
+
+
+/* List Of Clocks For CMU_AUD */
+
+#define AUD_MOUT_SCLK_AUD_PCM 1
+#define AUD_MOUT_SCLK_AUD_I2S 2
+#define AUD_MOUT_AUD_PLL_USER 3
+#define AUD_DOUT_ACLK_AUD_131 4
+#define AUD_DOUT_SCLK_AUD_UART 5
+#define AUD_DOUT_SCLK_AUD_PCM 6
+#define AUD_DOUT_SCLK_AUD_I2S 7
+#define AUD_CLK_AUD_UART 8
+#define AUD_CLK_PCM 9
+#define AUD_CLK_I2S 10
+#define AUD_CLK_DMAC 11
+#define AUD_CLK_SRAMC 12
+#define AUD_SCLK_AUD_UART 13
+#define AUD_SCLK_PCM 14
+#define AUD_SCLK_I2S 15
+#define AUD_NR_CLK 16
+
+
+/* List Of Clocks For CMU_MFC */
+
+#define MFC_MOUT_ACLK_MFC_333_USER 1
+#define MFC_DOUT_PCLK_MFC_83 2
+#define MFC_CLK_MFC 3
+#define MFC_CLK_SMMU2_MFCM1 4
+#define MFC_CLK_SMMU2_MFCM0 5
+#define MFC_NR_CLK 6
+
+
+/* List Of Clocks For CMU_GSCL */
+
+#define GSCL_MOUT_ACLK_CSIS 1
+#define GSCL_MOUT_ACLK_GSCL_FIMC_USER 2
+#define GSCL_MOUT_ACLK_M2M_400_USER 3
+#define GSCL_MOUT_ACLK_GSCL_333_USER 4
+#define GSCL_DOUT_ACLK_CSIS_200 5
+#define GSCL_DOUT_PCLK_M2M_100 6
+#define GSCL_CLK_PIXEL_GSCL1 7
+#define GSCL_CLK_PIXEL_GSCL0 8
+#define GSCL_CLK_MSCL1 9
+#define GSCL_CLK_MSCL0 10
+#define GSCL_CLK_GSCL1 11
+#define GSCL_CLK_GSCL0 12
+#define GSCL_CLK_FIMC_LITE_D 13
+#define GSCL_CLK_FIMC_LITE_B 14
+#define GSCL_CLK_FIMC_LITE_A 15
+#define GSCL_CLK_CSIS1 16
+#define GSCL_CLK_CSIS0 17
+#define GSCL_CLK_SMMU3_LITE_D 18
+#define GSCL_CLK_SMMU3_LITE_B 19
+#define GSCL_CLK_SMMU3_LITE_A 20
+#define GSCL_CLK_SMMU3_GSCL0 21
+#define GSCL_CLK_SMMU3_GSCL1 22
+#define GSCL_CLK_SMMU3_MSCL0 23
+#define GSCL_CLK_SMMU3_MSCL1 24
+#define GSCL_SCLK_CSIS1_WRAP 25
+#define GSCL_SCLK_CSIS0_WRAP 26
+#define GSCL_NR_CLK 27
+
+
+/* List Of Clocks For CMU_FSYS */
+
+#define FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER 1
+#define FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER 2
+#define FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER 3
+#define FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER 4
+#define FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER 5
+#define FSYS_CLK_TSI 6
+#define FSYS_CLK_USBLINK 7
+#define FSYS_CLK_USBHOST20 8
+#define FSYS_CLK_USBDRD30 9
+#define FSYS_CLK_SROMC 10
+#define FSYS_CLK_PDMA 11
+#define FSYS_CLK_MMC2 12
+#define FSYS_CLK_MMC1 13
+#define FSYS_CLK_MMC0 14
+#define FSYS_CLK_RTIC 15
+#define FSYS_CLK_SMMU_RTIC 16
+#define FSYS_PHYCLK_USBDRD30 17
+#define FSYS_PHYCLK_USBHOST20 18
+#define FSYS_NR_CLK 19
+
+
+/* List Of Clocks For CMU_PERI */
+
+#define PERI_MOUT_SCLK_SPDIF 1
+#define PERI_MOUT_SCLK_I2SCOD 2
+#define PERI_MOUT_SCLK_PCM 3
+#define PERI_DOUT_I2S 4
+#define PERI_DOUT_PCM 5
+#define PERI_CLK_WDT_KFC 6
+#define PERI_CLK_WDT_EGL 7
+#define PERI_CLK_HSIC3 8
+#define PERI_CLK_HSIC2 9
+#define PERI_CLK_HSIC1 10
+#define PERI_CLK_HSIC0 11
+#define PERI_CLK_PCM 12
+#define PERI_CLK_MCT 13
+#define PERI_CLK_I2S 14
+#define PERI_CLK_I2CHDMI 15
+#define PERI_CLK_I2C7 16
+#define PERI_CLK_I2C6 17
+#define PERI_CLK_I2C5 18
+#define PERI_CLK_I2C4 19
+#define PERI_CLK_I2C9 20
+#define PERI_CLK_I2C8 21
+#define PERI_CLK_I2C11 22
+#define PERI_CLK_I2C10 23
+#define PERI_CLK_HDMICEC 24
+#define PERI_CLK_EFUSE_WRITER 25
+#define PERI_CLK_ABB 26
+#define PERI_CLK_UART2 27
+#define PERI_CLK_UART1 28
+#define PERI_CLK_UART0 29
+#define PERI_CLK_ADC 30
+#define PERI_CLK_TMU4 31
+#define PERI_CLK_TMU3 32
+#define PERI_CLK_TMU2 33
+#define PERI_CLK_TMU1 34
+#define PERI_CLK_TMU0 35
+#define PERI_CLK_SPI2 36
+#define PERI_CLK_SPI1 37
+#define PERI_CLK_SPI0 38
+#define PERI_CLK_SPDIF 39
+#define PERI_CLK_PWM 40
+#define PERI_CLK_UART4 41
+#define PERI_CLK_CHIPID 42
+#define PERI_CLK_PROVKEY0 43
+#define PERI_CLK_PROVKEY1 44
+#define PERI_CLK_SECKEY 45
+#define PERI_CLK_TOP_RTC 46
+#define PERI_CLK_TZPC10 47
+#define PERI_CLK_TZPC9 48
+#define PERI_CLK_TZPC8 49
+#define PERI_CLK_TZPC7 50
+#define PERI_CLK_TZPC6 51
+#define PERI_CLK_TZPC5 52
+#define PERI_CLK_TZPC4 53
+#define PERI_CLK_TZPC3 54
+#define PERI_CLK_TZPC2 55
+#define PERI_CLK_TZPC1 56
+#define PERI_CLK_TZPC0 57
+#define PERI_SCLK_UART2 58
+#define PERI_SCLK_UART1 59
+#define PERI_SCLK_UART0 60
+#define PERI_SCLK_SPI2 61
+#define PERI_SCLK_SPI1 62
+#define PERI_SCLK_SPI0 63
+#define PERI_SCLK_SPDIF 64
+#define PERI_SCLK_I2S 65
+#define PERI_SCLK_PCM1 66
+#define PERI_NR_CLK 67
+
+
+/* List Of Clocks For CMU_DISP */
+
+#define DISP_MOUT_SCLK_HDMI_SPDIF 1
+#define DISP_MOUT_SCLK_HDMI_PIXEL 2
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER 3
+#define DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER 4
+#define DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER 5
+#define DISP_MOUT_HDMI_PHY_PIXEL 6
+#define DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER 7
+#define DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS 8
+#define DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER 9
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER 10
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER 11
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER 12
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER 13
+#define DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER 14
+#define DISP_MOUT_ACLK_DISP_222_USER 15
+#define DISP_MOUT_SCLK_DISP_PIXEL_USER 16
+#define DISP_MOUT_ACLK_DISP_333_USER 17
+#define DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI 18
+#define DISP_DOUT_SCLK_FIMD1_EXTCLKPLL 19
+#define DISP_DOUT_PCLK_DISP_111 20
+#define DISP_CLK_SMMU_TV 21
+#define DISP_CLK_SMMU_FIMD1M1 22
+#define DISP_CLK_SMMU_FIMD1M0 23
+#define DISP_CLK_PIXEL_MIXER 24
+#define DISP_CLK_PIXEL_DISP 25
+#define DISP_CLK_MIXER 26
+#define DISP_CLK_MIPIPHY 27
+#define DISP_CLK_HDMIPHY 28
+#define DISP_CLK_HDMI 29
+#define DISP_CLK_FIMD1 30
+#define DISP_CLK_DSIM1 31
+#define DISP_CLK_DPPHY 32
+#define DISP_CLK_DP 33
+#define DISP_SCLK_PIXEL 34
+#define DISP_MOUT_HDMI_PHY_PIXEL_USER 35
+#define DISP_NR_CLK 36
+
+
+/* List Of Clocks For CMU_G2D */
+
+#define G2D_MOUT_ACLK_G2D_333_USER 1
+#define G2D_DOUT_PCLK_G2D_83 2
+#define G2D_CLK_SMMU3_JPEG 3
+#define G2D_CLK_MDMA 4
+#define G2D_CLK_JPEG 5
+#define G2D_CLK_G2D 6
+#define G2D_CLK_SSS 7
+#define G2D_CLK_SLIM_SSS 8
+#define G2D_CLK_SMMU_SLIM_SSS 9
+#define G2D_CLK_SMMU_SSS 10
+#define G2D_CLK_SMMU_MDMA 11
+#define G2D_CLK_SMMU3_G2D 12
+#define G2D_NR_CLK 13
+
+
+/* List Of Clocks For CMU_ISP */
+
+#define ISP_MOUT_ISP_400_USER 1
+#define ISP_MOUT_ISP_266_USER 2
+#define ISP_DOUT_SCLK_MPWM 3
+#define ISP_DOUT_CA5_PCLKDBG 4
+#define ISP_DOUT_CA5_ATCLKIN 5
+#define ISP_DOUT_PCLK_ISP_133 6
+#define ISP_DOUT_PCLK_ISP_66 7
+#define ISP_CLK_GIC 8
+#define ISP_CLK_WDT 9
+#define ISP_CLK_UART 10
+#define ISP_CLK_SPI1 11
+#define ISP_CLK_SPI0 12
+#define ISP_CLK_SMMU_SCALERP 13
+#define ISP_CLK_SMMU_SCALERC 14
+#define ISP_CLK_SMMU_ISPCX 15
+#define ISP_CLK_SMMU_ISP 16
+#define ISP_CLK_SMMU_FD 17
+#define ISP_CLK_SMMU_DRC 18
+#define ISP_CLK_PWM 19
+#define ISP_CLK_MTCADC 20
+#define ISP_CLK_MPWM 21
+#define ISP_CLK_MCUCTL 22
+#define ISP_CLK_I2C1 23
+#define ISP_CLK_I2C0 24
+#define ISP_CLK_FIMC_SCALERP 25
+#define ISP_CLK_FIMC_SCALERC 26
+#define ISP_CLK_FIMC 27
+#define ISP_CLK_FIMC_FD 28
+#define ISP_CLK_FIMC_DRC 29
+#define ISP_CLK_CA5 30
+#define ISP_SCLK_SPI0_EXT 31
+#define ISP_SCLK_SPI1_EXT 32
+#define ISP_SCLK_UART_EXT 33
+#define ISP_NR_CLK 34
+
+#endif
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
new file mode 100644
index 000000000..9b180f032
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -0,0 +1,33 @@
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_MPLL 4
+#define CLK_FOUT_BPLL 5
+#define CLK_FOUT_KPLL 6
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_MCT 315
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+
+#define CLK_NR_CLKS 512
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
new file mode 100644
index 000000000..99da0d117
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5420 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
+
+/* core clocks */
+#define CLK_FIN_PLL 1
+#define CLK_FOUT_APLL 2
+#define CLK_FOUT_CPLL 3
+#define CLK_FOUT_DPLL 4
+#define CLK_FOUT_EPLL 5
+#define CLK_FOUT_RPLL 6
+#define CLK_FOUT_IPLL 7
+#define CLK_FOUT_SPLL 8
+#define CLK_FOUT_VPLL 9
+#define CLK_FOUT_MPLL 10
+#define CLK_FOUT_BPLL 11
+#define CLK_FOUT_KPLL 12
+
+/* gate for special clocks (sclk) */
+#define CLK_SCLK_UART0 128
+#define CLK_SCLK_UART1 129
+#define CLK_SCLK_UART2 130
+#define CLK_SCLK_UART3 131
+#define CLK_SCLK_MMC0 132
+#define CLK_SCLK_MMC1 133
+#define CLK_SCLK_MMC2 134
+#define CLK_SCLK_SPI0 135
+#define CLK_SCLK_SPI1 136
+#define CLK_SCLK_SPI2 137
+#define CLK_SCLK_I2S1 138
+#define CLK_SCLK_I2S2 139
+#define CLK_SCLK_PCM1 140
+#define CLK_SCLK_PCM2 141
+#define CLK_SCLK_SPDIF 142
+#define CLK_SCLK_HDMI 143
+#define CLK_SCLK_PIXEL 144
+#define CLK_SCLK_DP1 145
+#define CLK_SCLK_MIPI1 146
+#define CLK_SCLK_FIMD1 147
+#define CLK_SCLK_MAUDIO0 148
+#define CLK_SCLK_MAUPCM0 149
+#define CLK_SCLK_USBD300 150
+#define CLK_SCLK_USBD301 151
+#define CLK_SCLK_USBPHY300 152
+#define CLK_SCLK_USBPHY301 153
+#define CLK_SCLK_UNIPRO 154
+#define CLK_SCLK_PWM 155
+#define CLK_SCLK_GSCL_WA 156
+#define CLK_SCLK_GSCL_WB 157
+#define CLK_SCLK_HDMIPHY 158
+#define CLK_MAU_EPLL 159
+#define CLK_SCLK_HSIC_12M 160
+#define CLK_SCLK_MPHY_IXTAL24 161
+
+/* gate clocks */
+#define CLK_UART0 257
+#define CLK_UART1 258
+#define CLK_UART2 259
+#define CLK_UART3 260
+#define CLK_I2C0 261
+#define CLK_I2C1 262
+#define CLK_I2C2 263
+#define CLK_I2C3 264
+#define CLK_USI0 265
+#define CLK_USI1 266
+#define CLK_USI2 267
+#define CLK_USI3 268
+#define CLK_I2C_HDMI 269
+#define CLK_TSADC 270
+#define CLK_SPI0 271
+#define CLK_SPI1 272
+#define CLK_SPI2 273
+#define CLK_KEYIF 274
+#define CLK_I2S1 275
+#define CLK_I2S2 276
+#define CLK_PCM1 277
+#define CLK_PCM2 278
+#define CLK_PWM 279
+#define CLK_SPDIF 280
+#define CLK_USI4 281
+#define CLK_USI5 282
+#define CLK_USI6 283
+#define CLK_ACLK66_PSGEN 300
+#define CLK_CHIPID 301
+#define CLK_SYSREG 302
+#define CLK_TZPC0 303
+#define CLK_TZPC1 304
+#define CLK_TZPC2 305
+#define CLK_TZPC3 306
+#define CLK_TZPC4 307
+#define CLK_TZPC5 308
+#define CLK_TZPC6 309
+#define CLK_TZPC7 310
+#define CLK_TZPC8 311
+#define CLK_TZPC9 312
+#define CLK_HDMI_CEC 313
+#define CLK_SECKEY 314
+#define CLK_MCT 315
+#define CLK_WDT 316
+#define CLK_RTC 317
+#define CLK_TMU 318
+#define CLK_TMU_GPU 319
+#define CLK_PCLK66_GPIO 330
+#define CLK_ACLK200_FSYS2 350
+#define CLK_MMC0 351
+#define CLK_MMC1 352
+#define CLK_MMC2 353
+#define CLK_SROMC 354
+#define CLK_UFS 355
+#define CLK_ACLK200_FSYS 360
+#define CLK_TSI 361
+#define CLK_PDMA0 362
+#define CLK_PDMA1 363
+#define CLK_RTIC 364
+#define CLK_USBH20 365
+#define CLK_USBD300 366
+#define CLK_USBD301 367
+#define CLK_ACLK400_MSCL 380
+#define CLK_MSCL0 381
+#define CLK_MSCL1 382
+#define CLK_MSCL2 383
+#define CLK_SMMU_MSCL0 384
+#define CLK_SMMU_MSCL1 385
+#define CLK_SMMU_MSCL2 386
+#define CLK_ACLK333 400
+#define CLK_MFC 401
+#define CLK_SMMU_MFCL 402
+#define CLK_SMMU_MFCR 403
+#define CLK_ACLK200_DISP1 410
+#define CLK_DSIM1 411
+#define CLK_DP1 412
+#define CLK_HDMI 413
+#define CLK_ACLK300_DISP1 420
+#define CLK_FIMD1 421
+#define CLK_SMMU_FIMD1M0 422
+#define CLK_SMMU_FIMD1M1 423
+#define CLK_ACLK166 430
+#define CLK_MIXER 431
+#define CLK_ACLK266 440
+#define CLK_ROTATOR 441
+#define CLK_MDMA1 442
+#define CLK_SMMU_ROTATOR 443
+#define CLK_SMMU_MDMA1 444
+#define CLK_ACLK300_JPEG 450
+#define CLK_JPEG 451
+#define CLK_JPEG2 452
+#define CLK_SMMU_JPEG 453
+#define CLK_SMMU_JPEG2 454
+#define CLK_ACLK300_GSCL 460
+#define CLK_SMMU_GSCL0 461
+#define CLK_SMMU_GSCL1 462
+#define CLK_GSCL_WA 463
+#define CLK_GSCL_WB 464
+#define CLK_GSCL0 465
+#define CLK_GSCL1 466
+#define CLK_FIMC_3AA 467
+#define CLK_ACLK266_G2D 470
+#define CLK_SSS 471
+#define CLK_SLIM_SSS 472
+#define CLK_MDMA0 473
+#define CLK_ACLK333_G2D 480
+#define CLK_G2D 481
+#define CLK_ACLK333_432_GSCL 490
+#define CLK_SMMU_3AA 491
+#define CLK_SMMU_FIMCL0 492
+#define CLK_SMMU_FIMCL1 493
+#define CLK_SMMU_FIMCL3 494
+#define CLK_FIMC_LITE3 495
+#define CLK_FIMC_LITE0 496
+#define CLK_FIMC_LITE1 497
+#define CLK_ACLK_G3D 500
+#define CLK_G3D 501
+#define CLK_SMMU_MIXER 502
+#define CLK_SMMU_G2D 503
+#define CLK_SMMU_MDMA0 504
+#define CLK_MC 505
+#define CLK_TOP_RTC 506
+#define CLK_SCLK_UART_ISP 510
+#define CLK_SCLK_SPI0_ISP 511
+#define CLK_SCLK_SPI1_ISP 512
+#define CLK_SCLK_PWM_ISP 513
+#define CLK_SCLK_ISP_SENSOR0 514
+#define CLK_SCLK_ISP_SENSOR1 515
+#define CLK_SCLK_ISP_SENSOR2 516
+#define CLK_ACLK432_SCALER 517
+#define CLK_ACLK432_CAM 518
+#define CLK_ACLK_FL1550_CAM 519
+#define CLK_ACLK550_CAM 520
+
+/* mux clocks */
+#define CLK_MOUT_HDMI 640
+#define CLK_MOUT_G3D 641
+#define CLK_MOUT_VPLL 642
+#define CLK_MOUT_MAUDIO0 643
+#define CLK_MOUT_USER_ACLK333 644
+#define CLK_MOUT_SW_ACLK333 645
+#define CLK_MOUT_USER_ACLK200_DISP1 646
+#define CLK_MOUT_SW_ACLK200 647
+#define CLK_MOUT_USER_ACLK300_DISP1 648
+#define CLK_MOUT_SW_ACLK300 649
+#define CLK_MOUT_USER_ACLK400_DISP1 650
+#define CLK_MOUT_SW_ACLK400 651
+
+/* divider clocks */
+#define CLK_DOUT_PIXEL 768
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS 769
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
new file mode 100644
index 000000000..5bd80d5ec
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -0,0 +1,1403 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
+#define _DT_BINDINGS_CLOCK_EXYNOS5433_H
+
+/* CMU_TOP */
+#define CLK_FOUT_ISP_PLL 1
+#define CLK_FOUT_AUD_PLL 2
+
+#define CLK_MOUT_AUD_PLL 10
+#define CLK_MOUT_ISP_PLL 11
+#define CLK_MOUT_AUD_PLL_USER_T 12
+#define CLK_MOUT_MPHY_PLL_USER 13
+#define CLK_MOUT_MFC_PLL_USER 14
+#define CLK_MOUT_BUS_PLL_USER 15
+#define CLK_MOUT_ACLK_HEVC_400 16
+#define CLK_MOUT_ACLK_CAM1_333 17
+#define CLK_MOUT_ACLK_CAM1_552_B 18
+#define CLK_MOUT_ACLK_CAM1_552_A 19
+#define CLK_MOUT_ACLK_ISP_DIS_400 20
+#define CLK_MOUT_ACLK_ISP_400 21
+#define CLK_MOUT_ACLK_BUS0_400 22
+#define CLK_MOUT_ACLK_MSCL_400_B 23
+#define CLK_MOUT_ACLK_MSCL_400_A 24
+#define CLK_MOUT_ACLK_GSCL_333 25
+#define CLK_MOUT_ACLK_G2D_400_B 26
+#define CLK_MOUT_ACLK_G2D_400_A 27
+#define CLK_MOUT_SCLK_JPEG_C 28
+#define CLK_MOUT_SCLK_JPEG_B 29
+#define CLK_MOUT_SCLK_JPEG_A 30
+#define CLK_MOUT_SCLK_MMC2_B 31
+#define CLK_MOUT_SCLK_MMC2_A 32
+#define CLK_MOUT_SCLK_MMC1_B 33
+#define CLK_MOUT_SCLK_MMC1_A 34
+#define CLK_MOUT_SCLK_MMC0_D 35
+#define CLK_MOUT_SCLK_MMC0_C 36
+#define CLK_MOUT_SCLK_MMC0_B 37
+#define CLK_MOUT_SCLK_MMC0_A 38
+#define CLK_MOUT_SCLK_SPI4 39
+#define CLK_MOUT_SCLK_SPI3 40
+#define CLK_MOUT_SCLK_UART2 41
+#define CLK_MOUT_SCLK_UART1 42
+#define CLK_MOUT_SCLK_UART0 43
+#define CLK_MOUT_SCLK_SPI2 44
+#define CLK_MOUT_SCLK_SPI1 45
+#define CLK_MOUT_SCLK_SPI0 46
+#define CLK_MOUT_ACLK_MFC_400_C 47
+#define CLK_MOUT_ACLK_MFC_400_B 48
+#define CLK_MOUT_ACLK_MFC_400_A 49
+#define CLK_MOUT_SCLK_ISP_SENSOR2 50
+#define CLK_MOUT_SCLK_ISP_SENSOR1 51
+#define CLK_MOUT_SCLK_ISP_SENSOR0 52
+#define CLK_MOUT_SCLK_ISP_UART 53
+#define CLK_MOUT_SCLK_ISP_SPI1 54
+#define CLK_MOUT_SCLK_ISP_SPI0 55
+#define CLK_MOUT_SCLK_PCIE_100 56
+#define CLK_MOUT_SCLK_UFSUNIPRO 57
+#define CLK_MOUT_SCLK_USBHOST30 58
+#define CLK_MOUT_SCLK_USBDRD30 59
+#define CLK_MOUT_SCLK_SLIMBUS 60
+#define CLK_MOUT_SCLK_SPDIF 61
+#define CLK_MOUT_SCLK_AUDIO1 62
+#define CLK_MOUT_SCLK_AUDIO0 63
+#define CLK_MOUT_SCLK_HDMI_SPDIF 64
+
+#define CLK_DIV_ACLK_FSYS_200 100
+#define CLK_DIV_ACLK_IMEM_SSSX_266 101
+#define CLK_DIV_ACLK_IMEM_200 102
+#define CLK_DIV_ACLK_IMEM_266 103
+#define CLK_DIV_ACLK_PERIC_66_B 104
+#define CLK_DIV_ACLK_PERIC_66_A 105
+#define CLK_DIV_ACLK_PERIS_66_B 106
+#define CLK_DIV_ACLK_PERIS_66_A 107
+#define CLK_DIV_SCLK_MMC1_B 108
+#define CLK_DIV_SCLK_MMC1_A 109
+#define CLK_DIV_SCLK_MMC0_B 110
+#define CLK_DIV_SCLK_MMC0_A 111
+#define CLK_DIV_SCLK_MMC2_B 112
+#define CLK_DIV_SCLK_MMC2_A 113
+#define CLK_DIV_SCLK_SPI1_B 114
+#define CLK_DIV_SCLK_SPI1_A 115
+#define CLK_DIV_SCLK_SPI0_B 116
+#define CLK_DIV_SCLK_SPI0_A 117
+#define CLK_DIV_SCLK_SPI2_B 118
+#define CLK_DIV_SCLK_SPI2_A 119
+#define CLK_DIV_SCLK_UART2 120
+#define CLK_DIV_SCLK_UART1 121
+#define CLK_DIV_SCLK_UART0 122
+#define CLK_DIV_SCLK_SPI4_B 123
+#define CLK_DIV_SCLK_SPI4_A 124
+#define CLK_DIV_SCLK_SPI3_B 125
+#define CLK_DIV_SCLK_SPI3_A 126
+#define CLK_DIV_SCLK_I2S1 127
+#define CLK_DIV_SCLK_PCM1 128
+#define CLK_DIV_SCLK_AUDIO1 129
+#define CLK_DIV_SCLK_AUDIO0 130
+#define CLK_DIV_ACLK_GSCL_111 131
+#define CLK_DIV_ACLK_GSCL_333 132
+#define CLK_DIV_ACLK_HEVC_400 133
+#define CLK_DIV_ACLK_MFC_400 134
+#define CLK_DIV_ACLK_G2D_266 135
+#define CLK_DIV_ACLK_G2D_400 136
+#define CLK_DIV_ACLK_G3D_400 137
+#define CLK_DIV_ACLK_BUS0_400 138
+#define CLK_DIV_ACLK_BUS1_400 139
+#define CLK_DIV_SCLK_PCIE_100 140
+#define CLK_DIV_SCLK_USBHOST30 141
+#define CLK_DIV_SCLK_UFSUNIPRO 142
+#define CLK_DIV_SCLK_USBDRD30 143
+#define CLK_DIV_SCLK_JPEG 144
+#define CLK_DIV_ACLK_MSCL_400 145
+#define CLK_DIV_ACLK_ISP_DIS_400 146
+#define CLK_DIV_ACLK_ISP_400 147
+#define CLK_DIV_ACLK_CAM0_333 148
+#define CLK_DIV_ACLK_CAM0_400 149
+#define CLK_DIV_ACLK_CAM0_552 150
+#define CLK_DIV_ACLK_CAM1_333 151
+#define CLK_DIV_ACLK_CAM1_400 152
+#define CLK_DIV_ACLK_CAM1_552 153
+#define CLK_DIV_SCLK_ISP_UART 154
+#define CLK_DIV_SCLK_ISP_SPI1_B 155
+#define CLK_DIV_SCLK_ISP_SPI1_A 156
+#define CLK_DIV_SCLK_ISP_SPI0_B 157
+#define CLK_DIV_SCLK_ISP_SPI0_A 158
+#define CLK_DIV_SCLK_ISP_SENSOR2_B 159
+#define CLK_DIV_SCLK_ISP_SENSOR2_A 160
+#define CLK_DIV_SCLK_ISP_SENSOR1_B 161
+#define CLK_DIV_SCLK_ISP_SENSOR1_A 162
+#define CLK_DIV_SCLK_ISP_SENSOR0_B 163
+#define CLK_DIV_SCLK_ISP_SENSOR0_A 164
+
+#define CLK_ACLK_PERIC_66 200
+#define CLK_ACLK_PERIS_66 201
+#define CLK_ACLK_FSYS_200 202
+#define CLK_SCLK_MMC2_FSYS 203
+#define CLK_SCLK_MMC1_FSYS 204
+#define CLK_SCLK_MMC0_FSYS 205
+#define CLK_SCLK_SPI4_PERIC 206
+#define CLK_SCLK_SPI3_PERIC 207
+#define CLK_SCLK_UART2_PERIC 208
+#define CLK_SCLK_UART1_PERIC 209
+#define CLK_SCLK_UART0_PERIC 210
+#define CLK_SCLK_SPI2_PERIC 211
+#define CLK_SCLK_SPI1_PERIC 212
+#define CLK_SCLK_SPI0_PERIC 213
+#define CLK_SCLK_SPDIF_PERIC 214
+#define CLK_SCLK_I2S1_PERIC 215
+#define CLK_SCLK_PCM1_PERIC 216
+#define CLK_SCLK_SLIMBUS 217
+#define CLK_SCLK_AUDIO1 218
+#define CLK_SCLK_AUDIO0 219
+#define CLK_ACLK_G2D_266 220
+#define CLK_ACLK_G2D_400 221
+#define CLK_ACLK_G3D_400 222
+#define CLK_ACLK_IMEM_SSX_266 223
+#define CLK_ACLK_BUS0_400 224
+#define CLK_ACLK_BUS1_400 225
+#define CLK_ACLK_IMEM_200 226
+#define CLK_ACLK_IMEM_266 227
+#define CLK_SCLK_PCIE_100_FSYS 228
+#define CLK_SCLK_UFSUNIPRO_FSYS 229
+#define CLK_SCLK_USBHOST30_FSYS 230
+#define CLK_SCLK_USBDRD30_FSYS 231
+#define CLK_ACLK_GSCL_111 232
+#define CLK_ACLK_GSCL_333 233
+#define CLK_SCLK_JPEG_MSCL 234
+#define CLK_ACLK_MSCL_400 235
+#define CLK_ACLK_MFC_400 236
+#define CLK_ACLK_HEVC_400 237
+#define CLK_ACLK_ISP_DIS_400 238
+#define CLK_ACLK_ISP_400 239
+#define CLK_ACLK_CAM0_333 240
+#define CLK_ACLK_CAM0_400 241
+#define CLK_ACLK_CAM0_552 242
+#define CLK_ACLK_CAM1_333 243
+#define CLK_ACLK_CAM1_400 244
+#define CLK_ACLK_CAM1_552 245
+#define CLK_SCLK_ISP_SENSOR2 246
+#define CLK_SCLK_ISP_SENSOR1 247
+#define CLK_SCLK_ISP_SENSOR0 248
+#define CLK_SCLK_ISP_MCTADC_CAM1 249
+#define CLK_SCLK_ISP_UART_CAM1 250
+#define CLK_SCLK_ISP_SPI1_CAM1 251
+#define CLK_SCLK_ISP_SPI0_CAM1 252
+#define CLK_SCLK_HDMI_SPDIF_DISP 253
+
+#define TOP_NR_CLK 254
+
+/* CMU_CPIF */
+#define CLK_FOUT_MPHY_PLL 1
+
+#define CLK_MOUT_MPHY_PLL 2
+
+#define CLK_DIV_SCLK_MPHY 10
+
+#define CLK_SCLK_MPHY_PLL 11
+#define CLK_SCLK_UFS_MPHY 11
+
+#define CPIF_NR_CLK 12
+
+/* CMU_MIF */
+#define CLK_FOUT_MEM0_PLL 1
+#define CLK_FOUT_MEM1_PLL 2
+#define CLK_FOUT_BUS_PLL 3
+#define CLK_FOUT_MFC_PLL 4
+#define CLK_DOUT_MFC_PLL 5
+#define CLK_DOUT_BUS_PLL 6
+#define CLK_DOUT_MEM1_PLL 7
+#define CLK_DOUT_MEM0_PLL 8
+
+#define CLK_MOUT_MFC_PLL_DIV2 10
+#define CLK_MOUT_BUS_PLL_DIV2 11
+#define CLK_MOUT_MEM1_PLL_DIV2 12
+#define CLK_MOUT_MEM0_PLL_DIV2 13
+#define CLK_MOUT_MFC_PLL 14
+#define CLK_MOUT_BUS_PLL 15
+#define CLK_MOUT_MEM1_PLL 16
+#define CLK_MOUT_MEM0_PLL 17
+#define CLK_MOUT_CLK2X_PHY_C 18
+#define CLK_MOUT_CLK2X_PHY_B 19
+#define CLK_MOUT_CLK2X_PHY_A 20
+#define CLK_MOUT_CLKM_PHY_C 21
+#define CLK_MOUT_CLKM_PHY_B 22
+#define CLK_MOUT_CLKM_PHY_A 23
+#define CLK_MOUT_ACLK_MIFNM_200 24
+#define CLK_MOUT_ACLK_MIFNM_400 25
+#define CLK_MOUT_ACLK_DISP_333_B 26
+#define CLK_MOUT_ACLK_DISP_333_A 27
+#define CLK_MOUT_SCLK_DECON_VCLK_C 28
+#define CLK_MOUT_SCLK_DECON_VCLK_B 29
+#define CLK_MOUT_SCLK_DECON_VCLK_A 30
+#define CLK_MOUT_SCLK_DECON_ECLK_C 31
+#define CLK_MOUT_SCLK_DECON_ECLK_B 32
+#define CLK_MOUT_SCLK_DECON_ECLK_A 33
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
+#define CLK_MOUT_SCLK_DSD_C 37
+#define CLK_MOUT_SCLK_DSD_B 38
+#define CLK_MOUT_SCLK_DSD_A 39
+#define CLK_MOUT_SCLK_DSIM0_C 40
+#define CLK_MOUT_SCLK_DSIM0_B 41
+#define CLK_MOUT_SCLK_DSIM0_A 42
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
+#define CLK_MOUT_SCLK_DSIM1_C 49
+#define CLK_MOUT_SCLK_DSIM1_B 50
+#define CLK_MOUT_SCLK_DSIM1_A 51
+
+#define CLK_DIV_SCLK_HPM_MIF 55
+#define CLK_DIV_ACLK_DREX1 56
+#define CLK_DIV_ACLK_DREX0 57
+#define CLK_DIV_CLK2XPHY 58
+#define CLK_DIV_ACLK_MIF_266 59
+#define CLK_DIV_ACLK_MIFND_133 60
+#define CLK_DIV_ACLK_MIF_133 61
+#define CLK_DIV_ACLK_MIFNM_200 62
+#define CLK_DIV_ACLK_MIF_200 63
+#define CLK_DIV_ACLK_MIF_400 64
+#define CLK_DIV_ACLK_BUS2_400 65
+#define CLK_DIV_ACLK_DISP_333 66
+#define CLK_DIV_ACLK_CPIF_200 67
+#define CLK_DIV_SCLK_DSIM1 68
+#define CLK_DIV_SCLK_DECON_TV_VCLK 69
+#define CLK_DIV_SCLK_DSIM0 70
+#define CLK_DIV_SCLK_DSD 71
+#define CLK_DIV_SCLK_DECON_TV_ECLK 72
+#define CLK_DIV_SCLK_DECON_VCLK 73
+#define CLK_DIV_SCLK_DECON_ECLK 74
+#define CLK_DIV_MIF_PRE 75
+
+#define CLK_CLK2X_PHY1 80
+#define CLK_CLK2X_PHY0 81
+#define CLK_CLKM_PHY1 82
+#define CLK_CLKM_PHY0 83
+#define CLK_RCLK_DREX1 84
+#define CLK_RCLK_DREX0 85
+#define CLK_ACLK_DREX1_TZ 86
+#define CLK_ACLK_DREX0_TZ 87
+#define CLK_ACLK_DREX1_PEREV 88
+#define CLK_ACLK_DREX0_PEREV 89
+#define CLK_ACLK_DREX1_MEMIF 90
+#define CLK_ACLK_DREX0_MEMIF 91
+#define CLK_ACLK_DREX1_SCH 92
+#define CLK_ACLK_DREX0_SCH 93
+#define CLK_ACLK_DREX1_BUSIF 94
+#define CLK_ACLK_DREX0_BUSIF 95
+#define CLK_ACLK_DREX1_BUSIF_RD 96
+#define CLK_ACLK_DREX0_BUSIF_RD 97
+#define CLK_ACLK_DREX1 98
+#define CLK_ACLK_DREX0 99
+#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
+#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
+#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
+#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
+#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
+#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
+#define CLK_ACLK_ASYNCAXIS_CP1 106
+#define CLK_ACLK_ASYNCAXIM_CP1 107
+#define CLK_ACLK_ASYNCAXIS_CP0 108
+#define CLK_ACLK_ASYNCAXIM_CP0 109
+#define CLK_ACLK_ASYNCAXIS_DREX1_3 110
+#define CLK_ACLK_ASYNCAXIM_DREX1_3 111
+#define CLK_ACLK_ASYNCAXIS_DREX1_1 112
+#define CLK_ACLK_ASYNCAXIM_DREX1_1 113
+#define CLK_ACLK_ASYNCAXIS_DREX1_0 114
+#define CLK_ACLK_ASYNCAXIM_DREX1_0 115
+#define CLK_ACLK_ASYNCAXIS_DREX0_3 116
+#define CLK_ACLK_ASYNCAXIM_DREX0_3 117
+#define CLK_ACLK_ASYNCAXIS_DREX0_1 118
+#define CLK_ACLK_ASYNCAXIM_DREX0_1 119
+#define CLK_ACLK_ASYNCAXIS_DREX0_0 120
+#define CLK_ACLK_ASYNCAXIM_DREX0_0 121
+#define CLK_ACLK_AHB2APB_MIF2P 122
+#define CLK_ACLK_AHB2APB_MIF1P 123
+#define CLK_ACLK_AHB2APB_MIF0P 124
+#define CLK_ACLK_IXIU_CCI 125
+#define CLK_ACLK_XIU_MIFSFRX 126
+#define CLK_ACLK_MIFNP_133 127
+#define CLK_ACLK_MIFNM_200 128
+#define CLK_ACLK_MIFND_133 129
+#define CLK_ACLK_MIFND_400 130
+#define CLK_ACLK_CCI 131
+#define CLK_ACLK_MIFND_266 132
+#define CLK_ACLK_PPMU_DREX1S3 133
+#define CLK_ACLK_PPMU_DREX1S1 134
+#define CLK_ACLK_PPMU_DREX1S0 135
+#define CLK_ACLK_PPMU_DREX0S3 136
+#define CLK_ACLK_PPMU_DREX0S1 137
+#define CLK_ACLK_PPMU_DREX0S0 138
+#define CLK_ACLK_BTS_APOLLO 139
+#define CLK_ACLK_BTS_ATLAS 140
+#define CLK_ACLK_ACE_SEL_APOLL 141
+#define CLK_ACLK_ACE_SEL_ATLAS 142
+#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
+#define CLK_ACLK_AXIUS_ATLAS_CCI 144
+#define CLK_ACLK_AXISYNCDNS_CCI 145
+#define CLK_ACLK_AXISYNCDN_CCI 146
+#define CLK_ACLK_AXISYNCDN_NOC_D 147
+#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
+#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
+#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
+#define CLK_ACLK_BUS2_400 151
+#define CLK_ACLK_DISP_333 152
+#define CLK_ACLK_CPIF_200 153
+#define CLK_PCLK_PPMU_DREX1S3 154
+#define CLK_PCLK_PPMU_DREX1S1 155
+#define CLK_PCLK_PPMU_DREX1S0 156
+#define CLK_PCLK_PPMU_DREX0S3 157
+#define CLK_PCLK_PPMU_DREX0S1 158
+#define CLK_PCLK_PPMU_DREX0S0 159
+#define CLK_PCLK_BTS_APOLLO 160
+#define CLK_PCLK_BTS_ATLAS 161
+#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
+#define CLK_PCLK_ASYNCAXI_CP1 163
+#define CLK_PCLK_ASYNCAXI_CP0 164
+#define CLK_PCLK_ASYNCAXI_DREX1_3 165
+#define CLK_PCLK_ASYNCAXI_DREX1_1 166
+#define CLK_PCLK_ASYNCAXI_DREX1_0 167
+#define CLK_PCLK_ASYNCAXI_DREX0_3 168
+#define CLK_PCLK_ASYNCAXI_DREX0_1 169
+#define CLK_PCLK_ASYNCAXI_DREX0_0 170
+#define CLK_PCLK_MIFSRVND_133 171
+#define CLK_PCLK_PMU_MIF 172
+#define CLK_PCLK_SYSREG_MIF 173
+#define CLK_PCLK_GPIO_ALIVE 174
+#define CLK_PCLK_ABB 175
+#define CLK_PCLK_PMU_APBIF 176
+#define CLK_PCLK_DDR_PHY1 177
+#define CLK_PCLK_DREX1 178
+#define CLK_PCLK_DDR_PHY0 179
+#define CLK_PCLK_DREX0 180
+#define CLK_PCLK_DREX0_TZ 181
+#define CLK_PCLK_DREX1_TZ 182
+#define CLK_PCLK_MONOTONIC_CNT 183
+#define CLK_PCLK_RTC 184
+#define CLK_SCLK_DSIM1_DISP 185
+#define CLK_SCLK_DECON_TV_VCLK_DISP 186
+#define CLK_SCLK_FREQ_DET_BUS_PLL 187
+#define CLK_SCLK_FREQ_DET_MFC_PLL 188
+#define CLK_SCLK_FREQ_DET_MEM0_PLL 189
+#define CLK_SCLK_FREQ_DET_MEM1_PLL 190
+#define CLK_SCLK_DSIM0_DISP 191
+#define CLK_SCLK_DSD_DISP 192
+#define CLK_SCLK_DECON_TV_ECLK_DISP 193
+#define CLK_SCLK_DECON_VCLK_DISP 194
+#define CLK_SCLK_DECON_ECLK_DISP 195
+#define CLK_SCLK_HPM_MIF 196
+#define CLK_SCLK_MFC_PLL 197
+#define CLK_SCLK_BUS_PLL 198
+#define CLK_SCLK_BUS_PLL_APOLLO 199
+#define CLK_SCLK_BUS_PLL_ATLAS 200
+
+#define MIF_NR_CLK 201
+
+/* CMU_PERIC */
+#define CLK_PCLK_SPI2 1
+#define CLK_PCLK_SPI1 2
+#define CLK_PCLK_SPI0 3
+#define CLK_PCLK_UART2 4
+#define CLK_PCLK_UART1 5
+#define CLK_PCLK_UART0 6
+#define CLK_PCLK_HSI2C3 7
+#define CLK_PCLK_HSI2C2 8
+#define CLK_PCLK_HSI2C1 9
+#define CLK_PCLK_HSI2C0 10
+#define CLK_PCLK_I2C7 11
+#define CLK_PCLK_I2C6 12
+#define CLK_PCLK_I2C5 13
+#define CLK_PCLK_I2C4 14
+#define CLK_PCLK_I2C3 15
+#define CLK_PCLK_I2C2 16
+#define CLK_PCLK_I2C1 17
+#define CLK_PCLK_I2C0 18
+#define CLK_PCLK_SPI4 19
+#define CLK_PCLK_SPI3 20
+#define CLK_PCLK_HSI2C11 21
+#define CLK_PCLK_HSI2C10 22
+#define CLK_PCLK_HSI2C9 23
+#define CLK_PCLK_HSI2C8 24
+#define CLK_PCLK_HSI2C7 25
+#define CLK_PCLK_HSI2C6 26
+#define CLK_PCLK_HSI2C5 27
+#define CLK_PCLK_HSI2C4 28
+#define CLK_SCLK_SPI4 29
+#define CLK_SCLK_SPI3 30
+#define CLK_SCLK_SPI2 31
+#define CLK_SCLK_SPI1 32
+#define CLK_SCLK_SPI0 33
+#define CLK_SCLK_UART2 34
+#define CLK_SCLK_UART1 35
+#define CLK_SCLK_UART0 36
+#define CLK_ACLK_AHB2APB_PERIC2P 37
+#define CLK_ACLK_AHB2APB_PERIC1P 38
+#define CLK_ACLK_AHB2APB_PERIC0P 39
+#define CLK_ACLK_PERICNP_66 40
+#define CLK_PCLK_SCI 41
+#define CLK_PCLK_GPIO_FINGER 42
+#define CLK_PCLK_GPIO_ESE 43
+#define CLK_PCLK_PWM 44
+#define CLK_PCLK_SPDIF 45
+#define CLK_PCLK_PCM1 46
+#define CLK_PCLK_I2S1 47
+#define CLK_PCLK_ADCIF 48
+#define CLK_PCLK_GPIO_TOUCH 49
+#define CLK_PCLK_GPIO_NFC 50
+#define CLK_PCLK_GPIO_PERIC 51
+#define CLK_PCLK_PMU_PERIC 52
+#define CLK_PCLK_SYSREG_PERIC 53
+#define CLK_SCLK_IOCLK_SPI4 54
+#define CLK_SCLK_IOCLK_SPI3 55
+#define CLK_SCLK_SCI 56
+#define CLK_SCLK_SC_IN 57
+#define CLK_SCLK_PWM 58
+#define CLK_SCLK_IOCLK_SPI2 59
+#define CLK_SCLK_IOCLK_SPI1 60
+#define CLK_SCLK_IOCLK_SPI0 61
+#define CLK_SCLK_IOCLK_I2S1_BCLK 62
+#define CLK_SCLK_SPDIF 63
+#define CLK_SCLK_PCM1 64
+#define CLK_SCLK_I2S1 65
+
+#define CLK_DIV_SCLK_SCI 70
+#define CLK_DIV_SCLK_SC_IN 71
+
+#define PERIC_NR_CLK 72
+
+/* CMU_PERIS */
+#define CLK_PCLK_HPM_APBIF 1
+#define CLK_PCLK_TMU1_APBIF 2
+#define CLK_PCLK_TMU0_APBIF 3
+#define CLK_PCLK_PMU_PERIS 4
+#define CLK_PCLK_SYSREG_PERIS 5
+#define CLK_PCLK_CMU_TOP_APBIF 6
+#define CLK_PCLK_WDT_APOLLO 7
+#define CLK_PCLK_WDT_ATLAS 8
+#define CLK_PCLK_MCT 9
+#define CLK_PCLK_HDMI_CEC 10
+#define CLK_ACLK_AHB2APB_PERIS1P 11
+#define CLK_ACLK_AHB2APB_PERIS0P 12
+#define CLK_ACLK_PERISNP_66 13
+#define CLK_PCLK_TZPC12 14
+#define CLK_PCLK_TZPC11 15
+#define CLK_PCLK_TZPC10 16
+#define CLK_PCLK_TZPC9 17
+#define CLK_PCLK_TZPC8 18
+#define CLK_PCLK_TZPC7 19
+#define CLK_PCLK_TZPC6 20
+#define CLK_PCLK_TZPC5 21
+#define CLK_PCLK_TZPC4 22
+#define CLK_PCLK_TZPC3 23
+#define CLK_PCLK_TZPC2 24
+#define CLK_PCLK_TZPC1 25
+#define CLK_PCLK_TZPC0 26
+#define CLK_PCLK_SECKEY_APBIF 27
+#define CLK_PCLK_CHIPID_APBIF 28
+#define CLK_PCLK_TOPRTC 29
+#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
+#define CLK_PCLK_ANTIRBK_CNT_APBIF 31
+#define CLK_PCLK_OTP_CON_APBIF 32
+#define CLK_SCLK_ASV_TB 33
+#define CLK_SCLK_TMU1 34
+#define CLK_SCLK_TMU0 35
+#define CLK_SCLK_SECKEY 36
+#define CLK_SCLK_CHIPID 37
+#define CLK_SCLK_TOPRTC 38
+#define CLK_SCLK_CUSTOM_EFUSE 39
+#define CLK_SCLK_ANTIRBK_CNT 40
+#define CLK_SCLK_OTP_CON 41
+
+#define PERIS_NR_CLK 42
+
+/* CMU_FSYS */
+#define CLK_MOUT_ACLK_FSYS_200_USER 1
+#define CLK_MOUT_SCLK_MMC2_USER 2
+#define CLK_MOUT_SCLK_MMC1_USER 3
+#define CLK_MOUT_SCLK_MMC0_USER 4
+#define CLK_MOUT_SCLK_UFS_MPHY_USER 5
+#define CLK_MOUT_SCLK_PCIE_100_USER 6
+#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
+#define CLK_MOUT_SCLK_USBHOST30_USER 8
+#define CLK_MOUT_SCLK_USBDRD30_USER 9
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
+#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
+#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
+#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
+#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
+#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
+#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
+#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
+#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
+#define CLK_MOUT_SCLK_MPHY 23
+
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
+#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
+#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
+#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
+#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
+#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
+
+#define CLK_ACLK_PCIE 50
+#define CLK_ACLK_PDMA1 51
+#define CLK_ACLK_TSI 52
+#define CLK_ACLK_MMC2 53
+#define CLK_ACLK_MMC1 54
+#define CLK_ACLK_MMC0 55
+#define CLK_ACLK_UFS 56
+#define CLK_ACLK_USBHOST20 57
+#define CLK_ACLK_USBHOST30 58
+#define CLK_ACLK_USBDRD30 59
+#define CLK_ACLK_PDMA0 60
+#define CLK_SCLK_MMC2 61
+#define CLK_SCLK_MMC1 62
+#define CLK_SCLK_MMC0 63
+#define CLK_PDMA1 64
+#define CLK_PDMA0 65
+#define CLK_ACLK_XIU_FSYSPX 66
+#define CLK_ACLK_AHB_USBLINKH1 67
+#define CLK_ACLK_SMMU_PDMA1 68
+#define CLK_ACLK_BTS_PCIE 69
+#define CLK_ACLK_AXIUS_PDMA1 70
+#define CLK_ACLK_SMMU_PDMA0 71
+#define CLK_ACLK_BTS_UFS 72
+#define CLK_ACLK_BTS_USBHOST30 73
+#define CLK_ACLK_BTS_USBDRD30 74
+#define CLK_ACLK_AXIUS_PDMA0 75
+#define CLK_ACLK_AXIUS_USBHS 76
+#define CLK_ACLK_AXIUS_FSYSSX 77
+#define CLK_ACLK_AHB2APB_FSYSP 78
+#define CLK_ACLK_AHB2AXI_USBHS 79
+#define CLK_ACLK_AHB_USBLINKH0 80
+#define CLK_ACLK_AHB_USBHS 81
+#define CLK_ACLK_AHB_FSYSH 82
+#define CLK_ACLK_XIU_FSYSX 83
+#define CLK_ACLK_XIU_FSYSSX 84
+#define CLK_ACLK_FSYSNP_200 85
+#define CLK_ACLK_FSYSND_200 86
+#define CLK_PCLK_PCIE_CTRL 87
+#define CLK_PCLK_SMMU_PDMA1 88
+#define CLK_PCLK_PCIE_PHY 89
+#define CLK_PCLK_BTS_PCIE 90
+#define CLK_PCLK_SMMU_PDMA0 91
+#define CLK_PCLK_BTS_UFS 92
+#define CLK_PCLK_BTS_USBHOST30 93
+#define CLK_PCLK_BTS_USBDRD30 94
+#define CLK_PCLK_GPIO_FSYS 95
+#define CLK_PCLK_PMU_FSYS 96
+#define CLK_PCLK_SYSREG_FSYS 97
+#define CLK_SCLK_PCIE_100 98
+#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
+#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
+#define CLK_PHYCLK_UFS_RX1_SYMBOL 101
+#define CLK_PHYCLK_UFS_RX0_SYMBOL 102
+#define CLK_PHYCLK_UFS_TX1_SYMBOL 103
+#define CLK_PHYCLK_UFS_TX0_SYMBOL 104
+#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
+#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
+#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
+#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
+#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
+#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
+#define CLK_SCLK_MPHY 111
+#define CLK_SCLK_UFSUNIPRO 112
+#define CLK_SCLK_USBHOST30 113
+#define CLK_SCLK_USBDRD30 114
+
+#define FSYS_NR_CLK 115
+
+/* CMU_G2D */
+#define CLK_MUX_ACLK_G2D_266_USER 1
+#define CLK_MUX_ACLK_G2D_400_USER 2
+
+#define CLK_DIV_PCLK_G2D 3
+
+#define CLK_ACLK_SMMU_MDMA1 4
+#define CLK_ACLK_BTS_MDMA1 5
+#define CLK_ACLK_BTS_G2D 6
+#define CLK_ACLK_ALB_G2D 7
+#define CLK_ACLK_AXIUS_G2DX 8
+#define CLK_ACLK_ASYNCAXI_SYSX 9
+#define CLK_ACLK_AHB2APB_G2D1P 10
+#define CLK_ACLK_AHB2APB_G2D0P 11
+#define CLK_ACLK_XIU_G2DX 12
+#define CLK_ACLK_G2DNP_133 13
+#define CLK_ACLK_G2DND_400 14
+#define CLK_ACLK_MDMA1 15
+#define CLK_ACLK_G2D 16
+#define CLK_ACLK_SMMU_G2D 17
+#define CLK_PCLK_SMMU_MDMA1 18
+#define CLK_PCLK_BTS_MDMA1 19
+#define CLK_PCLK_BTS_G2D 20
+#define CLK_PCLK_ALB_G2D 21
+#define CLK_PCLK_ASYNCAXI_SYSX 22
+#define CLK_PCLK_PMU_G2D 23
+#define CLK_PCLK_SYSREG_G2D 24
+#define CLK_PCLK_G2D 25
+#define CLK_PCLK_SMMU_G2D 26
+
+#define G2D_NR_CLK 27
+
+/* CMU_DISP */
+#define CLK_FOUT_DISP_PLL 1
+
+#define CLK_MOUT_DISP_PLL 2
+#define CLK_MOUT_SCLK_DSIM1_USER 3
+#define CLK_MOUT_SCLK_DSIM0_USER 4
+#define CLK_MOUT_SCLK_DSD_USER 5
+#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
+#define CLK_MOUT_SCLK_DECON_VCLK_USER 7
+#define CLK_MOUT_SCLK_DECON_ECLK_USER 8
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
+#define CLK_MOUT_ACLK_DISP_333_USER 10
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
+#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
+#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
+#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
+#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
+#define CLK_MOUT_SCLK_DSIM0 17
+#define CLK_MOUT_SCLK_DECON_TV_ECLK 18
+#define CLK_MOUT_SCLK_DECON_VCLK 19
+#define CLK_MOUT_SCLK_DECON_ECLK 20
+#define CLK_MOUT_SCLK_DSIM1_B_DISP 21
+#define CLK_MOUT_SCLK_DSIM1_A_DISP 22
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
+#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
+
+#define CLK_DIV_SCLK_DSIM1_DISP 30
+#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
+#define CLK_DIV_SCLK_DSIM0_DISP 32
+#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
+#define CLK_DIV_SCLK_DECON_VCLK_DISP 34
+#define CLK_DIV_SCLK_DECON_ECLK_DISP 35
+#define CLK_DIV_PCLK_DISP 36
+
+#define CLK_ACLK_DECON_TV 40
+#define CLK_ACLK_DECON 41
+#define CLK_ACLK_SMMU_TV1X 42
+#define CLK_ACLK_SMMU_TV0X 43
+#define CLK_ACLK_SMMU_DECON1X 44
+#define CLK_ACLK_SMMU_DECON0X 45
+#define CLK_ACLK_BTS_DECON_TV_M3 46
+#define CLK_ACLK_BTS_DECON_TV_M2 47
+#define CLK_ACLK_BTS_DECON_TV_M1 48
+#define CLK_ACLK_BTS_DECON_TV_M0 49
+#define CLK_ACLK_BTS_DECON_NM4 50
+#define CLK_ACLK_BTS_DECON_NM3 51
+#define CLK_ACLK_BTS_DECON_NM2 52
+#define CLK_ACLK_BTS_DECON_NM1 53
+#define CLK_ACLK_BTS_DECON_NM0 54
+#define CLK_ACLK_AHB2APB_DISPSFR2P 55
+#define CLK_ACLK_AHB2APB_DISPSFR1P 56
+#define CLK_ACLK_AHB2APB_DISPSFR0P 57
+#define CLK_ACLK_AHB_DISPH 58
+#define CLK_ACLK_XIU_TV1X 59
+#define CLK_ACLK_XIU_TV0X 60
+#define CLK_ACLK_XIU_DECON1X 61
+#define CLK_ACLK_XIU_DECON0X 62
+#define CLK_ACLK_XIU_DISP1X 63
+#define CLK_ACLK_XIU_DISPNP_100 64
+#define CLK_ACLK_DISP1ND_333 65
+#define CLK_ACLK_DISP0ND_333 66
+#define CLK_PCLK_SMMU_TV1X 67
+#define CLK_PCLK_SMMU_TV0X 68
+#define CLK_PCLK_SMMU_DECON1X 69
+#define CLK_PCLK_SMMU_DECON0X 70
+#define CLK_PCLK_BTS_DECON_TV_M3 71
+#define CLK_PCLK_BTS_DECON_TV_M2 72
+#define CLK_PCLK_BTS_DECON_TV_M1 73
+#define CLK_PCLK_BTS_DECON_TV_M0 74
+#define CLK_PCLK_BTS_DECONM4 75
+#define CLK_PCLK_BTS_DECONM3 76
+#define CLK_PCLK_BTS_DECONM2 77
+#define CLK_PCLK_BTS_DECONM1 78
+#define CLK_PCLK_BTS_DECONM0 79
+#define CLK_PCLK_MIC1 80
+#define CLK_PCLK_PMU_DISP 81
+#define CLK_PCLK_SYSREG_DISP 82
+#define CLK_PCLK_HDMIPHY 83
+#define CLK_PCLK_HDMI 84
+#define CLK_PCLK_MIC0 85
+#define CLK_PCLK_DSIM1 86
+#define CLK_PCLK_DSIM0 87
+#define CLK_PCLK_DECON_TV 88
+#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
+#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
+#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
+#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
+#define CLK_SCLK_DSIM1 93
+#define CLK_SCLK_DECON_TV_VCLK 94
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
+#define CLK_PHYCLK_HDMI_PIXEL 98
+#define CLK_SCLK_RGB_VCLK_TO_SMIES 99
+#define CLK_SCLK_FREQ_DET_DISP_PLL 100
+#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
+#define CLK_SCLK_RGB_VCLK_TO_MIC0 102
+#define CLK_SCLK_DSD 103
+#define CLK_SCLK_HDMI_SPDIF 104
+#define CLK_SCLK_DSIM0 105
+#define CLK_SCLK_DECON_TV_ECLK 106
+#define CLK_SCLK_DECON_VCLK 107
+#define CLK_SCLK_DECON_ECLK 108
+#define CLK_SCLK_RGB_VCLK 109
+#define CLK_SCLK_RGB_TV_VCLK 110
+
+#define DISP_NR_CLK 111
+
+/* CMU_AUD */
+#define CLK_MOUT_AUD_PLL_USER 1
+#define CLK_MOUT_SCLK_AUD_PCM 2
+#define CLK_MOUT_SCLK_AUD_I2S 3
+
+#define CLK_DIV_ATCLK_AUD 4
+#define CLK_DIV_PCLK_DBG_AUD 5
+#define CLK_DIV_ACLK_AUD 6
+#define CLK_DIV_AUD_CA5 7
+#define CLK_DIV_SCLK_AUD_SLIMBUS 8
+#define CLK_DIV_SCLK_AUD_UART 9
+#define CLK_DIV_SCLK_AUD_PCM 10
+#define CLK_DIV_SCLK_AUD_I2S 11
+
+#define CLK_ACLK_INTR_CTRL 12
+#define CLK_ACLK_AXIDS2_LPASSP 13
+#define CLK_ACLK_AXIDS1_LPASSP 14
+#define CLK_ACLK_AXI2APB1_LPASSP 15
+#define CLK_ACLK_AXI2APH_LPASSP 16
+#define CLK_ACLK_SMMU_LPASSX 17
+#define CLK_ACLK_AXIDS0_LPASSP 18
+#define CLK_ACLK_AXI2APB0_LPASSP 19
+#define CLK_ACLK_XIU_LPASSX 20
+#define CLK_ACLK_AUDNP_133 21
+#define CLK_ACLK_AUDND_133 22
+#define CLK_ACLK_SRAMC 23
+#define CLK_ACLK_DMAC 24
+#define CLK_PCLK_WDT1 25
+#define CLK_PCLK_WDT0 26
+#define CLK_PCLK_SFR1 27
+#define CLK_PCLK_SMMU_LPASSX 28
+#define CLK_PCLK_GPIO_AUD 29
+#define CLK_PCLK_PMU_AUD 30
+#define CLK_PCLK_SYSREG_AUD 31
+#define CLK_PCLK_AUD_SLIMBUS 32
+#define CLK_PCLK_AUD_UART 33
+#define CLK_PCLK_AUD_PCM 34
+#define CLK_PCLK_AUD_I2S 35
+#define CLK_PCLK_TIMER 36
+#define CLK_PCLK_SFR0_CTRL 37
+#define CLK_ATCLK_AUD 38
+#define CLK_PCLK_DBG_AUD 39
+#define CLK_SCLK_AUD_CA5 40
+#define CLK_SCLK_JTAG_TCK 41
+#define CLK_SCLK_SLIMBUS_CLKIN 42
+#define CLK_SCLK_AUD_SLIMBUS 43
+#define CLK_SCLK_AUD_UART 44
+#define CLK_SCLK_AUD_PCM 45
+#define CLK_SCLK_I2S_BCLK 46
+#define CLK_SCLK_AUD_I2S 47
+
+#define AUD_NR_CLK 48
+
+/* CMU_BUS{0|1|2} */
+#define CLK_DIV_PCLK_BUS_133 1
+
+#define CLK_ACLK_AHB2APB_BUSP 2
+#define CLK_ACLK_BUSNP_133 3
+#define CLK_ACLK_BUSND_400 4
+#define CLK_PCLK_BUSSRVND_133 5
+#define CLK_PCLK_PMU_BUS 6
+#define CLK_PCLK_SYSREG_BUS 7
+
+#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
+#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
+
+#define BUSx_NR_CLK 11
+
+/* CMU_G3D */
+#define CLK_FOUT_G3D_PLL 1
+
+#define CLK_MOUT_ACLK_G3D_400 2
+#define CLK_MOUT_G3D_PLL 3
+
+#define CLK_DIV_SCLK_HPM_G3D 4
+#define CLK_DIV_PCLK_G3D 5
+#define CLK_DIV_ACLK_G3D 6
+#define CLK_ACLK_BTS_G3D1 7
+#define CLK_ACLK_BTS_G3D0 8
+#define CLK_ACLK_ASYNCAPBS_G3D 9
+#define CLK_ACLK_ASYNCAPBM_G3D 10
+#define CLK_ACLK_AHB2APB_G3DP 11
+#define CLK_ACLK_G3DNP_150 12
+#define CLK_ACLK_G3DND_600 13
+#define CLK_ACLK_G3D 14
+#define CLK_PCLK_BTS_G3D1 15
+#define CLK_PCLK_BTS_G3D0 16
+#define CLK_PCLK_PMU_G3D 17
+#define CLK_PCLK_SYSREG_G3D 18
+#define CLK_SCLK_HPM_G3D 19
+
+#define G3D_NR_CLK 20
+
+/* CMU_GSCL */
+#define CLK_MOUT_ACLK_GSCL_111_USER 1
+#define CLK_MOUT_ACLK_GSCL_333_USER 2
+
+#define CLK_ACLK_BTS_GSCL2 3
+#define CLK_ACLK_BTS_GSCL1 4
+#define CLK_ACLK_BTS_GSCL0 5
+#define CLK_ACLK_AHB2APB_GSCLP 6
+#define CLK_ACLK_XIU_GSCLX 7
+#define CLK_ACLK_GSCLNP_111 8
+#define CLK_ACLK_GSCLRTND_333 9
+#define CLK_ACLK_GSCLBEND_333 10
+#define CLK_ACLK_GSD 11
+#define CLK_ACLK_GSCL2 12
+#define CLK_ACLK_GSCL1 13
+#define CLK_ACLK_GSCL0 14
+#define CLK_ACLK_SMMU_GSCL0 15
+#define CLK_ACLK_SMMU_GSCL1 16
+#define CLK_ACLK_SMMU_GSCL2 17
+#define CLK_PCLK_BTS_GSCL2 18
+#define CLK_PCLK_BTS_GSCL1 19
+#define CLK_PCLK_BTS_GSCL0 20
+#define CLK_PCLK_PMU_GSCL 21
+#define CLK_PCLK_SYSREG_GSCL 22
+#define CLK_PCLK_GSCL2 23
+#define CLK_PCLK_GSCL1 24
+#define CLK_PCLK_GSCL0 25
+#define CLK_PCLK_SMMU_GSCL0 26
+#define CLK_PCLK_SMMU_GSCL1 27
+#define CLK_PCLK_SMMU_GSCL2 28
+
+#define GSCL_NR_CLK 29
+
+/* CMU_APOLLO */
+#define CLK_FOUT_APOLLO_PLL 1
+
+#define CLK_MOUT_APOLLO_PLL 2
+#define CLK_MOUT_BUS_PLL_APOLLO_USER 3
+#define CLK_MOUT_APOLLO 4
+
+#define CLK_DIV_CNTCLK_APOLLO 5
+#define CLK_DIV_PCLK_DBG_APOLLO 6
+#define CLK_DIV_ATCLK_APOLLO 7
+#define CLK_DIV_PCLK_APOLLO 8
+#define CLK_DIV_ACLK_APOLLO 9
+#define CLK_DIV_APOLLO2 10
+#define CLK_DIV_APOLLO1 11
+#define CLK_DIV_SCLK_HPM_APOLLO 12
+#define CLK_DIV_APOLLO_PLL 13
+
+#define CLK_ACLK_ATBDS_APOLLO_3 14
+#define CLK_ACLK_ATBDS_APOLLO_2 15
+#define CLK_ACLK_ATBDS_APOLLO_1 16
+#define CLK_ACLK_ATBDS_APOLLO_0 17
+#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
+#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
+#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
+#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
+#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
+#define CLK_ACLK_AHB2APB_APOLLOP 23
+#define CLK_ACLK_APOLLONP_200 24
+#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
+#define CLK_PCLK_PMU_APOLLO 26
+#define CLK_PCLK_SYSREG_APOLLO 27
+#define CLK_CNTCLK_APOLLO 28
+#define CLK_SCLK_HPM_APOLLO 29
+#define CLK_SCLK_APOLLO 30
+
+#define APOLLO_NR_CLK 31
+
+/* CMU_ATLAS */
+#define CLK_FOUT_ATLAS_PLL 1
+
+#define CLK_MOUT_ATLAS_PLL 2
+#define CLK_MOUT_BUS_PLL_ATLAS_USER 3
+#define CLK_MOUT_ATLAS 4
+
+#define CLK_DIV_CNTCLK_ATLAS 5
+#define CLK_DIV_PCLK_DBG_ATLAS 6
+#define CLK_DIV_ATCLK_ATLASO 7
+#define CLK_DIV_PCLK_ATLAS 8
+#define CLK_DIV_ACLK_ATLAS 9
+#define CLK_DIV_ATLAS2 10
+#define CLK_DIV_ATLAS1 11
+#define CLK_DIV_SCLK_HPM_ATLAS 12
+#define CLK_DIV_ATLAS_PLL 13
+
+#define CLK_ACLK_ATB_AUD_CSSYS 14
+#define CLK_ACLK_ATB_APOLLO3_CSSYS 15
+#define CLK_ACLK_ATB_APOLLO2_CSSYS 16
+#define CLK_ACLK_ATB_APOLLO1_CSSYS 17
+#define CLK_ACLK_ATB_APOLLO0_CSSYS 18
+#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19
+#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20
+#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21
+#define CLK_ACLK_AHB2APB_ATLASP 22
+#define CLK_ACLK_ATLASNP_200 23
+#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24
+#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
+#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26
+#define CLK_PCLK_PMU_ATLAS 27
+#define CLK_PCLK_SYSREG_ATLAS 28
+#define CLK_PCLK_SECJTAG 29
+#define CLK_CNTCLK_ATLAS 30
+#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31
+#define CLK_SCLK_HPM_ATLAS 32
+#define CLK_TRACECLK 33
+#define CLK_CTMCLK 34
+#define CLK_HCLK_CSSYS 35
+#define CLK_PCLK_DBG_CSSYS 36
+#define CLK_PCLK_DBG 37
+#define CLK_ATCLK 38
+#define CLK_SCLK_ATLAS 39
+
+#define ATLAS_NR_CLK 40
+
+/* CMU_MSCL */
+#define CLK_MOUT_SCLK_JPEG_USER 1
+#define CLK_MOUT_ACLK_MSCL_400_USER 2
+#define CLK_MOUT_SCLK_JPEG 3
+
+#define CLK_DIV_PCLK_MSCL 4
+
+#define CLK_ACLK_BTS_JPEG 5
+#define CLK_ACLK_BTS_M2MSCALER1 6
+#define CLK_ACLK_BTS_M2MSCALER0 7
+#define CLK_ACLK_AHB2APB_MSCL0P 8
+#define CLK_ACLK_XIU_MSCLX 9
+#define CLK_ACLK_MSCLNP_100 10
+#define CLK_ACLK_MSCLND_400 11
+#define CLK_ACLK_JPEG 12
+#define CLK_ACLK_M2MSCALER1 13
+#define CLK_ACLK_M2MSCALER0 14
+#define CLK_ACLK_SMMU_M2MSCALER0 15
+#define CLK_ACLK_SMMU_M2MSCALER1 16
+#define CLK_ACLK_SMMU_JPEG 17
+#define CLK_PCLK_BTS_JPEG 18
+#define CLK_PCLK_BTS_M2MSCALER1 19
+#define CLK_PCLK_BTS_M2MSCALER0 20
+#define CLK_PCLK_PMU_MSCL 21
+#define CLK_PCLK_SYSREG_MSCL 22
+#define CLK_PCLK_JPEG 23
+#define CLK_PCLK_M2MSCALER1 24
+#define CLK_PCLK_M2MSCALER0 25
+#define CLK_PCLK_SMMU_M2MSCALER0 26
+#define CLK_PCLK_SMMU_M2MSCALER1 27
+#define CLK_PCLK_SMMU_JPEG 28
+#define CLK_SCLK_JPEG 29
+
+#define MSCL_NR_CLK 30
+
+/* CMU_MFC */
+#define CLK_MOUT_ACLK_MFC_400_USER 1
+
+#define CLK_DIV_PCLK_MFC 2
+
+#define CLK_ACLK_BTS_MFC_1 3
+#define CLK_ACLK_BTS_MFC_0 4
+#define CLK_ACLK_AHB2APB_MFCP 5
+#define CLK_ACLK_XIU_MFCX 6
+#define CLK_ACLK_MFCNP_100 7
+#define CLK_ACLK_MFCND_400 8
+#define CLK_ACLK_MFC 9
+#define CLK_ACLK_SMMU_MFC_1 10
+#define CLK_ACLK_SMMU_MFC_0 11
+#define CLK_PCLK_BTS_MFC_1 12
+#define CLK_PCLK_BTS_MFC_0 13
+#define CLK_PCLK_PMU_MFC 14
+#define CLK_PCLK_SYSREG_MFC 15
+#define CLK_PCLK_MFC 16
+#define CLK_PCLK_SMMU_MFC_1 17
+#define CLK_PCLK_SMMU_MFC_0 18
+
+#define MFC_NR_CLK 19
+
+/* CMU_HEVC */
+#define CLK_MOUT_ACLK_HEVC_400_USER 1
+
+#define CLK_DIV_PCLK_HEVC 2
+
+#define CLK_ACLK_BTS_HEVC_1 3
+#define CLK_ACLK_BTS_HEVC_0 4
+#define CLK_ACLK_AHB2APB_HEVCP 5
+#define CLK_ACLK_XIU_HEVCX 6
+#define CLK_ACLK_HEVCNP_100 7
+#define CLK_ACLK_HEVCND_400 8
+#define CLK_ACLK_HEVC 9
+#define CLK_ACLK_SMMU_HEVC_1 10
+#define CLK_ACLK_SMMU_HEVC_0 11
+#define CLK_PCLK_BTS_HEVC_1 12
+#define CLK_PCLK_BTS_HEVC_0 13
+#define CLK_PCLK_PMU_HEVC 14
+#define CLK_PCLK_SYSREG_HEVC 15
+#define CLK_PCLK_HEVC 16
+#define CLK_PCLK_SMMU_HEVC_1 17
+#define CLK_PCLK_SMMU_HEVC_0 18
+
+#define HEVC_NR_CLK 19
+
+/* CMU_ISP */
+#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1
+#define CLK_MOUT_ACLK_ISP_400_USER 2
+
+#define CLK_DIV_PCLK_ISP_DIS 3
+#define CLK_DIV_PCLK_ISP 4
+#define CLK_DIV_ACLK_ISP_D_200 5
+#define CLK_DIV_ACLK_ISP_C_200 6
+
+#define CLK_ACLK_ISP_D_GLUE 7
+#define CLK_ACLK_SCALERP 8
+#define CLK_ACLK_3DNR 9
+#define CLK_ACLK_DIS 10
+#define CLK_ACLK_SCALERC 11
+#define CLK_ACLK_DRC 12
+#define CLK_ACLK_ISP 13
+#define CLK_ACLK_AXIUS_SCALERP 14
+#define CLK_ACLK_AXIUS_SCALERC 15
+#define CLK_ACLK_AXIUS_DRC 16
+#define CLK_ACLK_ASYNCAHBM_ISP2P 17
+#define CLK_ACLK_ASYNCAHBM_ISP1P 18
+#define CLK_ACLK_ASYNCAXIS_DIS1 19
+#define CLK_ACLK_ASYNCAXIS_DIS0 20
+#define CLK_ACLK_ASYNCAXIM_DIS1 21
+#define CLK_ACLK_ASYNCAXIM_DIS0 22
+#define CLK_ACLK_ASYNCAXIM_ISP2P 23
+#define CLK_ACLK_ASYNCAXIM_ISP1P 24
+#define CLK_ACLK_AHB2APB_ISP2P 25
+#define CLK_ACLK_AHB2APB_ISP1P 26
+#define CLK_ACLK_AXI2APB_ISP2P 27
+#define CLK_ACLK_AXI2APB_ISP1P 28
+#define CLK_ACLK_XIU_ISPEX1 29
+#define CLK_ACLK_XIU_ISPEX0 30
+#define CLK_ACLK_ISPND_400 31
+#define CLK_ACLK_SMMU_SCALERP 32
+#define CLK_ACLK_SMMU_3DNR 33
+#define CLK_ACLK_SMMU_DIS1 34
+#define CLK_ACLK_SMMU_DIS0 35
+#define CLK_ACLK_SMMU_SCALERC 36
+#define CLK_ACLK_SMMU_DRC 37
+#define CLK_ACLK_SMMU_ISP 38
+#define CLK_ACLK_BTS_SCALERP 39
+#define CLK_ACLK_BTS_3DR 40
+#define CLK_ACLK_BTS_DIS1 41
+#define CLK_ACLK_BTS_DIS0 42
+#define CLK_ACLK_BTS_SCALERC 43
+#define CLK_ACLK_BTS_DRC 44
+#define CLK_ACLK_BTS_ISP 45
+#define CLK_PCLK_SMMU_SCALERP 46
+#define CLK_PCLK_SMMU_3DNR 47
+#define CLK_PCLK_SMMU_DIS1 48
+#define CLK_PCLK_SMMU_DIS0 49
+#define CLK_PCLK_SMMU_SCALERC 50
+#define CLK_PCLK_SMMU_DRC 51
+#define CLK_PCLK_SMMU_ISP 52
+#define CLK_PCLK_BTS_SCALERP 53
+#define CLK_PCLK_BTS_3DNR 54
+#define CLK_PCLK_BTS_DIS1 55
+#define CLK_PCLK_BTS_DIS0 56
+#define CLK_PCLK_BTS_SCALERC 57
+#define CLK_PCLK_BTS_DRC 58
+#define CLK_PCLK_BTS_ISP 59
+#define CLK_PCLK_ASYNCAXI_DIS1 60
+#define CLK_PCLK_ASYNCAXI_DIS0 61
+#define CLK_PCLK_PMU_ISP 62
+#define CLK_PCLK_SYSREG_ISP 63
+#define CLK_PCLK_CMU_ISP_LOCAL 64
+#define CLK_PCLK_SCALERP 65
+#define CLK_PCLK_3DNR 66
+#define CLK_PCLK_DIS_CORE 67
+#define CLK_PCLK_DIS 68
+#define CLK_PCLK_SCALERC 69
+#define CLK_PCLK_DRC 70
+#define CLK_PCLK_ISP 71
+#define CLK_SCLK_PIXELASYNCS_DIS 72
+#define CLK_SCLK_PIXELASYNCM_DIS 73
+#define CLK_SCLK_PIXELASYNCS_SCALERP 74
+#define CLK_SCLK_PIXELASYNCM_ISPD 75
+#define CLK_SCLK_PIXELASYNCS_ISPC 76
+#define CLK_SCLK_PIXELASYNCM_ISPC 77
+
+#define ISP_NR_CLK 78
+
+/* CMU_CAM0 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2
+
+#define CLK_MOUT_ACLK_CAM0_333_USER 3
+#define CLK_MOUT_ACLK_CAM0_400_USER 4
+#define CLK_MOUT_ACLK_CAM0_552_USER 5
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7
+#define CLK_MOUT_ACLK_LITE_D_B 8
+#define CLK_MOUT_ACLK_LITE_D_A 9
+#define CLK_MOUT_ACLK_LITE_B_B 10
+#define CLK_MOUT_ACLK_LITE_B_A 11
+#define CLK_MOUT_ACLK_LITE_A_B 12
+#define CLK_MOUT_ACLK_LITE_A_A 13
+#define CLK_MOUT_ACLK_CAM0_400 14
+#define CLK_MOUT_ACLK_CSIS1_B 15
+#define CLK_MOUT_ACLK_CSIS1_A 16
+#define CLK_MOUT_ACLK_CSIS0_B 17
+#define CLK_MOUT_ACLK_CSIS0_A 18
+#define CLK_MOUT_ACLK_3AA1_B 19
+#define CLK_MOUT_ACLK_3AA1_A 20
+#define CLK_MOUT_ACLK_3AA0_B 21
+#define CLK_MOUT_ACLK_3AA0_A 22
+#define CLK_MOUT_SCLK_LITE_FREECNT_C 23
+#define CLK_MOUT_SCLK_LITE_FREECNT_B 24
+#define CLK_MOUT_SCLK_LITE_FREECNT_A 25
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28
+#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29
+
+#define CLK_DIV_PCLK_CAM0_50 30
+#define CLK_DIV_ACLK_CAM0_200 31
+#define CLK_DIV_ACLK_CAM0_BUS_400 32
+#define CLK_DIV_PCLK_LITE_D 33
+#define CLK_DIV_ACLK_LITE_D 34
+#define CLK_DIV_PCLK_LITE_B 35
+#define CLK_DIV_ACLK_LITE_B 36
+#define CLK_DIV_PCLK_LITE_A 37
+#define CLK_DIV_ACLK_LITE_A 38
+#define CLK_DIV_ACLK_CSIS1 39
+#define CLK_DIV_ACLK_CSIS0 40
+#define CLK_DIV_PCLK_3AA1 41
+#define CLK_DIV_ACLK_3AA1 42
+#define CLK_DIV_PCLK_3AA0 43
+#define CLK_DIV_ACLK_3AA0 44
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45
+#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46
+#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47
+
+#define CLK_ACLK_CSIS1 50
+#define CLK_ACLK_CSIS0 51
+#define CLK_ACLK_3AA1 52
+#define CLK_ACLK_3AA0 53
+#define CLK_ACLK_LITE_D 54
+#define CLK_ACLK_LITE_B 55
+#define CLK_ACLK_LITE_A 56
+#define CLK_ACLK_AHBSYNCDN 57
+#define CLK_ACLK_AXIUS_LITE_D 58
+#define CLK_ACLK_AXIUS_LITE_B 59
+#define CLK_ACLK_AXIUS_LITE_A 60
+#define CLK_ACLK_ASYNCAPBM_3AA1 61
+#define CLK_ACLK_ASYNCAPBS_3AA1 62
+#define CLK_ACLK_ASYNCAPBM_3AA0 63
+#define CLK_ACLK_ASYNCAPBS_3AA0 64
+#define CLK_ACLK_ASYNCAPBM_LITE_D 65
+#define CLK_ACLK_ASYNCAPBS_LITE_D 66
+#define CLK_ACLK_ASYNCAPBM_LITE_B 67
+#define CLK_ACLK_ASYNCAPBS_LITE_B 68
+#define CLK_ACLK_ASYNCAPBM_LITE_A 69
+#define CLK_ACLK_ASYNCAPBS_LITE_A 70
+#define CLK_ACLK_ASYNCAXIM_ISP0P 71
+#define CLK_ACLK_ASYNCAXIM_3AA1 72
+#define CLK_ACLK_ASYNCAXIS_3AA1 73
+#define CLK_ACLK_ASYNCAXIM_3AA0 74
+#define CLK_ACLK_ASYNCAXIS_3AA0 75
+#define CLK_ACLK_ASYNCAXIM_LITE_D 76
+#define CLK_ACLK_ASYNCAXIS_LITE_D 77
+#define CLK_ACLK_ASYNCAXIM_LITE_B 78
+#define CLK_ACLK_ASYNCAXIS_LITE_B 79
+#define CLK_ACLK_ASYNCAXIM_LITE_A 80
+#define CLK_ACLK_ASYNCAXIS_LITE_A 81
+#define CLK_ACLK_AHB2APB_ISPSFRP 82
+#define CLK_ACLK_AXI2APB_ISP0P 83
+#define CLK_ACLK_AXI2AHB_ISP0P 84
+#define CLK_ACLK_XIU_IS0X 85
+#define CLK_ACLK_XIU_ISP0EX 86
+#define CLK_ACLK_CAM0NP_276 87
+#define CLK_ACLK_CAM0ND_400 88
+#define CLK_ACLK_SMMU_3AA1 89
+#define CLK_ACLK_SMMU_3AA0 90
+#define CLK_ACLK_SMMU_LITE_D 91
+#define CLK_ACLK_SMMU_LITE_B 92
+#define CLK_ACLK_SMMU_LITE_A 93
+#define CLK_ACLK_BTS_3AA1 94
+#define CLK_ACLK_BTS_3AA0 95
+#define CLK_ACLK_BTS_LITE_D 96
+#define CLK_ACLK_BTS_LITE_B 97
+#define CLK_ACLK_BTS_LITE_A 98
+#define CLK_PCLK_SMMU_3AA1 99
+#define CLK_PCLK_SMMU_3AA0 100
+#define CLK_PCLK_SMMU_LITE_D 101
+#define CLK_PCLK_SMMU_LITE_B 102
+#define CLK_PCLK_SMMU_LITE_A 103
+#define CLK_PCLK_BTS_3AA1 104
+#define CLK_PCLK_BTS_3AA0 105
+#define CLK_PCLK_BTS_LITE_D 106
+#define CLK_PCLK_BTS_LITE_B 107
+#define CLK_PCLK_BTS_LITE_A 108
+#define CLK_PCLK_ASYNCAXI_CAM1 109
+#define CLK_PCLK_ASYNCAXI_3AA1 110
+#define CLK_PCLK_ASYNCAXI_3AA0 111
+#define CLK_PCLK_ASYNCAXI_LITE_D 112
+#define CLK_PCLK_ASYNCAXI_LITE_B 113
+#define CLK_PCLK_ASYNCAXI_LITE_A 114
+#define CLK_PCLK_PMU_CAM0 115
+#define CLK_PCLK_SYSREG_CAM0 116
+#define CLK_PCLK_CMU_CAM0_LOCAL 117
+#define CLK_PCLK_CSIS1 118
+#define CLK_PCLK_CSIS0 119
+#define CLK_PCLK_3AA1 120
+#define CLK_PCLK_3AA0 121
+#define CLK_PCLK_LITE_D 122
+#define CLK_PCLK_LITE_B 123
+#define CLK_PCLK_LITE_A 124
+#define CLK_PHYCLK_RXBYTECLKHS0_S4 125
+#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126
+#define CLK_SCLK_LITE_FREECNT 127
+#define CLK_SCLK_PIXELASYNCM_3AA1 128
+#define CLK_SCLK_PIXELASYNCM_3AA0 129
+#define CLK_SCLK_PIXELASYNCS_3AA0 130
+#define CLK_SCLK_PIXELASYNCM_LITE_C 131
+#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132
+#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133
+
+#define CAM0_NR_CLK 134
+
+/* CMU_CAM1 */
+#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1
+
+#define CLK_MOUT_SCLK_ISP_UART_USER 2
+#define CLK_MOUT_SCLK_ISP_SPI1_USER 3
+#define CLK_MOUT_SCLK_ISP_SPI0_USER 4
+#define CLK_MOUT_ACLK_CAM1_333_USER 5
+#define CLK_MOUT_ACLK_CAM1_400_USER 6
+#define CLK_MOUT_ACLK_CAM1_552_USER 7
+#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8
+#define CLK_MOUT_ACLK_CSIS2_B 9
+#define CLK_MOUT_ACLK_CSIS2_A 10
+#define CLK_MOUT_ACLK_FD_B 11
+#define CLK_MOUT_ACLK_FD_A 12
+#define CLK_MOUT_ACLK_LITE_C_B 13
+#define CLK_MOUT_ACLK_LITE_C_A 14
+
+#define CLK_DIV_SCLK_ISP_WPWM 15
+#define CLK_DIV_PCLK_CAM1_83 16
+#define CLK_DIV_PCLK_CAM1_166 17
+#define CLK_DIV_PCLK_DBG_CAM1 18
+#define CLK_DIV_ATCLK_CAM1 19
+#define CLK_DIV_ACLK_CSIS2 20
+#define CLK_DIV_PCLK_FD 21
+#define CLK_DIV_ACLK_FD 22
+#define CLK_DIV_PCLK_LITE_C 23
+#define CLK_DIV_ACLK_LITE_C 24
+
+#define CLK_ACLK_ISP_GIC 25
+#define CLK_ACLK_FD 26
+#define CLK_ACLK_LITE_C 27
+#define CLK_ACLK_CSIS2 28
+#define CLK_ACLK_ASYNCAPBM_FD 29
+#define CLK_ACLK_ASYNCAPBS_FD 30
+#define CLK_ACLK_ASYNCAPBM_LITE_C 31
+#define CLK_ACLK_ASYNCAPBS_LITE_C 32
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33
+#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34
+#define CLK_ACLK_ASYNCAXIM_CA5 35
+#define CLK_ACLK_ASYNCAXIS_CA5 36
+#define CLK_ACLK_ASYNCAXIS_ISPX2 37
+#define CLK_ACLK_ASYNCAXIS_ISPX1 38
+#define CLK_ACLK_ASYNCAXIS_ISPX0 39
+#define CLK_ACLK_ASYNCAXIM_ISPEX 40
+#define CLK_ACLK_ASYNCAXIM_ISP3P 41
+#define CLK_ACLK_ASYNCAXIS_ISP3P 42
+#define CLK_ACLK_ASYNCAXIM_FD 43
+#define CLK_ACLK_ASYNCAXIS_FD 44
+#define CLK_ACLK_ASYNCAXIM_LITE_C 45
+#define CLK_ACLK_ASYNCAXIS_LITE_C 46
+#define CLK_ACLK_AHB2APB_ISP5P 47
+#define CLK_ACLK_AHB2APB_ISP3P 48
+#define CLK_ACLK_AXI2APB_ISP3P 49
+#define CLK_ACLK_AHB_SFRISP2H 50
+#define CLK_ACLK_AXI_ISP_HX_R 51
+#define CLK_ACLK_AXI_ISP_CX_R 52
+#define CLK_ACLK_AXI_ISP_HX 53
+#define CLK_ACLK_AXI_ISP_CX 54
+#define CLK_ACLK_XIU_ISPX 55
+#define CLK_ACLK_XIU_ISPEX 56
+#define CLK_ACLK_CAM1NP_333 57
+#define CLK_ACLK_CAM1ND_400 58
+#define CLK_ACLK_SMMU_ISPCPU 59
+#define CLK_ACLK_SMMU_FD 60
+#define CLK_ACLK_SMMU_LITE_C 61
+#define CLK_ACLK_BTS_ISP3P 62
+#define CLK_ACLK_BTS_FD 63
+#define CLK_ACLK_BTS_LITE_C 64
+#define CLK_ACLK_AHBDN_SFRISP2H 65
+#define CLK_ACLK_AHBDN_ISP5P 66
+#define CLK_ACLK_AXIUS_ISP3P 67
+#define CLK_ACLK_AXIUS_FD 68
+#define CLK_ACLK_AXIUS_LITE_C 69
+#define CLK_PCLK_SMMU_ISPCPU 70
+#define CLK_PCLK_SMMU_FD 71
+#define CLK_PCLK_SMMU_LITE_C 72
+#define CLK_PCLK_BTS_ISP3P 73
+#define CLK_PCLK_BTS_FD 74
+#define CLK_PCLK_BTS_LITE_C 75
+#define CLK_PCLK_ASYNCAXIM_CA5 76
+#define CLK_PCLK_ASYNCAXIM_ISPEX 77
+#define CLK_PCLK_ASYNCAXIM_ISP3P 78
+#define CLK_PCLK_ASYNCAXIM_FD 79
+#define CLK_PCLK_ASYNCAXIM_LITE_C 80
+#define CLK_PCLK_PMU_CAM1 81
+#define CLK_PCLK_SYSREG_CAM1 82
+#define CLK_PCLK_CMU_CAM1_LOCAL 83
+#define CLK_PCLK_ISP_MCTADC 84
+#define CLK_PCLK_ISP_WDT 85
+#define CLK_PCLK_ISP_PWM 86
+#define CLK_PCLK_ISP_UART 87
+#define CLK_PCLK_ISP_MCUCTL 88
+#define CLK_PCLK_ISP_SPI1 89
+#define CLK_PCLK_ISP_SPI0 90
+#define CLK_PCLK_ISP_I2C2 91
+#define CLK_PCLK_ISP_I2C1 92
+#define CLK_PCLK_ISP_I2C0 93
+#define CLK_PCLK_ISP_MPWM 94
+#define CLK_PCLK_FD 95
+#define CLK_PCLK_LITE_C 96
+#define CLK_PCLK_CSIS2 97
+#define CLK_SCLK_ISP_I2C2 98
+#define CLK_SCLK_ISP_I2C1 99
+#define CLK_SCLK_ISP_I2C0 100
+#define CLK_SCLK_ISP_PWM 101
+#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102
+#define CLK_SCLK_LITE_C_FREECNT 103
+#define CLK_SCLK_PIXELASYNCM_FD 104
+#define CLK_SCLK_ISP_MCTADC 105
+#define CLK_SCLK_ISP_UART 106
+#define CLK_SCLK_ISP_SPI1 107
+#define CLK_SCLK_ISP_SPI0 108
+#define CLK_SCLK_ISP_MPWM 109
+#define CLK_PCLK_DBG_ISP 110
+#define CLK_ATCLK_ISP 111
+#define CLK_SCLK_ISP_CA5 112
+
+#define CAM1_NR_CLK 113
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h
new file mode 100644
index 000000000..c66fc405a
--- /dev/null
+++ b/include/dt-bindings/clock/exynos5440.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Andrzej Hajda <a.hajda@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Exynos5440 clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H
+#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H
+
+#define CLK_XTAL 1
+#define CLK_ARM_CLK 2
+#define CLK_SPI_BAUD 16
+#define CLK_PB0_250 17
+#define CLK_PR0_250 18
+#define CLK_PR1_250 19
+#define CLK_B_250 20
+#define CLK_B_125 21
+#define CLK_B_200 22
+#define CLK_SATA 23
+#define CLK_USB 24
+#define CLK_GMAC0 25
+#define CLK_CS250 26
+#define CLK_PB0_250_O 27
+#define CLK_PR0_250_O 28
+#define CLK_PR1_250_O 29
+#define CLK_B_250_O 30
+#define CLK_B_125_O 31
+#define CLK_B_200_O 32
+#define CLK_SATA_O 33
+#define CLK_USB_O 34
+#define CLK_GMAC0_O 35
+#define CLK_CS250_O 36
+
+/* must be greater than maximal clock id */
+#define CLK_NR_CLKS 37
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
new file mode 100644
index 000000000..e33c75a3c
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS 1
+#define DOUT_SCLK_BUS0_PLL 2
+#define DOUT_SCLK_BUS1_PLL 3
+#define DOUT_SCLK_CC_PLL 4
+#define DOUT_SCLK_MFC_PLL 5
+#define DOUT_ACLK_CCORE_133 6
+#define DOUT_ACLK_MSCL_532 7
+#define ACLK_MSCL_532 8
+#define DOUT_SCLK_AUD_PLL 9
+#define FOUT_AUD_PLL 10
+#define TOPC_NR_CLK 11
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1 1
+#define DOUT_ACLK_PERIC0 2
+#define CLK_SCLK_UART0 3
+#define CLK_SCLK_UART1 4
+#define CLK_SCLK_UART2 5
+#define CLK_SCLK_UART3 6
+#define CLK_SCLK_SPI0 7
+#define CLK_SCLK_SPI1 8
+#define CLK_SCLK_SPI2 9
+#define CLK_SCLK_SPI3 10
+#define CLK_SCLK_SPI4 11
+#define CLK_SCLK_SPDIF 12
+#define CLK_SCLK_PCM1 13
+#define CLK_SCLK_I2S1 14
+#define TOP0_NR_CLK 15
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200 1
+#define DOUT_ACLK_FSYS0_200 2
+#define DOUT_SCLK_MMC2 3
+#define DOUT_SCLK_MMC1 4
+#define DOUT_SCLK_MMC0 5
+#define CLK_SCLK_MMC2 6
+#define CLK_SCLK_MMC1 7
+#define CLK_SCLK_MMC0 8
+#define TOP1_NR_CLK 9
+
+/* CCORE */
+#define PCLK_RTC 1
+#define CCORE_NR_CLK 2
+
+/* PERIC0 */
+#define PCLK_UART0 1
+#define SCLK_UART0 2
+#define PCLK_HSI2C0 3
+#define PCLK_HSI2C1 4
+#define PCLK_HSI2C4 5
+#define PCLK_HSI2C5 6
+#define PCLK_HSI2C9 7
+#define PCLK_HSI2C10 8
+#define PCLK_HSI2C11 9
+#define PCLK_PWM 10
+#define SCLK_PWM 11
+#define PCLK_ADCIF 12
+#define PERIC0_NR_CLK 13
+
+/* PERIC1 */
+#define PCLK_UART1 1
+#define PCLK_UART2 2
+#define PCLK_UART3 3
+#define SCLK_UART1 4
+#define SCLK_UART2 5
+#define SCLK_UART3 6
+#define PCLK_HSI2C2 7
+#define PCLK_HSI2C3 8
+#define PCLK_HSI2C6 9
+#define PCLK_HSI2C7 10
+#define PCLK_HSI2C8 11
+#define PCLK_SPI0 12
+#define PCLK_SPI1 13
+#define PCLK_SPI2 14
+#define PCLK_SPI3 15
+#define PCLK_SPI4 16
+#define SCLK_SPI0 17
+#define SCLK_SPI1 18
+#define SCLK_SPI2 19
+#define SCLK_SPI3 20
+#define SCLK_SPI4 21
+#define PCLK_I2S1 22
+#define PCLK_PCM1 23
+#define PCLK_SPDIF 24
+#define SCLK_I2S1 25
+#define SCLK_PCM1 26
+#define SCLK_SPDIF 27
+#define PERIC1_NR_CLK 28
+
+/* PERIS */
+#define PCLK_CHIPID 1
+#define SCLK_CHIPID 2
+#define PCLK_WDT 3
+#define PCLK_TMU 4
+#define SCLK_TMU 5
+#define PERIS_NR_CLK 6
+
+/* FSYS0 */
+#define ACLK_MMC2 1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X 2
+#define ACLK_USBDRD300 3
+#define SCLK_USBDRD300_SUSPENDCLK 4
+#define SCLK_USBDRD300_REFCLK 5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK 11
+
+/* FSYS1 */
+#define ACLK_MMC1 1
+#define ACLK_MMC0 2
+#define FSYS1_NR_CLK 3
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532 1
+#define DOUT_PCLK_MSCL 2
+#define ACLK_MSCL_0 3
+#define ACLK_MSCL_1 4
+#define ACLK_JPEG 5
+#define ACLK_G2D 6
+#define ACLK_LH_ASYNC_SI_MSCL_0 7
+#define ACLK_LH_ASYNC_SI_MSCL_1 8
+#define ACLK_AXI2ACEL_BRIDGE 9
+#define ACLK_XIU_MSCLX_0 10
+#define ACLK_XIU_MSCLX_1 11
+#define ACLK_QE_MSCL_0 12
+#define ACLK_QE_MSCL_1 13
+#define ACLK_QE_JPEG 14
+#define ACLK_QE_G2D 15
+#define ACLK_PPMU_MSCL_0 16
+#define ACLK_PPMU_MSCL_1 17
+#define ACLK_MSCLNP_133 18
+#define ACLK_AHB2APB_MSCL0P 19
+#define ACLK_AHB2APB_MSCL1P 20
+
+#define PCLK_MSCL_0 21
+#define PCLK_MSCL_1 22
+#define PCLK_JPEG 23
+#define PCLK_G2D 24
+#define PCLK_QE_MSCL_0 25
+#define PCLK_QE_MSCL_1 26
+#define PCLK_QE_JPEG 27
+#define PCLK_QE_G2D 28
+#define PCLK_PPMU_MSCL_0 29
+#define PCLK_PPMU_MSCL_1 30
+#define PCLK_AXI2ACEL_BRIDGE 31
+#define PCLK_PMU_MSCL 32
+#define MSCL_NR_CLK 33
+
+/* AUD */
+#define SCLK_I2S 1
+#define SCLK_PCM 2
+#define PCLK_I2S 3
+#define PCLK_PCM 4
+#define ACLK_ADMA 5
+#define AUD_NR_CLK 6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/hi3620-clock.h b/include/dt-bindings/clock/hi3620-clock.h
new file mode 100644
index 000000000..21b9d0e2e
--- /dev/null
+++ b/include/dt-bindings/clock/hi3620-clock.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012-2013 Hisilicon Limited.
+ * Copyright (c) 2012-2013 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ * Xin Li <li.xin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HI3620_CLOCK_H
+#define __DTS_HI3620_CLOCK_H
+
+#define HI3620_NONE_CLOCK 0
+
+/* fixed rate & fixed factor clocks */
+#define HI3620_OSC32K 1
+#define HI3620_OSC26M 2
+#define HI3620_PCLK 3
+#define HI3620_PLL_ARM0 4
+#define HI3620_PLL_ARM1 5
+#define HI3620_PLL_PERI 6
+#define HI3620_PLL_USB 7
+#define HI3620_PLL_HDMI 8
+#define HI3620_PLL_GPU 9
+#define HI3620_RCLK_TCXO 10
+#define HI3620_RCLK_CFGAXI 11
+#define HI3620_RCLK_PICO 12
+
+/* mux clocks */
+#define HI3620_TIMER0_MUX 32
+#define HI3620_TIMER1_MUX 33
+#define HI3620_TIMER2_MUX 34
+#define HI3620_TIMER3_MUX 35
+#define HI3620_TIMER4_MUX 36
+#define HI3620_TIMER5_MUX 37
+#define HI3620_TIMER6_MUX 38
+#define HI3620_TIMER7_MUX 39
+#define HI3620_TIMER8_MUX 40
+#define HI3620_TIMER9_MUX 41
+#define HI3620_UART0_MUX 42
+#define HI3620_UART1_MUX 43
+#define HI3620_UART2_MUX 44
+#define HI3620_UART3_MUX 45
+#define HI3620_UART4_MUX 46
+#define HI3620_SPI0_MUX 47
+#define HI3620_SPI1_MUX 48
+#define HI3620_SPI2_MUX 49
+#define HI3620_SAXI_MUX 50
+#define HI3620_PWM0_MUX 51
+#define HI3620_PWM1_MUX 52
+#define HI3620_SD_MUX 53
+#define HI3620_MMC1_MUX 54
+#define HI3620_MMC1_MUX2 55
+#define HI3620_G2D_MUX 56
+#define HI3620_VENC_MUX 57
+#define HI3620_VDEC_MUX 58
+#define HI3620_VPP_MUX 59
+#define HI3620_EDC0_MUX 60
+#define HI3620_LDI0_MUX 61
+#define HI3620_EDC1_MUX 62
+#define HI3620_LDI1_MUX 63
+#define HI3620_RCLK_HSIC 64
+#define HI3620_MMC2_MUX 65
+#define HI3620_MMC3_MUX 66
+
+/* divider clocks */
+#define HI3620_SHAREAXI_DIV 128
+#define HI3620_CFGAXI_DIV 129
+#define HI3620_SD_DIV 130
+#define HI3620_MMC1_DIV 131
+#define HI3620_HSIC_DIV 132
+#define HI3620_MMC2_DIV 133
+#define HI3620_MMC3_DIV 134
+
+/* gate clocks */
+#define HI3620_TIMERCLK01 160
+#define HI3620_TIMER_RCLK01 161
+#define HI3620_TIMERCLK23 162
+#define HI3620_TIMER_RCLK23 163
+#define HI3620_TIMERCLK45 164
+#define HI3620_TIMERCLK67 165
+#define HI3620_TIMERCLK89 166
+#define HI3620_RTCCLK 167
+#define HI3620_KPC_CLK 168
+#define HI3620_GPIOCLK0 169
+#define HI3620_GPIOCLK1 170
+#define HI3620_GPIOCLK2 171
+#define HI3620_GPIOCLK3 172
+#define HI3620_GPIOCLK4 173
+#define HI3620_GPIOCLK5 174
+#define HI3620_GPIOCLK6 175
+#define HI3620_GPIOCLK7 176
+#define HI3620_GPIOCLK8 177
+#define HI3620_GPIOCLK9 178
+#define HI3620_GPIOCLK10 179
+#define HI3620_GPIOCLK11 180
+#define HI3620_GPIOCLK12 181
+#define HI3620_GPIOCLK13 182
+#define HI3620_GPIOCLK14 183
+#define HI3620_GPIOCLK15 184
+#define HI3620_GPIOCLK16 185
+#define HI3620_GPIOCLK17 186
+#define HI3620_GPIOCLK18 187
+#define HI3620_GPIOCLK19 188
+#define HI3620_GPIOCLK20 189
+#define HI3620_GPIOCLK21 190
+#define HI3620_DPHY0_CLK 191
+#define HI3620_DPHY1_CLK 192
+#define HI3620_DPHY2_CLK 193
+#define HI3620_USBPHY_CLK 194
+#define HI3620_ACP_CLK 195
+#define HI3620_PWMCLK0 196
+#define HI3620_PWMCLK1 197
+#define HI3620_UARTCLK0 198
+#define HI3620_UARTCLK1 199
+#define HI3620_UARTCLK2 200
+#define HI3620_UARTCLK3 201
+#define HI3620_UARTCLK4 202
+#define HI3620_SPICLK0 203
+#define HI3620_SPICLK1 204
+#define HI3620_SPICLK2 205
+#define HI3620_I2CCLK0 206
+#define HI3620_I2CCLK1 207
+#define HI3620_I2CCLK2 208
+#define HI3620_I2CCLK3 209
+#define HI3620_SCI_CLK 210
+#define HI3620_DDRC_PER_CLK 211
+#define HI3620_DMAC_CLK 212
+#define HI3620_USB2DVC_CLK 213
+#define HI3620_SD_CLK 214
+#define HI3620_MMC_CLK1 215
+#define HI3620_MMC_CLK2 216
+#define HI3620_MMC_CLK3 217
+#define HI3620_MCU_CLK 218
+
+#define HI3620_SD_CIUCLK 0
+#define HI3620_MMC_CIUCLK1 1
+#define HI3620_MMC_CIUCLK2 2
+#define HI3620_MMC_CIUCLK3 3
+
+#define HI3620_NR_CLKS 219
+
+#endif /* __DTS_HI3620_CLOCK_H */
diff --git a/include/dt-bindings/clock/hip04-clock.h b/include/dt-bindings/clock/hip04-clock.h
new file mode 100644
index 000000000..695e61cd1
--- /dev/null
+++ b/include/dt-bindings/clock/hip04-clock.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 Linaro Limited.
+ *
+ * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __DTS_HIP04_CLOCK_H
+#define __DTS_HIP04_CLOCK_H
+
+#define HIP04_NONE_CLOCK 0
+
+/* fixed rate & fixed factor clocks */
+#define HIP04_OSC50M 1
+#define HIP04_CLK_50M 2
+#define HIP04_CLK_168M 3
+
+#define HIP04_NR_CLKS 64
+
+#endif /* __DTS_HIP04_CLOCK_H */
diff --git a/include/dt-bindings/clock/hix5hd2-clock.h b/include/dt-bindings/clock/hix5hd2-clock.h
new file mode 100644
index 000000000..fd29c174b
--- /dev/null
+++ b/include/dt-bindings/clock/hix5hd2-clock.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2014 Linaro Ltd.
+ * Copyright (c) 2014 Hisilicon Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __DTS_HIX5HD2_CLOCK_H
+#define __DTS_HIX5HD2_CLOCK_H
+
+/* fixed rate */
+#define HIX5HD2_FIXED_1200M 1
+#define HIX5HD2_FIXED_400M 2
+#define HIX5HD2_FIXED_48M 3
+#define HIX5HD2_FIXED_24M 4
+#define HIX5HD2_FIXED_600M 5
+#define HIX5HD2_FIXED_300M 6
+#define HIX5HD2_FIXED_75M 7
+#define HIX5HD2_FIXED_200M 8
+#define HIX5HD2_FIXED_100M 9
+#define HIX5HD2_FIXED_40M 10
+#define HIX5HD2_FIXED_150M 11
+#define HIX5HD2_FIXED_1728M 12
+#define HIX5HD2_FIXED_28P8M 13
+#define HIX5HD2_FIXED_432M 14
+#define HIX5HD2_FIXED_345P6M 15
+#define HIX5HD2_FIXED_288M 16
+#define HIX5HD2_FIXED_60M 17
+#define HIX5HD2_FIXED_750M 18
+#define HIX5HD2_FIXED_500M 19
+#define HIX5HD2_FIXED_54M 20
+#define HIX5HD2_FIXED_27M 21
+#define HIX5HD2_FIXED_1500M 22
+#define HIX5HD2_FIXED_375M 23
+#define HIX5HD2_FIXED_187M 24
+#define HIX5HD2_FIXED_250M 25
+#define HIX5HD2_FIXED_125M 26
+#define HIX5HD2_FIXED_2P02M 27
+#define HIX5HD2_FIXED_50M 28
+#define HIX5HD2_FIXED_25M 29
+#define HIX5HD2_FIXED_83M 30
+
+/* mux clocks */
+#define HIX5HD2_SFC_MUX 64
+#define HIX5HD2_MMC_MUX 65
+#define HIX5HD2_FEPHY_MUX 66
+#define HIX5HD2_SD_MUX 67
+
+/* gate clocks */
+#define HIX5HD2_SFC_RST 128
+#define HIX5HD2_SFC_CLK 129
+#define HIX5HD2_MMC_CIU_CLK 130
+#define HIX5HD2_MMC_BIU_CLK 131
+#define HIX5HD2_MMC_CIU_RST 132
+#define HIX5HD2_FWD_BUS_CLK 133
+#define HIX5HD2_FWD_SYS_CLK 134
+#define HIX5HD2_MAC0_PHY_CLK 135
+#define HIX5HD2_SD_CIU_CLK 136
+#define HIX5HD2_SD_BIU_CLK 137
+#define HIX5HD2_SD_CIU_RST 138
+#define HIX5HD2_WDG0_CLK 139
+#define HIX5HD2_WDG0_RST 140
+#define HIX5HD2_I2C0_CLK 141
+#define HIX5HD2_I2C0_RST 142
+#define HIX5HD2_I2C1_CLK 143
+#define HIX5HD2_I2C1_RST 144
+#define HIX5HD2_I2C2_CLK 145
+#define HIX5HD2_I2C2_RST 146
+#define HIX5HD2_I2C3_CLK 147
+#define HIX5HD2_I2C3_RST 148
+#define HIX5HD2_I2C4_CLK 149
+#define HIX5HD2_I2C4_RST 150
+#define HIX5HD2_I2C5_CLK 151
+#define HIX5HD2_I2C5_RST 152
+
+/* complex */
+#define HIX5HD2_MAC0_CLK 192
+#define HIX5HD2_MAC1_CLK 193
+#define HIX5HD2_SATA_CLK 194
+#define HIX5HD2_USB_CLK 195
+
+#define HIX5HD2_NR_CLKS 256
+#endif /* __DTS_HIX5HD2_CLOCK_H */
diff --git a/include/dt-bindings/clock/imx1-clock.h b/include/dt-bindings/clock/imx1-clock.h
new file mode 100644
index 000000000..607bf01a3
--- /dev/null
+++ b/include/dt-bindings/clock/imx1-clock.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX1_H
+#define __DT_BINDINGS_CLOCK_IMX1_H
+
+#define IMX1_CLK_DUMMY 0
+#define IMX1_CLK_CLK32 1
+#define IMX1_CLK_CLK16M_EXT 2
+#define IMX1_CLK_CLK16M 3
+#define IMX1_CLK_CLK32_PREMULT 4
+#define IMX1_CLK_PREM 5
+#define IMX1_CLK_MPLL 6
+#define IMX1_CLK_MPLL_GATE 7
+#define IMX1_CLK_SPLL 8
+#define IMX1_CLK_SPLL_GATE 9
+#define IMX1_CLK_MCU 10
+#define IMX1_CLK_FCLK 11
+#define IMX1_CLK_HCLK 12
+#define IMX1_CLK_CLK48M 13
+#define IMX1_CLK_PER1 14
+#define IMX1_CLK_PER2 15
+#define IMX1_CLK_PER3 16
+#define IMX1_CLK_CLKO 17
+#define IMX1_CLK_UART3_GATE 18
+#define IMX1_CLK_SSI2_GATE 19
+#define IMX1_CLK_BROM_GATE 20
+#define IMX1_CLK_DMA_GATE 21
+#define IMX1_CLK_CSI_GATE 22
+#define IMX1_CLK_MMA_GATE 23
+#define IMX1_CLK_USBD_GATE 24
+#define IMX1_CLK_MAX 25
+
+#endif
diff --git a/include/dt-bindings/clock/imx21-clock.h b/include/dt-bindings/clock/imx21-clock.h
new file mode 100644
index 000000000..b13596cf5
--- /dev/null
+++ b/include/dt-bindings/clock/imx21-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX21_H
+#define __DT_BINDINGS_CLOCK_IMX21_H
+
+#define IMX21_CLK_DUMMY 0
+#define IMX21_CLK_CKIL 1
+#define IMX21_CLK_CKIH 2
+#define IMX21_CLK_FPM 3
+#define IMX21_CLK_CKIH_DIV1P5 4
+#define IMX21_CLK_MPLL_GATE 5
+#define IMX21_CLK_SPLL_GATE 6
+#define IMX21_CLK_FPM_GATE 7
+#define IMX21_CLK_CKIH_GATE 8
+#define IMX21_CLK_MPLL_OSC_SEL 9
+#define IMX21_CLK_IPG 10
+#define IMX21_CLK_HCLK 11
+#define IMX21_CLK_MPLL_SEL 12
+#define IMX21_CLK_SPLL_SEL 13
+#define IMX21_CLK_SSI1_SEL 14
+#define IMX21_CLK_SSI2_SEL 15
+#define IMX21_CLK_USB_DIV 16
+#define IMX21_CLK_FCLK 17
+#define IMX21_CLK_MPLL 18
+#define IMX21_CLK_SPLL 19
+#define IMX21_CLK_NFC_DIV 20
+#define IMX21_CLK_SSI1_DIV 21
+#define IMX21_CLK_SSI2_DIV 22
+#define IMX21_CLK_PER1 23
+#define IMX21_CLK_PER2 24
+#define IMX21_CLK_PER3 25
+#define IMX21_CLK_PER4 26
+#define IMX21_CLK_UART1_IPG_GATE 27
+#define IMX21_CLK_UART2_IPG_GATE 28
+#define IMX21_CLK_UART3_IPG_GATE 29
+#define IMX21_CLK_UART4_IPG_GATE 30
+#define IMX21_CLK_CSPI1_IPG_GATE 31
+#define IMX21_CLK_CSPI2_IPG_GATE 32
+#define IMX21_CLK_SSI1_GATE 33
+#define IMX21_CLK_SSI2_GATE 34
+#define IMX21_CLK_SDHC1_IPG_GATE 35
+#define IMX21_CLK_SDHC2_IPG_GATE 36
+#define IMX21_CLK_GPIO_GATE 37
+#define IMX21_CLK_I2C_GATE 38
+#define IMX21_CLK_DMA_GATE 39
+#define IMX21_CLK_USB_GATE 40
+#define IMX21_CLK_EMMA_GATE 41
+#define IMX21_CLK_SSI2_BAUD_GATE 42
+#define IMX21_CLK_SSI1_BAUD_GATE 43
+#define IMX21_CLK_LCDC_IPG_GATE 44
+#define IMX21_CLK_NFC_GATE 45
+#define IMX21_CLK_LCDC_HCLK_GATE 46
+#define IMX21_CLK_PER4_GATE 47
+#define IMX21_CLK_BMI_GATE 48
+#define IMX21_CLK_USB_HCLK_GATE 49
+#define IMX21_CLK_SLCDC_GATE 50
+#define IMX21_CLK_SLCDC_HCLK_GATE 51
+#define IMX21_CLK_EMMA_HCLK_GATE 52
+#define IMX21_CLK_BROM_GATE 53
+#define IMX21_CLK_DMA_HCLK_GATE 54
+#define IMX21_CLK_CSI_HCLK_GATE 55
+#define IMX21_CLK_CSPI3_IPG_GATE 56
+#define IMX21_CLK_WDOG_GATE 57
+#define IMX21_CLK_GPT1_IPG_GATE 58
+#define IMX21_CLK_GPT2_IPG_GATE 59
+#define IMX21_CLK_GPT3_IPG_GATE 60
+#define IMX21_CLK_PWM_IPG_GATE 61
+#define IMX21_CLK_RTC_GATE 62
+#define IMX21_CLK_KPP_GATE 63
+#define IMX21_CLK_OWIRE_GATE 64
+#define IMX21_CLK_MAX 65
+
+#endif
diff --git a/include/dt-bindings/clock/imx27-clock.h b/include/dt-bindings/clock/imx27-clock.h
new file mode 100644
index 000000000..148b053e5
--- /dev/null
+++ b/include/dt-bindings/clock/imx27-clock.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX27_H
+#define __DT_BINDINGS_CLOCK_IMX27_H
+
+#define IMX27_CLK_DUMMY 0
+#define IMX27_CLK_CKIH 1
+#define IMX27_CLK_CKIL 2
+#define IMX27_CLK_MPLL 3
+#define IMX27_CLK_SPLL 4
+#define IMX27_CLK_MPLL_MAIN2 5
+#define IMX27_CLK_AHB 6
+#define IMX27_CLK_IPG 7
+#define IMX27_CLK_NFC_DIV 8
+#define IMX27_CLK_PER1_DIV 9
+#define IMX27_CLK_PER2_DIV 10
+#define IMX27_CLK_PER3_DIV 11
+#define IMX27_CLK_PER4_DIV 12
+#define IMX27_CLK_VPU_SEL 13
+#define IMX27_CLK_VPU_DIV 14
+#define IMX27_CLK_USB_DIV 15
+#define IMX27_CLK_CPU_SEL 16
+#define IMX27_CLK_CLKO_SEL 17
+#define IMX27_CLK_CPU_DIV 18
+#define IMX27_CLK_CLKO_DIV 19
+#define IMX27_CLK_SSI1_SEL 20
+#define IMX27_CLK_SSI2_SEL 21
+#define IMX27_CLK_SSI1_DIV 22
+#define IMX27_CLK_SSI2_DIV 23
+#define IMX27_CLK_CLKO_EN 24
+#define IMX27_CLK_SSI2_IPG_GATE 25
+#define IMX27_CLK_SSI1_IPG_GATE 26
+#define IMX27_CLK_SLCDC_IPG_GATE 27
+#define IMX27_CLK_SDHC3_IPG_GATE 28
+#define IMX27_CLK_SDHC2_IPG_GATE 29
+#define IMX27_CLK_SDHC1_IPG_GATE 30
+#define IMX27_CLK_SCC_IPG_GATE 31
+#define IMX27_CLK_SAHARA_IPG_GATE 32
+#define IMX27_CLK_RTC_IPG_GATE 33
+#define IMX27_CLK_PWM_IPG_GATE 34
+#define IMX27_CLK_OWIRE_IPG_GATE 35
+#define IMX27_CLK_LCDC_IPG_GATE 36
+#define IMX27_CLK_KPP_IPG_GATE 37
+#define IMX27_CLK_IIM_IPG_GATE 38
+#define IMX27_CLK_I2C2_IPG_GATE 39
+#define IMX27_CLK_I2C1_IPG_GATE 40
+#define IMX27_CLK_GPT6_IPG_GATE 41
+#define IMX27_CLK_GPT5_IPG_GATE 42
+#define IMX27_CLK_GPT4_IPG_GATE 43
+#define IMX27_CLK_GPT3_IPG_GATE 44
+#define IMX27_CLK_GPT2_IPG_GATE 45
+#define IMX27_CLK_GPT1_IPG_GATE 46
+#define IMX27_CLK_GPIO_IPG_GATE 47
+#define IMX27_CLK_FEC_IPG_GATE 48
+#define IMX27_CLK_EMMA_IPG_GATE 49
+#define IMX27_CLK_DMA_IPG_GATE 50
+#define IMX27_CLK_CSPI3_IPG_GATE 51
+#define IMX27_CLK_CSPI2_IPG_GATE 52
+#define IMX27_CLK_CSPI1_IPG_GATE 53
+#define IMX27_CLK_NFC_BAUD_GATE 54
+#define IMX27_CLK_SSI2_BAUD_GATE 55
+#define IMX27_CLK_SSI1_BAUD_GATE 56
+#define IMX27_CLK_VPU_BAUD_GATE 57
+#define IMX27_CLK_PER4_GATE 58
+#define IMX27_CLK_PER3_GATE 59
+#define IMX27_CLK_PER2_GATE 60
+#define IMX27_CLK_PER1_GATE 61
+#define IMX27_CLK_USB_AHB_GATE 62
+#define IMX27_CLK_SLCDC_AHB_GATE 63
+#define IMX27_CLK_SAHARA_AHB_GATE 64
+#define IMX27_CLK_LCDC_AHB_GATE 65
+#define IMX27_CLK_VPU_AHB_GATE 66
+#define IMX27_CLK_FEC_AHB_GATE 67
+#define IMX27_CLK_EMMA_AHB_GATE 68
+#define IMX27_CLK_EMI_AHB_GATE 69
+#define IMX27_CLK_DMA_AHB_GATE 70
+#define IMX27_CLK_CSI_AHB_GATE 71
+#define IMX27_CLK_BROM_AHB_GATE 72
+#define IMX27_CLK_ATA_AHB_GATE 73
+#define IMX27_CLK_WDOG_IPG_GATE 74
+#define IMX27_CLK_USB_IPG_GATE 75
+#define IMX27_CLK_UART6_IPG_GATE 76
+#define IMX27_CLK_UART5_IPG_GATE 77
+#define IMX27_CLK_UART4_IPG_GATE 78
+#define IMX27_CLK_UART3_IPG_GATE 79
+#define IMX27_CLK_UART2_IPG_GATE 80
+#define IMX27_CLK_UART1_IPG_GATE 81
+#define IMX27_CLK_CKIH_DIV1P5 82
+#define IMX27_CLK_FPM 83
+#define IMX27_CLK_MPLL_OSC_SEL 84
+#define IMX27_CLK_MPLL_SEL 85
+#define IMX27_CLK_SPLL_GATE 86
+#define IMX27_CLK_MSHC_DIV 87
+#define IMX27_CLK_RTIC_IPG_GATE 88
+#define IMX27_CLK_MSHC_IPG_GATE 89
+#define IMX27_CLK_RTIC_AHB_GATE 90
+#define IMX27_CLK_MSHC_BAUD_GATE 91
+#define IMX27_CLK_CKIH_GATE 92
+#define IMX27_CLK_MAX 93
+
+#endif
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
new file mode 100644
index 000000000..f4b7478e2
--- /dev/null
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2013 Lucas Stach, Pengutronix <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX5_H
+#define __DT_BINDINGS_CLOCK_IMX5_H
+
+#define IMX5_CLK_DUMMY 0
+#define IMX5_CLK_CKIL 1
+#define IMX5_CLK_OSC 2
+#define IMX5_CLK_CKIH1 3
+#define IMX5_CLK_CKIH2 4
+#define IMX5_CLK_AHB 5
+#define IMX5_CLK_IPG 6
+#define IMX5_CLK_AXI_A 7
+#define IMX5_CLK_AXI_B 8
+#define IMX5_CLK_UART_PRED 9
+#define IMX5_CLK_UART_ROOT 10
+#define IMX5_CLK_ESDHC_A_PRED 11
+#define IMX5_CLK_ESDHC_B_PRED 12
+#define IMX5_CLK_ESDHC_C_SEL 13
+#define IMX5_CLK_ESDHC_D_SEL 14
+#define IMX5_CLK_EMI_SEL 15
+#define IMX5_CLK_EMI_SLOW_PODF 16
+#define IMX5_CLK_NFC_PODF 17
+#define IMX5_CLK_ECSPI_PRED 18
+#define IMX5_CLK_ECSPI_PODF 19
+#define IMX5_CLK_USBOH3_PRED 20
+#define IMX5_CLK_USBOH3_PODF 21
+#define IMX5_CLK_USB_PHY_PRED 22
+#define IMX5_CLK_USB_PHY_PODF 23
+#define IMX5_CLK_CPU_PODF 24
+#define IMX5_CLK_DI_PRED 25
+#define IMX5_CLK_TVE_SEL 27
+#define IMX5_CLK_UART1_IPG_GATE 28
+#define IMX5_CLK_UART1_PER_GATE 29
+#define IMX5_CLK_UART2_IPG_GATE 30
+#define IMX5_CLK_UART2_PER_GATE 31
+#define IMX5_CLK_UART3_IPG_GATE 32
+#define IMX5_CLK_UART3_PER_GATE 33
+#define IMX5_CLK_I2C1_GATE 34
+#define IMX5_CLK_I2C2_GATE 35
+#define IMX5_CLK_GPT_IPG_GATE 36
+#define IMX5_CLK_PWM1_IPG_GATE 37
+#define IMX5_CLK_PWM1_HF_GATE 38
+#define IMX5_CLK_PWM2_IPG_GATE 39
+#define IMX5_CLK_PWM2_HF_GATE 40
+#define IMX5_CLK_GPT_HF_GATE 41
+#define IMX5_CLK_FEC_GATE 42
+#define IMX5_CLK_USBOH3_PER_GATE 43
+#define IMX5_CLK_ESDHC1_IPG_GATE 44
+#define IMX5_CLK_ESDHC2_IPG_GATE 45
+#define IMX5_CLK_ESDHC3_IPG_GATE 46
+#define IMX5_CLK_ESDHC4_IPG_GATE 47
+#define IMX5_CLK_SSI1_IPG_GATE 48
+#define IMX5_CLK_SSI2_IPG_GATE 49
+#define IMX5_CLK_SSI3_IPG_GATE 50
+#define IMX5_CLK_ECSPI1_IPG_GATE 51
+#define IMX5_CLK_ECSPI1_PER_GATE 52
+#define IMX5_CLK_ECSPI2_IPG_GATE 53
+#define IMX5_CLK_ECSPI2_PER_GATE 54
+#define IMX5_CLK_CSPI_IPG_GATE 55
+#define IMX5_CLK_SDMA_GATE 56
+#define IMX5_CLK_EMI_SLOW_GATE 57
+#define IMX5_CLK_IPU_SEL 58
+#define IMX5_CLK_IPU_GATE 59
+#define IMX5_CLK_NFC_GATE 60
+#define IMX5_CLK_IPU_DI1_GATE 61
+#define IMX5_CLK_VPU_SEL 62
+#define IMX5_CLK_VPU_GATE 63
+#define IMX5_CLK_VPU_REFERENCE_GATE 64
+#define IMX5_CLK_UART4_IPG_GATE 65
+#define IMX5_CLK_UART4_PER_GATE 66
+#define IMX5_CLK_UART5_IPG_GATE 67
+#define IMX5_CLK_UART5_PER_GATE 68
+#define IMX5_CLK_TVE_GATE 69
+#define IMX5_CLK_TVE_PRED 70
+#define IMX5_CLK_ESDHC1_PER_GATE 71
+#define IMX5_CLK_ESDHC2_PER_GATE 72
+#define IMX5_CLK_ESDHC3_PER_GATE 73
+#define IMX5_CLK_ESDHC4_PER_GATE 74
+#define IMX5_CLK_USB_PHY_GATE 75
+#define IMX5_CLK_HSI2C_GATE 76
+#define IMX5_CLK_MIPI_HSC1_GATE 77
+#define IMX5_CLK_MIPI_HSC2_GATE 78
+#define IMX5_CLK_MIPI_ESC_GATE 79
+#define IMX5_CLK_MIPI_HSP_GATE 80
+#define IMX5_CLK_LDB_DI1_DIV_3_5 81
+#define IMX5_CLK_LDB_DI1_DIV 82
+#define IMX5_CLK_LDB_DI0_DIV_3_5 83
+#define IMX5_CLK_LDB_DI0_DIV 84
+#define IMX5_CLK_LDB_DI1_GATE 85
+#define IMX5_CLK_CAN2_SERIAL_GATE 86
+#define IMX5_CLK_CAN2_IPG_GATE 87
+#define IMX5_CLK_I2C3_GATE 88
+#define IMX5_CLK_LP_APM 89
+#define IMX5_CLK_PERIPH_APM 90
+#define IMX5_CLK_MAIN_BUS 91
+#define IMX5_CLK_AHB_MAX 92
+#define IMX5_CLK_AIPS_TZ1 93
+#define IMX5_CLK_AIPS_TZ2 94
+#define IMX5_CLK_TMAX1 95
+#define IMX5_CLK_TMAX2 96
+#define IMX5_CLK_TMAX3 97
+#define IMX5_CLK_SPBA 98
+#define IMX5_CLK_UART_SEL 99
+#define IMX5_CLK_ESDHC_A_SEL 100
+#define IMX5_CLK_ESDHC_B_SEL 101
+#define IMX5_CLK_ESDHC_A_PODF 102
+#define IMX5_CLK_ESDHC_B_PODF 103
+#define IMX5_CLK_ECSPI_SEL 104
+#define IMX5_CLK_USBOH3_SEL 105
+#define IMX5_CLK_USB_PHY_SEL 106
+#define IMX5_CLK_IIM_GATE 107
+#define IMX5_CLK_USBOH3_GATE 108
+#define IMX5_CLK_EMI_FAST_GATE 109
+#define IMX5_CLK_IPU_DI0_GATE 110
+#define IMX5_CLK_GPC_DVFS 111
+#define IMX5_CLK_PLL1_SW 112
+#define IMX5_CLK_PLL2_SW 113
+#define IMX5_CLK_PLL3_SW 114
+#define IMX5_CLK_IPU_DI0_SEL 115
+#define IMX5_CLK_IPU_DI1_SEL 116
+#define IMX5_CLK_TVE_EXT_SEL 117
+#define IMX5_CLK_MX51_MIPI 118
+#define IMX5_CLK_PLL4_SW 119
+#define IMX5_CLK_LDB_DI1_SEL 120
+#define IMX5_CLK_DI_PLL4_PODF 121
+#define IMX5_CLK_LDB_DI0_SEL 122
+#define IMX5_CLK_LDB_DI0_GATE 123
+#define IMX5_CLK_USB_PHY1_GATE 124
+#define IMX5_CLK_USB_PHY2_GATE 125
+#define IMX5_CLK_PER_LP_APM 126
+#define IMX5_CLK_PER_PRED1 127
+#define IMX5_CLK_PER_PRED2 128
+#define IMX5_CLK_PER_PODF 129
+#define IMX5_CLK_PER_ROOT 130
+#define IMX5_CLK_SSI_APM 131
+#define IMX5_CLK_SSI1_ROOT_SEL 132
+#define IMX5_CLK_SSI2_ROOT_SEL 133
+#define IMX5_CLK_SSI3_ROOT_SEL 134
+#define IMX5_CLK_SSI_EXT1_SEL 135
+#define IMX5_CLK_SSI_EXT2_SEL 136
+#define IMX5_CLK_SSI_EXT1_COM_SEL 137
+#define IMX5_CLK_SSI_EXT2_COM_SEL 138
+#define IMX5_CLK_SSI1_ROOT_PRED 139
+#define IMX5_CLK_SSI1_ROOT_PODF 140
+#define IMX5_CLK_SSI2_ROOT_PRED 141
+#define IMX5_CLK_SSI2_ROOT_PODF 142
+#define IMX5_CLK_SSI_EXT1_PRED 143
+#define IMX5_CLK_SSI_EXT1_PODF 144
+#define IMX5_CLK_SSI_EXT2_PRED 145
+#define IMX5_CLK_SSI_EXT2_PODF 146
+#define IMX5_CLK_SSI1_ROOT_GATE 147
+#define IMX5_CLK_SSI2_ROOT_GATE 148
+#define IMX5_CLK_SSI3_ROOT_GATE 149
+#define IMX5_CLK_SSI_EXT1_GATE 150
+#define IMX5_CLK_SSI_EXT2_GATE 151
+#define IMX5_CLK_EPIT1_IPG_GATE 152
+#define IMX5_CLK_EPIT1_HF_GATE 153
+#define IMX5_CLK_EPIT2_IPG_GATE 154
+#define IMX5_CLK_EPIT2_HF_GATE 155
+#define IMX5_CLK_CAN_SEL 156
+#define IMX5_CLK_CAN1_SERIAL_GATE 157
+#define IMX5_CLK_CAN1_IPG_GATE 158
+#define IMX5_CLK_OWIRE_GATE 159
+#define IMX5_CLK_GPU3D_SEL 160
+#define IMX5_CLK_GPU2D_SEL 161
+#define IMX5_CLK_GPU3D_GATE 162
+#define IMX5_CLK_GPU2D_GATE 163
+#define IMX5_CLK_GARB_GATE 164
+#define IMX5_CLK_CKO1_SEL 165
+#define IMX5_CLK_CKO1_PODF 166
+#define IMX5_CLK_CKO1 167
+#define IMX5_CLK_CKO2_SEL 168
+#define IMX5_CLK_CKO2_PODF 169
+#define IMX5_CLK_CKO2 170
+#define IMX5_CLK_SRTC_GATE 171
+#define IMX5_CLK_PATA_GATE 172
+#define IMX5_CLK_SATA_GATE 173
+#define IMX5_CLK_SPDIF_XTAL_SEL 174
+#define IMX5_CLK_SPDIF0_SEL 175
+#define IMX5_CLK_SPDIF1_SEL 176
+#define IMX5_CLK_SPDIF0_PRED 177
+#define IMX5_CLK_SPDIF0_PODF 178
+#define IMX5_CLK_SPDIF1_PRED 179
+#define IMX5_CLK_SPDIF1_PODF 180
+#define IMX5_CLK_SPDIF0_COM_SEL 181
+#define IMX5_CLK_SPDIF1_COM_SEL 182
+#define IMX5_CLK_SPDIF0_GATE 183
+#define IMX5_CLK_SPDIF1_GATE 184
+#define IMX5_CLK_SPDIF_IPG_GATE 185
+#define IMX5_CLK_OCRAM 186
+#define IMX5_CLK_SAHARA_IPG_GATE 187
+#define IMX5_CLK_SATA_REF 188
+#define IMX5_CLK_STEP_SEL 189
+#define IMX5_CLK_CPU_PODF_SEL 190
+#define IMX5_CLK_ARM 191
+#define IMX5_CLK_END 192
+
+#endif /* __DT_BINDINGS_CLOCK_IMX5_H */
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
new file mode 100644
index 000000000..878086845
--- /dev/null
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
+#define __DT_BINDINGS_CLOCK_IMX6QDL_H
+
+#define IMX6QDL_CLK_DUMMY 0
+#define IMX6QDL_CLK_CKIL 1
+#define IMX6QDL_CLK_CKIH 2
+#define IMX6QDL_CLK_OSC 3
+#define IMX6QDL_CLK_PLL2_PFD0_352M 4
+#define IMX6QDL_CLK_PLL2_PFD1_594M 5
+#define IMX6QDL_CLK_PLL2_PFD2_396M 6
+#define IMX6QDL_CLK_PLL3_PFD0_720M 7
+#define IMX6QDL_CLK_PLL3_PFD1_540M 8
+#define IMX6QDL_CLK_PLL3_PFD2_508M 9
+#define IMX6QDL_CLK_PLL3_PFD3_454M 10
+#define IMX6QDL_CLK_PLL2_198M 11
+#define IMX6QDL_CLK_PLL3_120M 12
+#define IMX6QDL_CLK_PLL3_80M 13
+#define IMX6QDL_CLK_PLL3_60M 14
+#define IMX6QDL_CLK_TWD 15
+#define IMX6QDL_CLK_STEP 16
+#define IMX6QDL_CLK_PLL1_SW 17
+#define IMX6QDL_CLK_PERIPH_PRE 18
+#define IMX6QDL_CLK_PERIPH2_PRE 19
+#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
+#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
+#define IMX6QDL_CLK_AXI_SEL 22
+#define IMX6QDL_CLK_ESAI_SEL 23
+#define IMX6QDL_CLK_ASRC_SEL 24
+#define IMX6QDL_CLK_SPDIF_SEL 25
+#define IMX6QDL_CLK_GPU2D_AXI 26
+#define IMX6QDL_CLK_GPU3D_AXI 27
+#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
+#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
+#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
+#define IMX6QDL_CLK_IPU1_SEL 31
+#define IMX6QDL_CLK_IPU2_SEL 32
+#define IMX6QDL_CLK_LDB_DI0_SEL 33
+#define IMX6QDL_CLK_LDB_DI1_SEL 34
+#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
+#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
+#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
+#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
+#define IMX6QDL_CLK_IPU1_DI0_SEL 39
+#define IMX6QDL_CLK_IPU1_DI1_SEL 40
+#define IMX6QDL_CLK_IPU2_DI0_SEL 41
+#define IMX6QDL_CLK_IPU2_DI1_SEL 42
+#define IMX6QDL_CLK_HSI_TX_SEL 43
+#define IMX6QDL_CLK_PCIE_AXI_SEL 44
+#define IMX6QDL_CLK_SSI1_SEL 45
+#define IMX6QDL_CLK_SSI2_SEL 46
+#define IMX6QDL_CLK_SSI3_SEL 47
+#define IMX6QDL_CLK_USDHC1_SEL 48
+#define IMX6QDL_CLK_USDHC2_SEL 49
+#define IMX6QDL_CLK_USDHC3_SEL 50
+#define IMX6QDL_CLK_USDHC4_SEL 51
+#define IMX6QDL_CLK_ENFC_SEL 52
+#define IMX6QDL_CLK_EIM_SEL 53
+#define IMX6QDL_CLK_EIM_SLOW_SEL 54
+#define IMX6QDL_CLK_VDO_AXI_SEL 55
+#define IMX6QDL_CLK_VPU_AXI_SEL 56
+#define IMX6QDL_CLK_CKO1_SEL 57
+#define IMX6QDL_CLK_PERIPH 58
+#define IMX6QDL_CLK_PERIPH2 59
+#define IMX6QDL_CLK_PERIPH_CLK2 60
+#define IMX6QDL_CLK_PERIPH2_CLK2 61
+#define IMX6QDL_CLK_IPG 62
+#define IMX6QDL_CLK_IPG_PER 63
+#define IMX6QDL_CLK_ESAI_PRED 64
+#define IMX6QDL_CLK_ESAI_PODF 65
+#define IMX6QDL_CLK_ASRC_PRED 66
+#define IMX6QDL_CLK_ASRC_PODF 67
+#define IMX6QDL_CLK_SPDIF_PRED 68
+#define IMX6QDL_CLK_SPDIF_PODF 69
+#define IMX6QDL_CLK_CAN_ROOT 70
+#define IMX6QDL_CLK_ECSPI_ROOT 71
+#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
+#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
+#define IMX6QDL_CLK_GPU3D_SHADER 74
+#define IMX6QDL_CLK_IPU1_PODF 75
+#define IMX6QDL_CLK_IPU2_PODF 76
+#define IMX6QDL_CLK_LDB_DI0_PODF 77
+#define IMX6QDL_CLK_LDB_DI1_PODF 78
+#define IMX6QDL_CLK_IPU1_DI0_PRE 79
+#define IMX6QDL_CLK_IPU1_DI1_PRE 80
+#define IMX6QDL_CLK_IPU2_DI0_PRE 81
+#define IMX6QDL_CLK_IPU2_DI1_PRE 82
+#define IMX6QDL_CLK_HSI_TX_PODF 83
+#define IMX6QDL_CLK_SSI1_PRED 84
+#define IMX6QDL_CLK_SSI1_PODF 85
+#define IMX6QDL_CLK_SSI2_PRED 86
+#define IMX6QDL_CLK_SSI2_PODF 87
+#define IMX6QDL_CLK_SSI3_PRED 88
+#define IMX6QDL_CLK_SSI3_PODF 89
+#define IMX6QDL_CLK_UART_SERIAL_PODF 90
+#define IMX6QDL_CLK_USDHC1_PODF 91
+#define IMX6QDL_CLK_USDHC2_PODF 92
+#define IMX6QDL_CLK_USDHC3_PODF 93
+#define IMX6QDL_CLK_USDHC4_PODF 94
+#define IMX6QDL_CLK_ENFC_PRED 95
+#define IMX6QDL_CLK_ENFC_PODF 96
+#define IMX6QDL_CLK_EIM_PODF 97
+#define IMX6QDL_CLK_EIM_SLOW_PODF 98
+#define IMX6QDL_CLK_VPU_AXI_PODF 99
+#define IMX6QDL_CLK_CKO1_PODF 100
+#define IMX6QDL_CLK_AXI 101
+#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
+#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
+#define IMX6QDL_CLK_ARM 104
+#define IMX6QDL_CLK_AHB 105
+#define IMX6QDL_CLK_APBH_DMA 106
+#define IMX6QDL_CLK_ASRC 107
+#define IMX6QDL_CLK_CAN1_IPG 108
+#define IMX6QDL_CLK_CAN1_SERIAL 109
+#define IMX6QDL_CLK_CAN2_IPG 110
+#define IMX6QDL_CLK_CAN2_SERIAL 111
+#define IMX6QDL_CLK_ECSPI1 112
+#define IMX6QDL_CLK_ECSPI2 113
+#define IMX6QDL_CLK_ECSPI3 114
+#define IMX6QDL_CLK_ECSPI4 115
+#define IMX6Q_CLK_ECSPI5 116
+#define IMX6DL_CLK_I2C4 116
+#define IMX6QDL_CLK_ENET 117
+#define IMX6QDL_CLK_ESAI_EXTAL 118
+#define IMX6QDL_CLK_GPT_IPG 119
+#define IMX6QDL_CLK_GPT_IPG_PER 120
+#define IMX6QDL_CLK_GPU2D_CORE 121
+#define IMX6QDL_CLK_GPU3D_CORE 122
+#define IMX6QDL_CLK_HDMI_IAHB 123
+#define IMX6QDL_CLK_HDMI_ISFR 124
+#define IMX6QDL_CLK_I2C1 125
+#define IMX6QDL_CLK_I2C2 126
+#define IMX6QDL_CLK_I2C3 127
+#define IMX6QDL_CLK_IIM 128
+#define IMX6QDL_CLK_ENFC 129
+#define IMX6QDL_CLK_IPU1 130
+#define IMX6QDL_CLK_IPU1_DI0 131
+#define IMX6QDL_CLK_IPU1_DI1 132
+#define IMX6QDL_CLK_IPU2 133
+#define IMX6QDL_CLK_IPU2_DI0 134
+#define IMX6QDL_CLK_LDB_DI0 135
+#define IMX6QDL_CLK_LDB_DI1 136
+#define IMX6QDL_CLK_IPU2_DI1 137
+#define IMX6QDL_CLK_HSI_TX 138
+#define IMX6QDL_CLK_MLB 139
+#define IMX6QDL_CLK_MMDC_CH0_AXI 140
+#define IMX6QDL_CLK_MMDC_CH1_AXI 141
+#define IMX6QDL_CLK_OCRAM 142
+#define IMX6QDL_CLK_OPENVG_AXI 143
+#define IMX6QDL_CLK_PCIE_AXI 144
+#define IMX6QDL_CLK_PWM1 145
+#define IMX6QDL_CLK_PWM2 146
+#define IMX6QDL_CLK_PWM3 147
+#define IMX6QDL_CLK_PWM4 148
+#define IMX6QDL_CLK_PER1_BCH 149
+#define IMX6QDL_CLK_GPMI_BCH_APB 150
+#define IMX6QDL_CLK_GPMI_BCH 151
+#define IMX6QDL_CLK_GPMI_IO 152
+#define IMX6QDL_CLK_GPMI_APB 153
+#define IMX6QDL_CLK_SATA 154
+#define IMX6QDL_CLK_SDMA 155
+#define IMX6QDL_CLK_SPBA 156
+#define IMX6QDL_CLK_SSI1 157
+#define IMX6QDL_CLK_SSI2 158
+#define IMX6QDL_CLK_SSI3 159
+#define IMX6QDL_CLK_UART_IPG 160
+#define IMX6QDL_CLK_UART_SERIAL 161
+#define IMX6QDL_CLK_USBOH3 162
+#define IMX6QDL_CLK_USDHC1 163
+#define IMX6QDL_CLK_USDHC2 164
+#define IMX6QDL_CLK_USDHC3 165
+#define IMX6QDL_CLK_USDHC4 166
+#define IMX6QDL_CLK_VDO_AXI 167
+#define IMX6QDL_CLK_VPU_AXI 168
+#define IMX6QDL_CLK_CKO1 169
+#define IMX6QDL_CLK_PLL1_SYS 170
+#define IMX6QDL_CLK_PLL2_BUS 171
+#define IMX6QDL_CLK_PLL3_USB_OTG 172
+#define IMX6QDL_CLK_PLL4_AUDIO 173
+#define IMX6QDL_CLK_PLL5_VIDEO 174
+#define IMX6QDL_CLK_PLL8_MLB 175
+#define IMX6QDL_CLK_PLL7_USB_HOST 176
+#define IMX6QDL_CLK_PLL6_ENET 177
+#define IMX6QDL_CLK_SSI1_IPG 178
+#define IMX6QDL_CLK_SSI2_IPG 179
+#define IMX6QDL_CLK_SSI3_IPG 180
+#define IMX6QDL_CLK_ROM 181
+#define IMX6QDL_CLK_USBPHY1 182
+#define IMX6QDL_CLK_USBPHY2 183
+#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
+#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
+#define IMX6QDL_CLK_SATA_REF 186
+#define IMX6QDL_CLK_SATA_REF_100M 187
+#define IMX6QDL_CLK_PCIE_REF 188
+#define IMX6QDL_CLK_PCIE_REF_125M 189
+#define IMX6QDL_CLK_ENET_REF 190
+#define IMX6QDL_CLK_USBPHY1_GATE 191
+#define IMX6QDL_CLK_USBPHY2_GATE 192
+#define IMX6QDL_CLK_PLL4_POST_DIV 193
+#define IMX6QDL_CLK_PLL5_POST_DIV 194
+#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
+#define IMX6QDL_CLK_EIM_SLOW 196
+#define IMX6QDL_CLK_SPDIF 197
+#define IMX6QDL_CLK_CKO2_SEL 198
+#define IMX6QDL_CLK_CKO2_PODF 199
+#define IMX6QDL_CLK_CKO2 200
+#define IMX6QDL_CLK_CKO 201
+#define IMX6QDL_CLK_VDOA 202
+#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
+#define IMX6QDL_CLK_LVDS1_SEL 204
+#define IMX6QDL_CLK_LVDS2_SEL 205
+#define IMX6QDL_CLK_LVDS1_GATE 206
+#define IMX6QDL_CLK_LVDS2_GATE 207
+#define IMX6QDL_CLK_ESAI_IPG 208
+#define IMX6QDL_CLK_ESAI_MEM 209
+#define IMX6QDL_CLK_ASRC_IPG 210
+#define IMX6QDL_CLK_ASRC_MEM 211
+#define IMX6QDL_CLK_LVDS1_IN 212
+#define IMX6QDL_CLK_LVDS2_IN 213
+#define IMX6QDL_CLK_ANACLK1 214
+#define IMX6QDL_CLK_ANACLK2 215
+#define IMX6QDL_PLL1_BYPASS_SRC 216
+#define IMX6QDL_PLL2_BYPASS_SRC 217
+#define IMX6QDL_PLL3_BYPASS_SRC 218
+#define IMX6QDL_PLL4_BYPASS_SRC 219
+#define IMX6QDL_PLL5_BYPASS_SRC 220
+#define IMX6QDL_PLL6_BYPASS_SRC 221
+#define IMX6QDL_PLL7_BYPASS_SRC 222
+#define IMX6QDL_CLK_PLL1 223
+#define IMX6QDL_CLK_PLL2 224
+#define IMX6QDL_CLK_PLL3 225
+#define IMX6QDL_CLK_PLL4 226
+#define IMX6QDL_CLK_PLL5 227
+#define IMX6QDL_CLK_PLL6 228
+#define IMX6QDL_CLK_PLL7 229
+#define IMX6QDL_PLL1_BYPASS 230
+#define IMX6QDL_PLL2_BYPASS 231
+#define IMX6QDL_PLL3_BYPASS 232
+#define IMX6QDL_PLL4_BYPASS 233
+#define IMX6QDL_PLL5_BYPASS 234
+#define IMX6QDL_PLL6_BYPASS 235
+#define IMX6QDL_PLL7_BYPASS 236
+#define IMX6QDL_CLK_GPT_3M 237
+#define IMX6QDL_CLK_VIDEO_27M 238
+#define IMX6QDL_CLK_MIPI_CORE_CFG 239
+#define IMX6QDL_CLK_MIPI_IPG 240
+#define IMX6QDL_CLK_END 241
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
new file mode 100644
index 000000000..9ce4e4210
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
+#define __DT_BINDINGS_CLOCK_IMX6SL_H
+
+#define IMX6SL_CLK_DUMMY 0
+#define IMX6SL_CLK_CKIL 1
+#define IMX6SL_CLK_OSC 2
+#define IMX6SL_CLK_PLL1_SYS 3
+#define IMX6SL_CLK_PLL2_BUS 4
+#define IMX6SL_CLK_PLL3_USB_OTG 5
+#define IMX6SL_CLK_PLL4_AUDIO 6
+#define IMX6SL_CLK_PLL5_VIDEO 7
+#define IMX6SL_CLK_PLL6_ENET 8
+#define IMX6SL_CLK_PLL7_USB_HOST 9
+#define IMX6SL_CLK_USBPHY1 10
+#define IMX6SL_CLK_USBPHY2 11
+#define IMX6SL_CLK_USBPHY1_GATE 12
+#define IMX6SL_CLK_USBPHY2_GATE 13
+#define IMX6SL_CLK_PLL4_POST_DIV 14
+#define IMX6SL_CLK_PLL5_POST_DIV 15
+#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
+#define IMX6SL_CLK_ENET_REF 17
+#define IMX6SL_CLK_PLL2_PFD0 18
+#define IMX6SL_CLK_PLL2_PFD1 19
+#define IMX6SL_CLK_PLL2_PFD2 20
+#define IMX6SL_CLK_PLL3_PFD0 21
+#define IMX6SL_CLK_PLL3_PFD1 22
+#define IMX6SL_CLK_PLL3_PFD2 23
+#define IMX6SL_CLK_PLL3_PFD3 24
+#define IMX6SL_CLK_PLL2_198M 25
+#define IMX6SL_CLK_PLL3_120M 26
+#define IMX6SL_CLK_PLL3_80M 27
+#define IMX6SL_CLK_PLL3_60M 28
+#define IMX6SL_CLK_STEP 29
+#define IMX6SL_CLK_PLL1_SW 30
+#define IMX6SL_CLK_OCRAM_ALT_SEL 31
+#define IMX6SL_CLK_OCRAM_SEL 32
+#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
+#define IMX6SL_CLK_PRE_PERIPH_SEL 34
+#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
+#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
+#define IMX6SL_CLK_CSI_SEL 37
+#define IMX6SL_CLK_LCDIF_AXI_SEL 38
+#define IMX6SL_CLK_USDHC1_SEL 39
+#define IMX6SL_CLK_USDHC2_SEL 40
+#define IMX6SL_CLK_USDHC3_SEL 41
+#define IMX6SL_CLK_USDHC4_SEL 42
+#define IMX6SL_CLK_SSI1_SEL 43
+#define IMX6SL_CLK_SSI2_SEL 44
+#define IMX6SL_CLK_SSI3_SEL 45
+#define IMX6SL_CLK_PERCLK_SEL 46
+#define IMX6SL_CLK_PXP_AXI_SEL 47
+#define IMX6SL_CLK_EPDC_AXI_SEL 48
+#define IMX6SL_CLK_GPU2D_OVG_SEL 49
+#define IMX6SL_CLK_GPU2D_SEL 50
+#define IMX6SL_CLK_LCDIF_PIX_SEL 51
+#define IMX6SL_CLK_EPDC_PIX_SEL 52
+#define IMX6SL_CLK_SPDIF0_SEL 53
+#define IMX6SL_CLK_SPDIF1_SEL 54
+#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
+#define IMX6SL_CLK_ECSPI_SEL 56
+#define IMX6SL_CLK_UART_SEL 57
+#define IMX6SL_CLK_PERIPH 58
+#define IMX6SL_CLK_PERIPH2 59
+#define IMX6SL_CLK_OCRAM_PODF 60
+#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
+#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
+#define IMX6SL_CLK_IPG 63
+#define IMX6SL_CLK_CSI_PODF 64
+#define IMX6SL_CLK_LCDIF_AXI_PODF 65
+#define IMX6SL_CLK_USDHC1_PODF 66
+#define IMX6SL_CLK_USDHC2_PODF 67
+#define IMX6SL_CLK_USDHC3_PODF 68
+#define IMX6SL_CLK_USDHC4_PODF 69
+#define IMX6SL_CLK_SSI1_PRED 70
+#define IMX6SL_CLK_SSI1_PODF 71
+#define IMX6SL_CLK_SSI2_PRED 72
+#define IMX6SL_CLK_SSI2_PODF 73
+#define IMX6SL_CLK_SSI3_PRED 74
+#define IMX6SL_CLK_SSI3_PODF 75
+#define IMX6SL_CLK_PERCLK 76
+#define IMX6SL_CLK_PXP_AXI_PODF 77
+#define IMX6SL_CLK_EPDC_AXI_PODF 78
+#define IMX6SL_CLK_GPU2D_OVG_PODF 79
+#define IMX6SL_CLK_GPU2D_PODF 80
+#define IMX6SL_CLK_LCDIF_PIX_PRED 81
+#define IMX6SL_CLK_EPDC_PIX_PRED 82
+#define IMX6SL_CLK_LCDIF_PIX_PODF 83
+#define IMX6SL_CLK_EPDC_PIX_PODF 84
+#define IMX6SL_CLK_SPDIF0_PRED 85
+#define IMX6SL_CLK_SPDIF0_PODF 86
+#define IMX6SL_CLK_SPDIF1_PRED 87
+#define IMX6SL_CLK_SPDIF1_PODF 88
+#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
+#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
+#define IMX6SL_CLK_ECSPI_ROOT 91
+#define IMX6SL_CLK_UART_ROOT 92
+#define IMX6SL_CLK_AHB 93
+#define IMX6SL_CLK_MMDC_ROOT 94
+#define IMX6SL_CLK_ARM 95
+#define IMX6SL_CLK_ECSPI1 96
+#define IMX6SL_CLK_ECSPI2 97
+#define IMX6SL_CLK_ECSPI3 98
+#define IMX6SL_CLK_ECSPI4 99
+#define IMX6SL_CLK_EPIT1 100
+#define IMX6SL_CLK_EPIT2 101
+#define IMX6SL_CLK_EXTERN_AUDIO 102
+#define IMX6SL_CLK_GPT 103
+#define IMX6SL_CLK_GPT_SERIAL 104
+#define IMX6SL_CLK_GPU2D_OVG 105
+#define IMX6SL_CLK_I2C1 106
+#define IMX6SL_CLK_I2C2 107
+#define IMX6SL_CLK_I2C3 108
+#define IMX6SL_CLK_OCOTP 109
+#define IMX6SL_CLK_CSI 110
+#define IMX6SL_CLK_PXP_AXI 111
+#define IMX6SL_CLK_EPDC_AXI 112
+#define IMX6SL_CLK_LCDIF_AXI 113
+#define IMX6SL_CLK_LCDIF_PIX 114
+#define IMX6SL_CLK_EPDC_PIX 115
+#define IMX6SL_CLK_OCRAM 116
+#define IMX6SL_CLK_PWM1 117
+#define IMX6SL_CLK_PWM2 118
+#define IMX6SL_CLK_PWM3 119
+#define IMX6SL_CLK_PWM4 120
+#define IMX6SL_CLK_SDMA 121
+#define IMX6SL_CLK_SPDIF 122
+#define IMX6SL_CLK_SSI1 123
+#define IMX6SL_CLK_SSI2 124
+#define IMX6SL_CLK_SSI3 125
+#define IMX6SL_CLK_UART 126
+#define IMX6SL_CLK_UART_SERIAL 127
+#define IMX6SL_CLK_USBOH3 128
+#define IMX6SL_CLK_USDHC1 129
+#define IMX6SL_CLK_USDHC2 130
+#define IMX6SL_CLK_USDHC3 131
+#define IMX6SL_CLK_USDHC4 132
+#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
+#define IMX6SL_CLK_SPBA 134
+#define IMX6SL_CLK_ENET 135
+#define IMX6SL_CLK_LVDS1_SEL 136
+#define IMX6SL_CLK_LVDS1_OUT 137
+#define IMX6SL_CLK_LVDS1_IN 138
+#define IMX6SL_CLK_ANACLK1 139
+#define IMX6SL_PLL1_BYPASS_SRC 140
+#define IMX6SL_PLL2_BYPASS_SRC 141
+#define IMX6SL_PLL3_BYPASS_SRC 142
+#define IMX6SL_PLL4_BYPASS_SRC 143
+#define IMX6SL_PLL5_BYPASS_SRC 144
+#define IMX6SL_PLL6_BYPASS_SRC 145
+#define IMX6SL_PLL7_BYPASS_SRC 146
+#define IMX6SL_CLK_PLL1 147
+#define IMX6SL_CLK_PLL2 148
+#define IMX6SL_CLK_PLL3 149
+#define IMX6SL_CLK_PLL4 150
+#define IMX6SL_CLK_PLL5 151
+#define IMX6SL_CLK_PLL6 152
+#define IMX6SL_CLK_PLL7 153
+#define IMX6SL_PLL1_BYPASS 154
+#define IMX6SL_PLL2_BYPASS 155
+#define IMX6SL_PLL3_BYPASS 156
+#define IMX6SL_PLL4_BYPASS 157
+#define IMX6SL_PLL5_BYPASS 158
+#define IMX6SL_PLL6_BYPASS 159
+#define IMX6SL_PLL7_BYPASS 160
+#define IMX6SL_CLK_SSI1_IPG 161
+#define IMX6SL_CLK_SSI2_IPG 162
+#define IMX6SL_CLK_SSI3_IPG 163
+#define IMX6SL_CLK_END 164
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
new file mode 100644
index 000000000..995709119
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
+#define __DT_BINDINGS_CLOCK_IMX6SX_H
+
+#define IMX6SX_CLK_DUMMY 0
+#define IMX6SX_CLK_CKIL 1
+#define IMX6SX_CLK_CKIH 2
+#define IMX6SX_CLK_OSC 3
+#define IMX6SX_CLK_PLL1_SYS 4
+#define IMX6SX_CLK_PLL2_BUS 5
+#define IMX6SX_CLK_PLL3_USB_OTG 6
+#define IMX6SX_CLK_PLL4_AUDIO 7
+#define IMX6SX_CLK_PLL5_VIDEO 8
+#define IMX6SX_CLK_PLL6_ENET 9
+#define IMX6SX_CLK_PLL7_USB_HOST 10
+#define IMX6SX_CLK_USBPHY1 11
+#define IMX6SX_CLK_USBPHY2 12
+#define IMX6SX_CLK_USBPHY1_GATE 13
+#define IMX6SX_CLK_USBPHY2_GATE 14
+#define IMX6SX_CLK_PCIE_REF 15
+#define IMX6SX_CLK_PCIE_REF_125M 16
+#define IMX6SX_CLK_ENET_REF 17
+#define IMX6SX_CLK_PLL2_PFD0 18
+#define IMX6SX_CLK_PLL2_PFD1 19
+#define IMX6SX_CLK_PLL2_PFD2 20
+#define IMX6SX_CLK_PLL2_PFD3 21
+#define IMX6SX_CLK_PLL3_PFD0 22
+#define IMX6SX_CLK_PLL3_PFD1 23
+#define IMX6SX_CLK_PLL3_PFD2 24
+#define IMX6SX_CLK_PLL3_PFD3 25
+#define IMX6SX_CLK_PLL2_198M 26
+#define IMX6SX_CLK_PLL3_120M 27
+#define IMX6SX_CLK_PLL3_80M 28
+#define IMX6SX_CLK_PLL3_60M 29
+#define IMX6SX_CLK_TWD 30
+#define IMX6SX_CLK_PLL4_POST_DIV 31
+#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
+#define IMX6SX_CLK_PLL5_POST_DIV 33
+#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
+#define IMX6SX_CLK_STEP 35
+#define IMX6SX_CLK_PLL1_SW 36
+#define IMX6SX_CLK_OCRAM_SEL 37
+#define IMX6SX_CLK_PERIPH_PRE 38
+#define IMX6SX_CLK_PERIPH2_PRE 39
+#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
+#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
+#define IMX6SX_CLK_PCIE_AXI_SEL 42
+#define IMX6SX_CLK_GPU_AXI_SEL 43
+#define IMX6SX_CLK_GPU_CORE_SEL 44
+#define IMX6SX_CLK_EIM_SLOW_SEL 45
+#define IMX6SX_CLK_USDHC1_SEL 46
+#define IMX6SX_CLK_USDHC2_SEL 47
+#define IMX6SX_CLK_USDHC3_SEL 48
+#define IMX6SX_CLK_USDHC4_SEL 49
+#define IMX6SX_CLK_SSI1_SEL 50
+#define IMX6SX_CLK_SSI2_SEL 51
+#define IMX6SX_CLK_SSI3_SEL 52
+#define IMX6SX_CLK_QSPI1_SEL 53
+#define IMX6SX_CLK_PERCLK_SEL 54
+#define IMX6SX_CLK_VID_SEL 55
+#define IMX6SX_CLK_ESAI_SEL 56
+#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
+#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
+#define IMX6SX_CLK_CAN_SEL 59
+#define IMX6SX_CLK_UART_SEL 60
+#define IMX6SX_CLK_QSPI2_SEL 61
+#define IMX6SX_CLK_LDB_DI1_SEL 62
+#define IMX6SX_CLK_LDB_DI0_SEL 63
+#define IMX6SX_CLK_SPDIF_SEL 64
+#define IMX6SX_CLK_AUDIO_SEL 65
+#define IMX6SX_CLK_ENET_PRE_SEL 66
+#define IMX6SX_CLK_ENET_SEL 67
+#define IMX6SX_CLK_M4_PRE_SEL 68
+#define IMX6SX_CLK_M4_SEL 69
+#define IMX6SX_CLK_ECSPI_SEL 70
+#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
+#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
+#define IMX6SX_CLK_LCDIF1_SEL 73
+#define IMX6SX_CLK_LCDIF2_SEL 74
+#define IMX6SX_CLK_DISPLAY_SEL 75
+#define IMX6SX_CLK_CSI_SEL 76
+#define IMX6SX_CLK_CKO1_SEL 77
+#define IMX6SX_CLK_CKO2_SEL 78
+#define IMX6SX_CLK_CKO 79
+#define IMX6SX_CLK_PERIPH_CLK2 80
+#define IMX6SX_CLK_PERIPH2_CLK2 81
+#define IMX6SX_CLK_IPG 82
+#define IMX6SX_CLK_GPU_CORE_PODF 83
+#define IMX6SX_CLK_GPU_AXI_PODF 84
+#define IMX6SX_CLK_LCDIF1_PODF 85
+#define IMX6SX_CLK_QSPI1_PODF 86
+#define IMX6SX_CLK_EIM_SLOW_PODF 87
+#define IMX6SX_CLK_LCDIF2_PODF 88
+#define IMX6SX_CLK_PERCLK 89
+#define IMX6SX_CLK_VID_PODF 90
+#define IMX6SX_CLK_CAN_PODF 91
+#define IMX6SX_CLK_USDHC1_PODF 92
+#define IMX6SX_CLK_USDHC2_PODF 93
+#define IMX6SX_CLK_USDHC3_PODF 94
+#define IMX6SX_CLK_USDHC4_PODF 95
+#define IMX6SX_CLK_UART_PODF 96
+#define IMX6SX_CLK_ESAI_PRED 97
+#define IMX6SX_CLK_ESAI_PODF 98
+#define IMX6SX_CLK_SSI3_PRED 99
+#define IMX6SX_CLK_SSI3_PODF 100
+#define IMX6SX_CLK_SSI1_PRED 101
+#define IMX6SX_CLK_SSI1_PODF 102
+#define IMX6SX_CLK_QSPI2_PRED 103
+#define IMX6SX_CLK_QSPI2_PODF 104
+#define IMX6SX_CLK_SSI2_PRED 105
+#define IMX6SX_CLK_SSI2_PODF 106
+#define IMX6SX_CLK_SPDIF_PRED 107
+#define IMX6SX_CLK_SPDIF_PODF 108
+#define IMX6SX_CLK_AUDIO_PRED 109
+#define IMX6SX_CLK_AUDIO_PODF 110
+#define IMX6SX_CLK_ENET_PODF 111
+#define IMX6SX_CLK_M4_PODF 112
+#define IMX6SX_CLK_ECSPI_PODF 113
+#define IMX6SX_CLK_LCDIF1_PRED 114
+#define IMX6SX_CLK_LCDIF2_PRED 115
+#define IMX6SX_CLK_DISPLAY_PODF 116
+#define IMX6SX_CLK_CSI_PODF 117
+#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
+#define IMX6SX_CLK_LDB_DI0_DIV_7 119
+#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
+#define IMX6SX_CLK_LDB_DI1_DIV_7 121
+#define IMX6SX_CLK_CKO1_PODF 122
+#define IMX6SX_CLK_CKO2_PODF 123
+#define IMX6SX_CLK_PERIPH 124
+#define IMX6SX_CLK_PERIPH2 125
+#define IMX6SX_CLK_OCRAM 126
+#define IMX6SX_CLK_AHB 127
+#define IMX6SX_CLK_MMDC_PODF 128
+#define IMX6SX_CLK_ARM 129
+#define IMX6SX_CLK_AIPS_TZ1 130
+#define IMX6SX_CLK_AIPS_TZ2 131
+#define IMX6SX_CLK_APBH_DMA 132
+#define IMX6SX_CLK_ASRC_GATE 133
+#define IMX6SX_CLK_CAAM_MEM 134
+#define IMX6SX_CLK_CAAM_ACLK 135
+#define IMX6SX_CLK_CAAM_IPG 136
+#define IMX6SX_CLK_CAN1_IPG 137
+#define IMX6SX_CLK_CAN1_SERIAL 138
+#define IMX6SX_CLK_CAN2_IPG 139
+#define IMX6SX_CLK_CAN2_SERIAL 140
+#define IMX6SX_CLK_CPU_DEBUG 141
+#define IMX6SX_CLK_DCIC1 142
+#define IMX6SX_CLK_DCIC2 143
+#define IMX6SX_CLK_AIPS_TZ3 144
+#define IMX6SX_CLK_ECSPI1 145
+#define IMX6SX_CLK_ECSPI2 146
+#define IMX6SX_CLK_ECSPI3 147
+#define IMX6SX_CLK_ECSPI4 148
+#define IMX6SX_CLK_ECSPI5 149
+#define IMX6SX_CLK_EPIT1 150
+#define IMX6SX_CLK_EPIT2 151
+#define IMX6SX_CLK_ESAI_EXTAL 152
+#define IMX6SX_CLK_WAKEUP 153
+#define IMX6SX_CLK_GPT_BUS 154
+#define IMX6SX_CLK_GPT_SERIAL 155
+#define IMX6SX_CLK_GPU 156
+#define IMX6SX_CLK_OCRAM_S 157
+#define IMX6SX_CLK_CANFD 158
+#define IMX6SX_CLK_CSI 159
+#define IMX6SX_CLK_I2C1 160
+#define IMX6SX_CLK_I2C2 161
+#define IMX6SX_CLK_I2C3 162
+#define IMX6SX_CLK_OCOTP 163
+#define IMX6SX_CLK_IOMUXC 164
+#define IMX6SX_CLK_IPMUX1 165
+#define IMX6SX_CLK_IPMUX2 166
+#define IMX6SX_CLK_IPMUX3 167
+#define IMX6SX_CLK_TZASC1 168
+#define IMX6SX_CLK_LCDIF_APB 169
+#define IMX6SX_CLK_PXP_AXI 170
+#define IMX6SX_CLK_M4 171
+#define IMX6SX_CLK_ENET 172
+#define IMX6SX_CLK_DISPLAY_AXI 173
+#define IMX6SX_CLK_LCDIF2_PIX 174
+#define IMX6SX_CLK_LCDIF1_PIX 175
+#define IMX6SX_CLK_LDB_DI0 176
+#define IMX6SX_CLK_QSPI1 177
+#define IMX6SX_CLK_MLB 178
+#define IMX6SX_CLK_MMDC_P0_FAST 179
+#define IMX6SX_CLK_MMDC_P0_IPG 180
+#define IMX6SX_CLK_AXI 181
+#define IMX6SX_CLK_PCIE_AXI 182
+#define IMX6SX_CLK_QSPI2 183
+#define IMX6SX_CLK_PER1_BCH 184
+#define IMX6SX_CLK_PER2_MAIN 185
+#define IMX6SX_CLK_PWM1 186
+#define IMX6SX_CLK_PWM2 187
+#define IMX6SX_CLK_PWM3 188
+#define IMX6SX_CLK_PWM4 189
+#define IMX6SX_CLK_GPMI_BCH_APB 190
+#define IMX6SX_CLK_GPMI_BCH 191
+#define IMX6SX_CLK_GPMI_IO 192
+#define IMX6SX_CLK_GPMI_APB 193
+#define IMX6SX_CLK_ROM 194
+#define IMX6SX_CLK_SDMA 195
+#define IMX6SX_CLK_SPBA 196
+#define IMX6SX_CLK_SPDIF 197
+#define IMX6SX_CLK_SSI1_IPG 198
+#define IMX6SX_CLK_SSI2_IPG 199
+#define IMX6SX_CLK_SSI3_IPG 200
+#define IMX6SX_CLK_SSI1 201
+#define IMX6SX_CLK_SSI2 202
+#define IMX6SX_CLK_SSI3 203
+#define IMX6SX_CLK_UART_IPG 204
+#define IMX6SX_CLK_UART_SERIAL 205
+#define IMX6SX_CLK_SAI1 206
+#define IMX6SX_CLK_SAI2 207
+#define IMX6SX_CLK_USBOH3 208
+#define IMX6SX_CLK_USDHC1 209
+#define IMX6SX_CLK_USDHC2 210
+#define IMX6SX_CLK_USDHC3 211
+#define IMX6SX_CLK_USDHC4 212
+#define IMX6SX_CLK_EIM_SLOW 213
+#define IMX6SX_CLK_PWM8 214
+#define IMX6SX_CLK_VADC 215
+#define IMX6SX_CLK_GIS 216
+#define IMX6SX_CLK_I2C4 217
+#define IMX6SX_CLK_PWM5 218
+#define IMX6SX_CLK_PWM6 219
+#define IMX6SX_CLK_PWM7 220
+#define IMX6SX_CLK_CKO1 221
+#define IMX6SX_CLK_CKO2 222
+#define IMX6SX_CLK_IPP_DI0 223
+#define IMX6SX_CLK_IPP_DI1 224
+#define IMX6SX_CLK_ENET_AHB 225
+#define IMX6SX_CLK_OCRAM_PODF 226
+#define IMX6SX_CLK_GPT_3M 227
+#define IMX6SX_CLK_ENET_PTP 228
+#define IMX6SX_CLK_ENET_PTP_REF 229
+#define IMX6SX_CLK_ENET2_REF 230
+#define IMX6SX_CLK_ENET2_REF_125M 231
+#define IMX6SX_CLK_AUDIO 232
+#define IMX6SX_CLK_LVDS1_SEL 233
+#define IMX6SX_CLK_LVDS1_OUT 234
+#define IMX6SX_CLK_ASRC_IPG 235
+#define IMX6SX_CLK_ASRC_MEM 236
+#define IMX6SX_CLK_SAI1_IPG 237
+#define IMX6SX_CLK_SAI2_IPG 238
+#define IMX6SX_CLK_ESAI_IPG 239
+#define IMX6SX_CLK_ESAI_MEM 240
+#define IMX6SX_CLK_LVDS1_IN 241
+#define IMX6SX_CLK_ANACLK1 242
+#define IMX6SX_PLL1_BYPASS_SRC 243
+#define IMX6SX_PLL2_BYPASS_SRC 244
+#define IMX6SX_PLL3_BYPASS_SRC 245
+#define IMX6SX_PLL4_BYPASS_SRC 246
+#define IMX6SX_PLL5_BYPASS_SRC 247
+#define IMX6SX_PLL6_BYPASS_SRC 248
+#define IMX6SX_PLL7_BYPASS_SRC 249
+#define IMX6SX_CLK_PLL1 250
+#define IMX6SX_CLK_PLL2 251
+#define IMX6SX_CLK_PLL3 252
+#define IMX6SX_CLK_PLL4 253
+#define IMX6SX_CLK_PLL5 254
+#define IMX6SX_CLK_PLL6 255
+#define IMX6SX_CLK_PLL7 256
+#define IMX6SX_PLL1_BYPASS 257
+#define IMX6SX_PLL2_BYPASS 258
+#define IMX6SX_PLL3_BYPASS 259
+#define IMX6SX_PLL4_BYPASS 260
+#define IMX6SX_PLL5_BYPASS 261
+#define IMX6SX_PLL6_BYPASS 262
+#define IMX6SX_PLL7_BYPASS 263
+#define IMX6SX_CLK_CLK_END 264
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
diff --git a/include/dt-bindings/clock/lsi,axm5516-clks.h b/include/dt-bindings/clock/lsi,axm5516-clks.h
new file mode 100644
index 000000000..beb41ace5
--- /dev/null
+++ b/include/dt-bindings/clock/lsi,axm5516-clks.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2014 LSI Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ */
+
+#ifndef _DT_BINDINGS_CLK_AXM5516_H
+#define _DT_BINDINGS_CLK_AXM5516_H
+
+#define AXXIA_CLK_FAB_PLL 0
+#define AXXIA_CLK_CPU_PLL 1
+#define AXXIA_CLK_SYS_PLL 2
+#define AXXIA_CLK_SM0_PLL 3
+#define AXXIA_CLK_SM1_PLL 4
+#define AXXIA_CLK_FAB_DIV 5
+#define AXXIA_CLK_SYS_DIV 6
+#define AXXIA_CLK_NRCP_DIV 7
+#define AXXIA_CLK_CPU0_DIV 8
+#define AXXIA_CLK_CPU1_DIV 9
+#define AXXIA_CLK_CPU2_DIV 10
+#define AXXIA_CLK_CPU3_DIV 11
+#define AXXIA_CLK_PER_DIV 12
+#define AXXIA_CLK_MMC_DIV 13
+#define AXXIA_CLK_FAB 14
+#define AXXIA_CLK_SYS 15
+#define AXXIA_CLK_NRCP 16
+#define AXXIA_CLK_CPU0 17
+#define AXXIA_CLK_CPU1 18
+#define AXXIA_CLK_CPU2 19
+#define AXXIA_CLK_CPU3 20
+#define AXXIA_CLK_PER 21
+#define AXXIA_CLK_MMC 22
+
+#endif
diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h
new file mode 100644
index 000000000..591f7fba8
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,mmp2.h
@@ -0,0 +1,74 @@
+#ifndef __DTS_MARVELL_MMP2_CLOCK_H
+#define __DTS_MARVELL_MMP2_CLOCK_H
+
+/* fixed clocks and plls */
+#define MMP2_CLK_CLK32 1
+#define MMP2_CLK_VCTCXO 2
+#define MMP2_CLK_PLL1 3
+#define MMP2_CLK_PLL1_2 8
+#define MMP2_CLK_PLL1_4 9
+#define MMP2_CLK_PLL1_8 10
+#define MMP2_CLK_PLL1_16 11
+#define MMP2_CLK_PLL1_3 12
+#define MMP2_CLK_PLL1_6 13
+#define MMP2_CLK_PLL1_12 14
+#define MMP2_CLK_PLL1_20 15
+#define MMP2_CLK_PLL2 16
+#define MMP2_CLK_PLL2_2 17
+#define MMP2_CLK_PLL2_4 18
+#define MMP2_CLK_PLL2_8 19
+#define MMP2_CLK_PLL2_16 20
+#define MMP2_CLK_PLL2_3 21
+#define MMP2_CLK_PLL2_6 22
+#define MMP2_CLK_PLL2_12 23
+#define MMP2_CLK_VCTCXO_2 24
+#define MMP2_CLK_VCTCXO_4 25
+#define MMP2_CLK_UART_PLL 26
+#define MMP2_CLK_USB_PLL 27
+
+/* apb periphrals */
+#define MMP2_CLK_TWSI0 60
+#define MMP2_CLK_TWSI1 61
+#define MMP2_CLK_TWSI2 62
+#define MMP2_CLK_TWSI3 63
+#define MMP2_CLK_TWSI4 64
+#define MMP2_CLK_TWSI5 65
+#define MMP2_CLK_GPIO 66
+#define MMP2_CLK_KPC 67
+#define MMP2_CLK_RTC 68
+#define MMP2_CLK_PWM0 69
+#define MMP2_CLK_PWM1 70
+#define MMP2_CLK_PWM2 71
+#define MMP2_CLK_PWM3 72
+#define MMP2_CLK_UART0 73
+#define MMP2_CLK_UART1 74
+#define MMP2_CLK_UART2 75
+#define MMP2_CLK_UART3 76
+#define MMP2_CLK_SSP0 77
+#define MMP2_CLK_SSP1 78
+#define MMP2_CLK_SSP2 79
+#define MMP2_CLK_SSP3 80
+
+/* axi periphrals */
+#define MMP2_CLK_SDH0 101
+#define MMP2_CLK_SDH1 102
+#define MMP2_CLK_SDH2 103
+#define MMP2_CLK_SDH3 104
+#define MMP2_CLK_USB 105
+#define MMP2_CLK_DISP0 106
+#define MMP2_CLK_DISP0_MUX 107
+#define MMP2_CLK_DISP0_SPHY 108
+#define MMP2_CLK_DISP1 109
+#define MMP2_CLK_DISP1_MUX 110
+#define MMP2_CLK_CCIC_ARBITER 111
+#define MMP2_CLK_CCIC0 112
+#define MMP2_CLK_CCIC0_MIX 113
+#define MMP2_CLK_CCIC0_PHY 114
+#define MMP2_CLK_CCIC0_SPHY 115
+#define MMP2_CLK_CCIC1 116
+#define MMP2_CLK_CCIC1_MIX 117
+#define MMP2_CLK_CCIC1_PHY 118
+#define MMP2_CLK_CCIC1_SPHY 119
+
+#define MMP2_NR_CLKS 200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h
new file mode 100644
index 000000000..79630b9d7
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa168.h
@@ -0,0 +1,57 @@
+#ifndef __DTS_MARVELL_PXA168_CLOCK_H
+#define __DTS_MARVELL_PXA168_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA168_CLK_CLK32 1
+#define PXA168_CLK_VCTCXO 2
+#define PXA168_CLK_PLL1 3
+#define PXA168_CLK_PLL1_2 8
+#define PXA168_CLK_PLL1_4 9
+#define PXA168_CLK_PLL1_8 10
+#define PXA168_CLK_PLL1_16 11
+#define PXA168_CLK_PLL1_6 12
+#define PXA168_CLK_PLL1_12 13
+#define PXA168_CLK_PLL1_24 14
+#define PXA168_CLK_PLL1_48 15
+#define PXA168_CLK_PLL1_96 16
+#define PXA168_CLK_PLL1_13 17
+#define PXA168_CLK_PLL1_13_1_5 18
+#define PXA168_CLK_PLL1_2_1_5 19
+#define PXA168_CLK_PLL1_3_16 20
+#define PXA168_CLK_UART_PLL 27
+
+/* apb periphrals */
+#define PXA168_CLK_TWSI0 60
+#define PXA168_CLK_TWSI1 61
+#define PXA168_CLK_TWSI2 62
+#define PXA168_CLK_TWSI3 63
+#define PXA168_CLK_GPIO 64
+#define PXA168_CLK_KPC 65
+#define PXA168_CLK_RTC 66
+#define PXA168_CLK_PWM0 67
+#define PXA168_CLK_PWM1 68
+#define PXA168_CLK_PWM2 69
+#define PXA168_CLK_PWM3 70
+#define PXA168_CLK_UART0 71
+#define PXA168_CLK_UART1 72
+#define PXA168_CLK_UART2 73
+#define PXA168_CLK_SSP0 74
+#define PXA168_CLK_SSP1 75
+#define PXA168_CLK_SSP2 76
+#define PXA168_CLK_SSP3 77
+#define PXA168_CLK_SSP4 78
+
+/* axi periphrals */
+#define PXA168_CLK_DFC 100
+#define PXA168_CLK_SDH0 101
+#define PXA168_CLK_SDH1 102
+#define PXA168_CLK_SDH2 103
+#define PXA168_CLK_USB 104
+#define PXA168_CLK_SPH 105
+#define PXA168_CLK_DISP0 106
+#define PXA168_CLK_CCIC0 107
+#define PXA168_CLK_CCIC0_PHY 108
+#define PXA168_CLK_CCIC0_SPHY 109
+
+#define PXA168_NR_CLKS 200
+#endif
diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h
new file mode 100644
index 000000000..719cffb2b
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa910.h
@@ -0,0 +1,54 @@
+#ifndef __DTS_MARVELL_PXA910_CLOCK_H
+#define __DTS_MARVELL_PXA910_CLOCK_H
+
+/* fixed clocks and plls */
+#define PXA910_CLK_CLK32 1
+#define PXA910_CLK_VCTCXO 2
+#define PXA910_CLK_PLL1 3
+#define PXA910_CLK_PLL1_2 8
+#define PXA910_CLK_PLL1_4 9
+#define PXA910_CLK_PLL1_8 10
+#define PXA910_CLK_PLL1_16 11
+#define PXA910_CLK_PLL1_6 12
+#define PXA910_CLK_PLL1_12 13
+#define PXA910_CLK_PLL1_24 14
+#define PXA910_CLK_PLL1_48 15
+#define PXA910_CLK_PLL1_96 16
+#define PXA910_CLK_PLL1_13 17
+#define PXA910_CLK_PLL1_13_1_5 18
+#define PXA910_CLK_PLL1_2_1_5 19
+#define PXA910_CLK_PLL1_3_16 20
+#define PXA910_CLK_UART_PLL 27
+
+/* apb periphrals */
+#define PXA910_CLK_TWSI0 60
+#define PXA910_CLK_TWSI1 61
+#define PXA910_CLK_TWSI2 62
+#define PXA910_CLK_TWSI3 63
+#define PXA910_CLK_GPIO 64
+#define PXA910_CLK_KPC 65
+#define PXA910_CLK_RTC 66
+#define PXA910_CLK_PWM0 67
+#define PXA910_CLK_PWM1 68
+#define PXA910_CLK_PWM2 69
+#define PXA910_CLK_PWM3 70
+#define PXA910_CLK_UART0 71
+#define PXA910_CLK_UART1 72
+#define PXA910_CLK_UART2 73
+#define PXA910_CLK_SSP0 74
+#define PXA910_CLK_SSP1 75
+
+/* axi periphrals */
+#define PXA910_CLK_DFC 100
+#define PXA910_CLK_SDH0 101
+#define PXA910_CLK_SDH1 102
+#define PXA910_CLK_SDH2 103
+#define PXA910_CLK_USB 104
+#define PXA910_CLK_SPH 105
+#define PXA910_CLK_DISP0 106
+#define PXA910_CLK_CCIC0 107
+#define PXA910_CLK_CCIC0_PHY 108
+#define PXA910_CLK_CCIC0_SPHY 109
+
+#define PXA910_NR_CLKS 200
+#endif
diff --git a/include/dt-bindings/clock/maxim,max77686.h b/include/dt-bindings/clock/maxim,max77686.h
new file mode 100644
index 000000000..7b28b0905
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77686.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77686 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77686_CLK_AP 0
+#define MAX77686_CLK_CP 1
+#define MAX77686_CLK_PMIC 2
+
+/* Total number of clocks. */
+#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 000000000..997312edc
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP 0
+#define MAX77802_CLK_32K_CP 1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/clock/mpc512x-clock.h b/include/dt-bindings/clock/mpc512x-clock.h
new file mode 100644
index 000000000..4f9491932
--- /dev/null
+++ b/include/dt-bindings/clock/mpc512x-clock.h
@@ -0,0 +1,76 @@
+/*
+ * This header provides constants for MPC512x clock specs in DT bindings.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MPC512x_CLOCK_H
+
+#define MPC512x_CLK_DUMMY 0
+#define MPC512x_CLK_REF 1
+#define MPC512x_CLK_SYS 2
+#define MPC512x_CLK_DIU 3
+#define MPC512x_CLK_VIU 4
+#define MPC512x_CLK_CSB 5
+#define MPC512x_CLK_E300 6
+#define MPC512x_CLK_IPS 7
+#define MPC512x_CLK_FEC 8
+#define MPC512x_CLK_SATA 9
+#define MPC512x_CLK_PATA 10
+#define MPC512x_CLK_NFC 11
+#define MPC512x_CLK_LPC 12
+#define MPC512x_CLK_MBX_BUS 13
+#define MPC512x_CLK_MBX 14
+#define MPC512x_CLK_MBX_3D 15
+#define MPC512x_CLK_AXE 16
+#define MPC512x_CLK_USB1 17
+#define MPC512x_CLK_USB2 18
+#define MPC512x_CLK_I2C 19
+#define MPC512x_CLK_MSCAN0_MCLK 20
+#define MPC512x_CLK_MSCAN1_MCLK 21
+#define MPC512x_CLK_MSCAN2_MCLK 22
+#define MPC512x_CLK_MSCAN3_MCLK 23
+#define MPC512x_CLK_BDLC 24
+#define MPC512x_CLK_SDHC 25
+#define MPC512x_CLK_PCI 26
+#define MPC512x_CLK_PSC_MCLK_IN 27
+#define MPC512x_CLK_SPDIF_TX 28
+#define MPC512x_CLK_SPDIF_RX 29
+#define MPC512x_CLK_SPDIF_MCLK 30
+#define MPC512x_CLK_SPDIF 31
+#define MPC512x_CLK_AC97 32
+#define MPC512x_CLK_PSC0_MCLK 33
+#define MPC512x_CLK_PSC1_MCLK 34
+#define MPC512x_CLK_PSC2_MCLK 35
+#define MPC512x_CLK_PSC3_MCLK 36
+#define MPC512x_CLK_PSC4_MCLK 37
+#define MPC512x_CLK_PSC5_MCLK 38
+#define MPC512x_CLK_PSC6_MCLK 39
+#define MPC512x_CLK_PSC7_MCLK 40
+#define MPC512x_CLK_PSC8_MCLK 41
+#define MPC512x_CLK_PSC9_MCLK 42
+#define MPC512x_CLK_PSC10_MCLK 43
+#define MPC512x_CLK_PSC11_MCLK 44
+#define MPC512x_CLK_PSC_FIFO 45
+#define MPC512x_CLK_PSC0 46
+#define MPC512x_CLK_PSC1 47
+#define MPC512x_CLK_PSC2 48
+#define MPC512x_CLK_PSC3 49
+#define MPC512x_CLK_PSC4 50
+#define MPC512x_CLK_PSC5 51
+#define MPC512x_CLK_PSC6 52
+#define MPC512x_CLK_PSC7 53
+#define MPC512x_CLK_PSC8 54
+#define MPC512x_CLK_PSC9 55
+#define MPC512x_CLK_PSC10 56
+#define MPC512x_CLK_PSC11 57
+#define MPC512x_CLK_SDHC2 58
+#define MPC512x_CLK_FEC2 59
+#define MPC512x_CLK_OUT0_CLK 60
+#define MPC512x_CLK_OUT1_CLK 61
+#define MPC512x_CLK_OUT2_CLK 62
+#define MPC512x_CLK_OUT3_CLK 63
+#define MPC512x_CLK_CAN_CLK_IN 64
+
+#define MPC512x_CLK_LAST_PUBLIC 64
+
+#endif
diff --git a/include/dt-bindings/clock/pistachio-clk.h b/include/dt-bindings/clock/pistachio-clk.h
new file mode 100644
index 000000000..039f83fac
--- /dev/null
+++ b/include/dt-bindings/clock/pistachio-clk.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2014 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
+#define _DT_BINDINGS_CLOCK_PISTACHIO_H
+
+/* PLLs */
+#define CLK_MIPS_PLL 0
+#define CLK_AUDIO_PLL 1
+#define CLK_RPU_V_PLL 2
+#define CLK_RPU_L_PLL 3
+#define CLK_SYS_PLL 4
+#define CLK_WIFI_PLL 5
+#define CLK_BT_PLL 6
+
+/* Fixed-factor clocks */
+#define CLK_WIFI_DIV4 16
+#define CLK_WIFI_DIV8 17
+
+/* Gate clocks */
+#define CLK_MIPS 32
+#define CLK_AUDIO_IN 33
+#define CLK_AUDIO 34
+#define CLK_I2S 35
+#define CLK_SPDIF 36
+#define CLK_AUDIO_DAC 37
+#define CLK_RPU_V 38
+#define CLK_RPU_L 39
+#define CLK_RPU_SLEEP 40
+#define CLK_WIFI_PLL_GATE 41
+#define CLK_RPU_CORE 42
+#define CLK_WIFI_ADC 43
+#define CLK_WIFI_DAC 44
+#define CLK_USB_PHY 45
+#define CLK_ENET_IN 46
+#define CLK_ENET 47
+#define CLK_UART0 48
+#define CLK_UART1 49
+#define CLK_PERIPH_SYS 50
+#define CLK_SPI0 51
+#define CLK_SPI1 52
+#define CLK_EVENT_TIMER 53
+#define CLK_AUX_ADC_INTERNAL 54
+#define CLK_AUX_ADC 55
+#define CLK_SD_HOST 56
+#define CLK_BT 57
+#define CLK_BT_DIV4 58
+#define CLK_BT_DIV8 59
+#define CLK_BT_1MHZ 60
+
+/* Divider clocks */
+#define CLK_MIPS_INTERNAL_DIV 64
+#define CLK_MIPS_DIV 65
+#define CLK_AUDIO_DIV 66
+#define CLK_I2S_DIV 67
+#define CLK_SPDIF_DIV 68
+#define CLK_AUDIO_DAC_DIV 69
+#define CLK_RPU_V_DIV 70
+#define CLK_RPU_L_DIV 71
+#define CLK_RPU_SLEEP_DIV 72
+#define CLK_RPU_CORE_DIV 73
+#define CLK_USB_PHY_DIV 74
+#define CLK_ENET_DIV 75
+#define CLK_UART0_INTERNAL_DIV 76
+#define CLK_UART0_DIV 77
+#define CLK_UART1_INTERNAL_DIV 78
+#define CLK_UART1_DIV 79
+#define CLK_SYS_INTERNAL_DIV 80
+#define CLK_SPI0_INTERNAL_DIV 81
+#define CLK_SPI0_DIV 82
+#define CLK_SPI1_INTERNAL_DIV 83
+#define CLK_SPI1_DIV 84
+#define CLK_EVENT_TIMER_INTERNAL_DIV 85
+#define CLK_EVENT_TIMER_DIV 86
+#define CLK_AUX_ADC_INTERNAL_DIV 87
+#define CLK_AUX_ADC_DIV 88
+#define CLK_SD_HOST_DIV 89
+#define CLK_BT_DIV 90
+#define CLK_BT_DIV4_DIV 91
+#define CLK_BT_DIV8_DIV 92
+#define CLK_BT_1MHZ_INTERNAL_DIV 93
+#define CLK_BT_1MHZ_DIV 94
+
+/* Mux clocks */
+#define CLK_AUDIO_REF_MUX 96
+#define CLK_MIPS_PLL_MUX 97
+#define CLK_AUDIO_PLL_MUX 98
+#define CLK_AUDIO_MUX 99
+#define CLK_RPU_V_PLL_MUX 100
+#define CLK_RPU_L_PLL_MUX 101
+#define CLK_RPU_L_MUX 102
+#define CLK_WIFI_PLL_MUX 103
+#define CLK_WIFI_DIV4_MUX 104
+#define CLK_WIFI_DIV8_MUX 105
+#define CLK_RPU_CORE_MUX 106
+#define CLK_SYS_PLL_MUX 107
+#define CLK_ENET_MUX 108
+#define CLK_EVENT_TIMER_MUX 109
+#define CLK_SD_HOST_MUX 110
+#define CLK_BT_PLL_MUX 111
+#define CLK_DEBUG_MUX 112
+
+#define CLK_NR_CLKS 113
+
+/* Peripheral gate clocks */
+#define PERIPH_CLK_SYS 0
+#define PERIPH_CLK_SYS_BUS 1
+#define PERIPH_CLK_DDR 2
+#define PERIPH_CLK_ROM 3
+#define PERIPH_CLK_COUNTER_FAST 4
+#define PERIPH_CLK_COUNTER_SLOW 5
+#define PERIPH_CLK_IR 6
+#define PERIPH_CLK_WD 7
+#define PERIPH_CLK_PDM 8
+#define PERIPH_CLK_PWM 9
+#define PERIPH_CLK_I2C0 10
+#define PERIPH_CLK_I2C1 11
+#define PERIPH_CLK_I2C2 12
+#define PERIPH_CLK_I2C3 13
+
+/* Peripheral divider clocks */
+#define PERIPH_CLK_ROM_DIV 32
+#define PERIPH_CLK_COUNTER_FAST_DIV 33
+#define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34
+#define PERIPH_CLK_COUNTER_SLOW_DIV 35
+#define PERIPH_CLK_IR_PRE_DIV 36
+#define PERIPH_CLK_IR_DIV 37
+#define PERIPH_CLK_WD_PRE_DIV 38
+#define PERIPH_CLK_WD_DIV 39
+#define PERIPH_CLK_PDM_PRE_DIV 40
+#define PERIPH_CLK_PDM_DIV 41
+#define PERIPH_CLK_PWM_PRE_DIV 42
+#define PERIPH_CLK_PWM_DIV 43
+#define PERIPH_CLK_I2C0_PRE_DIV 44
+#define PERIPH_CLK_I2C0_DIV 45
+#define PERIPH_CLK_I2C1_PRE_DIV 46
+#define PERIPH_CLK_I2C1_DIV 47
+#define PERIPH_CLK_I2C2_PRE_DIV 48
+#define PERIPH_CLK_I2C2_DIV 49
+#define PERIPH_CLK_I2C3_PRE_DIV 50
+#define PERIPH_CLK_I2C3_DIV 51
+
+#define PERIPH_CLK_NR_CLKS 52
+
+/* System gate clocks */
+#define SYS_CLK_I2C0 0
+#define SYS_CLK_I2C1 1
+#define SYS_CLK_I2C2 2
+#define SYS_CLK_I2C3 3
+#define SYS_CLK_I2S_IN 4
+#define SYS_CLK_PAUD_OUT 5
+#define SYS_CLK_SPDIF_OUT 6
+#define SYS_CLK_SPI0_MASTER 7
+#define SYS_CLK_SPI0_SLAVE 8
+#define SYS_CLK_PWM 9
+#define SYS_CLK_UART0 10
+#define SYS_CLK_UART1 11
+#define SYS_CLK_SPI1 12
+#define SYS_CLK_MDC 13
+#define SYS_CLK_SD_HOST 14
+#define SYS_CLK_ENET 15
+#define SYS_CLK_IR 16
+#define SYS_CLK_WD 17
+#define SYS_CLK_TIMER 18
+#define SYS_CLK_I2S_OUT 24
+#define SYS_CLK_SPDIF_IN 25
+#define SYS_CLK_EVENT_TIMER 26
+#define SYS_CLK_HASH 27
+
+#define SYS_CLK_NR_CLKS 28
+
+/* Gates for external input clocks */
+#define EXT_CLK_AUDIO_IN 0
+#define EXT_CLK_ENET_IN 1
+
+#define EXT_CLK_NR_CLKS 2
+
+#endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h
new file mode 100644
index 000000000..e65803b1d
--- /dev/null
+++ b/include/dt-bindings/clock/pxa-clock.h
@@ -0,0 +1,77 @@
+/*
+ * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
+ * Copyright (C) 2014 Robert Jarzmik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
+#define __DT_BINDINGS_CLOCK_PXA2XX_H__
+
+#define CLK_NONE 0
+#define CLK_1WIRE 1
+#define CLK_AC97 2
+#define CLK_AC97CONF 3
+#define CLK_ASSP 4
+#define CLK_BOOT 5
+#define CLK_BTUART 6
+#define CLK_CAMERA 7
+#define CLK_CIR 8
+#define CLK_CORE 9
+#define CLK_DMC 10
+#define CLK_FFUART 11
+#define CLK_FICP 12
+#define CLK_GPIO 13
+#define CLK_HSIO2 14
+#define CLK_HWUART 15
+#define CLK_I2C 16
+#define CLK_I2S 17
+#define CLK_IM 18
+#define CLK_INC 19
+#define CLK_ISC 20
+#define CLK_KEYPAD 21
+#define CLK_LCD 22
+#define CLK_MEMC 23
+#define CLK_MEMSTK 24
+#define CLK_MINI_IM 25
+#define CLK_MINI_LCD 26
+#define CLK_MMC 27
+#define CLK_MMC1 28
+#define CLK_MMC2 29
+#define CLK_MMC3 30
+#define CLK_MSL 31
+#define CLK_MSL0 32
+#define CLK_MVED 33
+#define CLK_NAND 34
+#define CLK_NSSP 35
+#define CLK_OSTIMER 36
+#define CLK_PWM0 37
+#define CLK_PWM1 38
+#define CLK_PWM2 39
+#define CLK_PWM3 40
+#define CLK_PWRI2C 41
+#define CLK_PXA300_GCU 42
+#define CLK_PXA320_GCU 43
+#define CLK_SMC 44
+#define CLK_SSP 45
+#define CLK_SSP1 46
+#define CLK_SSP2 47
+#define CLK_SSP3 48
+#define CLK_SSP4 49
+#define CLK_STUART 50
+#define CLK_TOUCH 51
+#define CLK_TPM 52
+#define CLK_UDC 53
+#define CLK_USB 54
+#define CLK_USB2 55
+#define CLK_USBH 56
+#define CLK_USBHOST 57
+#define CLK_USIM 58
+#define CLK_USIM1 59
+#define CLK_USMI0 60
+#define CLK_MAX 61
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
new file mode 100644
index 000000000..2c0da566c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define GPLL1 2
+#define GPLL1_VOTE 3
+#define GPLL2 4
+#define GPLL2_VOTE 5
+#define GPLL3 6
+#define GPLL3_VOTE 7
+#define GPLL4 8
+#define GPLL4_VOTE 9
+#define CONFIG_NOC_CLK_SRC 10
+#define PERIPH_NOC_CLK_SRC 11
+#define SYSTEM_NOC_CLK_SRC 12
+#define BLSP_UART_SIM_CLK_SRC 13
+#define QDSS_TSCTR_CLK_SRC 14
+#define UFS_AXI_CLK_SRC 15
+#define RPM_CLK_SRC 16
+#define KPSS_AHB_CLK_SRC 17
+#define QDSS_AT_CLK_SRC 18
+#define BIMC_DDR_CLK_SRC 19
+#define USB30_MASTER_CLK_SRC 20
+#define USB30_SEC_MASTER_CLK_SRC 21
+#define USB_HSIC_AHB_CLK_SRC 22
+#define MMSS_BIMC_GFX_CLK_SRC 23
+#define QDSS_STM_CLK_SRC 24
+#define ACC_CLK_SRC 25
+#define SEC_CTRL_CLK_SRC 26
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38
+#define BLSP1_UART1_APPS_CLK_SRC 39
+#define BLSP1_UART2_APPS_CLK_SRC 40
+#define BLSP1_UART3_APPS_CLK_SRC 41
+#define BLSP1_UART4_APPS_CLK_SRC 42
+#define BLSP1_UART5_APPS_CLK_SRC 43
+#define BLSP1_UART6_APPS_CLK_SRC 44
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56
+#define BLSP2_UART1_APPS_CLK_SRC 57
+#define BLSP2_UART2_APPS_CLK_SRC 58
+#define BLSP2_UART3_APPS_CLK_SRC 59
+#define BLSP2_UART4_APPS_CLK_SRC 60
+#define BLSP2_UART5_APPS_CLK_SRC 61
+#define BLSP2_UART6_APPS_CLK_SRC 62
+#define CE1_CLK_SRC 63
+#define CE2_CLK_SRC 64
+#define CE3_CLK_SRC 65
+#define GP1_CLK_SRC 66
+#define GP2_CLK_SRC 67
+#define GP3_CLK_SRC 68
+#define PDM2_CLK_SRC 69
+#define QDSS_TRACECLKIN_CLK_SRC 70
+#define RBCPR_CLK_SRC 71
+#define SATA_ASIC0_CLK_SRC 72
+#define SATA_PMALIVE_CLK_SRC 73
+#define SATA_RX_CLK_SRC 74
+#define SATA_RX_OOB_CLK_SRC 75
+#define SDCC1_APPS_CLK_SRC 76
+#define SDCC2_APPS_CLK_SRC 77
+#define SDCC3_APPS_CLK_SRC 78
+#define SDCC4_APPS_CLK_SRC 79
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80
+#define SPMI_AHB_CLK_SRC 81
+#define SPMI_SER_CLK_SRC 82
+#define TSIF_REF_CLK_SRC 83
+#define USB30_MOCK_UTMI_CLK_SRC 84
+#define USB30_SEC_MOCK_UTMI_CLK_SRC 85
+#define USB_HS_SYSTEM_CLK_SRC 86
+#define USB_HSIC_CLK_SRC 87
+#define USB_HSIC_IO_CAL_CLK_SRC 88
+#define USB_HSIC_MOCK_UTMI_CLK_SRC 89
+#define USB_HSIC_SYSTEM_CLK_SRC 90
+#define GCC_BAM_DMA_AHB_CLK 91
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92
+#define DDR_CLK_SRC 93
+#define GCC_BIMC_CFG_AHB_CLK 94
+#define GCC_BIMC_CLK 95
+#define GCC_BIMC_KPSS_AXI_CLK 96
+#define GCC_BIMC_SLEEP_CLK 97
+#define GCC_BIMC_SYSNOC_AXI_CLK 98
+#define GCC_BIMC_XO_CLK 99
+#define GCC_BLSP1_AHB_CLK 100
+#define GCC_BLSP1_SLEEP_CLK 101
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113
+#define GCC_BLSP1_UART1_APPS_CLK 114
+#define GCC_BLSP1_UART1_SIM_CLK 115
+#define GCC_BLSP1_UART2_APPS_CLK 116
+#define GCC_BLSP1_UART2_SIM_CLK 117
+#define GCC_BLSP1_UART3_APPS_CLK 118
+#define GCC_BLSP1_UART3_SIM_CLK 119
+#define GCC_BLSP1_UART4_APPS_CLK 120
+#define GCC_BLSP1_UART4_SIM_CLK 121
+#define GCC_BLSP1_UART5_APPS_CLK 122
+#define GCC_BLSP1_UART5_SIM_CLK 123
+#define GCC_BLSP1_UART6_APPS_CLK 124
+#define GCC_BLSP1_UART6_SIM_CLK 125
+#define GCC_BLSP2_AHB_CLK 126
+#define GCC_BLSP2_SLEEP_CLK 127
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139
+#define GCC_BLSP2_UART1_APPS_CLK 140
+#define GCC_BLSP2_UART1_SIM_CLK 141
+#define GCC_BLSP2_UART2_APPS_CLK 142
+#define GCC_BLSP2_UART2_SIM_CLK 143
+#define GCC_BLSP2_UART3_APPS_CLK 144
+#define GCC_BLSP2_UART3_SIM_CLK 145
+#define GCC_BLSP2_UART4_APPS_CLK 146
+#define GCC_BLSP2_UART4_SIM_CLK 147
+#define GCC_BLSP2_UART5_APPS_CLK 148
+#define GCC_BLSP2_UART5_SIM_CLK 149
+#define GCC_BLSP2_UART6_APPS_CLK 150
+#define GCC_BLSP2_UART6_SIM_CLK 151
+#define GCC_BOOT_ROM_AHB_CLK 152
+#define GCC_CE1_AHB_CLK 153
+#define GCC_CE1_AXI_CLK 154
+#define GCC_CE1_CLK 155
+#define GCC_CE2_AHB_CLK 156
+#define GCC_CE2_AXI_CLK 157
+#define GCC_CE2_CLK 158
+#define GCC_CE3_AHB_CLK 159
+#define GCC_CE3_AXI_CLK 160
+#define GCC_CE3_CLK 161
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168
+#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169
+#define GCC_CFG_NOC_AHB_CLK 170
+#define GCC_CFG_NOC_DDR_CFG_CLK 171
+#define GCC_CFG_NOC_RPM_AHB_CLK 172
+#define GCC_COPSS_SMMU_AHB_CLK 173
+#define GCC_COPSS_SMMU_AXI_CLK 174
+#define GCC_DCD_XO_CLK 175
+#define GCC_BIMC_DDR_CH0_CLK 176
+#define GCC_BIMC_DDR_CH1_CLK 177
+#define GCC_BIMC_DDR_CPLL0_CLK 178
+#define GCC_BIMC_DDR_CPLL1_CLK 179
+#define GCC_BIMC_GFX_CLK 180
+#define GCC_DDR_DIM_CFG_CLK 181
+#define GCC_DDR_DIM_SLEEP_CLK 182
+#define GCC_DEHR_CLK 183
+#define GCC_AHB_CLK 184
+#define GCC_IM_SLEEP_CLK 185
+#define GCC_XO_CLK 186
+#define GCC_XO_DIV4_CLK 187
+#define GCC_GP1_CLK 188
+#define GCC_GP2_CLK 189
+#define GCC_GP3_CLK 190
+#define GCC_IMEM_AXI_CLK 191
+#define GCC_IMEM_CFG_AHB_CLK 192
+#define GCC_KPSS_AHB_CLK 193
+#define GCC_KPSS_AXI_CLK 194
+#define GCC_LPASS_MPORT_AXI_CLK 195
+#define GCC_LPASS_Q6_AXI_CLK 196
+#define GCC_LPASS_SWAY_CLK 197
+#define GCC_MMSS_BIMC_GFX_CLK 198
+#define GCC_MMSS_NOC_AT_CLK 199
+#define GCC_MMSS_NOC_CFG_AHB_CLK 200
+#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201
+#define GCC_OCMEM_NOC_CFG_AHB_CLK 202
+#define GCC_OCMEM_SYS_NOC_AXI_CLK 203
+#define GCC_MPM_AHB_CLK 204
+#define GCC_MSG_RAM_AHB_CLK 205
+#define GCC_NOC_CONF_XPU_AHB_CLK 206
+#define GCC_PDM2_CLK 207
+#define GCC_PDM_AHB_CLK 208
+#define GCC_PDM_XO4_CLK 209
+#define GCC_PERIPH_NOC_AHB_CLK 210
+#define GCC_PERIPH_NOC_AT_CLK 211
+#define GCC_PERIPH_NOC_CFG_AHB_CLK 212
+#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214
+#define GCC_PERIPH_XPU_AHB_CLK 215
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220
+#define GCC_PRNG_AHB_CLK 221
+#define GCC_QDSS_AT_CLK 222
+#define GCC_QDSS_CFG_AHB_CLK 223
+#define GCC_QDSS_DAP_AHB_CLK 224
+#define GCC_QDSS_DAP_CLK 225
+#define GCC_QDSS_ETR_USB_CLK 226
+#define GCC_QDSS_STM_CLK 227
+#define GCC_QDSS_TRACECLKIN_CLK 228
+#define GCC_QDSS_TSCTR_DIV16_CLK 229
+#define GCC_QDSS_TSCTR_DIV2_CLK 230
+#define GCC_QDSS_TSCTR_DIV3_CLK 231
+#define GCC_QDSS_TSCTR_DIV4_CLK 232
+#define GCC_QDSS_TSCTR_DIV8_CLK 233
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234
+#define GCC_RBCPR_AHB_CLK 235
+#define GCC_RBCPR_CLK 236
+#define GCC_RPM_BUS_AHB_CLK 237
+#define GCC_RPM_PROC_HCLK 238
+#define GCC_RPM_SLEEP_CLK 239
+#define GCC_RPM_TIMER_CLK 240
+#define GCC_SATA_ASIC0_CLK 241
+#define GCC_SATA_AXI_CLK 242
+#define GCC_SATA_CFG_AHB_CLK 243
+#define GCC_SATA_PMALIVE_CLK 244
+#define GCC_SATA_RX_CLK 245
+#define GCC_SATA_RX_OOB_CLK 246
+#define GCC_SDCC1_AHB_CLK 247
+#define GCC_SDCC1_APPS_CLK 248
+#define GCC_SDCC1_CDCCAL_FF_CLK 249
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
+#define GCC_SDCC2_AHB_CLK 251
+#define GCC_SDCC2_APPS_CLK 252
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253
+#define GCC_SDCC3_AHB_CLK 254
+#define GCC_SDCC3_APPS_CLK 255
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256
+#define GCC_SDCC4_AHB_CLK 257
+#define GCC_SDCC4_APPS_CLK 258
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
+#define GCC_SEC_CTRL_ACC_CLK 260
+#define GCC_SEC_CTRL_AHB_CLK 261
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262
+#define GCC_SEC_CTRL_CLK 263
+#define GCC_SEC_CTRL_SENSE_CLK 264
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265
+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266
+#define GCC_SPDM_BIMC_CY_CLK 267
+#define GCC_SPDM_CFG_AHB_CLK 268
+#define GCC_SPDM_DEBUG_CY_CLK 269
+#define GCC_SPDM_FF_CLK 270
+#define GCC_SPDM_MSTR_AHB_CLK 271
+#define GCC_SPDM_PNOC_CY_CLK 272
+#define GCC_SPDM_RPM_CY_CLK 273
+#define GCC_SPDM_SNOC_CY_CLK 274
+#define GCC_SPMI_AHB_CLK 275
+#define GCC_SPMI_CNOC_AHB_CLK 276
+#define GCC_SPMI_SER_CLK 277
+#define GCC_SPSS_AHB_CLK 278
+#define GCC_SNOC_CNOC_AHB_CLK 279
+#define GCC_SNOC_PNOC_AHB_CLK 280
+#define GCC_SYS_NOC_AT_CLK 281
+#define GCC_SYS_NOC_AXI_CLK 282
+#define GCC_SYS_NOC_KPSS_AHB_CLK 283
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284
+#define GCC_SYS_NOC_UFS_AXI_CLK 285
+#define GCC_SYS_NOC_USB3_AXI_CLK 286
+#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287
+#define GCC_TCSR_AHB_CLK 288
+#define GCC_TLMM_AHB_CLK 289
+#define GCC_TLMM_CLK 290
+#define GCC_TSIF_AHB_CLK 291
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292
+#define GCC_TSIF_REF_CLK 293
+#define GCC_UFS_AHB_CLK 294
+#define GCC_UFS_AXI_CLK 295
+#define GCC_UFS_RX_CFG_CLK 296
+#define GCC_UFS_RX_SYMBOL_0_CLK 297
+#define GCC_UFS_RX_SYMBOL_1_CLK 298
+#define GCC_UFS_TX_CFG_CLK 299
+#define GCC_UFS_TX_SYMBOL_0_CLK 300
+#define GCC_UFS_TX_SYMBOL_1_CLK 301
+#define GCC_USB2A_PHY_SLEEP_CLK 302
+#define GCC_USB2B_PHY_SLEEP_CLK 303
+#define GCC_USB30_MASTER_CLK 304
+#define GCC_USB30_MOCK_UTMI_CLK 305
+#define GCC_USB30_SLEEP_CLK 306
+#define GCC_USB30_SEC_MASTER_CLK 307
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 308
+#define GCC_USB30_SEC_SLEEP_CLK 309
+#define GCC_USB_HS_AHB_CLK 310
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311
+#define GCC_USB_HS_SYSTEM_CLK 312
+#define GCC_USB_HSIC_AHB_CLK 313
+#define GCC_USB_HSIC_CLK 314
+#define GCC_USB_HSIC_IO_CAL_CLK 315
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
+#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
+#define GCC_USB_HSIC_SYSTEM_CLK 318
+#define PCIE_0_AUX_CLK_SRC 319
+#define PCIE_0_PIPE_CLK_SRC 320
+#define PCIE_1_AUX_CLK_SRC 321
+#define PCIE_1_PIPE_CLK_SRC 322
+#define GCC_PCIE_0_AUX_CLK 323
+#define GCC_PCIE_0_CFG_AHB_CLK 324
+#define GCC_PCIE_0_MSTR_AXI_CLK 325
+#define GCC_PCIE_0_PIPE_CLK 326
+#define GCC_PCIE_0_SLV_AXI_CLK 327
+#define GCC_PCIE_1_AUX_CLK 328
+#define GCC_PCIE_1_CFG_AHB_CLK 329
+#define GCC_PCIE_1_MSTR_AXI_CLK 330
+#define GCC_PCIE_1_PIPE_CLK 331
+#define GCC_PCIE_1_SLV_AXI_CLK 332
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000..ebd63fd05
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -0,0 +1,293 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
+
+#define AFAB_CLK_SRC 0
+#define QDSS_STM_CLK 1
+#define SCSS_A_CLK 2
+#define SCSS_H_CLK 3
+#define AFAB_CORE_CLK 4
+#define SCSS_XO_SRC_CLK 5
+#define AFAB_EBI1_CH0_A_CLK 6
+#define AFAB_EBI1_CH1_A_CLK 7
+#define AFAB_AXI_S0_FCLK 8
+#define AFAB_AXI_S1_FCLK 9
+#define AFAB_AXI_S2_FCLK 10
+#define AFAB_AXI_S3_FCLK 11
+#define AFAB_AXI_S4_FCLK 12
+#define SFAB_CORE_CLK 13
+#define SFAB_AXI_S0_FCLK 14
+#define SFAB_AXI_S1_FCLK 15
+#define SFAB_AXI_S2_FCLK 16
+#define SFAB_AXI_S3_FCLK 17
+#define SFAB_AXI_S4_FCLK 18
+#define SFAB_AXI_S5_FCLK 19
+#define SFAB_AHB_S0_FCLK 20
+#define SFAB_AHB_S1_FCLK 21
+#define SFAB_AHB_S2_FCLK 22
+#define SFAB_AHB_S3_FCLK 23
+#define SFAB_AHB_S4_FCLK 24
+#define SFAB_AHB_S5_FCLK 25
+#define SFAB_AHB_S6_FCLK 26
+#define SFAB_AHB_S7_FCLK 27
+#define QDSS_AT_CLK_SRC 28
+#define QDSS_AT_CLK 29
+#define QDSS_TRACECLKIN_CLK_SRC 30
+#define QDSS_TRACECLKIN_CLK 31
+#define QDSS_TSCTR_CLK_SRC 32
+#define QDSS_TSCTR_CLK 33
+#define SFAB_ADM0_M0_A_CLK 34
+#define SFAB_ADM0_M1_A_CLK 35
+#define SFAB_ADM0_M2_H_CLK 36
+#define ADM0_CLK 37
+#define ADM0_PBUS_CLK 38
+#define IMEM0_A_CLK 39
+#define QDSS_H_CLK 40
+#define PCIE_A_CLK 41
+#define PCIE_AUX_CLK 42
+#define PCIE_H_CLK 43
+#define PCIE_PHY_CLK 44
+#define SFAB_CLK_SRC 45
+#define SFAB_LPASS_Q6_A_CLK 46
+#define SFAB_AFAB_M_A_CLK 47
+#define AFAB_SFAB_M0_A_CLK 48
+#define AFAB_SFAB_M1_A_CLK 49
+#define SFAB_SATA_S_H_CLK 50
+#define DFAB_CLK_SRC 51
+#define DFAB_CLK 52
+#define SFAB_DFAB_M_A_CLK 53
+#define DFAB_SFAB_M_A_CLK 54
+#define DFAB_SWAY0_H_CLK 55
+#define DFAB_SWAY1_H_CLK 56
+#define DFAB_ARB0_H_CLK 57
+#define DFAB_ARB1_H_CLK 58
+#define PPSS_H_CLK 59
+#define PPSS_PROC_CLK 60
+#define PPSS_TIMER0_CLK 61
+#define PPSS_TIMER1_CLK 62
+#define PMEM_A_CLK 63
+#define DMA_BAM_H_CLK 64
+#define SIC_H_CLK 65
+#define SPS_TIC_H_CLK 66
+#define CFPB_2X_CLK_SRC 67
+#define CFPB_CLK 68
+#define CFPB0_H_CLK 69
+#define CFPB1_H_CLK 70
+#define CFPB2_H_CLK 71
+#define SFAB_CFPB_M_H_CLK 72
+#define CFPB_MASTER_H_CLK 73
+#define SFAB_CFPB_S_H_CLK 74
+#define CFPB_SPLITTER_H_CLK 75
+#define TSIF_H_CLK 76
+#define TSIF_INACTIVITY_TIMERS_CLK 77
+#define TSIF_REF_SRC 78
+#define TSIF_REF_CLK 79
+#define CE1_H_CLK 80
+#define CE1_CORE_CLK 81
+#define CE1_SLEEP_CLK 82
+#define CE2_H_CLK 83
+#define CE2_CORE_CLK 84
+#define SFPB_H_CLK_SRC 85
+#define SFPB_H_CLK 86
+#define SFAB_SFPB_M_H_CLK 87
+#define SFAB_SFPB_S_H_CLK 88
+#define RPM_PROC_CLK 89
+#define RPM_BUS_H_CLK 90
+#define RPM_SLEEP_CLK 91
+#define RPM_TIMER_CLK 92
+#define RPM_MSG_RAM_H_CLK 93
+#define PMIC_ARB0_H_CLK 94
+#define PMIC_ARB1_H_CLK 95
+#define PMIC_SSBI2_SRC 96
+#define PMIC_SSBI2_CLK 97
+#define SDC1_H_CLK 98
+#define SDC2_H_CLK 99
+#define SDC3_H_CLK 100
+#define SDC4_H_CLK 101
+#define SDC1_SRC 102
+#define SDC1_CLK 103
+#define SDC2_SRC 104
+#define SDC2_CLK 105
+#define SDC3_SRC 106
+#define SDC3_CLK 107
+#define SDC4_SRC 108
+#define SDC4_CLK 109
+#define USB_HS1_H_CLK 110
+#define USB_HS1_XCVR_SRC 111
+#define USB_HS1_XCVR_CLK 112
+#define USB_HSIC_H_CLK 113
+#define USB_HSIC_XCVR_SRC 114
+#define USB_HSIC_XCVR_CLK 115
+#define USB_HSIC_SYSTEM_CLK_SRC 116
+#define USB_HSIC_SYSTEM_CLK 117
+#define CFPB0_C0_H_CLK 118
+#define CFPB0_D0_H_CLK 119
+#define CFPB0_C1_H_CLK 120
+#define CFPB0_D1_H_CLK 121
+#define USB_FS1_H_CLK 122
+#define USB_FS1_XCVR_SRC 123
+#define USB_FS1_XCVR_CLK 124
+#define USB_FS1_SYSTEM_CLK 125
+#define GSBI_COMMON_SIM_SRC 126
+#define GSBI1_H_CLK 127
+#define GSBI2_H_CLK 128
+#define GSBI3_H_CLK 129
+#define GSBI4_H_CLK 130
+#define GSBI5_H_CLK 131
+#define GSBI6_H_CLK 132
+#define GSBI7_H_CLK 133
+#define GSBI1_QUP_SRC 134
+#define GSBI1_QUP_CLK 135
+#define GSBI2_QUP_SRC 136
+#define GSBI2_QUP_CLK 137
+#define GSBI3_QUP_SRC 138
+#define GSBI3_QUP_CLK 139
+#define GSBI4_QUP_SRC 140
+#define GSBI4_QUP_CLK 141
+#define GSBI5_QUP_SRC 142
+#define GSBI5_QUP_CLK 143
+#define GSBI6_QUP_SRC 144
+#define GSBI6_QUP_CLK 145
+#define GSBI7_QUP_SRC 146
+#define GSBI7_QUP_CLK 147
+#define GSBI1_UART_SRC 148
+#define GSBI1_UART_CLK 149
+#define GSBI2_UART_SRC 150
+#define GSBI2_UART_CLK 151
+#define GSBI3_UART_SRC 152
+#define GSBI3_UART_CLK 153
+#define GSBI4_UART_SRC 154
+#define GSBI4_UART_CLK 155
+#define GSBI5_UART_SRC 156
+#define GSBI5_UART_CLK 157
+#define GSBI6_UART_SRC 158
+#define GSBI6_UART_CLK 159
+#define GSBI7_UART_SRC 160
+#define GSBI7_UART_CLK 161
+#define GSBI1_SIM_CLK 162
+#define GSBI2_SIM_CLK 163
+#define GSBI3_SIM_CLK 164
+#define GSBI4_SIM_CLK 165
+#define GSBI5_SIM_CLK 166
+#define GSBI6_SIM_CLK 167
+#define GSBI7_SIM_CLK 168
+#define USB_HSIC_HSIC_CLK_SRC 169
+#define USB_HSIC_HSIC_CLK 170
+#define USB_HSIC_HSIO_CAL_CLK 171
+#define SPDM_CFG_H_CLK 172
+#define SPDM_MSTR_H_CLK 173
+#define SPDM_FF_CLK_SRC 174
+#define SPDM_FF_CLK 175
+#define SEC_CTRL_CLK 176
+#define SEC_CTRL_ACC_CLK_SRC 177
+#define SEC_CTRL_ACC_CLK 178
+#define TLMM_H_CLK 179
+#define TLMM_CLK 180
+#define SATA_H_CLK 181
+#define SATA_CLK_SRC 182
+#define SATA_RXOOB_CLK 183
+#define SATA_PMALIVE_CLK 184
+#define SATA_PHY_REF_CLK 185
+#define SATA_A_CLK 186
+#define SATA_PHY_CFG_CLK 187
+#define TSSC_CLK_SRC 188
+#define TSSC_CLK 189
+#define PDM_SRC 190
+#define PDM_CLK 191
+#define GP0_SRC 192
+#define GP0_CLK 193
+#define GP1_SRC 194
+#define GP1_CLK 195
+#define GP2_SRC 196
+#define GP2_CLK 197
+#define MPM_CLK 198
+#define EBI1_CLK_SRC 199
+#define EBI1_CH0_CLK 200
+#define EBI1_CH1_CLK 201
+#define EBI1_2X_CLK 202
+#define EBI1_CH0_DQ_CLK 203
+#define EBI1_CH1_DQ_CLK 204
+#define EBI1_CH0_CA_CLK 205
+#define EBI1_CH1_CA_CLK 206
+#define EBI1_XO_CLK 207
+#define SFAB_SMPSS_S_H_CLK 208
+#define PRNG_SRC 209
+#define PRNG_CLK 210
+#define PXO_SRC 211
+#define SPDM_CY_PORT0_CLK 212
+#define SPDM_CY_PORT1_CLK 213
+#define SPDM_CY_PORT2_CLK 214
+#define SPDM_CY_PORT3_CLK 215
+#define SPDM_CY_PORT4_CLK 216
+#define SPDM_CY_PORT5_CLK 217
+#define SPDM_CY_PORT6_CLK 218
+#define SPDM_CY_PORT7_CLK 219
+#define PLL0 220
+#define PLL0_VOTE 221
+#define PLL3 222
+#define PLL3_VOTE 223
+#define PLL4_VOTE 225
+#define PLL8 226
+#define PLL8_VOTE 227
+#define PLL9 228
+#define PLL10 229
+#define PLL11 230
+#define PLL12 231
+#define PLL14 232
+#define PLL14_VOTE 233
+#define PLL18 234
+#define CE5_SRC 235
+#define CE5_H_CLK 236
+#define CE5_CORE_CLK 237
+#define CE3_SLEEP_CLK 238
+#define SFAB_AHB_S8_FCLK 239
+#define SPDM_CY_PORT8_CLK 246
+#define PCIE_ALT_REF_SRC 247
+#define PCIE_ALT_REF_CLK 248
+#define PCIE_1_A_CLK 249
+#define PCIE_1_AUX_CLK 250
+#define PCIE_1_H_CLK 251
+#define PCIE_1_PHY_CLK 252
+#define PCIE_1_ALT_REF_SRC 253
+#define PCIE_1_ALT_REF_CLK 254
+#define PCIE_2_A_CLK 255
+#define PCIE_2_AUX_CLK 256
+#define PCIE_2_H_CLK 257
+#define PCIE_2_PHY_CLK 258
+#define PCIE_2_ALT_REF_SRC 259
+#define PCIE_2_ALT_REF_CLK 260
+#define EBI2_CLK 261
+#define USB30_SLEEP_CLK 262
+#define USB30_UTMI_SRC 263
+#define USB30_0_UTMI_CLK 264
+#define USB30_1_UTMI_CLK 265
+#define USB30_MASTER_SRC 266
+#define USB30_0_MASTER_CLK 267
+#define USB30_1_MASTER_CLK 268
+#define GMAC_CORE1_CLK_SRC 269
+#define GMAC_CORE2_CLK_SRC 270
+#define GMAC_CORE3_CLK_SRC 271
+#define GMAC_CORE4_CLK_SRC 272
+#define GMAC_CORE1_CLK 273
+#define GMAC_CORE2_CLK 274
+#define GMAC_CORE3_CLK 275
+#define GMAC_CORE4_CLK 276
+#define UBI32_CORE1_CLK_SRC 277
+#define UBI32_CORE2_CLK_SRC 278
+#define UBI32_CORE1_CLK 279
+#define UBI32_CORE2_CLK 280
+#define EBI2_AON_CLK 281
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8660.h b/include/dt-bindings/clock/qcom,gcc-msm8660.h
new file mode 100644
index 000000000..67665f681
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8660.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8660_H
+
+#define AFAB_CLK_SRC 0
+#define AFAB_CORE_CLK 1
+#define SCSS_A_CLK 2
+#define SCSS_H_CLK 3
+#define SCSS_XO_SRC_CLK 4
+#define AFAB_EBI1_CH0_A_CLK 5
+#define AFAB_EBI1_CH1_A_CLK 6
+#define AFAB_AXI_S0_FCLK 7
+#define AFAB_AXI_S1_FCLK 8
+#define AFAB_AXI_S2_FCLK 9
+#define AFAB_AXI_S3_FCLK 10
+#define AFAB_AXI_S4_FCLK 11
+#define SFAB_CORE_CLK 12
+#define SFAB_AXI_S0_FCLK 13
+#define SFAB_AXI_S1_FCLK 14
+#define SFAB_AXI_S2_FCLK 15
+#define SFAB_AXI_S3_FCLK 16
+#define SFAB_AXI_S4_FCLK 17
+#define SFAB_AHB_S0_FCLK 18
+#define SFAB_AHB_S1_FCLK 19
+#define SFAB_AHB_S2_FCLK 20
+#define SFAB_AHB_S3_FCLK 21
+#define SFAB_AHB_S4_FCLK 22
+#define SFAB_AHB_S5_FCLK 23
+#define SFAB_AHB_S6_FCLK 24
+#define SFAB_ADM0_M0_A_CLK 25
+#define SFAB_ADM0_M1_A_CLK 26
+#define SFAB_ADM0_M2_A_CLK 27
+#define ADM0_CLK 28
+#define ADM0_PBUS_CLK 29
+#define SFAB_ADM1_M0_A_CLK 30
+#define SFAB_ADM1_M1_A_CLK 31
+#define SFAB_ADM1_M2_A_CLK 32
+#define MMFAB_ADM1_M3_A_CLK 33
+#define ADM1_CLK 34
+#define ADM1_PBUS_CLK 35
+#define IMEM0_A_CLK 36
+#define MAHB0_CLK 37
+#define SFAB_LPASS_Q6_A_CLK 38
+#define SFAB_AFAB_M_A_CLK 39
+#define AFAB_SFAB_M0_A_CLK 40
+#define AFAB_SFAB_M1_A_CLK 41
+#define DFAB_CLK_SRC 42
+#define DFAB_CLK 43
+#define DFAB_CORE_CLK 44
+#define SFAB_DFAB_M_A_CLK 45
+#define DFAB_SFAB_M_A_CLK 46
+#define DFAB_SWAY0_H_CLK 47
+#define DFAB_SWAY1_H_CLK 48
+#define DFAB_ARB0_H_CLK 49
+#define DFAB_ARB1_H_CLK 50
+#define PPSS_H_CLK 51
+#define PPSS_PROC_CLK 52
+#define PPSS_TIMER0_CLK 53
+#define PPSS_TIMER1_CLK 54
+#define PMEM_A_CLK 55
+#define DMA_BAM_H_CLK 56
+#define SIC_H_CLK 57
+#define SPS_TIC_H_CLK 58
+#define SLIMBUS_H_CLK 59
+#define SLIMBUS_XO_SRC_CLK 60
+#define CFPB_2X_CLK_SRC 61
+#define CFPB_CLK 62
+#define CFPB0_H_CLK 63
+#define CFPB1_H_CLK 64
+#define CFPB2_H_CLK 65
+#define EBI2_2X_CLK 66
+#define EBI2_CLK 67
+#define SFAB_CFPB_M_H_CLK 68
+#define CFPB_MASTER_H_CLK 69
+#define SFAB_CFPB_S_HCLK 70
+#define CFPB_SPLITTER_H_CLK 71
+#define TSIF_H_CLK 72
+#define TSIF_INACTIVITY_TIMERS_CLK 73
+#define TSIF_REF_SRC 74
+#define TSIF_REF_CLK 75
+#define CE1_H_CLK 76
+#define CE2_H_CLK 77
+#define SFPB_H_CLK_SRC 78
+#define SFPB_H_CLK 79
+#define SFAB_SFPB_M_H_CLK 80
+#define SFAB_SFPB_S_H_CLK 81
+#define RPM_PROC_CLK 82
+#define RPM_BUS_H_CLK 83
+#define RPM_SLEEP_CLK 84
+#define RPM_TIMER_CLK 85
+#define MODEM_AHB1_H_CLK 86
+#define MODEM_AHB2_H_CLK 87
+#define RPM_MSG_RAM_H_CLK 88
+#define SC_H_CLK 89
+#define SC_A_CLK 90
+#define PMIC_ARB0_H_CLK 91
+#define PMIC_ARB1_H_CLK 92
+#define PMIC_SSBI2_SRC 93
+#define PMIC_SSBI2_CLK 94
+#define SDC1_H_CLK 95
+#define SDC2_H_CLK 96
+#define SDC3_H_CLK 97
+#define SDC4_H_CLK 98
+#define SDC5_H_CLK 99
+#define SDC1_SRC 100
+#define SDC2_SRC 101
+#define SDC3_SRC 102
+#define SDC4_SRC 103
+#define SDC5_SRC 104
+#define SDC1_CLK 105
+#define SDC2_CLK 106
+#define SDC3_CLK 107
+#define SDC4_CLK 108
+#define SDC5_CLK 109
+#define USB_HS1_H_CLK 110
+#define USB_HS1_XCVR_SRC 111
+#define USB_HS1_XCVR_CLK 112
+#define USB_HS2_H_CLK 113
+#define USB_HS2_XCVR_SRC 114
+#define USB_HS2_XCVR_CLK 115
+#define USB_FS1_H_CLK 116
+#define USB_FS1_XCVR_FS_SRC 117
+#define USB_FS1_XCVR_FS_CLK 118
+#define USB_FS1_SYSTEM_CLK 119
+#define USB_FS2_H_CLK 120
+#define USB_FS2_XCVR_FS_SRC 121
+#define USB_FS2_XCVR_FS_CLK 122
+#define USB_FS2_SYSTEM_CLK 123
+#define GSBI_COMMON_SIM_SRC 124
+#define GSBI1_H_CLK 125
+#define GSBI2_H_CLK 126
+#define GSBI3_H_CLK 127
+#define GSBI4_H_CLK 128
+#define GSBI5_H_CLK 129
+#define GSBI6_H_CLK 130
+#define GSBI7_H_CLK 131
+#define GSBI8_H_CLK 132
+#define GSBI9_H_CLK 133
+#define GSBI10_H_CLK 134
+#define GSBI11_H_CLK 135
+#define GSBI12_H_CLK 136
+#define GSBI1_UART_SRC 137
+#define GSBI1_UART_CLK 138
+#define GSBI2_UART_SRC 139
+#define GSBI2_UART_CLK 140
+#define GSBI3_UART_SRC 141
+#define GSBI3_UART_CLK 142
+#define GSBI4_UART_SRC 143
+#define GSBI4_UART_CLK 144
+#define GSBI5_UART_SRC 145
+#define GSBI5_UART_CLK 146
+#define GSBI6_UART_SRC 147
+#define GSBI6_UART_CLK 148
+#define GSBI7_UART_SRC 149
+#define GSBI7_UART_CLK 150
+#define GSBI8_UART_SRC 151
+#define GSBI8_UART_CLK 152
+#define GSBI9_UART_SRC 153
+#define GSBI9_UART_CLK 154
+#define GSBI10_UART_SRC 155
+#define GSBI10_UART_CLK 156
+#define GSBI11_UART_SRC 157
+#define GSBI11_UART_CLK 158
+#define GSBI12_UART_SRC 159
+#define GSBI12_UART_CLK 160
+#define GSBI1_QUP_SRC 161
+#define GSBI1_QUP_CLK 162
+#define GSBI2_QUP_SRC 163
+#define GSBI2_QUP_CLK 164
+#define GSBI3_QUP_SRC 165
+#define GSBI3_QUP_CLK 166
+#define GSBI4_QUP_SRC 167
+#define GSBI4_QUP_CLK 168
+#define GSBI5_QUP_SRC 169
+#define GSBI5_QUP_CLK 170
+#define GSBI6_QUP_SRC 171
+#define GSBI6_QUP_CLK 172
+#define GSBI7_QUP_SRC 173
+#define GSBI7_QUP_CLK 174
+#define GSBI8_QUP_SRC 175
+#define GSBI8_QUP_CLK 176
+#define GSBI9_QUP_SRC 177
+#define GSBI9_QUP_CLK 178
+#define GSBI10_QUP_SRC 179
+#define GSBI10_QUP_CLK 180
+#define GSBI11_QUP_SRC 181
+#define GSBI11_QUP_CLK 182
+#define GSBI12_QUP_SRC 183
+#define GSBI12_QUP_CLK 184
+#define GSBI1_SIM_CLK 185
+#define GSBI2_SIM_CLK 186
+#define GSBI3_SIM_CLK 187
+#define GSBI4_SIM_CLK 188
+#define GSBI5_SIM_CLK 189
+#define GSBI6_SIM_CLK 190
+#define GSBI7_SIM_CLK 191
+#define GSBI8_SIM_CLK 192
+#define GSBI9_SIM_CLK 193
+#define GSBI10_SIM_CLK 194
+#define GSBI11_SIM_CLK 195
+#define GSBI12_SIM_CLK 196
+#define SPDM_CFG_H_CLK 197
+#define SPDM_MSTR_H_CLK 198
+#define SPDM_FF_CLK_SRC 199
+#define SPDM_FF_CLK 200
+#define SEC_CTRL_CLK 201
+#define SEC_CTRL_ACC_CLK_SRC 202
+#define SEC_CTRL_ACC_CLK 203
+#define TLMM_H_CLK 204
+#define TLMM_CLK 205
+#define MARM_CLK_SRC 206
+#define MARM_CLK 207
+#define MAHB1_SRC 208
+#define MAHB1_CLK 209
+#define SFAB_MSS_S_H_CLK 210
+#define MAHB2_SRC 211
+#define MAHB2_CLK 212
+#define MSS_MODEM_CLK_SRC 213
+#define MSS_MODEM_CXO_CLK 214
+#define MSS_SLP_CLK 215
+#define MSS_SYS_REF_CLK 216
+#define TSSC_CLK_SRC 217
+#define TSSC_CLK 218
+#define PDM_SRC 219
+#define PDM_CLK 220
+#define GP0_SRC 221
+#define GP0_CLK 222
+#define GP1_SRC 223
+#define GP1_CLK 224
+#define GP2_SRC 225
+#define GP2_CLK 226
+#define PMEM_CLK 227
+#define MPM_CLK 228
+#define EBI1_ASFAB_SRC 229
+#define EBI1_CLK_SRC 230
+#define EBI1_CH0_CLK 231
+#define EBI1_CH1_CLK 232
+#define SFAB_SMPSS_S_H_CLK 233
+#define PRNG_SRC 234
+#define PRNG_CLK 235
+#define PXO_SRC 236
+#define LPASS_CXO_CLK 237
+#define LPASS_PXO_CLK 238
+#define SPDM_CY_PORT0_CLK 239
+#define SPDM_CY_PORT1_CLK 240
+#define SPDM_CY_PORT2_CLK 241
+#define SPDM_CY_PORT3_CLK 242
+#define SPDM_CY_PORT4_CLK 243
+#define SPDM_CY_PORT5_CLK 244
+#define SPDM_CY_PORT6_CLK 245
+#define SPDM_CY_PORT7_CLK 246
+#define PLL0 247
+#define PLL0_VOTE 248
+#define PLL5 249
+#define PLL6 250
+#define PLL6_VOTE 251
+#define PLL8 252
+#define PLL8_VOTE 253
+#define PLL9 254
+#define PLL10 255
+#define PLL11 256
+#define PLL12 257
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h
new file mode 100644
index 000000000..e430f644d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8916_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define BIMC_PLL 2
+#define BIMC_PLL_VOTE 3
+#define GPLL1 4
+#define GPLL1_VOTE 5
+#define GPLL2 6
+#define GPLL2_VOTE 7
+#define PCNOC_BFDCD_CLK_SRC 8
+#define SYSTEM_NOC_BFDCD_CLK_SRC 9
+#define CAMSS_AHB_CLK_SRC 10
+#define APSS_AHB_CLK_SRC 11
+#define CSI0_CLK_SRC 12
+#define CSI1_CLK_SRC 13
+#define GFX3D_CLK_SRC 14
+#define VFE0_CLK_SRC 15
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
+#define BLSP1_UART1_APPS_CLK_SRC 28
+#define BLSP1_UART2_APPS_CLK_SRC 29
+#define CCI_CLK_SRC 30
+#define CAMSS_GP0_CLK_SRC 31
+#define CAMSS_GP1_CLK_SRC 32
+#define JPEG0_CLK_SRC 33
+#define MCLK0_CLK_SRC 34
+#define MCLK1_CLK_SRC 35
+#define CSI0PHYTIMER_CLK_SRC 36
+#define CSI1PHYTIMER_CLK_SRC 37
+#define CPP_CLK_SRC 38
+#define CRYPTO_CLK_SRC 39
+#define GP1_CLK_SRC 40
+#define GP2_CLK_SRC 41
+#define GP3_CLK_SRC 42
+#define BYTE0_CLK_SRC 43
+#define ESC0_CLK_SRC 44
+#define MDP_CLK_SRC 45
+#define PCLK0_CLK_SRC 46
+#define VSYNC_CLK_SRC 47
+#define PDM2_CLK_SRC 48
+#define SDCC1_APPS_CLK_SRC 49
+#define SDCC2_APPS_CLK_SRC 50
+#define APSS_TCU_CLK_SRC 51
+#define USB_HS_SYSTEM_CLK_SRC 52
+#define VCODEC0_CLK_SRC 53
+#define GCC_BLSP1_AHB_CLK 54
+#define GCC_BLSP1_SLEEP_CLK 55
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
+#define GCC_BLSP1_UART1_APPS_CLK 68
+#define GCC_BLSP1_UART2_APPS_CLK 69
+#define GCC_BOOT_ROM_AHB_CLK 70
+#define GCC_CAMSS_CCI_AHB_CLK 71
+#define GCC_CAMSS_CCI_CLK 72
+#define GCC_CAMSS_CSI0_AHB_CLK 73
+#define GCC_CAMSS_CSI0_CLK 74
+#define GCC_CAMSS_CSI0PHY_CLK 75
+#define GCC_CAMSS_CSI0PIX_CLK 76
+#define GCC_CAMSS_CSI0RDI_CLK 77
+#define GCC_CAMSS_CSI1_AHB_CLK 78
+#define GCC_CAMSS_CSI1_CLK 79
+#define GCC_CAMSS_CSI1PHY_CLK 80
+#define GCC_CAMSS_CSI1PIX_CLK 81
+#define GCC_CAMSS_CSI1RDI_CLK 82
+#define GCC_CAMSS_CSI_VFE0_CLK 83
+#define GCC_CAMSS_GP0_CLK 84
+#define GCC_CAMSS_GP1_CLK 85
+#define GCC_CAMSS_ISPIF_AHB_CLK 86
+#define GCC_CAMSS_JPEG0_CLK 87
+#define GCC_CAMSS_JPEG_AHB_CLK 88
+#define GCC_CAMSS_JPEG_AXI_CLK 89
+#define GCC_CAMSS_MCLK0_CLK 90
+#define GCC_CAMSS_MCLK1_CLK 91
+#define GCC_CAMSS_MICRO_AHB_CLK 92
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
+#define GCC_CAMSS_AHB_CLK 95
+#define GCC_CAMSS_TOP_AHB_CLK 96
+#define GCC_CAMSS_CPP_AHB_CLK 97
+#define GCC_CAMSS_CPP_CLK 98
+#define GCC_CAMSS_VFE0_CLK 99
+#define GCC_CAMSS_VFE_AHB_CLK 100
+#define GCC_CAMSS_VFE_AXI_CLK 101
+#define GCC_CRYPTO_AHB_CLK 102
+#define GCC_CRYPTO_AXI_CLK 103
+#define GCC_CRYPTO_CLK 104
+#define GCC_OXILI_GMEM_CLK 105
+#define GCC_GP1_CLK 106
+#define GCC_GP2_CLK 107
+#define GCC_GP3_CLK 108
+#define GCC_MDSS_AHB_CLK 109
+#define GCC_MDSS_AXI_CLK 110
+#define GCC_MDSS_BYTE0_CLK 111
+#define GCC_MDSS_ESC0_CLK 112
+#define GCC_MDSS_MDP_CLK 113
+#define GCC_MDSS_PCLK0_CLK 114
+#define GCC_MDSS_VSYNC_CLK 115
+#define GCC_MSS_CFG_AHB_CLK 116
+#define GCC_OXILI_AHB_CLK 117
+#define GCC_OXILI_GFX3D_CLK 118
+#define GCC_PDM2_CLK 119
+#define GCC_PDM_AHB_CLK 120
+#define GCC_PRNG_AHB_CLK 121
+#define GCC_SDCC1_AHB_CLK 122
+#define GCC_SDCC1_APPS_CLK 123
+#define GCC_SDCC2_AHB_CLK 124
+#define GCC_SDCC2_APPS_CLK 125
+#define GCC_GTCU_AHB_CLK 126
+#define GCC_JPEG_TBU_CLK 127
+#define GCC_MDP_TBU_CLK 128
+#define GCC_SMMU_CFG_CLK 129
+#define GCC_VENUS_TBU_CLK 130
+#define GCC_VFE_TBU_CLK 131
+#define GCC_USB2A_PHY_SLEEP_CLK 132
+#define GCC_USB_HS_AHB_CLK 133
+#define GCC_USB_HS_SYSTEM_CLK 134
+#define GCC_VENUS0_AHB_CLK 135
+#define GCC_VENUS0_AXI_CLK 136
+#define GCC_VENUS0_VCODEC0_CLK 137
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
new file mode 100644
index 000000000..7d20eedfe
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8960_H
+
+#define AFAB_CLK_SRC 0
+#define AFAB_CORE_CLK 1
+#define SFAB_MSS_Q6_SW_A_CLK 2
+#define SFAB_MSS_Q6_FW_A_CLK 3
+#define QDSS_STM_CLK 4
+#define SCSS_A_CLK 5
+#define SCSS_H_CLK 6
+#define SCSS_XO_SRC_CLK 7
+#define AFAB_EBI1_CH0_A_CLK 8
+#define AFAB_EBI1_CH1_A_CLK 9
+#define AFAB_AXI_S0_FCLK 10
+#define AFAB_AXI_S1_FCLK 11
+#define AFAB_AXI_S2_FCLK 12
+#define AFAB_AXI_S3_FCLK 13
+#define AFAB_AXI_S4_FCLK 14
+#define SFAB_CORE_CLK 15
+#define SFAB_AXI_S0_FCLK 16
+#define SFAB_AXI_S1_FCLK 17
+#define SFAB_AXI_S2_FCLK 18
+#define SFAB_AXI_S3_FCLK 19
+#define SFAB_AXI_S4_FCLK 20
+#define SFAB_AHB_S0_FCLK 21
+#define SFAB_AHB_S1_FCLK 22
+#define SFAB_AHB_S2_FCLK 23
+#define SFAB_AHB_S3_FCLK 24
+#define SFAB_AHB_S4_FCLK 25
+#define SFAB_AHB_S5_FCLK 26
+#define SFAB_AHB_S6_FCLK 27
+#define SFAB_AHB_S7_FCLK 28
+#define QDSS_AT_CLK_SRC 29
+#define QDSS_AT_CLK 30
+#define QDSS_TRACECLKIN_CLK_SRC 31
+#define QDSS_TRACECLKIN_CLK 32
+#define QDSS_TSCTR_CLK_SRC 33
+#define QDSS_TSCTR_CLK 34
+#define SFAB_ADM0_M0_A_CLK 35
+#define SFAB_ADM0_M1_A_CLK 36
+#define SFAB_ADM0_M2_H_CLK 37
+#define ADM0_CLK 38
+#define ADM0_PBUS_CLK 39
+#define MSS_XPU_CLK 40
+#define IMEM0_A_CLK 41
+#define QDSS_H_CLK 42
+#define PCIE_A_CLK 43
+#define PCIE_AUX_CLK 44
+#define PCIE_PHY_REF_CLK 45
+#define PCIE_H_CLK 46
+#define SFAB_CLK_SRC 47
+#define MAHB0_CLK 48
+#define Q6SW_CLK_SRC 49
+#define Q6SW_CLK 50
+#define Q6FW_CLK_SRC 51
+#define Q6FW_CLK 52
+#define SFAB_MSS_M_A_CLK 53
+#define SFAB_USB3_M_A_CLK 54
+#define SFAB_LPASS_Q6_A_CLK 55
+#define SFAB_AFAB_M_A_CLK 56
+#define AFAB_SFAB_M0_A_CLK 57
+#define AFAB_SFAB_M1_A_CLK 58
+#define SFAB_SATA_S_H_CLK 59
+#define DFAB_CLK_SRC 60
+#define DFAB_CLK 61
+#define SFAB_DFAB_M_A_CLK 62
+#define DFAB_SFAB_M_A_CLK 63
+#define DFAB_SWAY0_H_CLK 64
+#define DFAB_SWAY1_H_CLK 65
+#define DFAB_ARB0_H_CLK 66
+#define DFAB_ARB1_H_CLK 67
+#define PPSS_H_CLK 68
+#define PPSS_PROC_CLK 69
+#define PPSS_TIMER0_CLK 70
+#define PPSS_TIMER1_CLK 71
+#define PMEM_A_CLK 72
+#define DMA_BAM_H_CLK 73
+#define SIC_H_CLK 74
+#define SPS_TIC_H_CLK 75
+#define SLIMBUS_H_CLK 76
+#define SLIMBUS_XO_SRC_CLK 77
+#define CFPB_2X_CLK_SRC 78
+#define CFPB_CLK 79
+#define CFPB0_H_CLK 80
+#define CFPB1_H_CLK 81
+#define CFPB2_H_CLK 82
+#define SFAB_CFPB_M_H_CLK 83
+#define CFPB_MASTER_H_CLK 84
+#define SFAB_CFPB_S_H_CLK 85
+#define CFPB_SPLITTER_H_CLK 86
+#define TSIF_H_CLK 87
+#define TSIF_INACTIVITY_TIMERS_CLK 88
+#define TSIF_REF_SRC 89
+#define TSIF_REF_CLK 90
+#define CE1_H_CLK 91
+#define CE1_CORE_CLK 92
+#define CE1_SLEEP_CLK 93
+#define CE2_H_CLK 94
+#define CE2_CORE_CLK 95
+#define SFPB_H_CLK_SRC 97
+#define SFPB_H_CLK 98
+#define SFAB_SFPB_M_H_CLK 99
+#define SFAB_SFPB_S_H_CLK 100
+#define RPM_PROC_CLK 101
+#define RPM_BUS_H_CLK 102
+#define RPM_SLEEP_CLK 103
+#define RPM_TIMER_CLK 104
+#define RPM_MSG_RAM_H_CLK 105
+#define PMIC_ARB0_H_CLK 106
+#define PMIC_ARB1_H_CLK 107
+#define PMIC_SSBI2_SRC 108
+#define PMIC_SSBI2_CLK 109
+#define SDC1_H_CLK 110
+#define SDC2_H_CLK 111
+#define SDC3_H_CLK 112
+#define SDC4_H_CLK 113
+#define SDC5_H_CLK 114
+#define SDC1_SRC 115
+#define SDC2_SRC 116
+#define SDC3_SRC 117
+#define SDC4_SRC 118
+#define SDC5_SRC 119
+#define SDC1_CLK 120
+#define SDC2_CLK 121
+#define SDC3_CLK 122
+#define SDC4_CLK 123
+#define SDC5_CLK 124
+#define DFAB_A2_H_CLK 125
+#define USB_HS1_H_CLK 126
+#define USB_HS1_XCVR_SRC 127
+#define USB_HS1_XCVR_CLK 128
+#define USB_HSIC_H_CLK 129
+#define USB_HSIC_XCVR_FS_SRC 130
+#define USB_HSIC_XCVR_FS_CLK 131
+#define USB_HSIC_SYSTEM_CLK_SRC 132
+#define USB_HSIC_SYSTEM_CLK 133
+#define CFPB0_C0_H_CLK 134
+#define CFPB0_C1_H_CLK 135
+#define CFPB0_D0_H_CLK 136
+#define CFPB0_D1_H_CLK 137
+#define USB_FS1_H_CLK 138
+#define USB_FS1_XCVR_FS_SRC 139
+#define USB_FS1_XCVR_FS_CLK 140
+#define USB_FS1_SYSTEM_CLK 141
+#define USB_FS2_H_CLK 142
+#define USB_FS2_XCVR_FS_SRC 143
+#define USB_FS2_XCVR_FS_CLK 144
+#define USB_FS2_SYSTEM_CLK 145
+#define GSBI_COMMON_SIM_SRC 146
+#define GSBI1_H_CLK 147
+#define GSBI2_H_CLK 148
+#define GSBI3_H_CLK 149
+#define GSBI4_H_CLK 150
+#define GSBI5_H_CLK 151
+#define GSBI6_H_CLK 152
+#define GSBI7_H_CLK 153
+#define GSBI8_H_CLK 154
+#define GSBI9_H_CLK 155
+#define GSBI10_H_CLK 156
+#define GSBI11_H_CLK 157
+#define GSBI12_H_CLK 158
+#define GSBI1_UART_SRC 159
+#define GSBI1_UART_CLK 160
+#define GSBI2_UART_SRC 161
+#define GSBI2_UART_CLK 162
+#define GSBI3_UART_SRC 163
+#define GSBI3_UART_CLK 164
+#define GSBI4_UART_SRC 165
+#define GSBI4_UART_CLK 166
+#define GSBI5_UART_SRC 167
+#define GSBI5_UART_CLK 168
+#define GSBI6_UART_SRC 169
+#define GSBI6_UART_CLK 170
+#define GSBI7_UART_SRC 171
+#define GSBI7_UART_CLK 172
+#define GSBI8_UART_SRC 173
+#define GSBI8_UART_CLK 174
+#define GSBI9_UART_SRC 175
+#define GSBI9_UART_CLK 176
+#define GSBI10_UART_SRC 177
+#define GSBI10_UART_CLK 178
+#define GSBI11_UART_SRC 179
+#define GSBI11_UART_CLK 180
+#define GSBI12_UART_SRC 181
+#define GSBI12_UART_CLK 182
+#define GSBI1_QUP_SRC 183
+#define GSBI1_QUP_CLK 184
+#define GSBI2_QUP_SRC 185
+#define GSBI2_QUP_CLK 186
+#define GSBI3_QUP_SRC 187
+#define GSBI3_QUP_CLK 188
+#define GSBI4_QUP_SRC 189
+#define GSBI4_QUP_CLK 190
+#define GSBI5_QUP_SRC 191
+#define GSBI5_QUP_CLK 192
+#define GSBI6_QUP_SRC 193
+#define GSBI6_QUP_CLK 194
+#define GSBI7_QUP_SRC 195
+#define GSBI7_QUP_CLK 196
+#define GSBI8_QUP_SRC 197
+#define GSBI8_QUP_CLK 198
+#define GSBI9_QUP_SRC 199
+#define GSBI9_QUP_CLK 200
+#define GSBI10_QUP_SRC 201
+#define GSBI10_QUP_CLK 202
+#define GSBI11_QUP_SRC 203
+#define GSBI11_QUP_CLK 204
+#define GSBI12_QUP_SRC 205
+#define GSBI12_QUP_CLK 206
+#define GSBI1_SIM_CLK 207
+#define GSBI2_SIM_CLK 208
+#define GSBI3_SIM_CLK 209
+#define GSBI4_SIM_CLK 210
+#define GSBI5_SIM_CLK 211
+#define GSBI6_SIM_CLK 212
+#define GSBI7_SIM_CLK 213
+#define GSBI8_SIM_CLK 214
+#define GSBI9_SIM_CLK 215
+#define GSBI10_SIM_CLK 216
+#define GSBI11_SIM_CLK 217
+#define GSBI12_SIM_CLK 218
+#define USB_HSIC_HSIC_CLK_SRC 219
+#define USB_HSIC_HSIC_CLK 220
+#define USB_HSIC_HSIO_CAL_CLK 221
+#define SPDM_CFG_H_CLK 222
+#define SPDM_MSTR_H_CLK 223
+#define SPDM_FF_CLK_SRC 224
+#define SPDM_FF_CLK 225
+#define SEC_CTRL_CLK 226
+#define SEC_CTRL_ACC_CLK_SRC 227
+#define SEC_CTRL_ACC_CLK 228
+#define TLMM_H_CLK 229
+#define TLMM_CLK 230
+#define SFAB_MSS_S_H_CLK 231
+#define MSS_SLP_CLK 232
+#define MSS_Q6SW_JTAG_CLK 233
+#define MSS_Q6FW_JTAG_CLK 234
+#define MSS_S_H_CLK 235
+#define MSS_CXO_SRC_CLK 236
+#define SATA_H_CLK 237
+#define SATA_CLK_SRC 238
+#define SATA_RXOOB_CLK 239
+#define SATA_PMALIVE_CLK 240
+#define SATA_PHY_REF_CLK 241
+#define TSSC_CLK_SRC 242
+#define TSSC_CLK 243
+#define PDM_SRC 244
+#define PDM_CLK 245
+#define GP0_SRC 246
+#define GP0_CLK 247
+#define GP1_SRC 248
+#define GP1_CLK 249
+#define GP2_SRC 250
+#define GP2_CLK 251
+#define MPM_CLK 252
+#define EBI1_CLK_SRC 253
+#define EBI1_CH0_CLK 254
+#define EBI1_CH1_CLK 255
+#define EBI1_2X_CLK 256
+#define EBI1_CH0_DQ_CLK 257
+#define EBI1_CH1_DQ_CLK 258
+#define EBI1_CH0_CA_CLK 259
+#define EBI1_CH1_CA_CLK 260
+#define EBI1_XO_CLK 261
+#define SFAB_SMPSS_S_H_CLK 262
+#define PRNG_SRC 263
+#define PRNG_CLK 264
+#define PXO_SRC 265
+#define LPASS_CXO_CLK 266
+#define LPASS_PXO_CLK 267
+#define SPDM_CY_PORT0_CLK 268
+#define SPDM_CY_PORT1_CLK 269
+#define SPDM_CY_PORT2_CLK 270
+#define SPDM_CY_PORT3_CLK 271
+#define SPDM_CY_PORT4_CLK 272
+#define SPDM_CY_PORT5_CLK 273
+#define SPDM_CY_PORT6_CLK 274
+#define SPDM_CY_PORT7_CLK 275
+#define PLL0 276
+#define PLL0_VOTE 277
+#define PLL3 278
+#define PLL3_VOTE 279
+#define PLL4_VOTE 280
+#define PLL5 281
+#define PLL5_VOTE 282
+#define PLL6 283
+#define PLL6_VOTE 284
+#define PLL7_VOTE 285
+#define PLL8 286
+#define PLL8_VOTE 287
+#define PLL9 288
+#define PLL10 289
+#define PLL11 290
+#define PLL12 291
+#define PLL13 292
+#define PLL14 293
+#define PLL14_VOTE 294
+#define USB_HS3_H_CLK 295
+#define USB_HS3_XCVR_SRC 296
+#define USB_HS3_XCVR_CLK 297
+#define USB_HS4_H_CLK 298
+#define USB_HS4_XCVR_SRC 299
+#define USB_HS4_XCVR_CLK 300
+#define SATA_PHY_CFG_CLK 301
+#define SATA_A_CLK 302
+#define CE3_SRC 303
+#define CE3_CORE_CLK 304
+#define CE3_H_CLK 305
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8974.h b/include/dt-bindings/clock/qcom,gcc-msm8974.h
new file mode 100644
index 000000000..51e51c860
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-msm8974.h
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_GCC_8974_H
+
+#define GPLL0 0
+#define GPLL0_VOTE 1
+#define CONFIG_NOC_CLK_SRC 2
+#define GPLL2 3
+#define GPLL2_VOTE 4
+#define GPLL3 5
+#define GPLL3_VOTE 6
+#define PERIPH_NOC_CLK_SRC 7
+#define BLSP_UART_SIM_CLK_SRC 8
+#define QDSS_TSCTR_CLK_SRC 9
+#define BIMC_DDR_CLK_SRC 10
+#define SYSTEM_NOC_CLK_SRC 11
+#define GPLL1 12
+#define GPLL1_VOTE 13
+#define RPM_CLK_SRC 14
+#define GCC_BIMC_CLK 15
+#define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16
+#define KPSS_AHB_CLK_SRC 17
+#define QDSS_AT_CLK_SRC 18
+#define USB30_MASTER_CLK_SRC 19
+#define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20
+#define QDSS_STM_CLK_SRC 21
+#define ACC_CLK_SRC 22
+#define SEC_CTRL_CLK_SRC 23
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 24
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 26
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 28
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 29
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 30
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 31
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 32
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 33
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 34
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 35
+#define BLSP1_UART1_APPS_CLK_SRC 36
+#define BLSP1_UART2_APPS_CLK_SRC 37
+#define BLSP1_UART3_APPS_CLK_SRC 38
+#define BLSP1_UART4_APPS_CLK_SRC 39
+#define BLSP1_UART5_APPS_CLK_SRC 40
+#define BLSP1_UART6_APPS_CLK_SRC 41
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 42
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 44
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 46
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 47
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 48
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 49
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC 50
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC 51
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC 52
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC 53
+#define BLSP2_UART1_APPS_CLK_SRC 54
+#define BLSP2_UART2_APPS_CLK_SRC 55
+#define BLSP2_UART3_APPS_CLK_SRC 56
+#define BLSP2_UART4_APPS_CLK_SRC 57
+#define BLSP2_UART5_APPS_CLK_SRC 58
+#define BLSP2_UART6_APPS_CLK_SRC 59
+#define CE1_CLK_SRC 60
+#define CE2_CLK_SRC 61
+#define GP1_CLK_SRC 62
+#define GP2_CLK_SRC 63
+#define GP3_CLK_SRC 64
+#define PDM2_CLK_SRC 65
+#define QDSS_TRACECLKIN_CLK_SRC 66
+#define RBCPR_CLK_SRC 67
+#define SDCC1_APPS_CLK_SRC 68
+#define SDCC2_APPS_CLK_SRC 69
+#define SDCC3_APPS_CLK_SRC 70
+#define SDCC4_APPS_CLK_SRC 71
+#define SPMI_AHB_CLK_SRC 72
+#define SPMI_SER_CLK_SRC 73
+#define TSIF_REF_CLK_SRC 74
+#define USB30_MOCK_UTMI_CLK_SRC 75
+#define USB_HS_SYSTEM_CLK_SRC 76
+#define USB_HSIC_CLK_SRC 77
+#define USB_HSIC_IO_CAL_CLK_SRC 78
+#define USB_HSIC_SYSTEM_CLK_SRC 79
+#define GCC_BAM_DMA_AHB_CLK 80
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81
+#define GCC_BIMC_CFG_AHB_CLK 82
+#define GCC_BIMC_KPSS_AXI_CLK 83
+#define GCC_BIMC_SLEEP_CLK 84
+#define GCC_BIMC_SYSNOC_AXI_CLK 85
+#define GCC_BIMC_XO_CLK 86
+#define GCC_BLSP1_AHB_CLK 87
+#define GCC_BLSP1_SLEEP_CLK 88
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 89
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 90
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 91
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 92
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 93
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 94
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 95
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 96
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 97
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 98
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 99
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 100
+#define GCC_BLSP1_UART1_APPS_CLK 101
+#define GCC_BLSP1_UART1_SIM_CLK 102
+#define GCC_BLSP1_UART2_APPS_CLK 103
+#define GCC_BLSP1_UART2_SIM_CLK 104
+#define GCC_BLSP1_UART3_APPS_CLK 105
+#define GCC_BLSP1_UART3_SIM_CLK 106
+#define GCC_BLSP1_UART4_APPS_CLK 107
+#define GCC_BLSP1_UART4_SIM_CLK 108
+#define GCC_BLSP1_UART5_APPS_CLK 109
+#define GCC_BLSP1_UART5_SIM_CLK 110
+#define GCC_BLSP1_UART6_APPS_CLK 111
+#define GCC_BLSP1_UART6_SIM_CLK 112
+#define GCC_BLSP2_AHB_CLK 113
+#define GCC_BLSP2_SLEEP_CLK 114
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 115
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 116
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 117
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 118
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 119
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 120
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 121
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 122
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK 123
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK 124
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK 125
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK 126
+#define GCC_BLSP2_UART1_APPS_CLK 127
+#define GCC_BLSP2_UART1_SIM_CLK 128
+#define GCC_BLSP2_UART2_APPS_CLK 129
+#define GCC_BLSP2_UART2_SIM_CLK 130
+#define GCC_BLSP2_UART3_APPS_CLK 131
+#define GCC_BLSP2_UART3_SIM_CLK 132
+#define GCC_BLSP2_UART4_APPS_CLK 133
+#define GCC_BLSP2_UART4_SIM_CLK 134
+#define GCC_BLSP2_UART5_APPS_CLK 135
+#define GCC_BLSP2_UART5_SIM_CLK 136
+#define GCC_BLSP2_UART6_APPS_CLK 137
+#define GCC_BLSP2_UART6_SIM_CLK 138
+#define GCC_BOOT_ROM_AHB_CLK 139
+#define GCC_CE1_AHB_CLK 140
+#define GCC_CE1_AXI_CLK 141
+#define GCC_CE1_CLK 142
+#define GCC_CE2_AHB_CLK 143
+#define GCC_CE2_AXI_CLK 144
+#define GCC_CE2_CLK 145
+#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146
+#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147
+#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148
+#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149
+#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150
+#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151
+#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152
+#define GCC_CFG_NOC_AHB_CLK 153
+#define GCC_CFG_NOC_DDR_CFG_CLK 154
+#define GCC_CFG_NOC_RPM_AHB_CLK 155
+#define GCC_BIMC_DDR_CPLL0_CLK 156
+#define GCC_BIMC_DDR_CPLL1_CLK 157
+#define GCC_DDR_DIM_CFG_CLK 158
+#define GCC_DDR_DIM_SLEEP_CLK 159
+#define GCC_DEHR_CLK 160
+#define GCC_AHB_CLK 161
+#define GCC_IM_SLEEP_CLK 162
+#define GCC_XO_CLK 163
+#define GCC_XO_DIV4_CLK 164
+#define GCC_GP1_CLK 165
+#define GCC_GP2_CLK 166
+#define GCC_GP3_CLK 167
+#define GCC_IMEM_AXI_CLK 168
+#define GCC_IMEM_CFG_AHB_CLK 169
+#define GCC_KPSS_AHB_CLK 170
+#define GCC_KPSS_AXI_CLK 171
+#define GCC_LPASS_Q6_AXI_CLK 172
+#define GCC_MMSS_NOC_AT_CLK 173
+#define GCC_MMSS_NOC_CFG_AHB_CLK 174
+#define GCC_OCMEM_NOC_CFG_AHB_CLK 175
+#define GCC_OCMEM_SYS_NOC_AXI_CLK 176
+#define GCC_MPM_AHB_CLK 177
+#define GCC_MSG_RAM_AHB_CLK 178
+#define GCC_MSS_CFG_AHB_CLK 179
+#define GCC_MSS_Q6_BIMC_AXI_CLK 180
+#define GCC_NOC_CONF_XPU_AHB_CLK 181
+#define GCC_PDM2_CLK 182
+#define GCC_PDM_AHB_CLK 183
+#define GCC_PDM_XO4_CLK 184
+#define GCC_PERIPH_NOC_AHB_CLK 185
+#define GCC_PERIPH_NOC_AT_CLK 186
+#define GCC_PERIPH_NOC_CFG_AHB_CLK 187
+#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188
+#define GCC_PERIPH_XPU_AHB_CLK 189
+#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190
+#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191
+#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192
+#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193
+#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194
+#define GCC_PRNG_AHB_CLK 195
+#define GCC_QDSS_AT_CLK 196
+#define GCC_QDSS_CFG_AHB_CLK 197
+#define GCC_QDSS_DAP_AHB_CLK 198
+#define GCC_QDSS_DAP_CLK 199
+#define GCC_QDSS_ETR_USB_CLK 200
+#define GCC_QDSS_STM_CLK 201
+#define GCC_QDSS_TRACECLKIN_CLK 202
+#define GCC_QDSS_TSCTR_DIV16_CLK 203
+#define GCC_QDSS_TSCTR_DIV2_CLK 204
+#define GCC_QDSS_TSCTR_DIV3_CLK 205
+#define GCC_QDSS_TSCTR_DIV4_CLK 206
+#define GCC_QDSS_TSCTR_DIV8_CLK 207
+#define GCC_QDSS_RBCPR_XPU_AHB_CLK 208
+#define GCC_RBCPR_AHB_CLK 209
+#define GCC_RBCPR_CLK 210
+#define GCC_RPM_BUS_AHB_CLK 211
+#define GCC_RPM_PROC_HCLK 212
+#define GCC_RPM_SLEEP_CLK 213
+#define GCC_RPM_TIMER_CLK 214
+#define GCC_SDCC1_AHB_CLK 215
+#define GCC_SDCC1_APPS_CLK 216
+#define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217
+#define GCC_SDCC2_AHB_CLK 218
+#define GCC_SDCC2_APPS_CLK 219
+#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220
+#define GCC_SDCC3_AHB_CLK 221
+#define GCC_SDCC3_APPS_CLK 222
+#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223
+#define GCC_SDCC4_AHB_CLK 224
+#define GCC_SDCC4_APPS_CLK 225
+#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226
+#define GCC_SEC_CTRL_ACC_CLK 227
+#define GCC_SEC_CTRL_AHB_CLK 228
+#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229
+#define GCC_SEC_CTRL_CLK 230
+#define GCC_SEC_CTRL_SENSE_CLK 231
+#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232
+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233
+#define GCC_SPDM_BIMC_CY_CLK 234
+#define GCC_SPDM_CFG_AHB_CLK 235
+#define GCC_SPDM_DEBUG_CY_CLK 236
+#define GCC_SPDM_FF_CLK 237
+#define GCC_SPDM_MSTR_AHB_CLK 238
+#define GCC_SPDM_PNOC_CY_CLK 239
+#define GCC_SPDM_RPM_CY_CLK 240
+#define GCC_SPDM_SNOC_CY_CLK 241
+#define GCC_SPMI_AHB_CLK 242
+#define GCC_SPMI_CNOC_AHB_CLK 243
+#define GCC_SPMI_SER_CLK 244
+#define GCC_SNOC_CNOC_AHB_CLK 245
+#define GCC_SNOC_PNOC_AHB_CLK 246
+#define GCC_SYS_NOC_AT_CLK 247
+#define GCC_SYS_NOC_AXI_CLK 248
+#define GCC_SYS_NOC_KPSS_AHB_CLK 249
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250
+#define GCC_SYS_NOC_USB3_AXI_CLK 251
+#define GCC_TCSR_AHB_CLK 252
+#define GCC_TLMM_AHB_CLK 253
+#define GCC_TLMM_CLK 254
+#define GCC_TSIF_AHB_CLK 255
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 256
+#define GCC_TSIF_REF_CLK 257
+#define GCC_USB2A_PHY_SLEEP_CLK 258
+#define GCC_USB2B_PHY_SLEEP_CLK 259
+#define GCC_USB30_MASTER_CLK 260
+#define GCC_USB30_MOCK_UTMI_CLK 261
+#define GCC_USB30_SLEEP_CLK 262
+#define GCC_USB_HS_AHB_CLK 263
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264
+#define GCC_USB_HS_SYSTEM_CLK 265
+#define GCC_USB_HSIC_AHB_CLK 266
+#define GCC_USB_HSIC_CLK 267
+#define GCC_USB_HSIC_IO_CAL_CLK 268
+#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269
+#define GCC_USB_HSIC_SYSTEM_CLK 270
+#define GCC_WCSS_GPLL1_CLK_SRC 271
+#define GCC_MMSS_GPLL0_CLK_SRC 272
+#define GCC_LPASS_GPLL0_CLK_SRC 273
+#define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274
+#define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275
+#define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276
+#define GCC_IMEM_AXI_CLK_SLEEP_ENA 277
+#define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278
+#define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279
+#define GCC_KPSS_AHB_CLK_SLEEP_ENA 280
+#define GCC_KPSS_AXI_CLK_SLEEP_ENA 281
+#define GCC_MPM_AHB_CLK_SLEEP_ENA 282
+#define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283
+#define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284
+#define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285
+#define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286
+#define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287
+#define GCC_PRNG_AHB_CLK_SLEEP_ENA 288
+#define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289
+#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290
+#define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291
+#define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292
+#define GCC_TLMM_AHB_CLK_SLEEP_ENA 293
+#define GCC_TLMM_CLK_SLEEP_ENA 294
+#define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295
+#define GCC_CE1_CLK_SLEEP_ENA 296
+#define GCC_CE1_AXI_CLK_SLEEP_ENA 297
+#define GCC_CE1_AHB_CLK_SLEEP_ENA 298
+#define GCC_CE2_CLK_SLEEP_ENA 299
+#define GCC_CE2_AXI_CLK_SLEEP_ENA 300
+#define GCC_CE2_AHB_CLK_SLEEP_ENA 301
+#define GPLL4 302
+#define GPLL4_VOTE 303
+#define GCC_SDCC1_CDCCAL_SLEEP_CLK 304
+#define GCC_SDCC1_CDCCAL_FF_CLK 305
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-ipq806x.h b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
new file mode 100644
index 000000000..4e944b85c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
+#define _DT_BINDINGS_CLK_LCC_IPQ806X_H
+
+#define PLL4 0
+#define MI2S_OSR_SRC 1
+#define MI2S_OSR_CLK 2
+#define MI2S_DIV_CLK 3
+#define MI2S_BIT_DIV_CLK 4
+#define MI2S_BIT_CLK 5
+#define PCM_SRC 6
+#define PCM_CLK_OUT 7
+#define PCM_CLK 8
+#define SPDIF_SRC 9
+#define SPDIF_CLK 10
+#define AHBIX_CLK 11
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,lcc-msm8960.h b/include/dt-bindings/clock/qcom,lcc-msm8960.h
new file mode 100644
index 000000000..4fb2aa64d
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,lcc-msm8960.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
+#define _DT_BINDINGS_CLK_LCC_MSM8960_H
+
+#define PLL4 0
+#define MI2S_OSR_SRC 1
+#define MI2S_OSR_CLK 2
+#define MI2S_DIV_CLK 3
+#define MI2S_BIT_DIV_CLK 4
+#define MI2S_BIT_CLK 5
+#define PCM_SRC 6
+#define PCM_CLK_OUT 7
+#define PCM_CLK 8
+#define SLIMBUS_SRC 9
+#define AUDIO_SLIMBUS_CLK 10
+#define SPS_SLIMBUS_CLK 11
+#define CODEC_I2S_MIC_OSR_SRC 12
+#define CODEC_I2S_MIC_OSR_CLK 13
+#define CODEC_I2S_MIC_DIV_CLK 14
+#define CODEC_I2S_MIC_BIT_DIV_CLK 15
+#define CODEC_I2S_MIC_BIT_CLK 16
+#define SPARE_I2S_MIC_OSR_SRC 17
+#define SPARE_I2S_MIC_OSR_CLK 18
+#define SPARE_I2S_MIC_DIV_CLK 19
+#define SPARE_I2S_MIC_BIT_DIV_CLK 20
+#define SPARE_I2S_MIC_BIT_CLK 21
+#define CODEC_I2S_SPKR_OSR_SRC 22
+#define CODEC_I2S_SPKR_OSR_CLK 23
+#define CODEC_I2S_SPKR_DIV_CLK 24
+#define CODEC_I2S_SPKR_BIT_DIV_CLK 25
+#define CODEC_I2S_SPKR_BIT_CLK 26
+#define SPARE_I2S_SPKR_OSR_SRC 27
+#define SPARE_I2S_SPKR_OSR_CLK 28
+#define SPARE_I2S_SPKR_DIV_CLK 29
+#define SPARE_I2S_SPKR_BIT_DIV_CLK 30
+#define SPARE_I2S_SPKR_BIT_CLK 31
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000..d72b5b35f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
+
+#define MMSS_AHB_CLK_SRC 0
+#define MMSS_AXI_CLK_SRC 1
+#define MMPLL0 2
+#define MMPLL0_VOTE 3
+#define MMPLL1 4
+#define MMPLL1_VOTE 5
+#define MMPLL2 6
+#define MMPLL3 7
+#define MMPLL4 8
+#define CSI0_CLK_SRC 9
+#define CSI1_CLK_SRC 10
+#define CSI2_CLK_SRC 11
+#define CSI3_CLK_SRC 12
+#define VCODEC0_CLK_SRC 13
+#define VFE0_CLK_SRC 14
+#define VFE1_CLK_SRC 15
+#define MDP_CLK_SRC 16
+#define PCLK0_CLK_SRC 17
+#define PCLK1_CLK_SRC 18
+#define OCMEMNOC_CLK_SRC 19
+#define GFX3D_CLK_SRC 20
+#define JPEG0_CLK_SRC 21
+#define JPEG1_CLK_SRC 22
+#define JPEG2_CLK_SRC 23
+#define EDPPIXEL_CLK_SRC 24
+#define EXTPCLK_CLK_SRC 25
+#define VP_CLK_SRC 26
+#define CCI_CLK_SRC 27
+#define CAMSS_GP0_CLK_SRC 28
+#define CAMSS_GP1_CLK_SRC 29
+#define MCLK0_CLK_SRC 30
+#define MCLK1_CLK_SRC 31
+#define MCLK2_CLK_SRC 32
+#define MCLK3_CLK_SRC 33
+#define CSI0PHYTIMER_CLK_SRC 34
+#define CSI1PHYTIMER_CLK_SRC 35
+#define CSI2PHYTIMER_CLK_SRC 36
+#define CPP_CLK_SRC 37
+#define BYTE0_CLK_SRC 38
+#define BYTE1_CLK_SRC 39
+#define EDPAUX_CLK_SRC 40
+#define EDPLINK_CLK_SRC 41
+#define ESC0_CLK_SRC 42
+#define ESC1_CLK_SRC 43
+#define HDMI_CLK_SRC 44
+#define VSYNC_CLK_SRC 45
+#define MMSS_RBCPR_CLK_SRC 46
+#define RBBMTIMER_CLK_SRC 47
+#define MAPLE_CLK_SRC 48
+#define VDP_CLK_SRC 49
+#define VPU_BUS_CLK_SRC 50
+#define MMSS_CXO_CLK 51
+#define MMSS_SLEEPCLK_CLK 52
+#define AVSYNC_AHB_CLK 53
+#define AVSYNC_EDPPIXEL_CLK 54
+#define AVSYNC_EXTPCLK_CLK 55
+#define AVSYNC_PCLK0_CLK 56
+#define AVSYNC_PCLK1_CLK 57
+#define AVSYNC_VP_CLK 58
+#define CAMSS_AHB_CLK 59
+#define CAMSS_CCI_CCI_AHB_CLK 60
+#define CAMSS_CCI_CCI_CLK 61
+#define CAMSS_CSI0_AHB_CLK 62
+#define CAMSS_CSI0_CLK 63
+#define CAMSS_CSI0PHY_CLK 64
+#define CAMSS_CSI0PIX_CLK 65
+#define CAMSS_CSI0RDI_CLK 66
+#define CAMSS_CSI1_AHB_CLK 67
+#define CAMSS_CSI1_CLK 68
+#define CAMSS_CSI1PHY_CLK 69
+#define CAMSS_CSI1PIX_CLK 70
+#define CAMSS_CSI1RDI_CLK 71
+#define CAMSS_CSI2_AHB_CLK 72
+#define CAMSS_CSI2_CLK 73
+#define CAMSS_CSI2PHY_CLK 74
+#define CAMSS_CSI2PIX_CLK 75
+#define CAMSS_CSI2RDI_CLK 76
+#define CAMSS_CSI3_AHB_CLK 77
+#define CAMSS_CSI3_CLK 78
+#define CAMSS_CSI3PHY_CLK 79
+#define CAMSS_CSI3PIX_CLK 80
+#define CAMSS_CSI3RDI_CLK 81
+#define CAMSS_CSI_VFE0_CLK 82
+#define CAMSS_CSI_VFE1_CLK 83
+#define CAMSS_GP0_CLK 84
+#define CAMSS_GP1_CLK 85
+#define CAMSS_ISPIF_AHB_CLK 86
+#define CAMSS_JPEG_JPEG0_CLK 87
+#define CAMSS_JPEG_JPEG1_CLK 88
+#define CAMSS_JPEG_JPEG2_CLK 89
+#define CAMSS_JPEG_JPEG_AHB_CLK 90
+#define CAMSS_JPEG_JPEG_AXI_CLK 91
+#define CAMSS_MCLK0_CLK 92
+#define CAMSS_MCLK1_CLK 93
+#define CAMSS_MCLK2_CLK 94
+#define CAMSS_MCLK3_CLK 95
+#define CAMSS_MICRO_AHB_CLK 96
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
+#define CAMSS_TOP_AHB_CLK 100
+#define CAMSS_VFE_CPP_AHB_CLK 101
+#define CAMSS_VFE_CPP_CLK 102
+#define CAMSS_VFE_VFE0_CLK 103
+#define CAMSS_VFE_VFE1_CLK 104
+#define CAMSS_VFE_VFE_AHB_CLK 105
+#define CAMSS_VFE_VFE_AXI_CLK 106
+#define MDSS_AHB_CLK 107
+#define MDSS_AXI_CLK 108
+#define MDSS_BYTE0_CLK 109
+#define MDSS_BYTE1_CLK 110
+#define MDSS_EDPAUX_CLK 111
+#define MDSS_EDPLINK_CLK 112
+#define MDSS_EDPPIXEL_CLK 113
+#define MDSS_ESC0_CLK 114
+#define MDSS_ESC1_CLK 115
+#define MDSS_EXTPCLK_CLK 116
+#define MDSS_HDMI_AHB_CLK 117
+#define MDSS_HDMI_CLK 118
+#define MDSS_MDP_CLK 119
+#define MDSS_MDP_LUT_CLK 120
+#define MDSS_PCLK0_CLK 121
+#define MDSS_PCLK1_CLK 122
+#define MDSS_VSYNC_CLK 123
+#define MMSS_RBCPR_AHB_CLK 124
+#define MMSS_RBCPR_CLK 125
+#define MMSS_SPDM_AHB_CLK 126
+#define MMSS_SPDM_AXI_CLK 127
+#define MMSS_SPDM_CSI0_CLK 128
+#define MMSS_SPDM_GFX3D_CLK 129
+#define MMSS_SPDM_JPEG0_CLK 130
+#define MMSS_SPDM_JPEG1_CLK 131
+#define MMSS_SPDM_JPEG2_CLK 132
+#define MMSS_SPDM_MDP_CLK 133
+#define MMSS_SPDM_PCLK0_CLK 134
+#define MMSS_SPDM_PCLK1_CLK 135
+#define MMSS_SPDM_VCODEC0_CLK 136
+#define MMSS_SPDM_VFE0_CLK 137
+#define MMSS_SPDM_VFE1_CLK 138
+#define MMSS_SPDM_RM_AXI_CLK 139
+#define MMSS_SPDM_RM_OCMEMNOC_CLK 140
+#define MMSS_MISC_AHB_CLK 141
+#define MMSS_MMSSNOC_AHB_CLK 142
+#define MMSS_MMSSNOC_BTO_AHB_CLK 143
+#define MMSS_MMSSNOC_AXI_CLK 144
+#define MMSS_S0_AXI_CLK 145
+#define OCMEMCX_AHB_CLK 146
+#define OCMEMCX_OCMEMNOC_CLK 147
+#define OXILI_OCMEMGX_CLK 148
+#define OXILI_GFX3D_CLK 149
+#define OXILI_RBBMTIMER_CLK 150
+#define OXILICX_AHB_CLK 151
+#define VENUS0_AHB_CLK 152
+#define VENUS0_AXI_CLK 153
+#define VENUS0_CORE0_VCODEC_CLK 154
+#define VENUS0_CORE1_VCODEC_CLK 155
+#define VENUS0_OCMEMNOC_CLK 156
+#define VENUS0_VCODEC0_CLK 157
+#define VPU_AHB_CLK 158
+#define VPU_AXI_CLK 159
+#define VPU_BUS_CLK 160
+#define VPU_CXO_CLK 161
+#define VPU_MAPLE_CLK 162
+#define VPU_SLEEP_CLK 163
+#define VPU_VDP_CLK 164
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
new file mode 100644
index 000000000..85041b28f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8960_H
+
+#define MMSS_AHB_SRC 0
+#define FAB_AHB_CLK 1
+#define APU_AHB_CLK 2
+#define TV_ENC_AHB_CLK 3
+#define AMP_AHB_CLK 4
+#define DSI2_S_AHB_CLK 5
+#define JPEGD_AHB_CLK 6
+#define GFX2D0_AHB_CLK 7
+#define DSI_S_AHB_CLK 8
+#define DSI2_M_AHB_CLK 9
+#define VPE_AHB_CLK 10
+#define SMMU_AHB_CLK 11
+#define HDMI_M_AHB_CLK 12
+#define VFE_AHB_CLK 13
+#define ROT_AHB_CLK 14
+#define VCODEC_AHB_CLK 15
+#define MDP_AHB_CLK 16
+#define DSI_M_AHB_CLK 17
+#define CSI_AHB_CLK 18
+#define MMSS_IMEM_AHB_CLK 19
+#define IJPEG_AHB_CLK 20
+#define HDMI_S_AHB_CLK 21
+#define GFX3D_AHB_CLK 22
+#define GFX2D1_AHB_CLK 23
+#define MMSS_FPB_CLK 24
+#define MMSS_AXI_SRC 25
+#define MMSS_FAB_CORE 26
+#define FAB_MSP_AXI_CLK 27
+#define JPEGD_AXI_CLK 28
+#define GMEM_AXI_CLK 29
+#define MDP_AXI_CLK 30
+#define MMSS_IMEM_AXI_CLK 31
+#define IJPEG_AXI_CLK 32
+#define GFX3D_AXI_CLK 33
+#define VCODEC_AXI_CLK 34
+#define VFE_AXI_CLK 35
+#define VPE_AXI_CLK 36
+#define ROT_AXI_CLK 37
+#define VCODEC_AXI_A_CLK 38
+#define VCODEC_AXI_B_CLK 39
+#define MM_AXI_S3_FCLK 40
+#define MM_AXI_S2_FCLK 41
+#define MM_AXI_S1_FCLK 42
+#define MM_AXI_S0_FCLK 43
+#define MM_AXI_S2_CLK 44
+#define MM_AXI_S1_CLK 45
+#define MM_AXI_S0_CLK 46
+#define CSI0_SRC 47
+#define CSI0_CLK 48
+#define CSI0_PHY_CLK 49
+#define CSI1_SRC 50
+#define CSI1_CLK 51
+#define CSI1_PHY_CLK 52
+#define CSI2_SRC 53
+#define CSI2_CLK 54
+#define CSI2_PHY_CLK 55
+#define DSI_SRC 56
+#define DSI_CLK 57
+#define CSI_PIX_CLK 58
+#define CSI_RDI_CLK 59
+#define MDP_VSYNC_CLK 60
+#define HDMI_DIV_CLK 61
+#define HDMI_APP_CLK 62
+#define CSI_PIX1_CLK 63
+#define CSI_RDI2_CLK 64
+#define CSI_RDI1_CLK 65
+#define GFX2D0_SRC 66
+#define GFX2D0_CLK 67
+#define GFX2D1_SRC 68
+#define GFX2D1_CLK 69
+#define GFX3D_SRC 70
+#define GFX3D_CLK 71
+#define IJPEG_SRC 72
+#define IJPEG_CLK 73
+#define JPEGD_SRC 74
+#define JPEGD_CLK 75
+#define MDP_SRC 76
+#define MDP_CLK 77
+#define MDP_LUT_CLK 78
+#define DSI2_PIXEL_SRC 79
+#define DSI2_PIXEL_CLK 80
+#define DSI2_SRC 81
+#define DSI2_CLK 82
+#define DSI1_BYTE_SRC 83
+#define DSI1_BYTE_CLK 84
+#define DSI2_BYTE_SRC 85
+#define DSI2_BYTE_CLK 86
+#define DSI1_ESC_SRC 87
+#define DSI1_ESC_CLK 88
+#define DSI2_ESC_SRC 89
+#define DSI2_ESC_CLK 90
+#define ROT_SRC 91
+#define ROT_CLK 92
+#define TV_ENC_CLK 93
+#define TV_DAC_CLK 94
+#define HDMI_TV_CLK 95
+#define MDP_TV_CLK 96
+#define TV_SRC 97
+#define VCODEC_SRC 98
+#define VCODEC_CLK 99
+#define VFE_SRC 100
+#define VFE_CLK 101
+#define VFE_CSI_CLK 102
+#define VPE_SRC 103
+#define VPE_CLK 104
+#define DSI_PIXEL_SRC 105
+#define DSI_PIXEL_CLK 106
+#define CAMCLK0_SRC 107
+#define CAMCLK0_CLK 108
+#define CAMCLK1_SRC 109
+#define CAMCLK1_CLK 110
+#define CAMCLK2_SRC 111
+#define CAMCLK2_CLK 112
+#define CSIPHYTIMER_SRC 113
+#define CSIPHY2_TIMER_CLK 114
+#define CSIPHY1_TIMER_CLK 115
+#define CSIPHY0_TIMER_CLK 116
+#define PLL1 117
+#define PLL2 118
+#define RGB_TV_CLK 119
+#define NPL_TV_CLK 120
+#define VCAP_AHB_CLK 121
+#define VCAP_AXI_CLK 122
+#define VCAP_SRC 123
+#define VCAP_CLK 124
+#define VCAP_NPL_CLK 125
+#define PLL15 126
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8974.h b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
new file mode 100644
index 000000000..032ed87ef
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8974.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+#define _DT_BINDINGS_CLK_MSM_MMCC_8974_H
+
+#define MMSS_AHB_CLK_SRC 0
+#define MMSS_AXI_CLK_SRC 1
+#define MMPLL0 2
+#define MMPLL0_VOTE 3
+#define MMPLL1 4
+#define MMPLL1_VOTE 5
+#define MMPLL2 6
+#define MMPLL3 7
+#define CSI0_CLK_SRC 8
+#define CSI1_CLK_SRC 9
+#define CSI2_CLK_SRC 10
+#define CSI3_CLK_SRC 11
+#define VFE0_CLK_SRC 12
+#define VFE1_CLK_SRC 13
+#define MDP_CLK_SRC 14
+#define GFX3D_CLK_SRC 15
+#define JPEG0_CLK_SRC 16
+#define JPEG1_CLK_SRC 17
+#define JPEG2_CLK_SRC 18
+#define PCLK0_CLK_SRC 19
+#define PCLK1_CLK_SRC 20
+#define VCODEC0_CLK_SRC 21
+#define CCI_CLK_SRC 22
+#define CAMSS_GP0_CLK_SRC 23
+#define CAMSS_GP1_CLK_SRC 24
+#define MCLK0_CLK_SRC 25
+#define MCLK1_CLK_SRC 26
+#define MCLK2_CLK_SRC 27
+#define MCLK3_CLK_SRC 28
+#define CSI0PHYTIMER_CLK_SRC 29
+#define CSI1PHYTIMER_CLK_SRC 30
+#define CSI2PHYTIMER_CLK_SRC 31
+#define CPP_CLK_SRC 32
+#define BYTE0_CLK_SRC 33
+#define BYTE1_CLK_SRC 34
+#define EDPAUX_CLK_SRC 35
+#define EDPLINK_CLK_SRC 36
+#define EDPPIXEL_CLK_SRC 37
+#define ESC0_CLK_SRC 38
+#define ESC1_CLK_SRC 39
+#define EXTPCLK_CLK_SRC 40
+#define HDMI_CLK_SRC 41
+#define VSYNC_CLK_SRC 42
+#define MMSS_RBCPR_CLK_SRC 43
+#define CAMSS_CCI_CCI_AHB_CLK 44
+#define CAMSS_CCI_CCI_CLK 45
+#define CAMSS_CSI0_AHB_CLK 46
+#define CAMSS_CSI0_CLK 47
+#define CAMSS_CSI0PHY_CLK 48
+#define CAMSS_CSI0PIX_CLK 49
+#define CAMSS_CSI0RDI_CLK 50
+#define CAMSS_CSI1_AHB_CLK 51
+#define CAMSS_CSI1_CLK 52
+#define CAMSS_CSI1PHY_CLK 53
+#define CAMSS_CSI1PIX_CLK 54
+#define CAMSS_CSI1RDI_CLK 55
+#define CAMSS_CSI2_AHB_CLK 56
+#define CAMSS_CSI2_CLK 57
+#define CAMSS_CSI2PHY_CLK 58
+#define CAMSS_CSI2PIX_CLK 59
+#define CAMSS_CSI2RDI_CLK 60
+#define CAMSS_CSI3_AHB_CLK 61
+#define CAMSS_CSI3_CLK 62
+#define CAMSS_CSI3PHY_CLK 63
+#define CAMSS_CSI3PIX_CLK 64
+#define CAMSS_CSI3RDI_CLK 65
+#define CAMSS_CSI_VFE0_CLK 66
+#define CAMSS_CSI_VFE1_CLK 67
+#define CAMSS_GP0_CLK 68
+#define CAMSS_GP1_CLK 69
+#define CAMSS_ISPIF_AHB_CLK 70
+#define CAMSS_JPEG_JPEG0_CLK 71
+#define CAMSS_JPEG_JPEG1_CLK 72
+#define CAMSS_JPEG_JPEG2_CLK 73
+#define CAMSS_JPEG_JPEG_AHB_CLK 74
+#define CAMSS_JPEG_JPEG_AXI_CLK 75
+#define CAMSS_JPEG_JPEG_OCMEMNOC_CLK 76
+#define CAMSS_MCLK0_CLK 77
+#define CAMSS_MCLK1_CLK 78
+#define CAMSS_MCLK2_CLK 79
+#define CAMSS_MCLK3_CLK 80
+#define CAMSS_MICRO_AHB_CLK 81
+#define CAMSS_PHY0_CSI0PHYTIMER_CLK 82
+#define CAMSS_PHY1_CSI1PHYTIMER_CLK 83
+#define CAMSS_PHY2_CSI2PHYTIMER_CLK 84
+#define CAMSS_TOP_AHB_CLK 85
+#define CAMSS_VFE_CPP_AHB_CLK 86
+#define CAMSS_VFE_CPP_CLK 87
+#define CAMSS_VFE_VFE0_CLK 88
+#define CAMSS_VFE_VFE1_CLK 89
+#define CAMSS_VFE_VFE_AHB_CLK 90
+#define CAMSS_VFE_VFE_AXI_CLK 91
+#define CAMSS_VFE_VFE_OCMEMNOC_CLK 92
+#define MDSS_AHB_CLK 93
+#define MDSS_AXI_CLK 94
+#define MDSS_BYTE0_CLK 95
+#define MDSS_BYTE1_CLK 96
+#define MDSS_EDPAUX_CLK 97
+#define MDSS_EDPLINK_CLK 98
+#define MDSS_EDPPIXEL_CLK 99
+#define MDSS_ESC0_CLK 100
+#define MDSS_ESC1_CLK 101
+#define MDSS_EXTPCLK_CLK 102
+#define MDSS_HDMI_AHB_CLK 103
+#define MDSS_HDMI_CLK 104
+#define MDSS_MDP_CLK 105
+#define MDSS_MDP_LUT_CLK 106
+#define MDSS_PCLK0_CLK 107
+#define MDSS_PCLK1_CLK 108
+#define MDSS_VSYNC_CLK 109
+#define MMSS_MISC_AHB_CLK 110
+#define MMSS_MMSSNOC_AHB_CLK 111
+#define MMSS_MMSSNOC_BTO_AHB_CLK 112
+#define MMSS_MMSSNOC_AXI_CLK 113
+#define MMSS_S0_AXI_CLK 114
+#define OCMEMCX_AHB_CLK 115
+#define OCMEMCX_OCMEMNOC_CLK 116
+#define OXILI_OCMEMGX_CLK 117
+#define OCMEMNOC_CLK 118
+#define OXILI_GFX3D_CLK 119
+#define OXILICX_AHB_CLK 120
+#define OXILICX_AXI_CLK 121
+#define VENUS0_AHB_CLK 122
+#define VENUS0_AXI_CLK 123
+#define VENUS0_OCMEMNOC_CLK 124
+#define VENUS0_VCODEC0_CLK 125
+#define OCMEMNOC_CLK_SRC 126
+#define SPDM_JPEG0 127
+#define SPDM_JPEG1 128
+#define SPDM_MDP 129
+#define SPDM_AXI 130
+#define SPDM_VCODEC0 131
+#define SPDM_VFE0 132
+#define SPDM_VFE1 133
+#define SPDM_JPEG2 134
+#define SPDM_PCLK1 135
+#define SPDM_GFX3D 136
+#define SPDM_AHB 137
+#define SPDM_PCLK0 138
+#define SPDM_OCMEMNOC 139
+#define SPDM_CSI0 140
+#define SPDM_RM_AXI 141
+#define SPDM_RM_OCMEMNOC 142
+
+#endif
diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h
new file mode 100644
index 000000000..5128f4d94
--- /dev/null
+++ b/include/dt-bindings/clock/r7s72100-clock.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
+#define __DT_BINDINGS_CLOCK_R7S72100_H__
+
+#define R7S72100_CLK_PLL 0
+
+/* MSTP3 */
+#define R7S72100_CLK_MTU2 3
+
+/* MSTP4 */
+#define R7S72100_CLK_SCIF0 7
+#define R7S72100_CLK_SCIF1 6
+#define R7S72100_CLK_SCIF2 5
+#define R7S72100_CLK_SCIF3 4
+#define R7S72100_CLK_SCIF4 3
+#define R7S72100_CLK_SCIF5 2
+#define R7S72100_CLK_SCIF6 1
+#define R7S72100_CLK_SCIF7 0
+
+/* MSTP9 */
+#define R7S72100_CLK_I2C0 7
+#define R7S72100_CLK_I2C1 6
+#define R7S72100_CLK_I2C2 5
+#define R7S72100_CLK_I2C3 4
+
+/* MSTP10 */
+#define R7S72100_CLK_SPI0 7
+#define R7S72100_CLK_SPI1 6
+#define R7S72100_CLK_SPI2 5
+#define R7S72100_CLK_SPI3 4
+#define R7S72100_CLK_SPI4 3
+
+#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h
new file mode 100644
index 000000000..9a4b4c9ca
--- /dev/null
+++ b/include/dt-bindings/clock/r8a73a4-clock.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
+#define __DT_BINDINGS_CLOCK_R8A73A4_H__
+
+/* CPG */
+#define R8A73A4_CLK_MAIN 0
+#define R8A73A4_CLK_PLL0 1
+#define R8A73A4_CLK_PLL1 2
+#define R8A73A4_CLK_PLL2 3
+#define R8A73A4_CLK_PLL2S 4
+#define R8A73A4_CLK_PLL2H 5
+#define R8A73A4_CLK_Z 6
+#define R8A73A4_CLK_Z2 7
+#define R8A73A4_CLK_I 8
+#define R8A73A4_CLK_M3 9
+#define R8A73A4_CLK_B 10
+#define R8A73A4_CLK_M1 11
+#define R8A73A4_CLK_M2 12
+#define R8A73A4_CLK_ZX 13
+#define R8A73A4_CLK_ZS 14
+#define R8A73A4_CLK_HP 15
+
+/* MSTP2 */
+#define R8A73A4_CLK_DMAC 18
+#define R8A73A4_CLK_SCIFB3 17
+#define R8A73A4_CLK_SCIFB2 16
+#define R8A73A4_CLK_SCIFB1 7
+#define R8A73A4_CLK_SCIFB0 6
+#define R8A73A4_CLK_SCIFA0 4
+#define R8A73A4_CLK_SCIFA1 3
+
+/* MSTP3 */
+#define R8A73A4_CLK_CMT1 29
+#define R8A73A4_CLK_IIC1 23
+#define R8A73A4_CLK_IIC0 18
+#define R8A73A4_CLK_IIC7 17
+#define R8A73A4_CLK_IIC6 16
+#define R8A73A4_CLK_MMCIF0 15
+#define R8A73A4_CLK_SDHI0 14
+#define R8A73A4_CLK_SDHI1 13
+#define R8A73A4_CLK_SDHI2 12
+#define R8A73A4_CLK_MMCIF1 5
+#define R8A73A4_CLK_IIC2 0
+
+/* MSTP4 */
+#define R8A73A4_CLK_IIC3 11
+#define R8A73A4_CLK_IIC4 10
+#define R8A73A4_CLK_IIC5 9
+
+/* MSTP5 */
+#define R8A73A4_CLK_THERMAL 22
+#define R8A73A4_CLK_IIC8 15
+
+#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */
diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-bindings/clock/r8a7740-clock.h
new file mode 100644
index 000000000..476135da0
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7740-clock.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
+#define __DT_BINDINGS_CLOCK_R8A7740_H__
+
+/* CPG */
+#define R8A7740_CLK_SYSTEM 0
+#define R8A7740_CLK_PLLC0 1
+#define R8A7740_CLK_PLLC1 2
+#define R8A7740_CLK_PLLC2 3
+#define R8A7740_CLK_R 4
+#define R8A7740_CLK_USB24S 5
+#define R8A7740_CLK_I 6
+#define R8A7740_CLK_ZG 7
+#define R8A7740_CLK_B 8
+#define R8A7740_CLK_M1 9
+#define R8A7740_CLK_HP 10
+#define R8A7740_CLK_HPP 11
+#define R8A7740_CLK_USBP 12
+#define R8A7740_CLK_S 13
+#define R8A7740_CLK_ZB 14
+#define R8A7740_CLK_M3 15
+#define R8A7740_CLK_CP 16
+
+/* MSTP1 */
+#define R8A7740_CLK_CEU21 28
+#define R8A7740_CLK_CEU20 27
+#define R8A7740_CLK_TMU0 25
+#define R8A7740_CLK_LCDC1 17
+#define R8A7740_CLK_IIC0 16
+#define R8A7740_CLK_TMU1 11
+#define R8A7740_CLK_LCDC0 0
+
+/* MSTP2 */
+#define R8A7740_CLK_SCIFA6 30
+#define R8A7740_CLK_INTCA 29
+#define R8A7740_CLK_SCIFA7 22
+#define R8A7740_CLK_DMAC1 18
+#define R8A7740_CLK_DMAC2 17
+#define R8A7740_CLK_DMAC3 16
+#define R8A7740_CLK_USBDMAC 14
+#define R8A7740_CLK_SCIFA5 7
+#define R8A7740_CLK_SCIFB 6
+#define R8A7740_CLK_SCIFA0 4
+#define R8A7740_CLK_SCIFA1 3
+#define R8A7740_CLK_SCIFA2 2
+#define R8A7740_CLK_SCIFA3 1
+#define R8A7740_CLK_SCIFA4 0
+
+/* MSTP3 */
+#define R8A7740_CLK_CMT1 29
+#define R8A7740_CLK_FSI 28
+#define R8A7740_CLK_IIC1 23
+#define R8A7740_CLK_USBF 20
+#define R8A7740_CLK_SDHI0 14
+#define R8A7740_CLK_SDHI1 13
+#define R8A7740_CLK_MMC 12
+#define R8A7740_CLK_GETHER 9
+#define R8A7740_CLK_TPU0 4
+
+/* MSTP4 */
+#define R8A7740_CLK_USBH 16
+#define R8A7740_CLK_SDHI2 15
+#define R8A7740_CLK_USBFUNC 7
+#define R8A7740_CLK_USBPHY 6
+
+/* SUBCK* */
+#define R8A7740_CLK_SUBCK 9
+#define R8A7740_CLK_SUBCK2 10
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h
new file mode 100644
index 000000000..f6b07c539
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7778-clock.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
+#define __DT_BINDINGS_CLOCK_R8A7778_H__
+
+/* CPG */
+#define R8A7778_CLK_PLLA 0
+#define R8A7778_CLK_PLLB 1
+#define R8A7778_CLK_B 2
+#define R8A7778_CLK_OUT 3
+#define R8A7778_CLK_P 4
+#define R8A7778_CLK_S 5
+#define R8A7778_CLK_S1 6
+
+/* MSTP0 */
+#define R8A7778_CLK_I2C0 30
+#define R8A7778_CLK_I2C1 29
+#define R8A7778_CLK_I2C2 28
+#define R8A7778_CLK_I2C3 27
+#define R8A7778_CLK_SCIF0 26
+#define R8A7778_CLK_SCIF1 25
+#define R8A7778_CLK_SCIF2 24
+#define R8A7778_CLK_SCIF3 23
+#define R8A7778_CLK_SCIF4 22
+#define R8A7778_CLK_SCIF5 21
+#define R8A7778_CLK_TMU0 16
+#define R8A7778_CLK_TMU1 15
+#define R8A7778_CLK_TMU2 14
+#define R8A7778_CLK_SSI0 12
+#define R8A7778_CLK_SSI1 11
+#define R8A7778_CLK_SSI2 10
+#define R8A7778_CLK_SSI3 9
+#define R8A7778_CLK_SRU 8
+#define R8A7778_CLK_HSPI 7
+
+/* MSTP1 */
+#define R8A7778_CLK_ETHER 14
+#define R8A7778_CLK_VIN0 10
+#define R8A7778_CLK_VIN1 9
+#define R8A7778_CLK_USB 0
+
+/* MSTP3 */
+#define R8A7778_CLK_MMC 31
+#define R8A7778_CLK_SDHI0 23
+#define R8A7778_CLK_SDHI1 22
+#define R8A7778_CLK_SDHI2 21
+#define R8A7778_CLK_SSI4 11
+#define R8A7778_CLK_SSI5 10
+#define R8A7778_CLK_SSI6 9
+#define R8A7778_CLK_SSI7 8
+#define R8A7778_CLK_SSI8 7
+
+/* MSTP5 */
+#define R8A7778_CLK_SRU_SRC0 31
+#define R8A7778_CLK_SRU_SRC1 30
+#define R8A7778_CLK_SRU_SRC2 29
+#define R8A7778_CLK_SRU_SRC3 28
+#define R8A7778_CLK_SRU_SRC4 27
+#define R8A7778_CLK_SRU_SRC5 26
+#define R8A7778_CLK_SRU_SRC6 25
+#define R8A7778_CLK_SRU_SRC7 24
+#define R8A7778_CLK_SRU_SRC8 23
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */
diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h
new file mode 100644
index 000000000..381a61142
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7779-clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Horms Solutions Ltd.
+ *
+ * Contact: Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7779_H__
+#define __DT_BINDINGS_CLOCK_R8A7779_H__
+
+/* CPG */
+#define R8A7779_CLK_PLLA 0
+#define R8A7779_CLK_Z 1
+#define R8A7779_CLK_ZS 2
+#define R8A7779_CLK_S 3
+#define R8A7779_CLK_S1 4
+#define R8A7779_CLK_P 5
+#define R8A7779_CLK_B 6
+#define R8A7779_CLK_OUT 7
+
+/* MSTP 0 */
+#define R8A7779_CLK_HSPI 7
+#define R8A7779_CLK_TMU2 14
+#define R8A7779_CLK_TMU1 15
+#define R8A7779_CLK_TMU0 16
+#define R8A7779_CLK_HSCIF1 18
+#define R8A7779_CLK_HSCIF0 19
+#define R8A7779_CLK_SCIF5 21
+#define R8A7779_CLK_SCIF4 22
+#define R8A7779_CLK_SCIF3 23
+#define R8A7779_CLK_SCIF2 24
+#define R8A7779_CLK_SCIF1 25
+#define R8A7779_CLK_SCIF0 26
+#define R8A7779_CLK_I2C3 27
+#define R8A7779_CLK_I2C2 28
+#define R8A7779_CLK_I2C1 29
+#define R8A7779_CLK_I2C0 30
+
+/* MSTP 1 */
+#define R8A7779_CLK_USB01 0
+#define R8A7779_CLK_USB2 1
+#define R8A7779_CLK_DU 3
+#define R8A7779_CLK_VIN2 8
+#define R8A7779_CLK_VIN1 9
+#define R8A7779_CLK_VIN0 10
+#define R8A7779_CLK_ETHER 14
+#define R8A7779_CLK_SATA 15
+#define R8A7779_CLK_PCIE 16
+#define R8A7779_CLK_VIN3 20
+
+/* MSTP 3 */
+#define R8A7779_CLK_SDHI3 20
+#define R8A7779_CLK_SDHI2 21
+#define R8A7779_CLK_SDHI1 22
+#define R8A7779_CLK_SDHI0 23
+#define R8A7779_CLK_MMC1 30
+#define R8A7779_CLK_MMC0 31
+
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
new file mode 100644
index 000000000..3f2c6b198
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -0,0 +1,154 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
+#define __DT_BINDINGS_CLOCK_R8A7790_H__
+
+/* CPG */
+#define R8A7790_CLK_MAIN 0
+#define R8A7790_CLK_PLL0 1
+#define R8A7790_CLK_PLL1 2
+#define R8A7790_CLK_PLL3 3
+#define R8A7790_CLK_LB 4
+#define R8A7790_CLK_QSPI 5
+#define R8A7790_CLK_SDH 6
+#define R8A7790_CLK_SD0 7
+#define R8A7790_CLK_SD1 8
+#define R8A7790_CLK_Z 9
+#define R8A7790_CLK_RCAN 10
+#define R8A7790_CLK_ADSP 11
+
+/* MSTP0 */
+#define R8A7790_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7790_CLK_VCP1 0
+#define R8A7790_CLK_VCP0 1
+#define R8A7790_CLK_VPC1 2
+#define R8A7790_CLK_VPC0 3
+#define R8A7790_CLK_JPU 6
+#define R8A7790_CLK_SSP1 9
+#define R8A7790_CLK_TMU1 11
+#define R8A7790_CLK_3DG 12
+#define R8A7790_CLK_2DDMAC 15
+#define R8A7790_CLK_FDP1_2 17
+#define R8A7790_CLK_FDP1_1 18
+#define R8A7790_CLK_FDP1_0 19
+#define R8A7790_CLK_TMU3 21
+#define R8A7790_CLK_TMU2 22
+#define R8A7790_CLK_CMT0 24
+#define R8A7790_CLK_TMU0 25
+#define R8A7790_CLK_VSP1_DU1 27
+#define R8A7790_CLK_VSP1_DU0 28
+#define R8A7790_CLK_VSP1_R 30
+#define R8A7790_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7790_CLK_SCIFA2 2
+#define R8A7790_CLK_SCIFA1 3
+#define R8A7790_CLK_SCIFA0 4
+#define R8A7790_CLK_MSIOF2 5
+#define R8A7790_CLK_SCIFB0 6
+#define R8A7790_CLK_SCIFB1 7
+#define R8A7790_CLK_MSIOF1 8
+#define R8A7790_CLK_MSIOF3 15
+#define R8A7790_CLK_SCIFB2 16
+#define R8A7790_CLK_SYS_DMAC1 18
+#define R8A7790_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7790_CLK_IIC2 0
+#define R8A7790_CLK_TPU0 4
+#define R8A7790_CLK_MMCIF1 5
+#define R8A7790_CLK_SDHI3 11
+#define R8A7790_CLK_SDHI2 12
+#define R8A7790_CLK_SDHI1 13
+#define R8A7790_CLK_SDHI0 14
+#define R8A7790_CLK_MMCIF0 15
+#define R8A7790_CLK_IIC0 18
+#define R8A7790_CLK_PCIEC 19
+#define R8A7790_CLK_IIC1 23
+#define R8A7790_CLK_SSUSB 28
+#define R8A7790_CLK_CMT1 29
+#define R8A7790_CLK_USBDMAC0 30
+#define R8A7790_CLK_USBDMAC1 31
+
+/* MSTP5 */
+#define R8A7790_CLK_AUDIO_DMAC1 1
+#define R8A7790_CLK_AUDIO_DMAC0 2
+#define R8A7790_CLK_ADSP_MOD 6
+#define R8A7790_CLK_THERMAL 22
+#define R8A7790_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7790_CLK_EHCI 3
+#define R8A7790_CLK_HSUSB 4
+#define R8A7790_CLK_HSCIF1 16
+#define R8A7790_CLK_HSCIF0 17
+#define R8A7790_CLK_SCIF1 20
+#define R8A7790_CLK_SCIF0 21
+#define R8A7790_CLK_DU2 22
+#define R8A7790_CLK_DU1 23
+#define R8A7790_CLK_DU0 24
+#define R8A7790_CLK_LVDS1 25
+#define R8A7790_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7790_CLK_MLB 2
+#define R8A7790_CLK_VIN3 8
+#define R8A7790_CLK_VIN2 9
+#define R8A7790_CLK_VIN1 10
+#define R8A7790_CLK_VIN0 11
+#define R8A7790_CLK_ETHER 13
+#define R8A7790_CLK_SATA1 14
+#define R8A7790_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7790_CLK_GPIO5 7
+#define R8A7790_CLK_GPIO4 8
+#define R8A7790_CLK_GPIO3 9
+#define R8A7790_CLK_GPIO2 10
+#define R8A7790_CLK_GPIO1 11
+#define R8A7790_CLK_GPIO0 12
+#define R8A7790_CLK_RCAN1 15
+#define R8A7790_CLK_RCAN0 16
+#define R8A7790_CLK_QSPI_MOD 17
+#define R8A7790_CLK_IICDVFS 26
+#define R8A7790_CLK_I2C3 28
+#define R8A7790_CLK_I2C2 29
+#define R8A7790_CLK_I2C1 30
+#define R8A7790_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7790_CLK_SSI_ALL 5
+#define R8A7790_CLK_SSI9 6
+#define R8A7790_CLK_SSI8 7
+#define R8A7790_CLK_SSI7 8
+#define R8A7790_CLK_SSI6 9
+#define R8A7790_CLK_SSI5 10
+#define R8A7790_CLK_SSI4 11
+#define R8A7790_CLK_SSI3 12
+#define R8A7790_CLK_SSI2 13
+#define R8A7790_CLK_SSI1 14
+#define R8A7790_CLK_SSI0 15
+#define R8A7790_CLK_SCU_ALL 17
+#define R8A7790_CLK_SCU_DVC1 18
+#define R8A7790_CLK_SCU_DVC0 19
+#define R8A7790_CLK_SCU_SRC9 22
+#define R8A7790_CLK_SCU_SRC8 23
+#define R8A7790_CLK_SCU_SRC7 24
+#define R8A7790_CLK_SCU_SRC6 25
+#define R8A7790_CLK_SCU_SRC5 26
+#define R8A7790_CLK_SCU_SRC4 27
+#define R8A7790_CLK_SCU_SRC3 28
+#define R8A7790_CLK_SCU_SRC2 29
+#define R8A7790_CLK_SCU_SRC1 30
+#define R8A7790_CLK_SCU_SRC0 31
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
new file mode 100644
index 000000000..8fc5dc8fa
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
+#define __DT_BINDINGS_CLOCK_R8A7791_H__
+
+/* CPG */
+#define R8A7791_CLK_MAIN 0
+#define R8A7791_CLK_PLL0 1
+#define R8A7791_CLK_PLL1 2
+#define R8A7791_CLK_PLL3 3
+#define R8A7791_CLK_LB 4
+#define R8A7791_CLK_QSPI 5
+#define R8A7791_CLK_SDH 6
+#define R8A7791_CLK_SD0 7
+#define R8A7791_CLK_Z 8
+#define R8A7791_CLK_RCAN 9
+#define R8A7791_CLK_ADSP 10
+
+/* MSTP0 */
+#define R8A7791_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7791_CLK_VCP0 1
+#define R8A7791_CLK_VPC0 3
+#define R8A7791_CLK_JPU 6
+#define R8A7791_CLK_SSP1 9
+#define R8A7791_CLK_TMU1 11
+#define R8A7791_CLK_3DG 12
+#define R8A7791_CLK_2DDMAC 15
+#define R8A7791_CLK_FDP1_1 18
+#define R8A7791_CLK_FDP1_0 19
+#define R8A7791_CLK_TMU3 21
+#define R8A7791_CLK_TMU2 22
+#define R8A7791_CLK_CMT0 24
+#define R8A7791_CLK_TMU0 25
+#define R8A7791_CLK_VSP1_DU1 27
+#define R8A7791_CLK_VSP1_DU0 28
+#define R8A7791_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7791_CLK_SCIFA2 2
+#define R8A7791_CLK_SCIFA1 3
+#define R8A7791_CLK_SCIFA0 4
+#define R8A7791_CLK_MSIOF2 5
+#define R8A7791_CLK_SCIFB0 6
+#define R8A7791_CLK_SCIFB1 7
+#define R8A7791_CLK_MSIOF1 8
+#define R8A7791_CLK_SCIFB2 16
+#define R8A7791_CLK_SYS_DMAC1 18
+#define R8A7791_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7791_CLK_TPU0 4
+#define R8A7791_CLK_SDHI2 11
+#define R8A7791_CLK_SDHI1 12
+#define R8A7791_CLK_SDHI0 14
+#define R8A7791_CLK_MMCIF0 15
+#define R8A7791_CLK_IIC0 18
+#define R8A7791_CLK_PCIEC 19
+#define R8A7791_CLK_IIC1 23
+#define R8A7791_CLK_SSUSB 28
+#define R8A7791_CLK_CMT1 29
+#define R8A7791_CLK_USBDMAC0 30
+#define R8A7791_CLK_USBDMAC1 31
+
+/* MSTP5 */
+#define R8A7791_CLK_AUDIO_DMAC1 1
+#define R8A7791_CLK_AUDIO_DMAC0 2
+#define R8A7791_CLK_ADSP_MOD 6
+#define R8A7791_CLK_THERMAL 22
+#define R8A7791_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7791_CLK_EHCI 3
+#define R8A7791_CLK_HSUSB 4
+#define R8A7791_CLK_HSCIF2 13
+#define R8A7791_CLK_SCIF5 14
+#define R8A7791_CLK_SCIF4 15
+#define R8A7791_CLK_HSCIF1 16
+#define R8A7791_CLK_HSCIF0 17
+#define R8A7791_CLK_SCIF3 18
+#define R8A7791_CLK_SCIF2 19
+#define R8A7791_CLK_SCIF1 20
+#define R8A7791_CLK_SCIF0 21
+#define R8A7791_CLK_DU1 23
+#define R8A7791_CLK_DU0 24
+#define R8A7791_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7791_CLK_IPMMU_SGX 0
+#define R8A7791_CLK_MLB 2
+#define R8A7791_CLK_VIN2 9
+#define R8A7791_CLK_VIN1 10
+#define R8A7791_CLK_VIN0 11
+#define R8A7791_CLK_ETHER 13
+#define R8A7791_CLK_SATA1 14
+#define R8A7791_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7791_CLK_GPIO7 4
+#define R8A7791_CLK_GPIO6 5
+#define R8A7791_CLK_GPIO5 7
+#define R8A7791_CLK_GPIO4 8
+#define R8A7791_CLK_GPIO3 9
+#define R8A7791_CLK_GPIO2 10
+#define R8A7791_CLK_GPIO1 11
+#define R8A7791_CLK_GPIO0 12
+#define R8A7791_CLK_RCAN1 15
+#define R8A7791_CLK_RCAN0 16
+#define R8A7791_CLK_QSPI_MOD 17
+#define R8A7791_CLK_I2C5 25
+#define R8A7791_CLK_IICDVFS 26
+#define R8A7791_CLK_I2C4 27
+#define R8A7791_CLK_I2C3 28
+#define R8A7791_CLK_I2C2 29
+#define R8A7791_CLK_I2C1 30
+#define R8A7791_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7791_CLK_SSI_ALL 5
+#define R8A7791_CLK_SSI9 6
+#define R8A7791_CLK_SSI8 7
+#define R8A7791_CLK_SSI7 8
+#define R8A7791_CLK_SSI6 9
+#define R8A7791_CLK_SSI5 10
+#define R8A7791_CLK_SSI4 11
+#define R8A7791_CLK_SSI3 12
+#define R8A7791_CLK_SSI2 13
+#define R8A7791_CLK_SSI1 14
+#define R8A7791_CLK_SSI0 15
+#define R8A7791_CLK_SCU_ALL 17
+#define R8A7791_CLK_SCU_DVC1 18
+#define R8A7791_CLK_SCU_DVC0 19
+#define R8A7791_CLK_SCU_SRC9 22
+#define R8A7791_CLK_SCU_SRC8 23
+#define R8A7791_CLK_SCU_SRC7 24
+#define R8A7791_CLK_SCU_SRC6 25
+#define R8A7791_CLK_SCU_SRC5 26
+#define R8A7791_CLK_SCU_SRC4 27
+#define R8A7791_CLK_SCU_SRC3 28
+#define R8A7791_CLK_SCU_SRC2 29
+#define R8A7791_CLK_SCU_SRC1 30
+#define R8A7791_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7791_CLK_SCIFA3 6
+#define R8A7791_CLK_SCIFA4 7
+#define R8A7791_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
new file mode 100644
index 000000000..d63323032
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
+#define __DT_BINDINGS_CLOCK_R8A7794_H__
+
+/* CPG */
+#define R8A7794_CLK_MAIN 0
+#define R8A7794_CLK_PLL0 1
+#define R8A7794_CLK_PLL1 2
+#define R8A7794_CLK_PLL3 3
+#define R8A7794_CLK_LB 4
+#define R8A7794_CLK_QSPI 5
+#define R8A7794_CLK_SDH 6
+#define R8A7794_CLK_SD0 7
+#define R8A7794_CLK_Z 8
+
+/* MSTP0 */
+#define R8A7794_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7794_CLK_VCP0 1
+#define R8A7794_CLK_VPC0 3
+#define R8A7794_CLK_TMU1 11
+#define R8A7794_CLK_3DG 12
+#define R8A7794_CLK_2DDMAC 15
+#define R8A7794_CLK_FDP1_0 19
+#define R8A7794_CLK_TMU3 21
+#define R8A7794_CLK_TMU2 22
+#define R8A7794_CLK_CMT0 24
+#define R8A7794_CLK_TMU0 25
+#define R8A7794_CLK_VSP1_DU0 28
+#define R8A7794_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7794_CLK_SCIFA2 2
+#define R8A7794_CLK_SCIFA1 3
+#define R8A7794_CLK_SCIFA0 4
+#define R8A7794_CLK_MSIOF2 5
+#define R8A7794_CLK_SCIFB0 6
+#define R8A7794_CLK_SCIFB1 7
+#define R8A7794_CLK_MSIOF1 8
+#define R8A7794_CLK_SCIFB2 16
+#define R8A7794_CLK_SYS_DMAC1 18
+#define R8A7794_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7794_CLK_SDHI2 11
+#define R8A7794_CLK_SDHI1 12
+#define R8A7794_CLK_SDHI0 14
+#define R8A7794_CLK_MMCIF0 15
+#define R8A7794_CLK_CMT1 29
+#define R8A7794_CLK_USBDMAC0 30
+#define R8A7794_CLK_USBDMAC1 31
+
+/* MSTP5 */
+#define R8A7794_CLK_THERMAL 22
+#define R8A7794_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7794_CLK_EHCI 3
+#define R8A7794_CLK_HSUSB 4
+#define R8A7794_CLK_HSCIF2 13
+#define R8A7794_CLK_SCIF5 14
+#define R8A7794_CLK_SCIF4 15
+#define R8A7794_CLK_HSCIF1 16
+#define R8A7794_CLK_HSCIF0 17
+#define R8A7794_CLK_SCIF3 18
+#define R8A7794_CLK_SCIF2 19
+#define R8A7794_CLK_SCIF1 20
+#define R8A7794_CLK_SCIF0 21
+
+/* MSTP8 */
+#define R8A7794_CLK_VIN1 10
+#define R8A7794_CLK_VIN0 11
+#define R8A7794_CLK_ETHER 13
+
+/* MSTP9 */
+#define R8A7794_CLK_GPIO6 5
+#define R8A7794_CLK_GPIO5 7
+#define R8A7794_CLK_GPIO4 8
+#define R8A7794_CLK_GPIO3 9
+#define R8A7794_CLK_GPIO2 10
+#define R8A7794_CLK_GPIO1 11
+#define R8A7794_CLK_GPIO0 12
+#define R8A7794_CLK_QSPI_MOD 17
+#define R8A7794_CLK_I2C5 25
+#define R8A7794_CLK_I2C4 27
+#define R8A7794_CLK_I2C3 28
+#define R8A7794_CLK_I2C2 29
+#define R8A7794_CLK_I2C1 30
+#define R8A7794_CLK_I2C0 31
+
+/* MSTP11 */
+#define R8A7794_CLK_SCIFA3 6
+#define R8A7794_CLK_SCIFA4 7
+#define R8A7794_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 000000000..bc1ed1dbd
--- /dev/null
+++ b/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_SRST1 0
+#define SRST_SRST2 1
+
+#define SRST_L2MEM 18
+#define SRST_I2S0 23
+#define SRST_I2S1 24
+#define SRST_I2S2 25
+#define SRST_TIMER2 29
+
+#define SRST_GPIO4 36
+#define SRST_GPIO6 38
+
+#define SRST_TSADC 92
+
+#define SRST_HDMI 96
+#define SRST_HDMI_APB 97
+#define SRST_CIF1 111
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 000000000..6a370503c
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* core clocks from */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define CORE_PERI 5
+#define CORE_L2C 6
+#define ARMCLK 7
+
+/* sclk gates (special clocks) */
+#define SCLK_UART0 64
+#define SCLK_UART1 65
+#define SCLK_UART2 66
+#define SCLK_UART3 67
+#define SCLK_MAC 68
+#define SCLK_SPI0 69
+#define SCLK_SPI1 70
+#define SCLK_SARADC 71
+#define SCLK_SDMMC 72
+#define SCLK_SDIO 73
+#define SCLK_EMMC 74
+#define SCLK_I2S0 75
+#define SCLK_I2S1 76
+#define SCLK_I2S2 77
+#define SCLK_SPDIF 78
+#define SCLK_CIF0 79
+#define SCLK_CIF1 80
+#define SCLK_OTGPHY0 81
+#define SCLK_OTGPHY1 82
+#define SCLK_HSADC 83
+#define SCLK_TIMER0 84
+#define SCLK_TIMER1 85
+#define SCLK_TIMER2 86
+#define SCLK_TIMER3 87
+#define SCLK_TIMER4 88
+#define SCLK_TIMER5 89
+#define SCLK_TIMER6 90
+#define SCLK_JTAG 91
+#define SCLK_SMC 92
+
+#define DCLK_LCDC0 190
+#define DCLK_LCDC1 191
+
+/* aclk gates */
+#define ACLK_DMA1 192
+#define ACLK_DMA2 193
+#define ACLK_GPS 194
+#define ACLK_LCDC0 195
+#define ACLK_LCDC1 196
+#define ACLK_GPU 197
+#define ACLK_SMC 198
+#define ACLK_CIF 199
+#define ACLK_IPP 200
+#define ACLK_RGA 201
+#define ACLK_CIF0 202
+
+/* pclk gates */
+#define PCLK_GRF 320
+#define PCLK_PMU 321
+#define PCLK_TIMER0 322
+#define PCLK_TIMER1 323
+#define PCLK_TIMER2 324
+#define PCLK_TIMER3 325
+#define PCLK_PWM01 326
+#define PCLK_PWM23 327
+#define PCLK_SPI0 328
+#define PCLK_SPI1 329
+#define PCLK_SARADC 330
+#define PCLK_WDT 331
+#define PCLK_UART0 332
+#define PCLK_UART1 333
+#define PCLK_UART2 334
+#define PCLK_UART3 335
+#define PCLK_I2C0 336
+#define PCLK_I2C1 337
+#define PCLK_I2C2 338
+#define PCLK_I2C3 339
+#define PCLK_I2C4 340
+#define PCLK_GPIO0 341
+#define PCLK_GPIO1 342
+#define PCLK_GPIO2 343
+#define PCLK_GPIO3 344
+#define PCLK_GPIO4 345
+#define PCLK_GPIO6 346
+#define PCLK_EFUSE 347
+#define PCLK_TZPC 348
+#define PCLK_TSADC 349
+
+/* hclk gates */
+#define HCLK_SDMMC 448
+#define HCLK_SDIO 449
+#define HCLK_EMMC 450
+#define HCLK_OTG0 451
+#define HCLK_EMAC 452
+#define HCLK_SPDIF 453
+#define HCLK_I2S0 454
+#define HCLK_I2S1 455
+#define HCLK_I2S2 456
+#define HCLK_OTG1 457
+#define HCLK_HSIC 458
+#define HCLK_HSADC 459
+#define HCLK_PIDF 460
+#define HCLK_LCDC0 461
+#define HCLK_LCDC1 462
+#define HCLK_ROM 463
+#define HCLK_CIF0 464
+#define HCLK_IPP 465
+#define HCLK_RGA 466
+#define HCLK_NANDC0 467
+
+#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
+
+/* soft-reset indices */
+#define SRST_MCORE 2
+#define SRST_CORE0 3
+#define SRST_CORE1 4
+#define SRST_MCORE_DBG 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE0_WDT 12
+#define SRST_CORE1_WDT 13
+#define SRST_STRC_SYS 14
+#define SRST_L2C 15
+
+#define SRST_CPU_AHB 17
+#define SRST_AHB2APB 19
+#define SRST_DMA1 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_SPDIF 26
+#define SRST_TIMER0 27
+#define SRST_TIMER1 28
+#define SRST_EFUSE 30
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_UART3 42
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_I2C3 46
+#define SRST_I2C4 47
+
+#define SRST_PWM0 48
+#define SRST_PWM1 49
+#define SRST_DAP_PO 50
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_TPIU_ATB 53
+#define SRST_PMU_APB 54
+#define SRST_GRF 55
+#define SRST_PMU 56
+#define SRST_PERI_AXI 57
+#define SRST_PERI_AHB 58
+#define SRST_PERI_APB 59
+#define SRST_PERI_NIU 60
+#define SRST_CPU_PERI 61
+#define SRST_EMEM_PERI 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMA2 64
+#define SRST_SMC 65
+#define SRST_MAC 66
+#define SRST_NANC0 68
+#define SRST_USBOTG0 69
+#define SRST_USBPHY0 70
+#define SRST_OTGC0 71
+#define SRST_USBOTG1 72
+#define SRST_USBPHY1 73
+#define SRST_OTGC1 74
+#define SRST_HSADC 76
+#define SRST_PIDFILTER 77
+#define SRST_DDR_MSCH 79
+
+#define SRST_TZPC 80
+#define SRST_SDMMC 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI0 84
+#define SRST_SPI1 85
+#define SRST_WDT 86
+#define SRST_SARADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_APB 89
+#define SRST_DDRCTL 90
+#define SRST_DDRCTL_APB 91
+#define SRST_DDRPUB 93
+
+#define SRST_VIO0_AXI 98
+#define SRST_VIO0_AHB 99
+#define SRST_LCDC0_AXI 100
+#define SRST_LCDC0_AHB 101
+#define SRST_LCDC0_DCLK 102
+#define SRST_LCDC1_AXI 103
+#define SRST_LCDC1_AHB 104
+#define SRST_LCDC1_DCLK 105
+#define SRST_IPP_AXI 106
+#define SRST_IPP_AHB 107
+#define SRST_RGA_AXI 108
+#define SRST_RGA_AHB 109
+#define SRST_CIF0 110
+
+#define SRST_VCODEC_AXI 112
+#define SRST_VCODEC_AHB 113
+#define SRST_VIO1_AXI 114
+#define SRST_VCODEC_CPU 115
+#define SRST_VCODEC_NIU 116
+#define SRST_GPU 120
+#define SRST_GPU_NIU 122
+#define SRST_TFUN_ATB 125
+#define SRST_TFUN_APB 126
+#define SRST_CTI4_APB 127
+
+#define SRST_TPIU_APB 128
+#define SRST_TRACE 129
+#define SRST_CORE_DBG 130
+#define SRST_DBG_APB 131
+#define SRST_CTI0 132
+#define SRST_CTI0_APB 133
+#define SRST_CTI1 134
+#define SRST_CTI1_APB 135
+#define SRST_PTM_CORE0 136
+#define SRST_PTM_CORE1 137
+#define SRST_PTM0 138
+#define SRST_PTM0_ATB 139
+#define SRST_PTM1 140
+#define SRST_PTM1_ATB 141
+#define SRST_CTM 142
+#define SRST_TS 143
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 000000000..9fac8edd3
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/rk3188-cru-common.h>
+
+/* soft-reset indices */
+#define SRST_PTM_CORE2 0
+#define SRST_PTM_CORE3 1
+#define SRST_CORE2 5
+#define SRST_CORE3 6
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+
+#define SRST_TIMER2 16
+#define SRST_TIMER4 23
+#define SRST_I2S0 24
+#define SRST_TIMER5 25
+#define SRST_TIMER3 29
+#define SRST_TIMER6 31
+
+#define SRST_PTM3 36
+#define SRST_PTM3_ATB 37
+
+#define SRST_GPS 67
+#define SRST_HSICPHY 75
+#define SRST_TIMER 78
+
+#define SRST_PTM2 92
+#define SRST_CORE2_WDT 94
+#define SRST_CORE3_WDT 95
+
+#define SRST_PTM2_ATB 111
+
+#define SRST_HSIC 117
+#define SRST_CTI2 118
+#define SRST_CTI2_APB 119
+#define SRST_GPU_BRIDGE 121
+#define SRST_CTI3 123
+#define SRST_CTI3_APB 124
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 000000000..dea419708
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,378 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define PLL_NPLL 5
+#define ARMCLK 6
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU 64
+#define SCLK_SPI0 65
+#define SCLK_SPI1 66
+#define SCLK_SPI2 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO0 69
+#define SCLK_SDIO1 70
+#define SCLK_EMMC 71
+#define SCLK_TSADC 72
+#define SCLK_SARADC 73
+#define SCLK_PS2C 74
+#define SCLK_NANDC0 75
+#define SCLK_NANDC1 76
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_UART3 80
+#define SCLK_UART4 81
+#define SCLK_I2S0 82
+#define SCLK_SPDIF 83
+#define SCLK_SPDIF8CH 84
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_TIMER4 89
+#define SCLK_TIMER5 90
+#define SCLK_TIMER6 91
+#define SCLK_HSADC 92
+#define SCLK_OTGPHY0 93
+#define SCLK_OTGPHY1 94
+#define SCLK_OTGPHY2 95
+#define SCLK_OTG_ADP 96
+#define SCLK_HSICPHY480M 97
+#define SCLK_HSICPHY12M 98
+#define SCLK_MACREF 99
+#define SCLK_LCDC_PWM0 100
+#define SCLK_LCDC_PWM1 101
+#define SCLK_MAC_RX 102
+#define SCLK_MAC_TX 103
+#define SCLK_EDP_24M 104
+#define SCLK_EDP 105
+#define SCLK_RGA 106
+#define SCLK_ISP 107
+#define SCLK_ISP_JPE 108
+#define SCLK_HDMI_HDCP 109
+#define SCLK_HDMI_CEC 110
+#define SCLK_HEVC_CABAC 111
+#define SCLK_HEVC_CORE 112
+#define SCLK_I2S0_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO0_DRV 115
+#define SCLK_SDIO1_DRV 116
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO0_SAMPLE 119
+#define SCLK_SDIO1_SAMPLE 120
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_USBPHY480M_SRC 122
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+
+#define SCLK_MAC 151
+#define SCLK_MACREF_OUT 152
+
+#define DCLK_VOP0 190
+#define DCLK_VOP1 191
+
+/* aclk gates */
+#define ACLK_GPU 192
+#define ACLK_DMAC1 193
+#define ACLK_DMAC2 194
+#define ACLK_MMU 195
+#define ACLK_GMAC 196
+#define ACLK_VOP0 197
+#define ACLK_VOP1 198
+#define ACLK_CRYPTO 199
+#define ACLK_RGA 200
+#define ACLK_RGA_NIU 201
+#define ACLK_IEP 202
+#define ACLK_VIO0_NIU 203
+#define ACLK_VIP 204
+#define ACLK_ISP 205
+#define ACLK_VIO1_NIU 206
+#define ACLK_HEVC 207
+#define ACLK_VCODEC 208
+#define ACLK_CPU 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_GPIO4 324
+#define PCLK_GPIO5 325
+#define PCLK_GPIO6 326
+#define PCLK_GPIO7 327
+#define PCLK_GPIO8 328
+#define PCLK_GRF 329
+#define PCLK_SGRF 330
+#define PCLK_PMU 331
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_I2C4 336
+#define PCLK_I2C5 337
+#define PCLK_SPI0 338
+#define PCLK_SPI1 339
+#define PCLK_SPI2 340
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_UART3 344
+#define PCLK_UART4 345
+#define PCLK_TSADC 346
+#define PCLK_SARADC 347
+#define PCLK_SIM 348
+#define PCLK_GMAC 349
+#define PCLK_PWM 350
+#define PCLK_RKPWM 351
+#define PCLK_PS2C 352
+#define PCLK_TIMER 353
+#define PCLK_TZPC 354
+#define PCLK_EDP_CTRL 355
+#define PCLK_MIPI_DSI0 356
+#define PCLK_MIPI_DSI1 357
+#define PCLK_MIPI_CSI 358
+#define PCLK_LVDS_PHY 359
+#define PCLK_HDMI_CTRL 360
+#define PCLK_VIO2_H2P 361
+#define PCLK_CPU 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL0 364
+#define PCLK_PUBL0 365
+#define PCLK_DDRUPCTL1 366
+#define PCLK_PUBL1 367
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_GPS 448
+#define HCLK_OTG0 449
+#define HCLK_USBHOST0 450
+#define HCLK_USBHOST1 451
+#define HCLK_HSIC 452
+#define HCLK_NANDC0 453
+#define HCLK_NANDC1 454
+#define HCLK_TSP 455
+#define HCLK_SDMMC 456
+#define HCLK_SDIO0 457
+#define HCLK_SDIO1 458
+#define HCLK_EMMC 459
+#define HCLK_HSADC 460
+#define HCLK_CRYPTO 461
+#define HCLK_I2S0 462
+#define HCLK_SPDIF 463
+#define HCLK_SPDIF8CH 464
+#define HCLK_VOP0 465
+#define HCLK_VOP1 466
+#define HCLK_ROM 467
+#define HCLK_IEP 468
+#define HCLK_ISP 469
+#define HCLK_RGA 470
+#define HCLK_VIO_AHB_ARBI 471
+#define HCLK_VIO_NIU 472
+#define HCLK_VIP 473
+#define HCLK_VIO2_H2P 474
+#define HCLK_HEVC 475
+#define HCLK_VCODEC 476
+#define HCLK_CPU 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0 0
+#define SRST_CORE1 1
+#define SRST_CORE2 2
+#define SRST_CORE3 3
+#define SRST_CORE0_PO 4
+#define SRST_CORE1_PO 5
+#define SRST_CORE2_PO 6
+#define SRST_CORE3_PO 7
+#define SRST_PDCORE_STRSYS 8
+#define SRST_PDBUS_STRSYS 9
+#define SRST_L2C 10
+#define SRST_TOPDBG 11
+#define SRST_CORE0_DBG 12
+#define SRST_CORE1_DBG 13
+#define SRST_CORE2_DBG 14
+#define SRST_CORE3_DBG 15
+
+#define SRST_PDBUG_AHB_ARBITOR 16
+#define SRST_EFUSE256 17
+#define SRST_DMAC1 18
+#define SRST_INTMEM 19
+#define SRST_ROM 20
+#define SRST_SPDIF8CH 21
+#define SRST_TIMER 22
+#define SRST_I2S0 23
+#define SRST_SPDIF 24
+#define SRST_TIMER0 25
+#define SRST_TIMER1 26
+#define SRST_TIMER2 27
+#define SRST_TIMER3 28
+#define SRST_TIMER4 29
+#define SRST_TIMER5 30
+#define SRST_EFUSE 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+#define SRST_GPIO4 36
+#define SRST_GPIO5 37
+#define SRST_GPIO6 38
+#define SRST_GPIO7 39
+#define SRST_GPIO8 40
+#define SRST_I2C0 42
+#define SRST_I2C1 43
+#define SRST_I2C2 44
+#define SRST_I2C3 45
+#define SRST_I2C4 46
+#define SRST_I2C5 47
+
+#define SRST_DWPWM 48
+#define SRST_MMC_PERI 49
+#define SRST_PERIPH_MMU 50
+#define SRST_DAP 51
+#define SRST_DAP_SYS 52
+#define SRST_TPIU 53
+#define SRST_PMU_APB 54
+#define SRST_GRF 55
+#define SRST_PMU 56
+#define SRST_PERIPH_AXI 57
+#define SRST_PERIPH_AHB 58
+#define SRST_PERIPH_APB 59
+#define SRST_PERIPH_NIU 60
+#define SRST_PDPERI_AHB_ARBI 61
+#define SRST_EMEM 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMAC2 64
+#define SRST_MAC 66
+#define SRST_GPS 67
+#define SRST_RKPWM 69
+#define SRST_CCP 71
+#define SRST_USBHOST0 72
+#define SRST_HSIC 73
+#define SRST_HSIC_AUX 74
+#define SRST_HSIC_PHY 75
+#define SRST_HSADC 76
+#define SRST_NANDC0 77
+#define SRST_NANDC1 78
+
+#define SRST_TZPC 80
+#define SRST_SPI0 83
+#define SRST_SPI1 84
+#define SRST_SPI2 85
+#define SRST_SARADC 87
+#define SRST_PDALIVE_NIU 88
+#define SRST_PDPMU_INTMEM 89
+#define SRST_PDPMU_NIU 90
+#define SRST_SGRF 91
+
+#define SRST_VIO_ARBI 96
+#define SRST_RGA_NIU 97
+#define SRST_VIO0_NIU_AXI 98
+#define SRST_VIO_NIU_AHB 99
+#define SRST_LCDC0_AXI 100
+#define SRST_LCDC0_AHB 101
+#define SRST_LCDC0_DCLK 102
+#define SRST_VIO1_NIU_AXI 103
+#define SRST_VIP 104
+#define SRST_RGA_CORE 105
+#define SRST_IEP_AXI 106
+#define SRST_IEP_AHB 107
+#define SRST_RGA_AXI 108
+#define SRST_RGA_AHB 109
+#define SRST_ISP 110
+#define SRST_EDP 111
+
+#define SRST_VCODEC_AXI 112
+#define SRST_VCODEC_AHB 113
+#define SRST_VIO_H2P 114
+#define SRST_MIPIDSI0 115
+#define SRST_MIPIDSI1 116
+#define SRST_MIPICSI 117
+#define SRST_LVDS_PHY 118
+#define SRST_LVDS_CON 119
+#define SRST_GPU 120
+#define SRST_HDMI 121
+#define SRST_CORE_PVTM 124
+#define SRST_GPU_PVTM 125
+
+#define SRST_MMC0 128
+#define SRST_SDIO0 129
+#define SRST_SDIO1 130
+#define SRST_EMMC 131
+#define SRST_USBOTG_AHB 132
+#define SRST_USBOTG_PHY 133
+#define SRST_USBOTG_CON 134
+#define SRST_USBHOST0_AHB 135
+#define SRST_USBHOST0_PHY 136
+#define SRST_USBHOST0_CON 137
+#define SRST_USBHOST1_AHB 138
+#define SRST_USBHOST1_PHY 139
+#define SRST_USBHOST1_CON 140
+#define SRST_USB_ADP 141
+#define SRST_ACC_EFUSE 142
+
+#define SRST_CORESIGHT 144
+#define SRST_PD_CORE_AHB_NOC 145
+#define SRST_PD_CORE_APB_NOC 146
+#define SRST_PD_CORE_MP_AXI 147
+#define SRST_GIC 148
+#define SRST_LCDC_PWM0 149
+#define SRST_LCDC_PWM1 150
+#define SRST_VIO0_H2P_BRG 151
+#define SRST_VIO1_H2P_BRG 152
+#define SRST_RGA_H2P_BRG 153
+#define SRST_HEVC 154
+#define SRST_TSADC 159
+
+#define SRST_DDRPHY0 160
+#define SRST_DDRPHY0_APB 161
+#define SRST_DDRCTRL0 162
+#define SRST_DDRCTRL0_APB 163
+#define SRST_DDRPHY0_CTRL 164
+#define SRST_DDRPHY1 165
+#define SRST_DDRPHY1_APB 166
+#define SRST_DDRCTRL1 167
+#define SRST_DDRCTRL1_APB 168
+#define SRST_DDRPHY1_CTRL 169
+#define SRST_DDRMSCH0 170
+#define SRST_DDRMSCH1 171
+#define SRST_CRYPTO 174
+#define SRST_C2C_HOST 175
+
+#define SRST_LCDC1_AXI 176
+#define SRST_LCDC1_AHB 177
+#define SRST_LCDC1_DCLK 178
+#define SRST_UART0 179
+#define SRST_UART1 180
+#define SRST_UART2 181
+#define SRST_UART3 182
+#define SRST_UART4 183
+#define SRST_SIMC 186
+#define SRST_PS2C 187
+#define SRST_TSP 188
+#define SRST_TSP_CLKIN0 189
+#define SRST_TSP_CLKIN1 190
+#define SRST_TSP_27M 191
diff --git a/include/dt-bindings/clock/rockchip,rk808.h b/include/dt-bindings/clock/rockchip,rk808.h
new file mode 100644
index 000000000..1a873432f
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk808.h
@@ -0,0 +1,11 @@
+/*
+ * This header provides constants clk index RK808 pmic clkout
+ */
+#ifndef _CLK_ROCKCHIP_RK808
+#define _CLK_ROCKCHIP_RK808
+
+/* CLOCKOUT index */
+#define RK808_CLKOUT0 0
+#define RK808_CLKOUT1 1
+
+#endif
diff --git a/include/dt-bindings/clock/s3c2410.h b/include/dt-bindings/clock/s3c2410.h
new file mode 100644
index 000000000..352a7673f
--- /dev/null
+++ b/include/dt-bindings/clock/s3c2410.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+
+/* id 1 is reserved */
+#define MPLL 2
+#define UPLL 3
+#define FCLK 4
+#define HCLK 5
+#define PCLK 6
+#define UCLK 7
+#define ARMCLK 8
+
+/* pclk-gates */
+#define PCLK_UART0 16
+#define PCLK_UART1 17
+#define PCLK_UART2 18
+#define PCLK_I2C 19
+#define PCLK_SDI 20
+#define PCLK_SPI 21
+#define PCLK_ADC 22
+#define PCLK_AC97 23
+#define PCLK_I2S 24
+#define PCLK_PWM 25
+#define PCLK_RTC 26
+#define PCLK_GPIO 27
+
+
+/* hclk-gates */
+#define HCLK_LCD 32
+#define HCLK_USBH 33
+#define HCLK_USBD 34
+#define HCLK_NAND 35
+#define HCLK_CAM 36
+
+
+#define CAMIF 40
+
+
+/* Total number of clocks. */
+#define NR_CLKS (CAMIF + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
diff --git a/include/dt-bindings/clock/s3c2412.h b/include/dt-bindings/clock/s3c2412.h
new file mode 100644
index 000000000..aac1dcfda
--- /dev/null
+++ b/include/dt-bindings/clock/s3c2412.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2412.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+
+/* id 1 is reserved */
+#define MPLL 2
+#define UPLL 3
+#define MDIVCLK 4
+#define MSYSCLK 5
+#define USYSCLK 6
+#define HCLK 7
+#define PCLK 8
+#define ARMDIV 9
+#define ARMCLK 10
+
+
+/* Special clocks */
+#define SCLK_CAM 16
+#define SCLK_UART 17
+#define SCLK_I2S 18
+#define SCLK_USBD 19
+#define SCLK_USBH 20
+
+/* pclk-gates */
+#define PCLK_WDT 32
+#define PCLK_SPI 33
+#define PCLK_I2S 34
+#define PCLK_I2C 35
+#define PCLK_ADC 36
+#define PCLK_RTC 37
+#define PCLK_GPIO 38
+#define PCLK_UART2 39
+#define PCLK_UART1 40
+#define PCLK_UART0 41
+#define PCLK_SDI 42
+#define PCLK_PWM 43
+#define PCLK_USBD 44
+
+/* hclk-gates */
+#define HCLK_HALF 48
+#define HCLK_X2 49
+#define HCLK_SDRAM 50
+#define HCLK_USBH 51
+#define HCLK_LCD 52
+#define HCLK_NAND 53
+#define HCLK_DMA3 54
+#define HCLK_DMA2 55
+#define HCLK_DMA1 56
+#define HCLK_DMA0 57
+
+/* Total number of clocks. */
+#define NR_CLKS (HCLK_DMA0 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */
diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
new file mode 100644
index 000000000..37e66b054
--- /dev/null
+++ b/include/dt-bindings/clock/s3c2443.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+#define MSYSCLK 1
+#define ESYSCLK 2
+#define ARMDIV 3
+#define ARMCLK 4
+#define HCLK 5
+#define PCLK 6
+
+/* Special clocks */
+#define SCLK_HSSPI0 16
+#define SCLK_FIMD 17
+#define SCLK_I2S0 18
+#define SCLK_I2S1 19
+#define SCLK_HSMMC1 20
+#define SCLK_HSMMC_EXT 21
+#define SCLK_CAM 22
+#define SCLK_UART 23
+#define SCLK_USBH 24
+
+/* Muxes */
+#define MUX_HSSPI0 32
+#define MUX_HSSPI1 33
+#define MUX_HSMMC0 34
+#define MUX_HSMMC1 35
+
+/* hclk-gates */
+#define HCLK_DMA0 48
+#define HCLK_DMA1 49
+#define HCLK_DMA2 50
+#define HCLK_DMA3 51
+#define HCLK_DMA4 52
+#define HCLK_DMA5 53
+#define HCLK_DMA6 54
+#define HCLK_DMA7 55
+#define HCLK_CAM 56
+#define HCLK_LCD 57
+#define HCLK_USBH 58
+#define HCLK_USBD 59
+#define HCLK_IROM 60
+#define HCLK_HSMMC0 61
+#define HCLK_HSMMC1 62
+#define HCLK_CFC 63
+#define HCLK_SSMC 64
+#define HCLK_DRAM 65
+#define HCLK_2D 66
+
+/* pclk-gates */
+#define PCLK_UART0 72
+#define PCLK_UART1 73
+#define PCLK_UART2 74
+#define PCLK_UART3 75
+#define PCLK_I2C0 76
+#define PCLK_SDI 77
+#define PCLK_SPI0 78
+#define PCLK_ADC 79
+#define PCLK_AC97 80
+#define PCLK_I2S0 81
+#define PCLK_PWM 82
+#define PCLK_WDT 83
+#define PCLK_RTC 84
+#define PCLK_GPIO 85
+#define PCLK_SPI1 86
+#define PCLK_CHIPID 87
+#define PCLK_I2C1 88
+#define PCLK_I2S1 89
+#define PCLK_PCM 90
+
+/* Total number of clocks. */
+#define NR_CLKS (PCLK_PCM + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
diff --git a/include/dt-bindings/clock/s5pv210-audss.h b/include/dt-bindings/clock/s5pv210-audss.h
new file mode 100644
index 000000000..fe57406e2
--- /dev/null
+++ b/include/dt-bindings/clock/s5pv210-audss.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and s5pv210 audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
+
+#define CLK_MOUT_AUDSS 0
+#define CLK_MOUT_I2S_A 1
+
+#define CLK_DOUT_AUD_BUS 2
+#define CLK_DOUT_I2S_A 3
+
+#define CLK_I2S 4
+#define CLK_HCLK_I2S 5
+#define CLK_HCLK_UART 6
+#define CLK_HCLK_HWA 7
+#define CLK_HCLK_DMA 8
+#define CLK_HCLK_BUF 9
+#define CLK_HCLK_RP 10
+
+#define AUDSS_MAX_CLKS 11
+
+#endif
diff --git a/include/dt-bindings/clock/s5pv210.h b/include/dt-bindings/clock/s5pv210.h
new file mode 100644
index 000000000..e88986b7c
--- /dev/null
+++ b/include/dt-bindings/clock/s5pv210.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S5PV210 clock controller.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
+#define _DT_BINDINGS_CLOCK_S5PV210_H
+
+/* Core clocks. */
+#define FIN_PLL 1
+#define FOUT_APLL 2
+#define FOUT_MPLL 3
+#define FOUT_EPLL 4
+#define FOUT_VPLL 5
+
+/* Muxes. */
+#define MOUT_FLASH 6
+#define MOUT_PSYS 7
+#define MOUT_DSYS 8
+#define MOUT_MSYS 9
+#define MOUT_VPLL 10
+#define MOUT_EPLL 11
+#define MOUT_MPLL 12
+#define MOUT_APLL 13
+#define MOUT_VPLLSRC 14
+#define MOUT_CSIS 15
+#define MOUT_FIMD 16
+#define MOUT_CAM1 17
+#define MOUT_CAM0 18
+#define MOUT_DAC 19
+#define MOUT_MIXER 20
+#define MOUT_HDMI 21
+#define MOUT_G2D 22
+#define MOUT_MFC 23
+#define MOUT_G3D 24
+#define MOUT_FIMC2 25
+#define MOUT_FIMC1 26
+#define MOUT_FIMC0 27
+#define MOUT_UART3 28
+#define MOUT_UART2 29
+#define MOUT_UART1 30
+#define MOUT_UART0 31
+#define MOUT_MMC3 32
+#define MOUT_MMC2 33
+#define MOUT_MMC1 34
+#define MOUT_MMC0 35
+#define MOUT_PWM 36
+#define MOUT_SPI0 37
+#define MOUT_SPI1 38
+#define MOUT_DMC0 39
+#define MOUT_PWI 40
+#define MOUT_HPM 41
+#define MOUT_SPDIF 42
+#define MOUT_AUDIO2 43
+#define MOUT_AUDIO1 44
+#define MOUT_AUDIO0 45
+
+/* Dividers. */
+#define DOUT_PCLKP 46
+#define DOUT_HCLKP 47
+#define DOUT_PCLKD 48
+#define DOUT_HCLKD 49
+#define DOUT_PCLKM 50
+#define DOUT_HCLKM 51
+#define DOUT_A2M 52
+#define DOUT_APLL 53
+#define DOUT_CSIS 54
+#define DOUT_FIMD 55
+#define DOUT_CAM1 56
+#define DOUT_CAM0 57
+#define DOUT_TBLK 58
+#define DOUT_G2D 59
+#define DOUT_MFC 60
+#define DOUT_G3D 61
+#define DOUT_FIMC2 62
+#define DOUT_FIMC1 63
+#define DOUT_FIMC0 64
+#define DOUT_UART3 65
+#define DOUT_UART2 66
+#define DOUT_UART1 67
+#define DOUT_UART0 68
+#define DOUT_MMC3 69
+#define DOUT_MMC2 70
+#define DOUT_MMC1 71
+#define DOUT_MMC0 72
+#define DOUT_PWM 73
+#define DOUT_SPI1 74
+#define DOUT_SPI0 75
+#define DOUT_DMC0 76
+#define DOUT_PWI 77
+#define DOUT_HPM 78
+#define DOUT_COPY 79
+#define DOUT_FLASH 80
+#define DOUT_AUDIO2 81
+#define DOUT_AUDIO1 82
+#define DOUT_AUDIO0 83
+#define DOUT_DPM 84
+#define DOUT_DVSEM 85
+
+/* Gates */
+#define SCLK_FIMC 86
+#define CLK_CSIS 87
+#define CLK_ROTATOR 88
+#define CLK_FIMC2 89
+#define CLK_FIMC1 90
+#define CLK_FIMC0 91
+#define CLK_MFC 92
+#define CLK_G2D 93
+#define CLK_G3D 94
+#define CLK_IMEM 95
+#define CLK_PDMA1 96
+#define CLK_PDMA0 97
+#define CLK_MDMA 98
+#define CLK_DMC1 99
+#define CLK_DMC0 100
+#define CLK_NFCON 101
+#define CLK_SROMC 102
+#define CLK_CFCON 103
+#define CLK_NANDXL 104
+#define CLK_USB_HOST 105
+#define CLK_USB_OTG 106
+#define CLK_HDMI 107
+#define CLK_TVENC 108
+#define CLK_MIXER 109
+#define CLK_VP 110
+#define CLK_DSIM 111
+#define CLK_FIMD 112
+#define CLK_TZIC3 113
+#define CLK_TZIC2 114
+#define CLK_TZIC1 115
+#define CLK_TZIC0 116
+#define CLK_VIC3 117
+#define CLK_VIC2 118
+#define CLK_VIC1 119
+#define CLK_VIC0 120
+#define CLK_TSI 121
+#define CLK_HSMMC3 122
+#define CLK_HSMMC2 123
+#define CLK_HSMMC1 124
+#define CLK_HSMMC0 125
+#define CLK_JTAG 126
+#define CLK_MODEMIF 127
+#define CLK_CORESIGHT 128
+#define CLK_SDM 129
+#define CLK_SECSS 130
+#define CLK_PCM2 131
+#define CLK_PCM1 132
+#define CLK_PCM0 133
+#define CLK_SYSCON 134
+#define CLK_GPIO 135
+#define CLK_TSADC 136
+#define CLK_PWM 137
+#define CLK_WDT 138
+#define CLK_KEYIF 139
+#define CLK_UART3 140
+#define CLK_UART2 141
+#define CLK_UART1 142
+#define CLK_UART0 143
+#define CLK_SYSTIMER 144
+#define CLK_RTC 145
+#define CLK_SPI1 146
+#define CLK_SPI0 147
+#define CLK_I2C_HDMI_PHY 148
+#define CLK_I2C1 149
+#define CLK_I2C2 150
+#define CLK_I2C0 151
+#define CLK_I2S1 152
+#define CLK_I2S2 153
+#define CLK_I2S0 154
+#define CLK_AC97 155
+#define CLK_SPDIF 156
+#define CLK_TZPC3 157
+#define CLK_TZPC2 158
+#define CLK_TZPC1 159
+#define CLK_TZPC0 160
+#define CLK_SECKEY 161
+#define CLK_IEM_APC 162
+#define CLK_IEM_IEC 163
+#define CLK_CHIPID 164
+#define CLK_JPEG 163
+
+/* Special clocks*/
+#define SCLK_PWI 164
+#define SCLK_SPDIF 165
+#define SCLK_AUDIO2 166
+#define SCLK_AUDIO1 167
+#define SCLK_AUDIO0 168
+#define SCLK_PWM 169
+#define SCLK_SPI1 170
+#define SCLK_SPI0 171
+#define SCLK_UART3 172
+#define SCLK_UART2 173
+#define SCLK_UART1 174
+#define SCLK_UART0 175
+#define SCLK_MMC3 176
+#define SCLK_MMC2 177
+#define SCLK_MMC1 178
+#define SCLK_MMC0 179
+#define SCLK_FINVPLL 180
+#define SCLK_CSIS 181
+#define SCLK_FIMD 182
+#define SCLK_CAM1 183
+#define SCLK_CAM0 184
+#define SCLK_DAC 185
+#define SCLK_MIXER 186
+#define SCLK_HDMI 187
+#define SCLK_FIMC2 188
+#define SCLK_FIMC1 189
+#define SCLK_FIMC0 190
+#define SCLK_HDMI27M 191
+#define SCLK_HDMIPHY 192
+#define SCLK_USBPHY0 193
+#define SCLK_USBPHY1 194
+
+/* S5P6442-specific clocks */
+#define MOUT_D0SYNC 195
+#define MOUT_D1SYNC 196
+#define DOUT_MIXER 197
+#define CLK_ETB 198
+#define CLK_ETM 199
+
+/* CLKOUT */
+#define FOUT_APLL_CLKOUT 200
+#define FOUT_MPLL_CLKOUT 201
+#define DOUT_APLL_CLKOUT 202
+#define MOUT_CLKSEL 203
+#define DOUT_CLKOUT 204
+#define MOUT_CLKOUT 205
+
+/* Total number of clocks. */
+#define NR_CLKS 206
+
+#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */
diff --git a/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/include/dt-bindings/clock/samsung,s3c64xx-clock.h
new file mode 100644
index 000000000..ad95c7f50
--- /dev/null
+++ b/include/dt-bindings/clock/samsung,s3c64xx-clock.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for Samsung S3C64xx clock controller.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
+#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
+
+/*
+ * Let each exported clock get a unique index, which is used on DT-enabled
+ * platforms to lookup the clock from a clock specifier. These indices are
+ * therefore considered an ABI and so must not be changed. This implies
+ * that new clocks should be added either in free spaces between clock groups
+ * or at the end.
+ */
+
+/* Core clocks. */
+#define CLK27M 1
+#define CLK48M 2
+#define FOUT_APLL 3
+#define FOUT_MPLL 4
+#define FOUT_EPLL 5
+#define ARMCLK 6
+#define HCLKX2 7
+#define HCLK 8
+#define PCLK 9
+
+/* HCLK bus clocks. */
+#define HCLK_3DSE 16
+#define HCLK_UHOST 17
+#define HCLK_SECUR 18
+#define HCLK_SDMA1 19
+#define HCLK_SDMA0 20
+#define HCLK_IROM 21
+#define HCLK_DDR1 22
+#define HCLK_MEM1 23
+#define HCLK_MEM0 24
+#define HCLK_USB 25
+#define HCLK_HSMMC2 26
+#define HCLK_HSMMC1 27
+#define HCLK_HSMMC0 28
+#define HCLK_MDP 29
+#define HCLK_DHOST 30
+#define HCLK_IHOST 31
+#define HCLK_DMA1 32
+#define HCLK_DMA0 33
+#define HCLK_JPEG 34
+#define HCLK_CAMIF 35
+#define HCLK_SCALER 36
+#define HCLK_2D 37
+#define HCLK_TV 38
+#define HCLK_POST0 39
+#define HCLK_ROT 40
+#define HCLK_LCD 41
+#define HCLK_TZIC 42
+#define HCLK_INTC 43
+#define HCLK_MFC 44
+#define HCLK_DDR0 45
+
+/* PCLK bus clocks. */
+#define PCLK_IIC1 48
+#define PCLK_IIS2 49
+#define PCLK_SKEY 50
+#define PCLK_CHIPID 51
+#define PCLK_SPI1 52
+#define PCLK_SPI0 53
+#define PCLK_HSIRX 54
+#define PCLK_HSITX 55
+#define PCLK_GPIO 56
+#define PCLK_IIC0 57
+#define PCLK_IIS1 58
+#define PCLK_IIS0 59
+#define PCLK_AC97 60
+#define PCLK_TZPC 61
+#define PCLK_TSADC 62
+#define PCLK_KEYPAD 63
+#define PCLK_IRDA 64
+#define PCLK_PCM1 65
+#define PCLK_PCM0 66
+#define PCLK_PWM 67
+#define PCLK_RTC 68
+#define PCLK_WDT 69
+#define PCLK_UART3 70
+#define PCLK_UART2 71
+#define PCLK_UART1 72
+#define PCLK_UART0 73
+#define PCLK_MFC 74
+
+/* Special clocks. */
+#define SCLK_UHOST 80
+#define SCLK_MMC2_48 81
+#define SCLK_MMC1_48 82
+#define SCLK_MMC0_48 83
+#define SCLK_MMC2 84
+#define SCLK_MMC1 85
+#define SCLK_MMC0 86
+#define SCLK_SPI1_48 87
+#define SCLK_SPI0_48 88
+#define SCLK_SPI1 89
+#define SCLK_SPI0 90
+#define SCLK_DAC27 91
+#define SCLK_TV27 92
+#define SCLK_SCALER27 93
+#define SCLK_SCALER 94
+#define SCLK_LCD27 95
+#define SCLK_LCD 96
+#define SCLK_FIMC 97
+#define SCLK_POST0_27 98
+#define SCLK_AUDIO2 99
+#define SCLK_POST0 100
+#define SCLK_AUDIO1 101
+#define SCLK_AUDIO0 102
+#define SCLK_SECUR 103
+#define SCLK_IRDA 104
+#define SCLK_UART 105
+#define SCLK_MFC 106
+#define SCLK_CAM 107
+#define SCLK_JPEG 108
+#define SCLK_ONENAND 109
+
+/* MEM0 bus clocks - S3C6410-specific. */
+#define MEM0_CFCON 112
+#define MEM0_ONENAND1 113
+#define MEM0_ONENAND0 114
+#define MEM0_NFCON 115
+#define MEM0_SROM 116
+
+/* Muxes. */
+#define MOUT_APLL 128
+#define MOUT_MPLL 129
+#define MOUT_EPLL 130
+#define MOUT_MFC 131
+#define MOUT_AUDIO0 132
+#define MOUT_AUDIO1 133
+#define MOUT_UART 134
+#define MOUT_SPI0 135
+#define MOUT_SPI1 136
+#define MOUT_MMC0 137
+#define MOUT_MMC1 138
+#define MOUT_MMC2 139
+#define MOUT_UHOST 140
+#define MOUT_IRDA 141
+#define MOUT_LCD 142
+#define MOUT_SCALER 143
+#define MOUT_DAC27 144
+#define MOUT_TV27 145
+#define MOUT_AUDIO2 146
+
+/* Dividers. */
+#define DOUT_MPLL 160
+#define DOUT_SECUR 161
+#define DOUT_CAM 162
+#define DOUT_JPEG 163
+#define DOUT_MFC 164
+#define DOUT_MMC0 165
+#define DOUT_MMC1 166
+#define DOUT_MMC2 167
+#define DOUT_LCD 168
+#define DOUT_SCALER 169
+#define DOUT_UHOST 170
+#define DOUT_SPI0 171
+#define DOUT_SPI1 172
+#define DOUT_AUDIO0 173
+#define DOUT_AUDIO1 174
+#define DOUT_UART 175
+#define DOUT_IRDA 176
+#define DOUT_FIMC 177
+#define DOUT_AUDIO2 178
+
+/* Total number of clocks. */
+#define NR_CLKS (DOUT_AUDIO2 + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
new file mode 100644
index 000000000..53369568c
--- /dev/null
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2014 Ulrich Hecht
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
+#define __DT_BINDINGS_CLOCK_SH73A0_H__
+
+/* CPG */
+#define SH73A0_CLK_MAIN 0
+#define SH73A0_CLK_PLL0 1
+#define SH73A0_CLK_PLL1 2
+#define SH73A0_CLK_PLL2 3
+#define SH73A0_CLK_PLL3 4
+#define SH73A0_CLK_DSI0PHY 5
+#define SH73A0_CLK_DSI1PHY 6
+#define SH73A0_CLK_ZG 7
+#define SH73A0_CLK_M3 8
+#define SH73A0_CLK_B 9
+#define SH73A0_CLK_M1 10
+#define SH73A0_CLK_M2 11
+#define SH73A0_CLK_Z 12
+#define SH73A0_CLK_ZX 13
+#define SH73A0_CLK_HP 14
+
+/* MSTP0 */
+#define SH73A0_CLK_IIC2 1
+
+/* MSTP1 */
+#define SH73A0_CLK_CEU1 29
+#define SH73A0_CLK_CSI2_RX1 28
+#define SH73A0_CLK_CEU0 27
+#define SH73A0_CLK_CSI2_RX0 26
+#define SH73A0_CLK_TMU0 25
+#define SH73A0_CLK_DSITX0 18
+#define SH73A0_CLK_IIC0 16
+#define SH73A0_CLK_SGX 12
+#define SH73A0_CLK_LCDC0 0
+
+/* MSTP2 */
+#define SH73A0_CLK_SCIFA7 19
+#define SH73A0_CLK_SY_DMAC 18
+#define SH73A0_CLK_MP_DMAC 17
+#define SH73A0_CLK_SCIFA5 7
+#define SH73A0_CLK_SCIFB 6
+#define SH73A0_CLK_SCIFA0 4
+#define SH73A0_CLK_SCIFA1 3
+#define SH73A0_CLK_SCIFA2 2
+#define SH73A0_CLK_SCIFA3 1
+#define SH73A0_CLK_SCIFA4 0
+
+/* MSTP3 */
+#define SH73A0_CLK_SCIFA6 31
+#define SH73A0_CLK_CMT1 29
+#define SH73A0_CLK_FSI 28
+#define SH73A0_CLK_IRDA 25
+#define SH73A0_CLK_IIC1 23
+#define SH73A0_CLK_USB 22
+#define SH73A0_CLK_FLCTL 15
+#define SH73A0_CLK_SDHI0 14
+#define SH73A0_CLK_SDHI1 13
+#define SH73A0_CLK_MMCIF0 12
+#define SH73A0_CLK_SDHI2 11
+#define SH73A0_CLK_TPU0 4
+#define SH73A0_CLK_TPU1 3
+#define SH73A0_CLK_TPU2 2
+#define SH73A0_CLK_TPU3 1
+#define SH73A0_CLK_TPU4 0
+
+/* MSTP4 */
+#define SH73A0_CLK_IIC3 11
+#define SH73A0_CLK_IIC4 10
+#define SH73A0_CLK_KEYSC 3
+
+/* MSTP5 */
+#define SH73A0_CLK_INTCA0 8
+
+#endif
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
new file mode 100644
index 000000000..7af2b717b
--- /dev/null
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -0,0 +1,86 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH407 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH407
+#define _DT_BINDINGS_CLK_STIH407
+
+/* CLOCKGEN C0 */
+#define CLK_ICN_GPU 0
+#define CLK_FDMA 1
+#define CLK_NAND 2
+#define CLK_HVA 3
+#define CLK_PROC_STFE 4
+#define CLK_PROC_TP 5
+#define CLK_RX_ICN_DMU 6
+#define CLK_RX_ICN_DISP_0 6
+#define CLK_RX_ICN_DISP_1 6
+#define CLK_RX_ICN_HVA 7
+#define CLK_RX_ICN_TS 7
+#define CLK_ICN_CPU 8
+#define CLK_TX_ICN_DMU 9
+#define CLK_TX_ICN_HVA 9
+#define CLK_TX_ICN_TS 9
+#define CLK_ICN_COMPO 9
+#define CLK_MMC_0 10
+#define CLK_MMC_1 11
+#define CLK_JPEGDEC 12
+#define CLK_ICN_REG 13
+#define CLK_TRACE_A9 13
+#define CLK_PTI_STM 13
+#define CLK_EXT2F_A9 13
+#define CLK_IC_BDISP_0 14
+#define CLK_IC_BDISP_1 15
+#define CLK_PP_DMU 16
+#define CLK_VID_DMU 17
+#define CLK_DSS_LPC 18
+#define CLK_ST231_AUD_0 19
+#define CLK_ST231_GP_0 19
+#define CLK_ST231_GP_1 20
+#define CLK_ST231_DMU 21
+#define CLK_ICN_LMI 22
+#define CLK_TX_ICN_DISP_0 23
+#define CLK_TX_ICN_DISP_1 23
+#define CLK_ICN_SBC 24
+#define CLK_STFE_FRC2 25
+#define CLK_ETH_PHY 26
+#define CLK_ETH_REF_PHYCLK 27
+#define CLK_FLASH_PROMIP 28
+#define CLK_MAIN_DISP 29
+#define CLK_AUX_DISP 30
+#define CLK_COMPO_DVP 31
+
+/* CLOCKGEN D0 */
+#define CLK_PCM_0 0
+#define CLK_PCM_1 1
+#define CLK_PCM_2 2
+#define CLK_SPDIFF 3
+
+/* CLOCKGEN D2 */
+#define CLK_PIX_MAIN_DISP 0
+#define CLK_PIX_PIP 1
+#define CLK_PIX_GDP1 2
+#define CLK_PIX_GDP2 3
+#define CLK_PIX_GDP3 4
+#define CLK_PIX_GDP4 5
+#define CLK_PIX_AUX_DISP 6
+#define CLK_DENC 7
+#define CLK_PIX_HDDAC 8
+#define CLK_HDDAC 9
+#define CLK_SDDAC 10
+#define CLK_PIX_DVO 11
+#define CLK_DVO 12
+#define CLK_PIX_HDMI 13
+#define CLK_TMDS_HDMI 14
+#define CLK_REF_HDMIPHY 15
+
+/* CLOCKGEN D3 */
+#define CLK_STFE_FRC1 0
+#define CLK_TSOUT_0 1
+#define CLK_TSOUT_1 2
+#define CLK_MCHI 3
+#define CLK_VSENS_COMPO 4
+#define CLK_FRC1_REMOTE 5
+#define CLK_LPC_0 6
+#define CLK_LPC_1 7
+#endif
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 000000000..2097a4bbe
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES 32
+#define CLK_RX_ICN_HADES 33
+#define CLK_ICN_REG_16 34
+#define CLK_PP_HADES 35
+#define CLK_CLUST_HADES 36
+#define CLK_HWPE_HADES 37
+#define CLK_FC_HADES 38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER 4
+#define CLK_USB2_PHY 5
+
+#endif
diff --git a/include/dt-bindings/clock/stih415-clks.h b/include/dt-bindings/clock/stih415-clks.h
new file mode 100644
index 000000000..d80caa68a
--- /dev/null
+++ b/include/dt-bindings/clock/stih415-clks.h
@@ -0,0 +1,16 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH415 SoC.
+ */
+#ifndef _CLK_STIH415
+#define _CLK_STIH415
+
+/* CLOCKGEN A0 */
+#define CLK_ICN_REG 0
+#define CLK_ETH1_PHY 4
+
+/* CLOCKGEN A1 */
+#define CLK_ICN_IF_2 0
+#define CLK_GMAC0_PHY 3
+
+#endif
diff --git a/include/dt-bindings/clock/stih416-clks.h b/include/dt-bindings/clock/stih416-clks.h
new file mode 100644
index 000000000..f9bdbd135
--- /dev/null
+++ b/include/dt-bindings/clock/stih416-clks.h
@@ -0,0 +1,16 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH416 SoC.
+ */
+#ifndef _CLK_STIH416
+#define _CLK_STIH416
+
+/* CLOCKGEN A0 */
+#define CLK_ICN_REG 0
+#define CLK_ETH1_PHY 4
+
+/* CLOCKGEN A1 */
+#define CLK_ICN_IF_2 0
+#define CLK_GMAC0_PHY 3
+
+#endif
diff --git a/include/dt-bindings/clock/stih418-clks.h b/include/dt-bindings/clock/stih418-clks.h
new file mode 100644
index 000000000..b62aa0b20
--- /dev/null
+++ b/include/dt-bindings/clock/stih418-clks.h
@@ -0,0 +1,34 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH418 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH418
+#define _DT_BINDINGS_CLK_STIH418
+
+#include "stih410-clks.h"
+
+/* STiH418 introduces new clock outputs compared to STiH410 */
+
+/* CLOCKGEN C0 */
+#define CLK_PROC_BDISP_0 14
+#define CLK_PROC_BDISP_1 15
+#define CLK_TX_ICN_1 23
+#define CLK_ETH_PHYREF 27
+#define CLK_PP_HEVC 35
+#define CLK_CLUST_HEVC 36
+#define CLK_HWPE_HEVC 37
+#define CLK_FC_HEVC 38
+#define CLK_PROC_MIXER 39
+#define CLK_PROC_SC 40
+#define CLK_AVSP_HEVC 41
+
+/* CLOCKGEN D2 */
+#undef CLK_PIX_PIP
+#undef CLK_PIX_GDP1
+#undef CLK_PIX_GDP2
+#undef CLK_PIX_GDP3
+#undef CLK_PIX_GDP4
+
+#define CLK_TMDS_HDMI_DIV2 5
+#define CLK_VP9 47
+#endif
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
new file mode 100644
index 000000000..534c03f8a
--- /dev/null
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -0,0 +1,343 @@
+/*
+ * This header provides constants for binding nvidia,tegra114-car.
+ *
+ * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA114_CLK_RTC 4
+#define TEGRA114_CLK_TIMER 5
+#define TEGRA114_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA114_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA114_CLK_I2S1 11
+#define TEGRA114_CLK_I2C1 12
+#define TEGRA114_CLK_NDFLASH 13
+#define TEGRA114_CLK_SDMMC1 14
+#define TEGRA114_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA114_CLK_PWM 17
+#define TEGRA114_CLK_I2S2 18
+#define TEGRA114_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA114_CLK_GR2D 21
+#define TEGRA114_CLK_USBD 22
+#define TEGRA114_CLK_ISP 23
+#define TEGRA114_CLK_GR3D 24
+/* 25 */
+#define TEGRA114_CLK_DISP2 26
+#define TEGRA114_CLK_DISP1 27
+#define TEGRA114_CLK_HOST1X 28
+#define TEGRA114_CLK_VCP 29
+#define TEGRA114_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA114_CLK_MC 32
+/* 33 */
+#define TEGRA114_CLK_APBDMA 34
+/* 35 */
+#define TEGRA114_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA114_CLK_KFUSE 40
+#define TEGRA114_CLK_SBC1 41
+#define TEGRA114_CLK_NOR 42
+/* 43 */
+#define TEGRA114_CLK_SBC2 44
+/* 45 */
+#define TEGRA114_CLK_SBC3 46
+#define TEGRA114_CLK_I2C5 47
+#define TEGRA114_CLK_DSIA 48
+/* 49 */
+#define TEGRA114_CLK_MIPI 50
+#define TEGRA114_CLK_HDMI 51
+#define TEGRA114_CLK_CSI 52
+/* 53 */
+#define TEGRA114_CLK_I2C2 54
+#define TEGRA114_CLK_UARTC 55
+#define TEGRA114_CLK_MIPI_CAL 56
+#define TEGRA114_CLK_EMC 57
+#define TEGRA114_CLK_USB2 58
+#define TEGRA114_CLK_USB3 59
+/* 60 */
+#define TEGRA114_CLK_VDE 61
+#define TEGRA114_CLK_BSEA 62
+#define TEGRA114_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA114_CLK_UARTD 65
+/* 66 */
+#define TEGRA114_CLK_I2C3 67
+#define TEGRA114_CLK_SBC4 68
+#define TEGRA114_CLK_SDMMC3 69
+/* 70 */
+#define TEGRA114_CLK_OWR 71
+/* 72 */
+#define TEGRA114_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA114_CLK_LA 76
+#define TEGRA114_CLK_TRACE 77
+#define TEGRA114_CLK_SOC_THERM 78
+#define TEGRA114_CLK_DTV 79
+#define TEGRA114_CLK_NDSPEED 80
+#define TEGRA114_CLK_I2CSLOW 81
+#define TEGRA114_CLK_DSIB 82
+#define TEGRA114_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA114_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA114_CLK_MSENC 91
+#define TEGRA114_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA114_CLK_MSELECT 99
+#define TEGRA114_CLK_TSENSOR 100
+#define TEGRA114_CLK_I2S3 101
+#define TEGRA114_CLK_I2S4 102
+#define TEGRA114_CLK_I2C4 103
+#define TEGRA114_CLK_SBC5 104
+#define TEGRA114_CLK_SBC6 105
+#define TEGRA114_CLK_D_AUDIO 106
+#define TEGRA114_CLK_APBIF 107
+#define TEGRA114_CLK_DAM0 108
+#define TEGRA114_CLK_DAM1 109
+#define TEGRA114_CLK_DAM2 110
+#define TEGRA114_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA114_CLK_AUDIO0_2X 113
+#define TEGRA114_CLK_AUDIO1_2X 114
+#define TEGRA114_CLK_AUDIO2_2X 115
+#define TEGRA114_CLK_AUDIO3_2X 116
+#define TEGRA114_CLK_AUDIO4_2X 117
+#define TEGRA114_CLK_SPDIF_2X 118
+#define TEGRA114_CLK_ACTMON 119
+#define TEGRA114_CLK_EXTERN1 120
+#define TEGRA114_CLK_EXTERN2 121
+#define TEGRA114_CLK_EXTERN3 122
+/* 123 */
+/* 124 */
+#define TEGRA114_CLK_HDA 125
+/* 126 */
+#define TEGRA114_CLK_SE 127
+
+#define TEGRA114_CLK_HDA2HDMI 128
+/* 129 */
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/* xusb_host_src and xusb_ss_src) */
+#define TEGRA114_CLK_CILAB 144
+#define TEGRA114_CLK_CILCD 145
+#define TEGRA114_CLK_CILE 146
+#define TEGRA114_CLK_DSIALP 147
+#define TEGRA114_CLK_DSIBLP 148
+/* 149 */
+#define TEGRA114_CLK_DDS 150
+/* 151 */
+#define TEGRA114_CLK_DP2 152
+#define TEGRA114_CLK_AMX 153
+#define TEGRA114_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA114_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+/* 166 */
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+/* 171 */
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+/* 176 */
+/* 177 */
+/* 178 */
+/* 179 */
+/* 180 */
+/* 181 */
+/* 182 */
+/* 183 */
+/* 184 */
+/* 185 */
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+
+#define TEGRA114_CLK_UARTB 192
+#define TEGRA114_CLK_VFIR 193
+#define TEGRA114_CLK_SPDIF_IN 194
+#define TEGRA114_CLK_SPDIF_OUT 195
+#define TEGRA114_CLK_VI 196
+#define TEGRA114_CLK_VI_SENSOR 197
+#define TEGRA114_CLK_FUSE 198
+#define TEGRA114_CLK_FUSE_BURN 199
+#define TEGRA114_CLK_CLK_32K 200
+#define TEGRA114_CLK_CLK_M 201
+#define TEGRA114_CLK_CLK_M_DIV2 202
+#define TEGRA114_CLK_CLK_M_DIV4 203
+#define TEGRA114_CLK_PLL_REF 204
+#define TEGRA114_CLK_PLL_C 205
+#define TEGRA114_CLK_PLL_C_OUT1 206
+#define TEGRA114_CLK_PLL_C2 207
+#define TEGRA114_CLK_PLL_C3 208
+#define TEGRA114_CLK_PLL_M 209
+#define TEGRA114_CLK_PLL_M_OUT1 210
+#define TEGRA114_CLK_PLL_P 211
+#define TEGRA114_CLK_PLL_P_OUT1 212
+#define TEGRA114_CLK_PLL_P_OUT2 213
+#define TEGRA114_CLK_PLL_P_OUT3 214
+#define TEGRA114_CLK_PLL_P_OUT4 215
+#define TEGRA114_CLK_PLL_A 216
+#define TEGRA114_CLK_PLL_A_OUT0 217
+#define TEGRA114_CLK_PLL_D 218
+#define TEGRA114_CLK_PLL_D_OUT0 219
+#define TEGRA114_CLK_PLL_D2 220
+#define TEGRA114_CLK_PLL_D2_OUT0 221
+#define TEGRA114_CLK_PLL_U 222
+#define TEGRA114_CLK_PLL_U_480M 223
+
+#define TEGRA114_CLK_PLL_U_60M 224
+#define TEGRA114_CLK_PLL_U_48M 225
+#define TEGRA114_CLK_PLL_U_12M 226
+#define TEGRA114_CLK_PLL_X 227
+#define TEGRA114_CLK_PLL_X_OUT0 228
+#define TEGRA114_CLK_PLL_RE_VCO 229
+#define TEGRA114_CLK_PLL_RE_OUT 230
+#define TEGRA114_CLK_PLL_E_OUT0 231
+#define TEGRA114_CLK_SPDIF_IN_SYNC 232
+#define TEGRA114_CLK_I2S0_SYNC 233
+#define TEGRA114_CLK_I2S1_SYNC 234
+#define TEGRA114_CLK_I2S2_SYNC 235
+#define TEGRA114_CLK_I2S3_SYNC 236
+#define TEGRA114_CLK_I2S4_SYNC 237
+#define TEGRA114_CLK_VIMCLK_SYNC 238
+#define TEGRA114_CLK_AUDIO0 239
+#define TEGRA114_CLK_AUDIO1 240
+#define TEGRA114_CLK_AUDIO2 241
+#define TEGRA114_CLK_AUDIO3 242
+#define TEGRA114_CLK_AUDIO4 243
+#define TEGRA114_CLK_SPDIF 244
+#define TEGRA114_CLK_CLK_OUT_1 245
+#define TEGRA114_CLK_CLK_OUT_2 246
+#define TEGRA114_CLK_CLK_OUT_3 247
+#define TEGRA114_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA114_CLK_XUSB_HOST_SRC 252
+#define TEGRA114_CLK_XUSB_FALCON_SRC 253
+#define TEGRA114_CLK_XUSB_FS_SRC 254
+#define TEGRA114_CLK_XUSB_SS_SRC 255
+
+#define TEGRA114_CLK_XUSB_DEV_SRC 256
+#define TEGRA114_CLK_XUSB_DEV 257
+#define TEGRA114_CLK_XUSB_HS_SRC 258
+#define TEGRA114_CLK_SCLK 259
+#define TEGRA114_CLK_HCLK 260
+#define TEGRA114_CLK_PCLK 261
+#define TEGRA114_CLK_CCLK_G 262
+#define TEGRA114_CLK_CCLK_LP 263
+#define TEGRA114_CLK_DFLL_REF 264
+#define TEGRA114_CLK_DFLL_SOC 265
+/* 266 */
+/* 267 */
+/* 268 */
+/* 269 */
+/* 270 */
+/* 271 */
+/* 272 */
+/* 273 */
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA114_CLK_AUDIO0_MUX 300
+#define TEGRA114_CLK_AUDIO1_MUX 301
+#define TEGRA114_CLK_AUDIO2_MUX 302
+#define TEGRA114_CLK_AUDIO3_MUX 303
+#define TEGRA114_CLK_AUDIO4_MUX 304
+#define TEGRA114_CLK_SPDIF_MUX 305
+#define TEGRA114_CLK_CLK_OUT_1_MUX 306
+#define TEGRA114_CLK_CLK_OUT_2_MUX 307
+#define TEGRA114_CLK_CLK_OUT_3_MUX 308
+#define TEGRA114_CLK_DSIA_MUX 309
+#define TEGRA114_CLK_DSIB_MUX 310
+#define TEGRA114_CLK_XUSB_SS_DIV2 311
+#define TEGRA114_CLK_CLK_MAX 312
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
new file mode 100644
index 000000000..a21560905
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -0,0 +1,345 @@
+/*
+ * This header provides constants for binding nvidia,tegra124-car or
+ * nvidia,tegra132-car.
+ *
+ * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 185 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
+
+/* 0 */
+/* 1 */
+/* 2 */
+#define TEGRA124_CLK_ISPB 3
+#define TEGRA124_CLK_RTC 4
+#define TEGRA124_CLK_TIMER 5
+#define TEGRA124_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+/* 8 */
+#define TEGRA124_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA124_CLK_I2S1 11
+#define TEGRA124_CLK_I2C1 12
+/* 13 */
+#define TEGRA124_CLK_SDMMC1 14
+#define TEGRA124_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA124_CLK_PWM 17
+#define TEGRA124_CLK_I2S2 18
+/* 20 (register bit affects vi and vi_sensor) */
+/* 21 */
+#define TEGRA124_CLK_USBD 22
+#define TEGRA124_CLK_ISP 23
+/* 26 */
+/* 25 */
+#define TEGRA124_CLK_DISP2 26
+#define TEGRA124_CLK_DISP1 27
+#define TEGRA124_CLK_HOST1X 28
+#define TEGRA124_CLK_VCP 29
+#define TEGRA124_CLK_I2S0 30
+/* 31 */
+
+#define TEGRA124_CLK_MC 32
+/* 33 */
+#define TEGRA124_CLK_APBDMA 34
+/* 35 */
+#define TEGRA124_CLK_KBC 36
+/* 37 */
+/* 38 */
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA124_CLK_KFUSE 40
+#define TEGRA124_CLK_SBC1 41
+#define TEGRA124_CLK_NOR 42
+/* 43 */
+#define TEGRA124_CLK_SBC2 44
+/* 45 */
+#define TEGRA124_CLK_SBC3 46
+#define TEGRA124_CLK_I2C5 47
+#define TEGRA124_CLK_DSIA 48
+/* 49 */
+#define TEGRA124_CLK_MIPI 50
+#define TEGRA124_CLK_HDMI 51
+#define TEGRA124_CLK_CSI 52
+/* 53 */
+#define TEGRA124_CLK_I2C2 54
+#define TEGRA124_CLK_UARTC 55
+#define TEGRA124_CLK_MIPI_CAL 56
+#define TEGRA124_CLK_EMC 57
+#define TEGRA124_CLK_USB2 58
+#define TEGRA124_CLK_USB3 59
+/* 60 */
+#define TEGRA124_CLK_VDE 61
+#define TEGRA124_CLK_BSEA 62
+#define TEGRA124_CLK_BSEV 63
+
+/* 64 */
+#define TEGRA124_CLK_UARTD 65
+/* 66 */
+#define TEGRA124_CLK_I2C3 67
+#define TEGRA124_CLK_SBC4 68
+#define TEGRA124_CLK_SDMMC3 69
+#define TEGRA124_CLK_PCIE 70
+#define TEGRA124_CLK_OWR 71
+#define TEGRA124_CLK_AFI 72
+#define TEGRA124_CLK_CSITE 73
+/* 74 */
+/* 75 */
+#define TEGRA124_CLK_LA 76
+#define TEGRA124_CLK_TRACE 77
+#define TEGRA124_CLK_SOC_THERM 78
+#define TEGRA124_CLK_DTV 79
+/* 80 */
+#define TEGRA124_CLK_I2CSLOW 81
+#define TEGRA124_CLK_DSIB 82
+#define TEGRA124_CLK_TSEC 83
+/* 84 */
+/* 85 */
+/* 86 */
+/* 87 */
+/* 88 */
+#define TEGRA124_CLK_XUSB_HOST 89
+/* 90 */
+#define TEGRA124_CLK_MSENC 91
+#define TEGRA124_CLK_CSUS 92
+/* 93 */
+/* 94 */
+/* 95 (bit affects xusb_dev and xusb_dev_src) */
+
+/* 96 */
+/* 97 */
+/* 98 */
+#define TEGRA124_CLK_MSELECT 99
+#define TEGRA124_CLK_TSENSOR 100
+#define TEGRA124_CLK_I2S3 101
+#define TEGRA124_CLK_I2S4 102
+#define TEGRA124_CLK_I2C4 103
+#define TEGRA124_CLK_SBC5 104
+#define TEGRA124_CLK_SBC6 105
+#define TEGRA124_CLK_D_AUDIO 106
+#define TEGRA124_CLK_APBIF 107
+#define TEGRA124_CLK_DAM0 108
+#define TEGRA124_CLK_DAM1 109
+#define TEGRA124_CLK_DAM2 110
+#define TEGRA124_CLK_HDA2CODEC_2X 111
+/* 112 */
+#define TEGRA124_CLK_AUDIO0_2X 113
+#define TEGRA124_CLK_AUDIO1_2X 114
+#define TEGRA124_CLK_AUDIO2_2X 115
+#define TEGRA124_CLK_AUDIO3_2X 116
+#define TEGRA124_CLK_AUDIO4_2X 117
+#define TEGRA124_CLK_SPDIF_2X 118
+#define TEGRA124_CLK_ACTMON 119
+#define TEGRA124_CLK_EXTERN1 120
+#define TEGRA124_CLK_EXTERN2 121
+#define TEGRA124_CLK_EXTERN3 122
+#define TEGRA124_CLK_SATA_OOB 123
+#define TEGRA124_CLK_SATA 124
+#define TEGRA124_CLK_HDA 125
+/* 126 */
+#define TEGRA124_CLK_SE 127
+
+#define TEGRA124_CLK_HDA2HDMI 128
+#define TEGRA124_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
+/* xusb_host_src and xusb_ss_src) */
+#define TEGRA124_CLK_CILAB 144
+#define TEGRA124_CLK_CILCD 145
+#define TEGRA124_CLK_CILE 146
+#define TEGRA124_CLK_DSIALP 147
+#define TEGRA124_CLK_DSIBLP 148
+#define TEGRA124_CLK_ENTROPY 149
+#define TEGRA124_CLK_DDS 150
+/* 151 */
+#define TEGRA124_CLK_DP2 152
+#define TEGRA124_CLK_AMX 153
+#define TEGRA124_CLK_ADX 154
+/* 155 (bit affects dfll_ref and dfll_soc) */
+#define TEGRA124_CLK_XUSB_SS 156
+/* 157 */
+/* 158 */
+/* 159 */
+
+/* 160 */
+/* 161 */
+/* 162 */
+/* 163 */
+/* 164 */
+/* 165 */
+#define TEGRA124_CLK_I2C6 166
+/* 167 */
+/* 168 */
+/* 169 */
+/* 170 */
+#define TEGRA124_CLK_VIM2_CLK 171
+/* 172 */
+/* 173 */
+/* 174 */
+/* 175 */
+#define TEGRA124_CLK_HDMI_AUDIO 176
+#define TEGRA124_CLK_CLK72MHZ 177
+#define TEGRA124_CLK_VIC03 178
+/* 179 */
+#define TEGRA124_CLK_ADX1 180
+#define TEGRA124_CLK_DPAUX 181
+#define TEGRA124_CLK_SOR0 182
+/* 183 */
+#define TEGRA124_CLK_GPU 184
+#define TEGRA124_CLK_AMX1 185
+/* 186 */
+/* 187 */
+/* 188 */
+/* 189 */
+/* 190 */
+/* 191 */
+#define TEGRA124_CLK_UARTB 192
+#define TEGRA124_CLK_VFIR 193
+#define TEGRA124_CLK_SPDIF_IN 194
+#define TEGRA124_CLK_SPDIF_OUT 195
+#define TEGRA124_CLK_VI 196
+#define TEGRA124_CLK_VI_SENSOR 197
+#define TEGRA124_CLK_FUSE 198
+#define TEGRA124_CLK_FUSE_BURN 199
+#define TEGRA124_CLK_CLK_32K 200
+#define TEGRA124_CLK_CLK_M 201
+#define TEGRA124_CLK_CLK_M_DIV2 202
+#define TEGRA124_CLK_CLK_M_DIV4 203
+#define TEGRA124_CLK_PLL_REF 204
+#define TEGRA124_CLK_PLL_C 205
+#define TEGRA124_CLK_PLL_C_OUT1 206
+#define TEGRA124_CLK_PLL_C2 207
+#define TEGRA124_CLK_PLL_C3 208
+#define TEGRA124_CLK_PLL_M 209
+#define TEGRA124_CLK_PLL_M_OUT1 210
+#define TEGRA124_CLK_PLL_P 211
+#define TEGRA124_CLK_PLL_P_OUT1 212
+#define TEGRA124_CLK_PLL_P_OUT2 213
+#define TEGRA124_CLK_PLL_P_OUT3 214
+#define TEGRA124_CLK_PLL_P_OUT4 215
+#define TEGRA124_CLK_PLL_A 216
+#define TEGRA124_CLK_PLL_A_OUT0 217
+#define TEGRA124_CLK_PLL_D 218
+#define TEGRA124_CLK_PLL_D_OUT0 219
+#define TEGRA124_CLK_PLL_D2 220
+#define TEGRA124_CLK_PLL_D2_OUT0 221
+#define TEGRA124_CLK_PLL_U 222
+#define TEGRA124_CLK_PLL_U_480M 223
+
+#define TEGRA124_CLK_PLL_U_60M 224
+#define TEGRA124_CLK_PLL_U_48M 225
+#define TEGRA124_CLK_PLL_U_12M 226
+/* 227 */
+/* 228 */
+#define TEGRA124_CLK_PLL_RE_VCO 229
+#define TEGRA124_CLK_PLL_RE_OUT 230
+#define TEGRA124_CLK_PLL_E 231
+#define TEGRA124_CLK_SPDIF_IN_SYNC 232
+#define TEGRA124_CLK_I2S0_SYNC 233
+#define TEGRA124_CLK_I2S1_SYNC 234
+#define TEGRA124_CLK_I2S2_SYNC 235
+#define TEGRA124_CLK_I2S3_SYNC 236
+#define TEGRA124_CLK_I2S4_SYNC 237
+#define TEGRA124_CLK_VIMCLK_SYNC 238
+#define TEGRA124_CLK_AUDIO0 239
+#define TEGRA124_CLK_AUDIO1 240
+#define TEGRA124_CLK_AUDIO2 241
+#define TEGRA124_CLK_AUDIO3 242
+#define TEGRA124_CLK_AUDIO4 243
+#define TEGRA124_CLK_SPDIF 244
+#define TEGRA124_CLK_CLK_OUT_1 245
+#define TEGRA124_CLK_CLK_OUT_2 246
+#define TEGRA124_CLK_CLK_OUT_3 247
+#define TEGRA124_CLK_BLINK 248
+/* 249 */
+/* 250 */
+/* 251 */
+#define TEGRA124_CLK_XUSB_HOST_SRC 252
+#define TEGRA124_CLK_XUSB_FALCON_SRC 253
+#define TEGRA124_CLK_XUSB_FS_SRC 254
+#define TEGRA124_CLK_XUSB_SS_SRC 255
+
+#define TEGRA124_CLK_XUSB_DEV_SRC 256
+#define TEGRA124_CLK_XUSB_DEV 257
+#define TEGRA124_CLK_XUSB_HS_SRC 258
+#define TEGRA124_CLK_SCLK 259
+#define TEGRA124_CLK_HCLK 260
+#define TEGRA124_CLK_PCLK 261
+/* 262 */
+/* 263 */
+#define TEGRA124_CLK_DFLL_REF 264
+#define TEGRA124_CLK_DFLL_SOC 265
+#define TEGRA124_CLK_VI_SENSOR2 266
+#define TEGRA124_CLK_PLL_P_OUT5 267
+#define TEGRA124_CLK_CML0 268
+#define TEGRA124_CLK_CML1 269
+#define TEGRA124_CLK_PLL_C4 270
+#define TEGRA124_CLK_PLL_DP 271
+#define TEGRA124_CLK_PLL_E_MUX 272
+#define TEGRA124_CLK_PLL_D_DSI_OUT 273
+/* 274 */
+/* 275 */
+/* 276 */
+/* 277 */
+/* 278 */
+/* 279 */
+/* 280 */
+/* 281 */
+/* 282 */
+/* 283 */
+/* 284 */
+/* 285 */
+/* 286 */
+/* 287 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA124_CLK_AUDIO0_MUX 300
+#define TEGRA124_CLK_AUDIO1_MUX 301
+#define TEGRA124_CLK_AUDIO2_MUX 302
+#define TEGRA124_CLK_AUDIO3_MUX 303
+#define TEGRA124_CLK_AUDIO4_MUX 304
+#define TEGRA124_CLK_SPDIF_MUX 305
+#define TEGRA124_CLK_CLK_OUT_1_MUX 306
+#define TEGRA124_CLK_CLK_OUT_2_MUX 307
+#define TEGRA124_CLK_CLK_OUT_3_MUX 308
+/* 309 */
+/* 310 */
+#define TEGRA124_CLK_SOR0_LVDS 311
+#define TEGRA124_CLK_XUSB_SS_DIV2 312
+
+#define TEGRA124_CLK_PLL_M_UD 313
+#define TEGRA124_CLK_PLL_C_UD 314
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */
diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h
new file mode 100644
index 000000000..2860737f0
--- /dev/null
+++ b/include/dt-bindings/clock/tegra124-car.h
@@ -0,0 +1,19 @@
+/*
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
+ */
+
+#include <dt-bindings/clock/tegra124-car-common.h>
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H
+
+#define TEGRA124_CLK_PLL_X 227
+#define TEGRA124_CLK_PLL_X_OUT0 228
+
+#define TEGRA124_CLK_CCLK_G 262
+#define TEGRA124_CLK_CCLK_LP 263
+
+#define TEGRA124_CLK_CLK_MAX 315
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h
new file mode 100644
index 000000000..04500b243
--- /dev/null
+++ b/include/dt-bindings/clock/tegra20-car.h
@@ -0,0 +1,158 @@
+/*
+ * This header provides constants for binding nvidia,tegra20-car.
+ *
+ * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 95 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
+
+#define TEGRA20_CLK_CPU 0
+/* 1 */
+/* 2 */
+#define TEGRA20_CLK_AC97 3
+#define TEGRA20_CLK_RTC 4
+#define TEGRA20_CLK_TIMER 5
+#define TEGRA20_CLK_UARTA 6
+/* 7 (register bit affects uart2 and vfir) */
+#define TEGRA20_CLK_GPIO 8
+#define TEGRA20_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA20_CLK_I2S1 11
+#define TEGRA20_CLK_I2C1 12
+#define TEGRA20_CLK_NDFLASH 13
+#define TEGRA20_CLK_SDMMC1 14
+#define TEGRA20_CLK_SDMMC4 15
+#define TEGRA20_CLK_TWC 16
+#define TEGRA20_CLK_PWM 17
+#define TEGRA20_CLK_I2S2 18
+#define TEGRA20_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA20_CLK_GR2D 21
+#define TEGRA20_CLK_USBD 22
+#define TEGRA20_CLK_ISP 23
+#define TEGRA20_CLK_GR3D 24
+#define TEGRA20_CLK_IDE 25
+#define TEGRA20_CLK_DISP2 26
+#define TEGRA20_CLK_DISP1 27
+#define TEGRA20_CLK_HOST1X 28
+#define TEGRA20_CLK_VCP 29
+/* 30 */
+#define TEGRA20_CLK_CACHE2 31
+
+#define TEGRA20_CLK_MC 32
+#define TEGRA20_CLK_AHBDMA 33
+#define TEGRA20_CLK_APBDMA 34
+/* 35 */
+#define TEGRA20_CLK_KBC 36
+#define TEGRA20_CLK_STAT_MON 37
+#define TEGRA20_CLK_PMC 38
+#define TEGRA20_CLK_FUSE 39
+#define TEGRA20_CLK_KFUSE 40
+#define TEGRA20_CLK_SBC1 41
+#define TEGRA20_CLK_NOR 42
+#define TEGRA20_CLK_SPI 43
+#define TEGRA20_CLK_SBC2 44
+#define TEGRA20_CLK_XIO 45
+#define TEGRA20_CLK_SBC3 46
+#define TEGRA20_CLK_DVC 47
+#define TEGRA20_CLK_DSI 48
+/* 49 (register bit affects tvo and cve) */
+#define TEGRA20_CLK_MIPI 50
+#define TEGRA20_CLK_HDMI 51
+#define TEGRA20_CLK_CSI 52
+#define TEGRA20_CLK_TVDAC 53
+#define TEGRA20_CLK_I2C2 54
+#define TEGRA20_CLK_UARTC 55
+/* 56 */
+#define TEGRA20_CLK_EMC 57
+#define TEGRA20_CLK_USB2 58
+#define TEGRA20_CLK_USB3 59
+#define TEGRA20_CLK_MPE 60
+#define TEGRA20_CLK_VDE 61
+#define TEGRA20_CLK_BSEA 62
+#define TEGRA20_CLK_BSEV 63
+
+#define TEGRA20_CLK_SPEEDO 64
+#define TEGRA20_CLK_UARTD 65
+#define TEGRA20_CLK_UARTE 66
+#define TEGRA20_CLK_I2C3 67
+#define TEGRA20_CLK_SBC4 68
+#define TEGRA20_CLK_SDMMC3 69
+#define TEGRA20_CLK_PEX 70
+#define TEGRA20_CLK_OWR 71
+#define TEGRA20_CLK_AFI 72
+#define TEGRA20_CLK_CSITE 73
+/* 74 */
+#define TEGRA20_CLK_AVPUCQ 75
+#define TEGRA20_CLK_LA 76
+/* 77 */
+/* 78 */
+/* 79 */
+/* 80 */
+/* 81 */
+/* 82 */
+/* 83 */
+#define TEGRA20_CLK_IRAMA 84
+#define TEGRA20_CLK_IRAMB 85
+#define TEGRA20_CLK_IRAMC 86
+#define TEGRA20_CLK_IRAMD 87
+#define TEGRA20_CLK_CRAM2 88
+#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
+#define TEGRA20_CLK_CLK_D 90
+/* 91 */
+#define TEGRA20_CLK_CSUS 92
+#define TEGRA20_CLK_CDEV2 93
+#define TEGRA20_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA20_CLK_UARTB 96
+#define TEGRA20_CLK_VFIR 97
+#define TEGRA20_CLK_SPDIF_IN 98
+#define TEGRA20_CLK_SPDIF_OUT 99
+#define TEGRA20_CLK_VI 100
+#define TEGRA20_CLK_VI_SENSOR 101
+#define TEGRA20_CLK_TVO 102
+#define TEGRA20_CLK_CVE 103
+#define TEGRA20_CLK_OSC 104
+#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
+#define TEGRA20_CLK_CLK_M 106
+#define TEGRA20_CLK_SCLK 107
+#define TEGRA20_CLK_CCLK 108
+#define TEGRA20_CLK_HCLK 109
+#define TEGRA20_CLK_PCLK 110
+#define TEGRA20_CLK_BLINK 111
+#define TEGRA20_CLK_PLL_A 112
+#define TEGRA20_CLK_PLL_A_OUT0 113
+#define TEGRA20_CLK_PLL_C 114
+#define TEGRA20_CLK_PLL_C_OUT1 115
+#define TEGRA20_CLK_PLL_D 116
+#define TEGRA20_CLK_PLL_D_OUT0 117
+#define TEGRA20_CLK_PLL_E 118
+#define TEGRA20_CLK_PLL_M 119
+#define TEGRA20_CLK_PLL_M_OUT1 120
+#define TEGRA20_CLK_PLL_P 121
+#define TEGRA20_CLK_PLL_P_OUT1 122
+#define TEGRA20_CLK_PLL_P_OUT2 123
+#define TEGRA20_CLK_PLL_P_OUT3 124
+#define TEGRA20_CLK_PLL_P_OUT4 125
+#define TEGRA20_CLK_PLL_S 126
+#define TEGRA20_CLK_PLL_U 127
+
+#define TEGRA20_CLK_PLL_X 128
+#define TEGRA20_CLK_COP 129 /* a/k/a avp */
+#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
+#define TEGRA20_CLK_PLL_REF 131
+#define TEGRA20_CLK_TWD 132
+#define TEGRA20_CLK_CLK_MAX 133
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
new file mode 100644
index 000000000..889e49ba0
--- /dev/null
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -0,0 +1,273 @@
+/*
+ * This header provides constants for binding nvidia,tegra30-car.
+ *
+ * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+ * registers. These IDs often match those in the CAR's RST_DEVICES registers,
+ * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+ * this case, those clocks are assigned IDs above 160 in order to highlight
+ * this issue. Implementations that interpret these clock IDs as bit values
+ * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+ * explicitly handle these special cases.
+ *
+ * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
+ * above.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
+
+#define TEGRA30_CLK_CPU 0
+/* 1 */
+/* 2 */
+/* 3 */
+#define TEGRA30_CLK_RTC 4
+#define TEGRA30_CLK_TIMER 5
+#define TEGRA30_CLK_UARTA 6
+/* 7 (register bit affects uartb and vfir) */
+#define TEGRA30_CLK_GPIO 8
+#define TEGRA30_CLK_SDMMC2 9
+/* 10 (register bit affects spdif_in and spdif_out) */
+#define TEGRA30_CLK_I2S1 11
+#define TEGRA30_CLK_I2C1 12
+#define TEGRA30_CLK_NDFLASH 13
+#define TEGRA30_CLK_SDMMC1 14
+#define TEGRA30_CLK_SDMMC4 15
+/* 16 */
+#define TEGRA30_CLK_PWM 17
+#define TEGRA30_CLK_I2S2 18
+#define TEGRA30_CLK_EPP 19
+/* 20 (register bit affects vi and vi_sensor) */
+#define TEGRA30_CLK_GR2D 21
+#define TEGRA30_CLK_USBD 22
+#define TEGRA30_CLK_ISP 23
+#define TEGRA30_CLK_GR3D 24
+/* 25 */
+#define TEGRA30_CLK_DISP2 26
+#define TEGRA30_CLK_DISP1 27
+#define TEGRA30_CLK_HOST1X 28
+#define TEGRA30_CLK_VCP 29
+#define TEGRA30_CLK_I2S0 30
+#define TEGRA30_CLK_COP_CACHE 31
+
+#define TEGRA30_CLK_MC 32
+#define TEGRA30_CLK_AHBDMA 33
+#define TEGRA30_CLK_APBDMA 34
+/* 35 */
+#define TEGRA30_CLK_KBC 36
+#define TEGRA30_CLK_STATMON 37
+#define TEGRA30_CLK_PMC 38
+/* 39 (register bit affects fuse and fuse_burn) */
+#define TEGRA30_CLK_KFUSE 40
+#define TEGRA30_CLK_SBC1 41
+#define TEGRA30_CLK_NOR 42
+/* 43 */
+#define TEGRA30_CLK_SBC2 44
+/* 45 */
+#define TEGRA30_CLK_SBC3 46
+#define TEGRA30_CLK_I2C5 47
+#define TEGRA30_CLK_DSIA 48
+/* 49 (register bit affects cve and tvo) */
+#define TEGRA30_CLK_MIPI 50
+#define TEGRA30_CLK_HDMI 51
+#define TEGRA30_CLK_CSI 52
+#define TEGRA30_CLK_TVDAC 53
+#define TEGRA30_CLK_I2C2 54
+#define TEGRA30_CLK_UARTC 55
+/* 56 */
+#define TEGRA30_CLK_EMC 57
+#define TEGRA30_CLK_USB2 58
+#define TEGRA30_CLK_USB3 59
+#define TEGRA30_CLK_MPE 60
+#define TEGRA30_CLK_VDE 61
+#define TEGRA30_CLK_BSEA 62
+#define TEGRA30_CLK_BSEV 63
+
+#define TEGRA30_CLK_SPEEDO 64
+#define TEGRA30_CLK_UARTD 65
+#define TEGRA30_CLK_UARTE 66
+#define TEGRA30_CLK_I2C3 67
+#define TEGRA30_CLK_SBC4 68
+#define TEGRA30_CLK_SDMMC3 69
+#define TEGRA30_CLK_PCIE 70
+#define TEGRA30_CLK_OWR 71
+#define TEGRA30_CLK_AFI 72
+#define TEGRA30_CLK_CSITE 73
+/* 74 */
+#define TEGRA30_CLK_AVPUCQ 75
+#define TEGRA30_CLK_LA 76
+/* 77 */
+/* 78 */
+#define TEGRA30_CLK_DTV 79
+#define TEGRA30_CLK_NDSPEED 80
+#define TEGRA30_CLK_I2CSLOW 81
+#define TEGRA30_CLK_DSIB 82
+/* 83 */
+#define TEGRA30_CLK_IRAMA 84
+#define TEGRA30_CLK_IRAMB 85
+#define TEGRA30_CLK_IRAMC 86
+#define TEGRA30_CLK_IRAMD 87
+#define TEGRA30_CLK_CRAM2 88
+/* 89 */
+#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
+/* 91 */
+#define TEGRA30_CLK_CSUS 92
+#define TEGRA30_CLK_CDEV2 93
+#define TEGRA30_CLK_CDEV1 94
+/* 95 */
+
+#define TEGRA30_CLK_CPU_G 96
+#define TEGRA30_CLK_CPU_LP 97
+#define TEGRA30_CLK_GR3D2 98
+#define TEGRA30_CLK_MSELECT 99
+#define TEGRA30_CLK_TSENSOR 100
+#define TEGRA30_CLK_I2S3 101
+#define TEGRA30_CLK_I2S4 102
+#define TEGRA30_CLK_I2C4 103
+#define TEGRA30_CLK_SBC5 104
+#define TEGRA30_CLK_SBC6 105
+#define TEGRA30_CLK_D_AUDIO 106
+#define TEGRA30_CLK_APBIF 107
+#define TEGRA30_CLK_DAM0 108
+#define TEGRA30_CLK_DAM1 109
+#define TEGRA30_CLK_DAM2 110
+#define TEGRA30_CLK_HDA2CODEC_2X 111
+#define TEGRA30_CLK_ATOMICS 112
+#define TEGRA30_CLK_AUDIO0_2X 113
+#define TEGRA30_CLK_AUDIO1_2X 114
+#define TEGRA30_CLK_AUDIO2_2X 115
+#define TEGRA30_CLK_AUDIO3_2X 116
+#define TEGRA30_CLK_AUDIO4_2X 117
+#define TEGRA30_CLK_SPDIF_2X 118
+#define TEGRA30_CLK_ACTMON 119
+#define TEGRA30_CLK_EXTERN1 120
+#define TEGRA30_CLK_EXTERN2 121
+#define TEGRA30_CLK_EXTERN3 122
+#define TEGRA30_CLK_SATA_OOB 123
+#define TEGRA30_CLK_SATA 124
+#define TEGRA30_CLK_HDA 125
+/* 126 */
+#define TEGRA30_CLK_SE 127
+
+#define TEGRA30_CLK_HDA2HDMI 128
+#define TEGRA30_CLK_SATA_COLD 129
+/* 130 */
+/* 131 */
+/* 132 */
+/* 133 */
+/* 134 */
+/* 135 */
+/* 136 */
+/* 137 */
+/* 138 */
+/* 139 */
+/* 140 */
+/* 141 */
+/* 142 */
+/* 143 */
+/* 144 */
+/* 145 */
+/* 146 */
+/* 147 */
+/* 148 */
+/* 149 */
+/* 150 */
+/* 151 */
+/* 152 */
+/* 153 */
+/* 154 */
+/* 155 */
+/* 156 */
+/* 157 */
+/* 158 */
+/* 159 */
+
+#define TEGRA30_CLK_UARTB 160
+#define TEGRA30_CLK_VFIR 161
+#define TEGRA30_CLK_SPDIF_IN 162
+#define TEGRA30_CLK_SPDIF_OUT 163
+#define TEGRA30_CLK_VI 164
+#define TEGRA30_CLK_VI_SENSOR 165
+#define TEGRA30_CLK_FUSE 166
+#define TEGRA30_CLK_FUSE_BURN 167
+#define TEGRA30_CLK_CVE 168
+#define TEGRA30_CLK_TVO 169
+#define TEGRA30_CLK_CLK_32K 170
+#define TEGRA30_CLK_CLK_M 171
+#define TEGRA30_CLK_CLK_M_DIV2 172
+#define TEGRA30_CLK_CLK_M_DIV4 173
+#define TEGRA30_CLK_PLL_REF 174
+#define TEGRA30_CLK_PLL_C 175
+#define TEGRA30_CLK_PLL_C_OUT1 176
+#define TEGRA30_CLK_PLL_M 177
+#define TEGRA30_CLK_PLL_M_OUT1 178
+#define TEGRA30_CLK_PLL_P 179
+#define TEGRA30_CLK_PLL_P_OUT1 180
+#define TEGRA30_CLK_PLL_P_OUT2 181
+#define TEGRA30_CLK_PLL_P_OUT3 182
+#define TEGRA30_CLK_PLL_P_OUT4 183
+#define TEGRA30_CLK_PLL_A 184
+#define TEGRA30_CLK_PLL_A_OUT0 185
+#define TEGRA30_CLK_PLL_D 186
+#define TEGRA30_CLK_PLL_D_OUT0 187
+#define TEGRA30_CLK_PLL_D2 188
+#define TEGRA30_CLK_PLL_D2_OUT0 189
+#define TEGRA30_CLK_PLL_U 190
+#define TEGRA30_CLK_PLL_X 191
+
+#define TEGRA30_CLK_PLL_X_OUT0 192
+#define TEGRA30_CLK_PLL_E 193
+#define TEGRA30_CLK_SPDIF_IN_SYNC 194
+#define TEGRA30_CLK_I2S0_SYNC 195
+#define TEGRA30_CLK_I2S1_SYNC 196
+#define TEGRA30_CLK_I2S2_SYNC 197
+#define TEGRA30_CLK_I2S3_SYNC 198
+#define TEGRA30_CLK_I2S4_SYNC 199
+#define TEGRA30_CLK_VIMCLK_SYNC 200
+#define TEGRA30_CLK_AUDIO0 201
+#define TEGRA30_CLK_AUDIO1 202
+#define TEGRA30_CLK_AUDIO2 203
+#define TEGRA30_CLK_AUDIO3 204
+#define TEGRA30_CLK_AUDIO4 205
+#define TEGRA30_CLK_SPDIF 206
+#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
+#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
+#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
+#define TEGRA30_CLK_SCLK 210
+#define TEGRA30_CLK_BLINK 211
+#define TEGRA30_CLK_CCLK_G 212
+#define TEGRA30_CLK_CCLK_LP 213
+#define TEGRA30_CLK_TWD 214
+#define TEGRA30_CLK_CML0 215
+#define TEGRA30_CLK_CML1 216
+#define TEGRA30_CLK_HCLK 217
+#define TEGRA30_CLK_PCLK 218
+/* 219 */
+/* 220 */
+/* 221 */
+/* 222 */
+/* 223 */
+
+/* 288 */
+/* 289 */
+/* 290 */
+/* 291 */
+/* 292 */
+/* 293 */
+/* 294 */
+/* 295 */
+/* 296 */
+/* 297 */
+/* 298 */
+/* 299 */
+#define TEGRA30_CLK_CLK_OUT_1_MUX 300
+#define TEGRA30_CLK_CLK_OUT_2_MUX 301
+#define TEGRA30_CLK_CLK_OUT_3_MUX 302
+#define TEGRA30_CLK_AUDIO0_MUX 303
+#define TEGRA30_CLK_AUDIO1_MUX 304
+#define TEGRA30_CLK_AUDIO2_MUX 305
+#define TEGRA30_CLK_AUDIO3_MUX 306
+#define TEGRA30_CLK_AUDIO4_MUX 307
+#define TEGRA30_CLK_SPDIF_MUX 308
+#define TEGRA30_CLK_CLK_MAX 309
+
+#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
new file mode 100644
index 000000000..979d24a67
--- /dev/null
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_VF610_H
+#define __DT_BINDINGS_CLOCK_VF610_H
+
+#define VF610_CLK_DUMMY 0
+#define VF610_CLK_SIRC_128K 1
+#define VF610_CLK_SIRC_32K 2
+#define VF610_CLK_FIRC 3
+#define VF610_CLK_SXOSC 4
+#define VF610_CLK_FXOSC 5
+#define VF610_CLK_FXOSC_HALF 6
+#define VF610_CLK_SLOW_CLK_SEL 7
+#define VF610_CLK_FASK_CLK_SEL 8
+#define VF610_CLK_AUDIO_EXT 9
+#define VF610_CLK_ENET_EXT 10
+#define VF610_CLK_PLL1_SYS 11
+#define VF610_CLK_PLL1_PFD1 12
+#define VF610_CLK_PLL1_PFD2 13
+#define VF610_CLK_PLL1_PFD3 14
+#define VF610_CLK_PLL1_PFD4 15
+#define VF610_CLK_PLL2_BUS 16
+#define VF610_CLK_PLL2_PFD1 17
+#define VF610_CLK_PLL2_PFD2 18
+#define VF610_CLK_PLL2_PFD3 19
+#define VF610_CLK_PLL2_PFD4 20
+#define VF610_CLK_PLL3_USB_OTG 21
+#define VF610_CLK_PLL3_PFD1 22
+#define VF610_CLK_PLL3_PFD2 23
+#define VF610_CLK_PLL3_PFD3 24
+#define VF610_CLK_PLL3_PFD4 25
+#define VF610_CLK_PLL4_AUDIO 26
+#define VF610_CLK_PLL5_ENET 27
+#define VF610_CLK_PLL6_VIDEO 28
+#define VF610_CLK_PLL3_MAIN_DIV 29
+#define VF610_CLK_PLL4_MAIN_DIV 30
+#define VF610_CLK_PLL6_MAIN_DIV 31
+#define VF610_CLK_PLL1_PFD_SEL 32
+#define VF610_CLK_PLL2_PFD_SEL 33
+#define VF610_CLK_SYS_SEL 34
+#define VF610_CLK_DDR_SEL 35
+#define VF610_CLK_SYS_BUS 36
+#define VF610_CLK_PLATFORM_BUS 37
+#define VF610_CLK_IPG_BUS 38
+#define VF610_CLK_UART0 39
+#define VF610_CLK_UART1 40
+#define VF610_CLK_UART2 41
+#define VF610_CLK_UART3 42
+#define VF610_CLK_UART4 43
+#define VF610_CLK_UART5 44
+#define VF610_CLK_PIT 45
+#define VF610_CLK_I2C0 46
+#define VF610_CLK_I2C1 47
+#define VF610_CLK_I2C2 48
+#define VF610_CLK_I2C3 49
+#define VF610_CLK_FTM0_EXT_SEL 50
+#define VF610_CLK_FTM0_FIX_SEL 51
+#define VF610_CLK_FTM0_EXT_FIX_EN 52
+#define VF610_CLK_FTM1_EXT_SEL 53
+#define VF610_CLK_FTM1_FIX_SEL 54
+#define VF610_CLK_FTM1_EXT_FIX_EN 55
+#define VF610_CLK_FTM2_EXT_SEL 56
+#define VF610_CLK_FTM2_FIX_SEL 57
+#define VF610_CLK_FTM2_EXT_FIX_EN 58
+#define VF610_CLK_FTM3_EXT_SEL 59
+#define VF610_CLK_FTM3_FIX_SEL 60
+#define VF610_CLK_FTM3_EXT_FIX_EN 61
+#define VF610_CLK_FTM0 62
+#define VF610_CLK_FTM1 63
+#define VF610_CLK_FTM2 64
+#define VF610_CLK_FTM3 65
+#define VF610_CLK_ENET_50M 66
+#define VF610_CLK_ENET_25M 67
+#define VF610_CLK_ENET_SEL 68
+#define VF610_CLK_ENET 69
+#define VF610_CLK_ENET_TS_SEL 70
+#define VF610_CLK_ENET_TS 71
+#define VF610_CLK_DSPI0 72
+#define VF610_CLK_DSPI1 73
+#define VF610_CLK_DSPI2 74
+#define VF610_CLK_DSPI3 75
+#define VF610_CLK_WDT 76
+#define VF610_CLK_ESDHC0_SEL 77
+#define VF610_CLK_ESDHC0_EN 78
+#define VF610_CLK_ESDHC0_DIV 79
+#define VF610_CLK_ESDHC0 80
+#define VF610_CLK_ESDHC1_SEL 81
+#define VF610_CLK_ESDHC1_EN 82
+#define VF610_CLK_ESDHC1_DIV 83
+#define VF610_CLK_ESDHC1 84
+#define VF610_CLK_DCU0_SEL 85
+#define VF610_CLK_DCU0_EN 86
+#define VF610_CLK_DCU0_DIV 87
+#define VF610_CLK_DCU0 88
+#define VF610_CLK_DCU1_SEL 89
+#define VF610_CLK_DCU1_EN 90
+#define VF610_CLK_DCU1_DIV 91
+#define VF610_CLK_DCU1 92
+#define VF610_CLK_ESAI_SEL 93
+#define VF610_CLK_ESAI_EN 94
+#define VF610_CLK_ESAI_DIV 95
+#define VF610_CLK_ESAI 96
+#define VF610_CLK_SAI0_SEL 97
+#define VF610_CLK_SAI0_EN 98
+#define VF610_CLK_SAI0_DIV 99
+#define VF610_CLK_SAI0 100
+#define VF610_CLK_SAI1_SEL 101
+#define VF610_CLK_SAI1_EN 102
+#define VF610_CLK_SAI1_DIV 103
+#define VF610_CLK_SAI1 104
+#define VF610_CLK_SAI2_SEL 105
+#define VF610_CLK_SAI2_EN 106
+#define VF610_CLK_SAI2_DIV 107
+#define VF610_CLK_SAI2 108
+#define VF610_CLK_SAI3_SEL 109
+#define VF610_CLK_SAI3_EN 110
+#define VF610_CLK_SAI3_DIV 111
+#define VF610_CLK_SAI3 112
+#define VF610_CLK_USBC0 113
+#define VF610_CLK_USBC1 114
+#define VF610_CLK_QSPI0_SEL 115
+#define VF610_CLK_QSPI0_EN 116
+#define VF610_CLK_QSPI0_X4_DIV 117
+#define VF610_CLK_QSPI0_X2_DIV 118
+#define VF610_CLK_QSPI0_X1_DIV 119
+#define VF610_CLK_QSPI1_SEL 120
+#define VF610_CLK_QSPI1_EN 121
+#define VF610_CLK_QSPI1_X4_DIV 122
+#define VF610_CLK_QSPI1_X2_DIV 123
+#define VF610_CLK_QSPI1_X1_DIV 124
+#define VF610_CLK_QSPI0 125
+#define VF610_CLK_QSPI1 126
+#define VF610_CLK_NFC_SEL 127
+#define VF610_CLK_NFC_EN 128
+#define VF610_CLK_NFC_PRE_DIV 129
+#define VF610_CLK_NFC_FRAC_DIV 130
+#define VF610_CLK_NFC_INV 131
+#define VF610_CLK_NFC 132
+#define VF610_CLK_VADC_SEL 133
+#define VF610_CLK_VADC_EN 134
+#define VF610_CLK_VADC_DIV 135
+#define VF610_CLK_VADC_DIV_HALF 136
+#define VF610_CLK_VADC 137
+#define VF610_CLK_ADC0 138
+#define VF610_CLK_ADC1 139
+#define VF610_CLK_DAC0 140
+#define VF610_CLK_DAC1 141
+#define VF610_CLK_FLEXCAN0 142
+#define VF610_CLK_FLEXCAN1 143
+#define VF610_CLK_ASRC 144
+#define VF610_CLK_GPU_SEL 145
+#define VF610_CLK_GPU_EN 146
+#define VF610_CLK_GPU2D 147
+#define VF610_CLK_ENET0 148
+#define VF610_CLK_ENET1 149
+#define VF610_CLK_DMAMUX0 150
+#define VF610_CLK_DMAMUX1 151
+#define VF610_CLK_DMAMUX2 152
+#define VF610_CLK_DMAMUX3 153
+#define VF610_CLK_FLEXCAN0_EN 154
+#define VF610_CLK_FLEXCAN1_EN 155
+#define VF610_CLK_PLL7_USB_HOST 156
+#define VF610_CLK_USBPHY0 157
+#define VF610_CLK_USBPHY1 158
+#define VF610_CLK_LVDS1_IN 159
+#define VF610_CLK_ANACLK1 160
+#define VF610_CLK_PLL1_BYPASS_SRC 161
+#define VF610_CLK_PLL2_BYPASS_SRC 162
+#define VF610_CLK_PLL3_BYPASS_SRC 163
+#define VF610_CLK_PLL4_BYPASS_SRC 164
+#define VF610_CLK_PLL5_BYPASS_SRC 165
+#define VF610_CLK_PLL6_BYPASS_SRC 166
+#define VF610_CLK_PLL7_BYPASS_SRC 167
+#define VF610_CLK_PLL1 168
+#define VF610_CLK_PLL2 169
+#define VF610_CLK_PLL3 170
+#define VF610_CLK_PLL4 171
+#define VF610_CLK_PLL5 172
+#define VF610_CLK_PLL6 173
+#define VF610_CLK_PLL7 174
+#define VF610_PLL1_BYPASS 175
+#define VF610_PLL2_BYPASS 176
+#define VF610_PLL3_BYPASS 177
+#define VF610_PLL4_BYPASS 178
+#define VF610_PLL5_BYPASS 179
+#define VF610_PLL6_BYPASS 180
+#define VF610_PLL7_BYPASS 181
+#define VF610_CLK_SNVS 182
+#define VF610_CLK_END 183
+
+#endif /* __DT_BINDINGS_CLOCK_VF610_H */