diff options
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/bcm-cygnus.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 9 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx6qdl-clock.h | 16 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx6ul-clock.h | 149 | ||||
| -rw-r--r-- | include/dt-bindings/clock/lpc32xx-clock.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-ipq4019.h | 158 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-msm8916.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gcc-msm8996.h | 11 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msm8996.h | 17 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7793-clock.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7794-clock.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3036-cru.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3188-cru-common.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 12 |
14 files changed, 309 insertions, 77 deletions
diff --git a/include/dt-bindings/clock/bcm-cygnus.h b/include/dt-bindings/clock/bcm-cygnus.h index 32fbc4750..62ac5d782 100644 --- a/include/dt-bindings/clock/bcm-cygnus.h +++ b/include/dt-bindings/clock/bcm-cygnus.h @@ -65,4 +65,10 @@ #define BCM_CYGNUS_ASIU_ADC_CLK 1 #define BCM_CYGNUS_ASIU_PWM_CLK 2 +/* AUDIO clock ID */ +#define BCM_CYGNUS_AUDIOPLL 0 +#define BCM_CYGNUS_AUDIOPLL_CH0 1 +#define BCM_CYGNUS_AUDIOPLL_CH1 2 +#define BCM_CYGNUS_AUDIOPLL_CH2 3 + #endif /* _CLOCK_BCM_CYGNUS_H */ diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 5bd80d5ec..8e024fea2 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -765,7 +765,12 @@ #define CLK_SCLK_RGB_VCLK 109 #define CLK_SCLK_RGB_TV_VCLK 110 -#define DISP_NR_CLK 111 +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 + +#define CLK_PCLK_DECON 113 + +#define DISP_NR_CLK 114 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 @@ -1298,7 +1303,7 @@ #define CLK_MOUT_ACLK_LITE_C_B 13 #define CLK_MOUT_ACLK_LITE_C_A 14 -#define CLK_DIV_SCLK_ISP_WPWM 15 +#define CLK_DIV_SCLK_ISP_MPWM 15 #define CLK_DIV_PCLK_CAM1_83 16 #define CLK_DIV_PCLK_CAM1_166 17 #define CLK_DIV_PCLK_DBG_CAM1 18 diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 77985cc43..29050337d 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -255,6 +255,20 @@ #define IMX6QDL_CLK_CAAM_ACLK 242 #define IMX6QDL_CLK_CAAM_IPG 243 #define IMX6QDL_CLK_SPDIF_GCLK 244 -#define IMX6QDL_CLK_END 245 +#define IMX6QDL_CLK_UART_SEL 245 +#define IMX6QDL_CLK_IPG_PER_SEL 246 +#define IMX6QDL_CLK_ECSPI_SEL 247 +#define IMX6QDL_CLK_CAN_SEL 248 +#define IMX6QDL_CLK_MMDC_CH1_AXI_CG 249 +#define IMX6QDL_CLK_PRE0 250 +#define IMX6QDL_CLK_PRE1 251 +#define IMX6QDL_CLK_PRE2 252 +#define IMX6QDL_CLK_PRE3 253 +#define IMX6QDL_CLK_PRG0_AXI 254 +#define IMX6QDL_CLK_PRG1_AXI 255 +#define IMX6QDL_CLK_PRG0_APB 256 +#define IMX6QDL_CLK_PRG1_APB 257 +#define IMX6QDL_CLK_PRE_AXI 258 +#define IMX6QDL_CLK_END 259 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index c343894ce..fd8aee8f6 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -21,13 +21,13 @@ #define IMX6UL_PLL5_BYPASS_SRC 8 #define IMX6UL_PLL6_BYPASS_SRC 9 #define IMX6UL_PLL7_BYPASS_SRC 10 -#define IMX6UL_CLK_PLL1 11 -#define IMX6UL_CLK_PLL2 12 -#define IMX6UL_CLK_PLL3 13 -#define IMX6UL_CLK_PLL4 14 -#define IMX6UL_CLK_PLL5 15 -#define IMX6UL_CLK_PLL6 16 -#define IMX6UL_CLK_PLL7 17 +#define IMX6UL_CLK_PLL1 11 +#define IMX6UL_CLK_PLL2 12 +#define IMX6UL_CLK_PLL3 13 +#define IMX6UL_CLK_PLL4 14 +#define IMX6UL_CLK_PLL5 15 +#define IMX6UL_CLK_PLL6 16 +#define IMX6UL_CLK_PLL7 17 #define IMX6UL_PLL1_BYPASS 18 #define IMX6UL_PLL2_BYPASS 19 #define IMX6UL_PLL3_BYPASS 20 @@ -37,7 +37,7 @@ #define IMX6UL_PLL7_BYPASS 24 #define IMX6UL_CLK_PLL1_SYS 25 #define IMX6UL_CLK_PLL2_BUS 26 -#define IMX6UL_CLK_PLL3_USB_OTG 27 +#define IMX6UL_CLK_PLL3_USB_OTG 27 #define IMX6UL_CLK_PLL4_AUDIO 28 #define IMX6UL_CLK_PLL5_VIDEO 29 #define IMX6UL_CLK_PLL6_ENET 30 @@ -66,7 +66,7 @@ #define IMX6UL_CLK_PLL2_198M 53 #define IMX6UL_CLK_PLL3_80M 54 #define IMX6UL_CLK_PLL3_60M 55 -#define IMX6UL_CLK_STEP 56 +#define IMX6UL_CLK_STEP 56 #define IMX6UL_CLK_PLL1_SW 57 #define IMX6UL_CLK_AXI_ALT_SEL 58 #define IMX6UL_CLK_AXI_SEL 59 @@ -78,7 +78,7 @@ #define IMX6UL_CLK_USDHC2_SEL 65 #define IMX6UL_CLK_BCH_SEL 66 #define IMX6UL_CLK_GPMI_SEL 67 -#define IMX6UL_CLK_EIM_SLOW_SEL 68 +#define IMX6UL_CLK_EIM_SLOW_SEL 68 #define IMX6UL_CLK_SPDIF_SEL 69 #define IMX6UL_CLK_SAI1_SEL 70 #define IMX6UL_CLK_SAI2_SEL 71 @@ -105,9 +105,9 @@ #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 #define IMX6UL_CLK_ARM 93 #define IMX6UL_CLK_PERIPH_CLK2 94 -#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_PERIPH2_CLK2 95 #define IMX6UL_CLK_AHB 96 -#define IMX6UL_CLK_MMDC_PODF 97 +#define IMX6UL_CLK_MMDC_PODF 97 #define IMX6UL_CLK_AXI_PODF 98 #define IMX6UL_CLK_PERCLK 99 #define IMX6UL_CLK_IPG 100 @@ -133,16 +133,16 @@ #define IMX6UL_CLK_CAN_PODF 120 #define IMX6UL_CLK_ECSPI_PODF 121 #define IMX6UL_CLK_UART_PODF 122 -#define IMX6UL_CLK_ADC1 123 -#define IMX6UL_CLK_ADC2 124 +#define IMX6UL_CLK_ADC1 123 +#define IMX6UL_CLK_ADC2 124 #define IMX6UL_CLK_AIPSTZ1 125 #define IMX6UL_CLK_AIPSTZ2 126 #define IMX6UL_CLK_AIPSTZ3 127 #define IMX6UL_CLK_APBHDMA 128 #define IMX6UL_CLK_ASRC_IPG 129 #define IMX6UL_CLK_ASRC_MEM 130 -#define IMX6UL_CLK_GPMI_BCH_APB 131 -#define IMX6UL_CLK_GPMI_BCH 132 +#define IMX6UL_CLK_GPMI_BCH_APB 131 +#define IMX6UL_CLK_GPMI_BCH 132 #define IMX6UL_CLK_GPMI_IO 133 #define IMX6UL_CLK_GPMI_APB 134 #define IMX6UL_CLK_CAAM_MEM 135 @@ -154,7 +154,7 @@ #define IMX6UL_CLK_ECSPI3 141 #define IMX6UL_CLK_ECSPI4 142 #define IMX6UL_CLK_EIM 143 -#define IMX6UL_CLK_ENET 144 +#define IMX6UL_CLK_ENET 144 #define IMX6UL_CLK_ENET_AHB 145 #define IMX6UL_CLK_EPIT1 146 #define IMX6UL_CLK_EPIT2 147 @@ -166,63 +166,63 @@ #define IMX6UL_CLK_GPT1_SERIAL 153 #define IMX6UL_CLK_GPT2_BUS 154 #define IMX6UL_CLK_GPT2_SERIAL 155 -#define IMX6UL_CLK_I2C1 156 -#define IMX6UL_CLK_I2C2 157 -#define IMX6UL_CLK_I2C3 158 -#define IMX6UL_CLK_I2C4 159 -#define IMX6UL_CLK_IOMUXC 160 -#define IMX6UL_CLK_LCDIF_APB 161 -#define IMX6UL_CLK_LCDIF_PIX 162 -#define IMX6UL_CLK_MMDC_P0_FAST 163 -#define IMX6UL_CLK_MMDC_P0_IPG 164 -#define IMX6UL_CLK_OCOTP 165 -#define IMX6UL_CLK_OCRAM 166 -#define IMX6UL_CLK_PWM1 167 -#define IMX6UL_CLK_PWM2 168 -#define IMX6UL_CLK_PWM3 169 -#define IMX6UL_CLK_PWM4 170 -#define IMX6UL_CLK_PWM5 171 -#define IMX6UL_CLK_PWM6 172 -#define IMX6UL_CLK_PWM7 173 -#define IMX6UL_CLK_PWM8 174 -#define IMX6UL_CLK_PXP 175 -#define IMX6UL_CLK_QSPI 176 -#define IMX6UL_CLK_ROM 177 -#define IMX6UL_CLK_SAI1 178 -#define IMX6UL_CLK_SAI1_IPG 179 -#define IMX6UL_CLK_SAI2 180 -#define IMX6UL_CLK_SAI2_IPG 181 -#define IMX6UL_CLK_SAI3 182 -#define IMX6UL_CLK_SAI3_IPG 183 -#define IMX6UL_CLK_SDMA 184 -#define IMX6UL_CLK_SIM 185 -#define IMX6UL_CLK_SIM_S 186 -#define IMX6UL_CLK_SPBA 187 -#define IMX6UL_CLK_SPDIF 188 -#define IMX6UL_CLK_UART1_IPG 189 -#define IMX6UL_CLK_UART1_SERIAL 190 -#define IMX6UL_CLK_UART2_IPG 191 -#define IMX6UL_CLK_UART2_SERIAL 192 -#define IMX6UL_CLK_UART3_IPG 193 -#define IMX6UL_CLK_UART3_SERIAL 194 -#define IMX6UL_CLK_UART4_IPG 195 -#define IMX6UL_CLK_UART4_SERIAL 196 -#define IMX6UL_CLK_UART5_IPG 197 -#define IMX6UL_CLK_UART5_SERIAL 198 -#define IMX6UL_CLK_UART6_IPG 199 -#define IMX6UL_CLK_UART6_SERIAL 200 -#define IMX6UL_CLK_UART7_IPG 201 -#define IMX6UL_CLK_UART7_SERIAL 202 -#define IMX6UL_CLK_UART8_IPG 203 -#define IMX6UL_CLK_UART8_SERIAL 204 -#define IMX6UL_CLK_USBOH3 205 -#define IMX6UL_CLK_USDHC1 206 -#define IMX6UL_CLK_USDHC2 207 -#define IMX6UL_CLK_WDOG1 208 -#define IMX6UL_CLK_WDOG2 209 -#define IMX6UL_CLK_WDOG3 210 +#define IMX6UL_CLK_I2C1 156 +#define IMX6UL_CLK_I2C2 157 +#define IMX6UL_CLK_I2C3 158 +#define IMX6UL_CLK_I2C4 159 +#define IMX6UL_CLK_IOMUXC 160 +#define IMX6UL_CLK_LCDIF_APB 161 +#define IMX6UL_CLK_LCDIF_PIX 162 +#define IMX6UL_CLK_MMDC_P0_FAST 163 +#define IMX6UL_CLK_MMDC_P0_IPG 164 +#define IMX6UL_CLK_OCOTP 165 +#define IMX6UL_CLK_OCRAM 166 +#define IMX6UL_CLK_PWM1 167 +#define IMX6UL_CLK_PWM2 168 +#define IMX6UL_CLK_PWM3 169 +#define IMX6UL_CLK_PWM4 170 +#define IMX6UL_CLK_PWM5 171 +#define IMX6UL_CLK_PWM6 172 +#define IMX6UL_CLK_PWM7 173 +#define IMX6UL_CLK_PWM8 174 +#define IMX6UL_CLK_PXP 175 +#define IMX6UL_CLK_QSPI 176 +#define IMX6UL_CLK_ROM 177 +#define IMX6UL_CLK_SAI1 178 +#define IMX6UL_CLK_SAI1_IPG 179 +#define IMX6UL_CLK_SAI2 180 +#define IMX6UL_CLK_SAI2_IPG 181 +#define IMX6UL_CLK_SAI3 182 +#define IMX6UL_CLK_SAI3_IPG 183 +#define IMX6UL_CLK_SDMA 184 +#define IMX6UL_CLK_SIM 185 +#define IMX6UL_CLK_SIM_S 186 +#define IMX6UL_CLK_SPBA 187 +#define IMX6UL_CLK_SPDIF 188 +#define IMX6UL_CLK_UART1_IPG 189 +#define IMX6UL_CLK_UART1_SERIAL 190 +#define IMX6UL_CLK_UART2_IPG 191 +#define IMX6UL_CLK_UART2_SERIAL 192 +#define IMX6UL_CLK_UART3_IPG 193 +#define IMX6UL_CLK_UART3_SERIAL 194 +#define IMX6UL_CLK_UART4_IPG 195 +#define IMX6UL_CLK_UART4_SERIAL 196 +#define IMX6UL_CLK_UART5_IPG 197 +#define IMX6UL_CLK_UART5_SERIAL 198 +#define IMX6UL_CLK_UART6_IPG 199 +#define IMX6UL_CLK_UART6_SERIAL 200 +#define IMX6UL_CLK_UART7_IPG 201 +#define IMX6UL_CLK_UART7_SERIAL 202 +#define IMX6UL_CLK_UART8_IPG 203 +#define IMX6UL_CLK_UART8_SERIAL 204 +#define IMX6UL_CLK_USBOH3 205 +#define IMX6UL_CLK_USDHC1 206 +#define IMX6UL_CLK_USDHC2 207 +#define IMX6UL_CLK_WDOG1 208 +#define IMX6UL_CLK_WDOG2 209 +#define IMX6UL_CLK_WDOG3 210 #define IMX6UL_CLK_LDB_DI0 211 -#define IMX6UL_CLK_AXI 212 +#define IMX6UL_CLK_AXI 212 #define IMX6UL_CLK_SPDIF_GCLK 213 #define IMX6UL_CLK_GPT_3M 214 #define IMX6UL_CLK_SIM2 215 @@ -234,7 +234,8 @@ #define IMX6UL_CLK_CSI_SEL 221 #define IMX6UL_CLK_CSI_PODF 222 #define IMX6UL_CLK_PLL3_120M 223 +#define IMX6UL_CLK_KPP 224 -#define IMX6UL_CLK_END 224 +#define IMX6UL_CLK_END 225 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h index bcb1c9a73..d41b6fea1 100644 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ b/include/dt-bindings/clock/lpc32xx-clock.h @@ -47,6 +47,7 @@ #define LPC32XX_CLK_PWM1 32 #define LPC32XX_CLK_PWM2 33 #define LPC32XX_CLK_ADC 34 +#define LPC32XX_CLK_HCLK_PLL 35 /* LPC32XX USB clocks */ #define LPC32XX_USB_CLK_I2C 1 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq4019.h b/include/dt-bindings/clock/qcom,gcc-ipq4019.h new file mode 100644 index 000000000..6240e5b0e --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h @@ -0,0 +1,158 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_CLK_IPQ4019_H__ +#define __QCOM_CLK_IPQ4019_H__ + +#define GCC_DUMMY_CLK 0 +#define AUDIO_CLK_SRC 1 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 +#define BLSP1_UART1_APPS_CLK_SRC 6 +#define BLSP1_UART2_APPS_CLK_SRC 7 +#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 +#define GCC_APPS_CLK_SRC 9 +#define GCC_APPS_AHB_CLK_SRC 10 +#define GP1_CLK_SRC 11 +#define GP2_CLK_SRC 12 +#define GP3_CLK_SRC 13 +#define SDCC1_APPS_CLK_SRC 14 +#define FEPHY_125M_DLY_CLK_SRC 15 +#define WCSS2G_CLK_SRC 16 +#define WCSS5G_CLK_SRC 17 +#define GCC_APSS_AHB_CLK 18 +#define GCC_AUDIO_AHB_CLK 19 +#define GCC_AUDIO_PWM_CLK 20 +#define GCC_BLSP1_AHB_CLK 21 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_DCD_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP2_CLK 30 +#define GCC_GP3_CLK 31 +#define GCC_BOOT_ROM_AHB_CLK 32 +#define GCC_CRYPTO_AHB_CLK 33 +#define GCC_CRYPTO_AXI_CLK 34 +#define GCC_CRYPTO_CLK 35 +#define GCC_ESS_CLK 36 +#define GCC_IMEM_AXI_CLK 37 +#define GCC_IMEM_CFG_AHB_CLK 38 +#define GCC_PCIE_AHB_CLK 39 +#define GCC_PCIE_AXI_M_CLK 40 +#define GCC_PCIE_AXI_S_CLK 41 +#define GCC_PCNOC_AHB_CLK 42 +#define GCC_PRNG_AHB_CLK 43 +#define GCC_QPIC_AHB_CLK 44 +#define GCC_QPIC_CLK 45 +#define GCC_SDCC1_AHB_CLK 46 +#define GCC_SDCC1_APPS_CLK 47 +#define GCC_SNOC_PCNOC_AHB_CLK 48 +#define GCC_SYS_NOC_125M_CLK 49 +#define GCC_SYS_NOC_AXI_CLK 50 +#define GCC_TCSR_AHB_CLK 51 +#define GCC_TLMM_AHB_CLK 52 +#define GCC_USB2_MASTER_CLK 53 +#define GCC_USB2_SLEEP_CLK 54 +#define GCC_USB2_MOCK_UTMI_CLK 55 +#define GCC_USB3_MASTER_CLK 56 +#define GCC_USB3_SLEEP_CLK 57 +#define GCC_USB3_MOCK_UTMI_CLK 58 +#define GCC_WCSS2G_CLK 59 +#define GCC_WCSS2G_REF_CLK 60 +#define GCC_WCSS2G_RTC_CLK 61 +#define GCC_WCSS5G_CLK 62 +#define GCC_WCSS5G_REF_CLK 63 +#define GCC_WCSS5G_RTC_CLK 64 + +#define WIFI0_CPU_INIT_RESET 0 +#define WIFI0_RADIO_SRIF_RESET 1 +#define WIFI0_RADIO_WARM_RESET 2 +#define WIFI0_RADIO_COLD_RESET 3 +#define WIFI0_CORE_WARM_RESET 4 +#define WIFI0_CORE_COLD_RESET 5 +#define WIFI1_CPU_INIT_RESET 6 +#define WIFI1_RADIO_SRIF_RESET 7 +#define WIFI1_RADIO_WARM_RESET 8 +#define WIFI1_RADIO_COLD_RESET 9 +#define WIFI1_CORE_WARM_RESET 10 +#define WIFI1_CORE_COLD_RESET 11 +#define USB3_UNIPHY_PHY_ARES 12 +#define USB3_HSPHY_POR_ARES 13 +#define USB3_HSPHY_S_ARES 14 +#define USB2_HSPHY_POR_ARES 15 +#define USB2_HSPHY_S_ARES 16 +#define PCIE_PHY_AHB_ARES 17 +#define PCIE_AHB_ARES 18 +#define PCIE_PWR_ARES 19 +#define PCIE_PIPE_STICKY_ARES 20 +#define PCIE_AXI_M_STICKY_ARES 21 +#define PCIE_PHY_ARES 22 +#define PCIE_PARF_XPU_ARES 23 +#define PCIE_AXI_S_XPU_ARES 24 +#define PCIE_AXI_M_VMIDMT_ARES 25 +#define PCIE_PIPE_ARES 26 +#define PCIE_AXI_S_ARES 27 +#define PCIE_AXI_M_ARES 28 +#define ESS_RESET 29 +#define GCC_BLSP1_BCR 30 +#define GCC_BLSP1_QUP1_BCR 31 +#define GCC_BLSP1_UART1_BCR 32 +#define GCC_BLSP1_QUP2_BCR 33 +#define GCC_BLSP1_UART2_BCR 34 +#define GCC_BIMC_BCR 35 +#define GCC_TLMM_BCR 36 +#define GCC_IMEM_BCR 37 +#define GCC_ESS_BCR 38 +#define GCC_PRNG_BCR 39 +#define GCC_BOOT_ROM_BCR 40 +#define GCC_CRYPTO_BCR 41 +#define GCC_SDCC1_BCR 42 +#define GCC_SEC_CTRL_BCR 43 +#define GCC_AUDIO_BCR 44 +#define GCC_QPIC_BCR 45 +#define GCC_PCIE_BCR 46 +#define GCC_USB2_BCR 47 +#define GCC_USB2_PHY_BCR 48 +#define GCC_USB3_BCR 49 +#define GCC_USB3_PHY_BCR 50 +#define GCC_SYSTEM_NOC_BCR 51 +#define GCC_PCNOC_BCR 52 +#define GCC_DCD_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_TCSR_BCR 68 +#define GCC_QDSS_BCR 69 +#define GCC_MPM_BCR 70 +#define GCC_SPDM_BCR 71 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h b/include/dt-bindings/clock/qcom,gcc-msm8916.h index 257e2fbed..28a27a4ed 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8916.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h @@ -174,6 +174,7 @@ #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 #define GCC_CODEC_DIGCODEC_CLK 159 +#define GCC_MSS_Q6_BIMC_AXI_CLK 160 /* Indexes for GDSCs */ #define BIMC_GDSC 0 diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h index 888e75ce8..6f814db11 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -336,4 +336,15 @@ #define GCC_MSS_Q6_BCR 99 #define GCC_QREFS_VBG_CAL_BCR 100 +/* Indexes for GDSCs */ +#define AGGRE0_NOC_GDSC 0 +#define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 +#define HLOS1_VOTE_LPASS_ADSP_GDSC 2 +#define HLOS1_VOTE_LPASS_CORE_GDSC 3 +#define USB30_GDSC 4 +#define PCIE0_GDSC 5 +#define PCIE1_GDSC 6 +#define PCIE2_GDSC 7 +#define UFS_GDSC 8 + #endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h index 9b81ca65f..7d3a7fa1a 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h @@ -282,4 +282,21 @@ #define FD_BCR 58 #define MMSS_SPDM_RM_BCR 59 +/* Indexes for GDSCs */ +#define MMAGIC_VIDEO_GDSC 0 +#define MMAGIC_MDSS_GDSC 1 +#define MMAGIC_CAMSS_GDSC 2 +#define GPU_GDSC 3 +#define VENUS_GDSC 4 +#define VENUS_CORE0_GDSC 5 +#define VENUS_CORE1_GDSC 6 +#define CAMSS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 +#define JPEG_GDSC 10 +#define CPP_GDSC 11 +#define FD_GDSC 12 +#define MDSS_GDSC 13 +#define GPU_GX_GDSC 14 + #endif diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h index 1579e07f9..efcbc594f 100644 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ b/include/dt-bindings/clock/r8a7793-clock.h @@ -145,6 +145,8 @@ #define R8A7793_CLK_SCU_ALL 17 #define R8A7793_CLK_SCU_DVC1 18 #define R8A7793_CLK_SCU_DVC0 19 +#define R8A7793_CLK_SCU_CTU1_MIX1 20 +#define R8A7793_CLK_SCU_CTU0_MIX0 21 #define R8A7793_CLK_SCU_SRC9 22 #define R8A7793_CLK_SCU_SRC8 23 #define R8A7793_CLK_SCU_SRC7 24 diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index a7a7e0370..f843de6bf 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -84,6 +84,7 @@ /* MSTP8 */ #define R8A7794_CLK_VIN1 10 #define R8A7794_CLK_VIN0 11 +#define R8A7794_CLK_ETHERAVB 12 #define R8A7794_CLK_ETHER 13 /* MSTP9 */ diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h index ebc7a7b43..de44109a3 100644 --- a/include/dt-bindings/clock/rk3036-cru.h +++ b/include/dt-bindings/clock/rk3036-cru.h @@ -54,6 +54,7 @@ #define SCLK_PVTM_VIDEO 125 #define SCLK_MAC 151 #define SCLK_MACREF 152 +#define SCLK_MACPLL 153 #define SCLK_SFC 160 /* aclk gates */ @@ -92,6 +93,7 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_MAC 460 #define HCLK_I2S 462 #define HCLK_LCDC 465 #define HCLK_ROM 467 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 8df77a7c0..4f53e70f6 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -55,6 +55,7 @@ #define SCLK_TIMER6 90 #define SCLK_JTAG 91 #define SCLK_SMC 92 +#define SCLK_TSADC 93 #define DCLK_LCDC0 190 #define DCLK_LCDC1 191 diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index a78dd891e..5d43ed9b0 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -29,6 +29,7 @@ #define SCLK_SDMMC 68 #define SCLK_SDIO 69 #define SCLK_EMMC 71 +#define SCLK_TSADC 72 #define SCLK_UART0 77 #define SCLK_UART1 78 #define SCLK_UART2 79 @@ -49,10 +50,17 @@ #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_EMMC_SAMPLE 121 +#define SCLK_VOP 122 +#define SCLK_HDMI_HDCP 123 + +/* dclk gates */ +#define DCLK_VOP 190 +#define DCLK_HDMI_PHY 191 /* aclk gates */ #define ACLK_DMAC 194 #define ACLK_PERI 210 +#define ACLK_VOP 211 /* pclk gates */ #define PCLK_GPIO0 320 @@ -68,11 +76,15 @@ #define PCLK_UART0 341 #define PCLK_UART1 342 #define PCLK_UART2 343 +#define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 #define PCLK_PERI 363 +#define PCLK_HDMI_CTRL 364 +#define PCLK_HDMI_PHY 365 /* hclk gates */ +#define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 #define HCLK_SDIO 457 |