From 57f0f512b273f60d52568b8c6b77e17f5636edc0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Fabian=20Silva=20Delgado?= Date: Wed, 5 Aug 2015 17:04:01 -0300 Subject: Initial import --- arch/arm/boot/dts/exynos5440-ssdk5440.dts | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 arch/arm/boot/dts/exynos5440-ssdk5440.dts (limited to 'arch/arm/boot/dts/exynos5440-ssdk5440.dts') diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts new file mode 100644 index 000000000..ff55dac6e --- /dev/null +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -0,0 +1,78 @@ +/* + * SAMSUNG SSDK5440 board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +#include "exynos5440.dtsi" + +/ { + model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; + compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; + + chosen { + bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; + }; + + spi_0: spi@D0000 { + + flash: w25q128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128"; + spi-max-frequency = <15625000>; + reg = <0>; + controller-data { + samsung,spi-feedback-delay = <0>; + }; + + partition@00000 { + label = "BootLoader"; + reg = <0x60000 0x80000>; + read-only; + }; + + partition@e0000 { + label = "Recovery-Kernel"; + reg = <0xe0000 0x300000>; + read-only; + }; + + partition@3e0000 { + label = "CRAM-FS"; + reg = <0x3e0000 0x700000>; + read-only; + }; + + partition@ae0000 { + label = "User-Data"; + reg = <0xae0000 0x520000>; + }; + + }; + + }; + + fixed-rate-clocks { + xtal { + compatible = "samsung,clock-xtal"; + clock-frequency = <50000000>; + }; + }; + + pcie@290000 { + reset-gpio = <&pin_ctrl 5 0>; + status = "okay"; + }; + + pcie@2a0000 { + reset-gpio = <&pin_ctrl 22 0>; + status = "okay"; + }; +}; -- cgit v1.2.3