From 03dd4cb26d967f9588437b0fc9cc0e8353322bb7 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Fri, 25 Mar 2016 03:53:42 -0300 Subject: Linux-libre 4.5-gnu --- arch/arm/mach-mv78xx0/Kconfig | 15 ++- arch/arm/mach-mv78xx0/Makefile | 2 + arch/arm/mach-mv78xx0/bridge-regs.h | 35 +++++++ arch/arm/mach-mv78xx0/buffalo-wxl-setup.c | 3 +- arch/arm/mach-mv78xx0/common.c | 4 +- arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 3 +- arch/arm/mach-mv78xx0/include/mach/bridge-regs.h | 37 ------- arch/arm/mach-mv78xx0/include/mach/entry-macro.S | 41 -------- arch/arm/mach-mv78xx0/include/mach/hardware.h | 14 --- arch/arm/mach-mv78xx0/include/mach/irqs.h | 94 ----------------- arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | 127 ----------------------- arch/arm/mach-mv78xx0/include/mach/uncompress.h | 46 -------- arch/arm/mach-mv78xx0/irq.c | 35 ++++++- arch/arm/mach-mv78xx0/irqs.h | 92 ++++++++++++++++ arch/arm/mach-mv78xx0/mpp.c | 2 +- arch/arm/mach-mv78xx0/mv78xx0.h | 127 +++++++++++++++++++++++ arch/arm/mach-mv78xx0/pcie.c | 2 +- arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 3 +- 18 files changed, 311 insertions(+), 371 deletions(-) create mode 100644 arch/arm/mach-mv78xx0/bridge-regs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/bridge-regs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/entry-macro.S delete mode 100644 arch/arm/mach-mv78xx0/include/mach/hardware.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/irqs.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/mv78xx0.h delete mode 100644 arch/arm/mach-mv78xx0/include/mach/uncompress.h create mode 100644 arch/arm/mach-mv78xx0/irqs.h create mode 100644 arch/arm/mach-mv78xx0/mv78xx0.h (limited to 'arch/arm/mach-mv78xx0') diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index f2d309d06..a32575fa3 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -1,6 +1,15 @@ -if ARCH_MV78XX0 +menuconfig ARCH_MV78XX0 + bool "Marvell MV78xx0" if ARCH_MULTI_V5 + select ARCH_REQUIRE_GPIOLIB + select CPU_FEROCEON + select MVEBU_MBUS + select PCI + select PLAT_ORION_LEGACY + help + Support for the following Marvell MV78xx0 series SoCs: + MV781x0, MV782x0. -menu "Marvell MV78xx0 Implementations" +if ARCH_MV78XX0 config MACH_DB78X00_BP bool "Marvell DB-78x00-BP Development Board" @@ -20,6 +29,4 @@ config MACH_TERASTATION_WXL Say 'Y' here if you want your kernel to support the Buffalo WXL Nas. -endmenu - endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 7cd04634d..ddb3aa98a 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,3 +1,5 @@ +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include + obj-y += common.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o diff --git a/arch/arm/mach-mv78xx0/bridge-regs.h b/arch/arm/mach-mv78xx0/bridge-regs.h new file mode 100644 index 000000000..2f54e1753 --- /dev/null +++ b/arch/arm/mach-mv78xx0/bridge-regs.h @@ -0,0 +1,35 @@ +/* + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include "mv78xx0.h" + +#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) +#define L2_WRITETHROUGH 0x00020000 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) +#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) +#define IRQ_CAUSE_ERR_OFF 0x0000 +#define IRQ_CAUSE_LOW_OFF 0x0004 +#define IRQ_CAUSE_HIGH_OFF 0x0008 +#define IRQ_MASK_ERR_OFF 0x000c +#define IRQ_MASK_LOW_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) +#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) + +#endif diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c index 1f2ef98b3..e112f2e7c 100644 --- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -17,9 +17,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" #include "mpp.h" @@ -146,6 +146,7 @@ subsys_initcall(wxl_pci_init); MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") /* Maintainer: Sebastien Requiem */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = wxl_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index e6ac679be..a1a04df9c 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -18,13 +18,13 @@ #include #include #include -#include -#include #include #include #include #include #include +#include "mv78xx0.h" +#include "bridge-regs.h" #include "common.h" static int get_tclk(void); diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 4e0f22b30..cf16e08d4 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c @@ -15,9 +15,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" static struct mv643xx_eth_platform_data db78x00_ge00_data = { @@ -94,6 +94,7 @@ subsys_initcall(db78x00_pci_init); MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = db78x00_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h deleted file mode 100644 index e20d6da23..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_BRIDGE_REGS_H -#define __ASM_ARCH_BRIDGE_REGS_H - -#include - -#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) -#define L2_WRITETHROUGH 0x00020000 - -#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) -#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) -#define SOFT_RESET_OUT_EN 0x00000004 - -#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) -#define SOFT_RESET 0x00000001 - -#define BRIDGE_INT_TIMER1_CLR (~0x0004) - -#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) -#define IRQ_CAUSE_ERR_OFF 0x0000 -#define IRQ_CAUSE_LOW_OFF 0x0004 -#define IRQ_CAUSE_HIGH_OFF 0x0008 -#define IRQ_MASK_ERR_OFF 0x000c -#define IRQ_MASK_LOW_OFF 0x0010 -#define IRQ_MASK_HIGH_OFF 0x0014 - -#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) -#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S b/arch/arm/mach-mv78xx0/include/mach/entry-macro.S deleted file mode 100644 index 6b1f088e0..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/entry-macro.S +++ /dev/null @@ -1,41 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for Marvell MV78xx0 platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include - - .macro get_irqnr_preamble, base, tmp - ldr \base, =IRQ_VIRT_BASE - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - @ check low interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] - ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] - mov \irqnr, #31 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no low interrupts set, check high interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] - ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF] - mov \irqnr, #63 - ands \irqstat, \irqstat, \tmp - bne 1001f - - @ if no high interrupts set, check error interrupts - ldr \irqstat, [\base, #IRQ_CAUSE_ERR_OFF] - ldr \tmp, [\base, #IRQ_MASK_ERR_OFF] - mov \irqnr, #95 - ands \irqstat, \irqstat, \tmp - - @ find first active interrupt source -1001: clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm diff --git a/arch/arm/mach-mv78xx0/include/mach/hardware.h b/arch/arm/mach-mv78xx0/include/mach/hardware.h deleted file mode 100644 index 67cab0a08..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/hardware.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/hardware.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include "mv78xx0.h" - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/irqs.h b/arch/arm/mach-mv78xx0/include/mach/irqs.h deleted file mode 100644 index fa1d42219..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/irqs.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/irqs.h - * - * IRQ definitions for Marvell MV78xx0 SoCs - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_IRQS_H -#define __ASM_ARCH_IRQS_H - -/* - * MV78xx0 Low Interrupt Controller - */ -#define IRQ_MV78XX0_ERR 0 -#define IRQ_MV78XX0_SPI 1 -#define IRQ_MV78XX0_I2C_0 2 -#define IRQ_MV78XX0_I2C_1 3 -#define IRQ_MV78XX0_IDMA_0 4 -#define IRQ_MV78XX0_IDMA_1 5 -#define IRQ_MV78XX0_IDMA_2 6 -#define IRQ_MV78XX0_IDMA_3 7 -#define IRQ_MV78XX0_TIMER_0 8 -#define IRQ_MV78XX0_TIMER_1 9 -#define IRQ_MV78XX0_TIMER_2 10 -#define IRQ_MV78XX0_TIMER_3 11 -#define IRQ_MV78XX0_UART_0 12 -#define IRQ_MV78XX0_UART_1 13 -#define IRQ_MV78XX0_UART_2 14 -#define IRQ_MV78XX0_UART_3 15 -#define IRQ_MV78XX0_USB_0 16 -#define IRQ_MV78XX0_USB_1 17 -#define IRQ_MV78XX0_USB_2 18 -#define IRQ_MV78XX0_CRYPTO 19 -#define IRQ_MV78XX0_SDIO_0 20 -#define IRQ_MV78XX0_SDIO_1 21 -#define IRQ_MV78XX0_XOR_0 22 -#define IRQ_MV78XX0_XOR_1 23 -#define IRQ_MV78XX0_I2S_0 24 -#define IRQ_MV78XX0_I2S_1 25 -#define IRQ_MV78XX0_SATA 26 -#define IRQ_MV78XX0_TDMI 27 - -/* - * MV78xx0 High Interrupt Controller - */ -#define IRQ_MV78XX0_PCIE_00 32 -#define IRQ_MV78XX0_PCIE_01 33 -#define IRQ_MV78XX0_PCIE_02 34 -#define IRQ_MV78XX0_PCIE_03 35 -#define IRQ_MV78XX0_PCIE_10 36 -#define IRQ_MV78XX0_PCIE_11 37 -#define IRQ_MV78XX0_PCIE_12 38 -#define IRQ_MV78XX0_PCIE_13 39 -#define IRQ_MV78XX0_GE00_SUM 40 -#define IRQ_MV78XX0_GE00_RX 41 -#define IRQ_MV78XX0_GE00_TX 42 -#define IRQ_MV78XX0_GE00_MISC 43 -#define IRQ_MV78XX0_GE01_SUM 44 -#define IRQ_MV78XX0_GE01_RX 45 -#define IRQ_MV78XX0_GE01_TX 46 -#define IRQ_MV78XX0_GE01_MISC 47 -#define IRQ_MV78XX0_GE10_SUM 48 -#define IRQ_MV78XX0_GE10_RX 49 -#define IRQ_MV78XX0_GE10_TX 50 -#define IRQ_MV78XX0_GE10_MISC 51 -#define IRQ_MV78XX0_GE11_SUM 52 -#define IRQ_MV78XX0_GE11_RX 53 -#define IRQ_MV78XX0_GE11_TX 54 -#define IRQ_MV78XX0_GE11_MISC 55 -#define IRQ_MV78XX0_GPIO_0_7 56 -#define IRQ_MV78XX0_GPIO_8_15 57 -#define IRQ_MV78XX0_GPIO_16_23 58 -#define IRQ_MV78XX0_GPIO_24_31 59 -#define IRQ_MV78XX0_DB_IN 60 -#define IRQ_MV78XX0_DB_OUT 61 - -/* - * MV78xx0 Error Interrupt Controller - */ -#define IRQ_MV78XX0_GE_ERR 70 - -/* - * MV78XX0 General Purpose Pins - */ -#define IRQ_MV78XX0_GPIO_START 96 -#define NR_GPIO_IRQS 32 - -#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) - - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h deleted file mode 100644 index 723748d8b..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/mv78xx0.h - * - * Generic definitions for Marvell MV78xx0 SoC flavors: - * MV781x0 and MV782x0. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef __ASM_ARCH_MV78XX0_H -#define __ASM_ARCH_MV78XX0_H - -/* - * Marvell MV78xx0 address maps. - * - * phys - * c0000000 PCIe Memory space - * f0800000 PCIe #0 I/O space - * f0900000 PCIe #1 I/O space - * f0a00000 PCIe #2 I/O space - * f0b00000 PCIe #3 I/O space - * f0c00000 PCIe #4 I/O space - * f0d00000 PCIe #5 I/O space - * f0e00000 PCIe #6 I/O space - * f0f00000 PCIe #7 I/O space - * f1000000 on-chip peripheral registers - * - * virt phys size - * fe400000 f102x000 16K core-specific peripheral registers - * fee00000 f0800000 64K PCIe #0 I/O space - * fee10000 f0900000 64K PCIe #1 I/O space - * fee20000 f0a00000 64K PCIe #2 I/O space - * fee30000 f0b00000 64K PCIe #3 I/O space - * fee40000 f0c00000 64K PCIe #4 I/O space - * fee50000 f0d00000 64K PCIe #5 I/O space - * fee60000 f0e00000 64K PCIe #6 I/O space - * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers - */ -#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 -#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 -#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) -#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 -#define MV78XX0_CORE_REGS_SIZE SZ_16K - -#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) -#define MV78XX0_PCIE_IO_SIZE SZ_1M - -#define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) -#define MV78XX0_REGS_SIZE SZ_1M - -#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 -#define MV78XX0_PCIE_MEM_SIZE 0x30000000 - -/* - * Core-specific peripheral registers. - */ -#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) -#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) -#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) -#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) -#define BRIDGE_WINS_SZ (0xA000) - -/* - * Register Map - */ -#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) -#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) -#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) -#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) -#define DDR_WINDOW_CPU_SZ (0x20) - -#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) -#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) -#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) -#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) -#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) -#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) -#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) -#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) -#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) -#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) -#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) -#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) -#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) -#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) -#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) - -#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) -#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) - -#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) -#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) -#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) -#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) - -#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) -#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) -#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) - -#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) -#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) - -#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) -#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) -#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) -#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) - -#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) - -/* - * Supported devices and revisions. - */ -#define MV78X00_Z0_DEV_ID 0x6381 -#define MV78X00_REV_Z0 1 - -#define MV78100_DEV_ID 0x7810 -#define MV78100_REV_A0 1 -#define MV78100_REV_A1 2 - -#define MV78200_DEV_ID 0x7820 -#define MV78200_REV_A0 1 - -#endif diff --git a/arch/arm/mach-mv78xx0/include/mach/uncompress.h b/arch/arm/mach-mv78xx0/include/mach/uncompress.h deleted file mode 100644 index 6a761c44a..000000000 --- a/arch/arm/mach-mv78xx0/include/mach/uncompress.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * arch/arm/mach-mv78xx0/include/mach/uncompress.h - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include - -#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE) - -static void putc(const char c) -{ - unsigned char *base = SERIAL_BASE; - int i; - - for (i = 0; i < 0x1000; i++) { - if (base[UART_LSR << 2] & UART_LSR_THRE) - break; - barrier(); - } - - base[UART_TX << 2] = c; -} - -static void flush(void) -{ - unsigned char *base = SERIAL_BASE; - unsigned char mask; - int i; - - mask = UART_LSR_TEMT | UART_LSR_THRE; - - for (i = 0; i < 0x1000; i++) { - if ((base[UART_LSR << 2] & mask) == mask) - break; - barrier(); - } -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 320734440..788569e96 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -11,9 +11,10 @@ #include #include #include -#include +#include #include #include +#include "bridge-regs.h" #include "common.h" static int __initdata gpio0_irqs[4] = { @@ -23,12 +24,44 @@ static int __initdata gpio0_irqs[4] = { IRQ_MV78XX0_GPIO_24_31, }; +static void __iomem *mv78xx0_irq_base = IRQ_VIRT_BASE; + +static asmlinkage void +__exception_irq_entry mv78xx0_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); + stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); + if (stat) { + unsigned int hwirq = 64 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} + void __init mv78xx0_init_irq(void) { orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF); + set_handle_irq(mv78xx0_legacy_handle_irq); + /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of diff --git a/arch/arm/mach-mv78xx0/irqs.h b/arch/arm/mach-mv78xx0/irqs.h new file mode 100644 index 000000000..67e0fe730 --- /dev/null +++ b/arch/arm/mach-mv78xx0/irqs.h @@ -0,0 +1,92 @@ +/* + * IRQ definitions for Marvell MV78xx0 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * MV78xx0 Low Interrupt Controller + */ +#define IRQ_MV78XX0_ERR 0 +#define IRQ_MV78XX0_SPI 1 +#define IRQ_MV78XX0_I2C_0 2 +#define IRQ_MV78XX0_I2C_1 3 +#define IRQ_MV78XX0_IDMA_0 4 +#define IRQ_MV78XX0_IDMA_1 5 +#define IRQ_MV78XX0_IDMA_2 6 +#define IRQ_MV78XX0_IDMA_3 7 +#define IRQ_MV78XX0_TIMER_0 8 +#define IRQ_MV78XX0_TIMER_1 9 +#define IRQ_MV78XX0_TIMER_2 10 +#define IRQ_MV78XX0_TIMER_3 11 +#define IRQ_MV78XX0_UART_0 12 +#define IRQ_MV78XX0_UART_1 13 +#define IRQ_MV78XX0_UART_2 14 +#define IRQ_MV78XX0_UART_3 15 +#define IRQ_MV78XX0_USB_0 16 +#define IRQ_MV78XX0_USB_1 17 +#define IRQ_MV78XX0_USB_2 18 +#define IRQ_MV78XX0_CRYPTO 19 +#define IRQ_MV78XX0_SDIO_0 20 +#define IRQ_MV78XX0_SDIO_1 21 +#define IRQ_MV78XX0_XOR_0 22 +#define IRQ_MV78XX0_XOR_1 23 +#define IRQ_MV78XX0_I2S_0 24 +#define IRQ_MV78XX0_I2S_1 25 +#define IRQ_MV78XX0_SATA 26 +#define IRQ_MV78XX0_TDMI 27 + +/* + * MV78xx0 High Interrupt Controller + */ +#define IRQ_MV78XX0_PCIE_00 32 +#define IRQ_MV78XX0_PCIE_01 33 +#define IRQ_MV78XX0_PCIE_02 34 +#define IRQ_MV78XX0_PCIE_03 35 +#define IRQ_MV78XX0_PCIE_10 36 +#define IRQ_MV78XX0_PCIE_11 37 +#define IRQ_MV78XX0_PCIE_12 38 +#define IRQ_MV78XX0_PCIE_13 39 +#define IRQ_MV78XX0_GE00_SUM 40 +#define IRQ_MV78XX0_GE00_RX 41 +#define IRQ_MV78XX0_GE00_TX 42 +#define IRQ_MV78XX0_GE00_MISC 43 +#define IRQ_MV78XX0_GE01_SUM 44 +#define IRQ_MV78XX0_GE01_RX 45 +#define IRQ_MV78XX0_GE01_TX 46 +#define IRQ_MV78XX0_GE01_MISC 47 +#define IRQ_MV78XX0_GE10_SUM 48 +#define IRQ_MV78XX0_GE10_RX 49 +#define IRQ_MV78XX0_GE10_TX 50 +#define IRQ_MV78XX0_GE10_MISC 51 +#define IRQ_MV78XX0_GE11_SUM 52 +#define IRQ_MV78XX0_GE11_RX 53 +#define IRQ_MV78XX0_GE11_TX 54 +#define IRQ_MV78XX0_GE11_MISC 55 +#define IRQ_MV78XX0_GPIO_0_7 56 +#define IRQ_MV78XX0_GPIO_8_15 57 +#define IRQ_MV78XX0_GPIO_16_23 58 +#define IRQ_MV78XX0_GPIO_24_31 59 +#define IRQ_MV78XX0_DB_IN 60 +#define IRQ_MV78XX0_DB_OUT 61 + +/* + * MV78xx0 Error Interrupt Controller + */ +#define IRQ_MV78XX0_GE_ERR 70 + +/* + * MV78XX0 General Purpose Pins + */ +#define IRQ_MV78XX0_GPIO_START 96 +#define NR_GPIO_IRQS 32 + +#define MV78XX0_NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS) + + +#endif diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c index df5034217..72843c02e 100644 --- a/arch/arm/mach-mv78xx0/mpp.c +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include "mv78xx0.h" #include "common.h" #include "mpp.h" diff --git a/arch/arm/mach-mv78xx0/mv78xx0.h b/arch/arm/mach-mv78xx0/mv78xx0.h new file mode 100644 index 000000000..2db1265ec --- /dev/null +++ b/arch/arm/mach-mv78xx0/mv78xx0.h @@ -0,0 +1,127 @@ +/* + * Generic definitions for Marvell MV78xx0 SoC flavors: + * MV781x0 and MV782x0. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_MV78XX0_H +#define __ASM_ARCH_MV78XX0_H + +#include "irqs.h" + +/* + * Marvell MV78xx0 address maps. + * + * phys + * c0000000 PCIe Memory space + * f0800000 PCIe #0 I/O space + * f0900000 PCIe #1 I/O space + * f0a00000 PCIe #2 I/O space + * f0b00000 PCIe #3 I/O space + * f0c00000 PCIe #4 I/O space + * f0d00000 PCIe #5 I/O space + * f0e00000 PCIe #6 I/O space + * f0f00000 PCIe #7 I/O space + * f1000000 on-chip peripheral registers + * + * virt phys size + * fe400000 f102x000 16K core-specific peripheral registers + * fee00000 f0800000 64K PCIe #0 I/O space + * fee10000 f0900000 64K PCIe #1 I/O space + * fee20000 f0a00000 64K PCIe #2 I/O space + * fee30000 f0b00000 64K PCIe #3 I/O space + * fee40000 f0c00000 64K PCIe #4 I/O space + * fee50000 f0d00000 64K PCIe #5 I/O space + * fee60000 f0e00000 64K PCIe #6 I/O space + * fee70000 f0f00000 64K PCIe #7 I/O space + * fd000000 f1000000 1M on-chip peripheral registers + */ +#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 +#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 +#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) +#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 +#define MV78XX0_CORE_REGS_SIZE SZ_16K + +#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_SIZE SZ_1M + +#define MV78XX0_REGS_PHYS_BASE 0xf1000000 +#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) +#define MV78XX0_REGS_SIZE SZ_1M + +#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 +#define MV78XX0_PCIE_MEM_SIZE 0x30000000 + +/* + * Core-specific peripheral registers. + */ +#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) +#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE) +#define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE) +#define BRIDGE_WINS_SZ (0xA000) + +/* + * Register Map + */ +#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) +#define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000) +#define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500) +#define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570) +#define DDR_WINDOW_CPU_SZ (0x20) + +#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) +#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) +#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) +#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) +#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) +#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) +#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) +#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) +#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) +#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) +#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) +#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) +#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) +#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) +#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) + +#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) +#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) + +#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) +#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) +#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) +#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) + +#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) +#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) +#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) + +#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) +#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) + +#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) +#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) +#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) +#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) + +#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) + +/* + * Supported devices and revisions. + */ +#define MV78X00_Z0_DEV_ID 0x6381 +#define MV78X00_REV_Z0 1 + +#define MV78100_DEV_ID 0x7810 +#define MV78100_REV_A0 1 +#define MV78100_REV_A1 2 + +#define MV78200_DEV_ID 0x7820 +#define MV78200_REV_A0 1 + +#endif diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index 097ea4cb1..13a7d72ee 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include "mv78xx0.h" #include "common.h" #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c index d2d06f395..308ab71ec 100644 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c @@ -14,9 +14,9 @@ #include #include #include -#include #include #include +#include "mv78xx0.h" #include "common.h" static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { @@ -79,6 +79,7 @@ subsys_initcall(rd78x00_pci_init); MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") /* Maintainer: Lennert Buytenhek */ .atag_offset = 0x100, + .nr_irqs = MV78XX0_NR_IRQS, .init_machine = rd78x00_masa_init, .map_io = mv78xx0_map_io, .init_early = mv78xx0_init_early, -- cgit v1.2.3-54-g00ecf