From 57f0f512b273f60d52568b8c6b77e17f5636edc0 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Wed, 5 Aug 2015 17:04:01 -0300 Subject: Initial import --- arch/arm/mach-sa1100/include/mach/memory.h | 36 ++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/arm/mach-sa1100/include/mach/memory.h (limited to 'arch/arm/mach-sa1100/include/mach/memory.h') diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h new file mode 100644 index 000000000..2054051eb --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-sa1100/include/mach/memory.h + * + * Copyright (C) 1999-2000 Nicolas Pitre + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#include + +/* + * Because of the wide memory address space between physical RAM banks on the + * SA1100, it's much convenient to use Linux's SparseMEM support to implement + * our memory map representation. Assuming all memory nodes have equal access + * characteristics, we then have generic discontiguous memory support. + * + * The sparsemem banks are matched with the physical memory bank addresses + * which are incidentally the same as virtual addresses. + * + * node 0: 0xc0000000 - 0xc7ffffff + * node 1: 0xc8000000 - 0xcfffffff + * node 2: 0xd0000000 - 0xd7ffffff + * node 3: 0xd8000000 - 0xdfffffff + */ +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS 27 + +/* + * Cache flushing area - SA1100 zero bank + */ +#define FLUSH_BASE_PHYS 0xe0000000 +#define FLUSH_BASE 0xf5000000 +#define FLUSH_BASE_MINICACHE 0xf5100000 + +#endif -- cgit v1.2.3-54-g00ecf