From 03dd4cb26d967f9588437b0fc9cc0e8353322bb7 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Fri, 25 Mar 2016 03:53:42 -0300 Subject: Linux-libre 4.5-gnu --- arch/arm/mach-tegra/Kconfig | 55 ++----------------------------------- arch/arm/mach-tegra/common.h | 2 +- arch/arm/mach-tegra/platsmp.c | 2 +- arch/arm/mach-tegra/sleep-tegra20.S | 3 ++ arch/arm/mach-tegra/sleep-tegra30.S | 3 ++ 5 files changed, 10 insertions(+), 55 deletions(-) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 0fa4c5f8b..0fa8b84ed 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,6 @@ menuconfig ARCH_TEGRA - bool "NVIDIA Tegra" if ARCH_MULTI_V7 + bool "NVIDIA Tegra" + depends on ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS select ARM_AMBA @@ -12,57 +13,5 @@ menuconfig ARCH_TEGRA select ARCH_HAS_RESET_CONTROLLER select RESET_CONTROLLER select SOC_BUS - select USB_ULPI if USB_PHY - select USB_ULPI_VIEWPORT if USB_PHY help This enables support for NVIDIA Tegra based systems. - -if ARCH_TEGRA - -config ARCH_TEGRA_2x_SOC - bool "Enable support for Tegra20 family" - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP - select ARM_ERRATA_720789 - select ARM_ERRATA_754327 if SMP - select ARM_ERRATA_764369 if SMP - select PINCTRL_TEGRA20 - select PL310_ERRATA_727915 if CACHE_L2X0 - select PL310_ERRATA_769419 if CACHE_L2X0 - select TEGRA_TIMER - help - Support for NVIDIA Tegra AP20 and T20 processors, based on the - ARM CortexA9MP CPU and the ARM PL310 L2 cache controller - -config ARCH_TEGRA_3x_SOC - bool "Enable support for Tegra30 family" - select ARM_ERRATA_754322 - select ARM_ERRATA_764369 if SMP - select PINCTRL_TEGRA30 - select PL310_ERRATA_769419 if CACHE_L2X0 - select TEGRA_TIMER - help - Support for NVIDIA Tegra T30 processor family, based on the - ARM CortexA9MP CPU and the ARM PL310 L2 cache controller - -config ARCH_TEGRA_114_SOC - bool "Enable support for Tegra114 family" - select ARM_ERRATA_798181 if SMP - select ARM_L1_CACHE_SHIFT_6 - select HAVE_ARM_ARCH_TIMER - select PINCTRL_TEGRA114 - select TEGRA_TIMER - help - Support for NVIDIA Tegra T114 processor family, based on the - ARM CortexA15MP CPU - -config ARCH_TEGRA_124_SOC - bool "Enable support for Tegra124 family" - select ARM_L1_CACHE_SHIFT_6 - select HAVE_ARM_ARCH_TIMER - select PINCTRL_TEGRA124 - select TEGRA_TIMER - help - Support for NVIDIA Tegra T124 processor family, based on the - ARM CortexA15MP CPU - -endif diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h index 5900cc44f..1f6fb808e 100644 --- a/arch/arm/mach-tegra/common.h +++ b/arch/arm/mach-tegra/common.h @@ -1,4 +1,4 @@ -extern struct smp_operations tegra_smp_ops; +extern const struct smp_operations tegra_smp_ops; extern int tegra_cpu_kill(unsigned int cpu); extern void tegra_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index b45086666..f3f61dbbd 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -192,7 +192,7 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) scu_enable(IO_ADDRESS(scu_a9_get_base())); } -struct smp_operations tegra_smp_ops __initdata = { +const struct smp_operations tegra_smp_ops __initconst = { .smp_prepare_cpus = tegra_smp_prepare_cpus, .smp_secondary_init = tegra_secondary_init, .smp_boot_secondary = tegra_boot_secondary, diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index e6b684e14..f5d196674 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -231,8 +231,11 @@ ENDPROC(tegra20_cpu_is_resettable_soon) * tegra20_tear_down_core in IRAM */ ENTRY(tegra20_sleep_core_finish) + mov r4, r0 /* Flush, disable the L1 data cache and exit SMP */ + mov r0, #TEGRA_FLUSH_CACHE_ALL bl tegra_disable_clean_inv_dcache + mov r0, r4 mov32 r3, tegra_shut_off_mmu add r3, r3, r0 diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 9a2f0b051..16e5ff033 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -242,8 +242,11 @@ ENDPROC(tegra30_cpu_shutdown) * tegra30_tear_down_core in IRAM */ ENTRY(tegra30_sleep_core_finish) + mov r4, r0 /* Flush, disable the L1 data cache and exit SMP */ + mov r0, #TEGRA_FLUSH_CACHE_ALL bl tegra_disable_clean_inv_dcache + mov r0, r4 /* * Preload all the address literals that are needed for the -- cgit v1.2.3-54-g00ecf