From 57f0f512b273f60d52568b8c6b77e17f5636edc0 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Wed, 5 Aug 2015 17:04:01 -0300 Subject: Initial import --- arch/frv/lib/__ashldi3.S | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/frv/lib/__ashldi3.S (limited to 'arch/frv/lib/__ashldi3.S') diff --git a/arch/frv/lib/__ashldi3.S b/arch/frv/lib/__ashldi3.S new file mode 100644 index 000000000..db5b6dc37 --- /dev/null +++ b/arch/frv/lib/__ashldi3.S @@ -0,0 +1,40 @@ +/* __ashldi3.S: 64-bit arithmetic shift left + * + * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved. + * Written by David Howells (dhowells@redhat.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + + .text + .p2align 4 + +############################################################################### +# +# unsigned long long __ashldi3(unsigned long long value [GR8:GR9], unsigned by [GR10]) +# +############################################################################### + .globl __ashldi3 + .type __ashldi3,@function +__ashldi3: + andicc.p gr10,#63,gr10,icc0 + setlos #32,gr5 + andicc.p gr10,#32,gr0,icc1 + beqlr icc0,#0 + ckeq icc1,cc4 ; cc4 is true if 0> M + + # deal with a shift in the range 32<=N<=63 + csll gr9,gr10,gr8 ,cc4,#0 ; MSW = LSW << (N & 31 [implicit AND]) + cor.p gr0,gr0,gr9 ,cc4,#0 ; LSW = 0 + bralr + .size __ashldi3, .-__ashldi3 -- cgit v1.2.3-54-g00ecf