From d0b2f91bede3bd5e3d24dd6803e56eee959c1797 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Thu, 20 Oct 2016 00:10:27 -0300 Subject: Linux-libre 4.8.2-gnu --- drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c | 31 +- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c | 44 ++- drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h | 2 + drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c | 9 - drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 203 ++++++------ drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 113 ++++--- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 14 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 16 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 26 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 10 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 125 +------- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 339 +++++++++++++-------- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 16 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c | 235 ++++++++++++++ drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 22 +- 15 files changed, 691 insertions(+), 514 deletions(-) create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c (limited to 'drivers/gpu/drm/msm/mdp') diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c index 35ad78a1d..24258e302 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c @@ -23,7 +23,6 @@ struct mdp4_dtv_encoder { struct drm_encoder base; - struct clk *src_clk; struct clk *hdmi_clk; struct clk *mdp_clk; unsigned long int pixclock; @@ -179,7 +178,6 @@ static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder) */ mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC); - clk_disable_unprepare(mdp4_dtv_encoder->src_clk); clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk); clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk); @@ -208,19 +206,21 @@ static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder) bs_set(mdp4_dtv_encoder, 1); - DBG("setting src_clk=%lu", pc); + DBG("setting mdp_clk=%lu", pc); - ret = clk_set_rate(mdp4_dtv_encoder->src_clk, pc); + ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc); if (ret) - dev_err(dev->dev, "failed to set src_clk to %lu: %d\n", pc, ret); - clk_prepare_enable(mdp4_dtv_encoder->src_clk); - ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); - if (ret) - dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret); + dev_err(dev->dev, "failed to set mdp_clk to %lu: %d\n", + pc, ret); + ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk); if (ret) dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret); + ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk); + if (ret) + dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret); + mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1); mdp4_dtv_encoder->enabled = true; @@ -235,7 +235,7 @@ static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = { long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate) { struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder); - return clk_round_rate(mdp4_dtv_encoder->src_clk, rate); + return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate); } /* initialize encoder */ @@ -257,13 +257,6 @@ struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) DRM_MODE_ENCODER_TMDS, NULL); drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs); - mdp4_dtv_encoder->src_clk = devm_clk_get(dev->dev, "src_clk"); - if (IS_ERR(mdp4_dtv_encoder->src_clk)) { - dev_err(dev->dev, "failed to get src_clk\n"); - ret = PTR_ERR(mdp4_dtv_encoder->src_clk); - goto fail; - } - mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk"); if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) { dev_err(dev->dev, "failed to get hdmi_clk\n"); @@ -271,9 +264,9 @@ struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev) goto fail; } - mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "mdp_clk"); + mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk"); if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) { - dev_err(dev->dev, "failed to get mdp_clk\n"); + dev_err(dev->dev, "failed to get tv_clk\n"); ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk); goto fail; } diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c index 67442d50a..7b39e89fb 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c @@ -106,31 +106,27 @@ out: static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); - int i, ncrtcs = state->dev->mode_config.num_crtc; + int i; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; mdp4_enable(mdp4_kms); /* see 119ecb7fd */ - for (i = 0; i < ncrtcs; i++) { - struct drm_crtc *crtc = state->crtcs[i]; - if (!crtc) - continue; + for_each_crtc_in_state(state, crtc, crtc_state, i) drm_crtc_vblank_get(crtc); - } } static void mdp4_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); - int i, ncrtcs = state->dev->mode_config.num_crtc; + int i; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; /* see 119ecb7fd */ - for (i = 0; i < ncrtcs; i++) { - struct drm_crtc *crtc = state->crtcs[i]; - if (!crtc) - continue; + for_each_crtc_in_state(state, crtc, crtc_state, i) drm_crtc_vblank_put(crtc); - } mdp4_disable(mdp4_kms); } @@ -162,6 +158,7 @@ static const char * const iommu_ports[] = { static void mdp4_destroy(struct msm_kms *kms) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); + struct device *dev = mdp4_kms->dev->dev; struct msm_mmu *mmu = mdp4_kms->mmu; if (mmu) { @@ -171,8 +168,11 @@ static void mdp4_destroy(struct msm_kms *kms) if (mdp4_kms->blank_cursor_iova) msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id); - if (mdp4_kms->blank_cursor_bo) - drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo); + drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo); + + if (mdp4_kms->rpm_enabled) + pm_runtime_disable(dev); + kfree(mdp4_kms); } @@ -440,7 +440,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) struct mdp4_kms *mdp4_kms; struct msm_kms *kms = NULL; struct msm_mmu *mmu; - int ret; + int irq, ret; mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); if (!mdp4_kms) { @@ -461,6 +461,15 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) goto fail; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; + dev_err(dev->dev, "failed to get irq: %d\n", ret); + goto fail; + } + + kms->irq = irq; + /* NOTE: driver for this regulator still missing upstream.. use * _get_exclusive() and ignore the error if it does not exist * (and hope that the bootloader left it on for us) @@ -496,7 +505,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) goto fail; } - mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk"); + mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); if (IS_ERR(mdp4_kms->axi_clk)) { dev_err(dev->dev, "failed to get axi_clk\n"); ret = PTR_ERR(mdp4_kms->axi_clk); @@ -506,6 +515,9 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev) clk_set_rate(mdp4_kms->clk, config->max_clk); clk_set_rate(mdp4_kms->lut_clk, config->max_clk); + pm_runtime_enable(dev->dev); + mdp4_kms->rpm_enabled = true; + /* make sure things are off before attaching iommu (bootloader could * have left things on, in which case we'll start getting faults if * we don't disable): diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h index c5d045d56..25fb83997 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h @@ -47,6 +47,8 @@ struct mdp4_kms { struct mdp_irq error_handler; + bool rpm_enabled; + /* empty/blank cursor bo to use when cursor is "disabled" */ struct drm_gem_object *blank_cursor_bo; uint32_t blank_cursor_iova; diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c index 2648cd763..353429b05 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_connector.c @@ -90,14 +90,6 @@ static int mdp4_lvds_connector_mode_valid(struct drm_connector *connector, return MODE_OK; } -static struct drm_encoder * -mdp4_lvds_connector_best_encoder(struct drm_connector *connector) -{ - struct mdp4_lvds_connector *mdp4_lvds_connector = - to_mdp4_lvds_connector(connector); - return mdp4_lvds_connector->encoder; -} - static const struct drm_connector_funcs mdp4_lvds_connector_funcs = { .dpms = drm_atomic_helper_connector_dpms, .detect = mdp4_lvds_connector_detect, @@ -111,7 +103,6 @@ static const struct drm_connector_funcs mdp4_lvds_connector_funcs = { static const struct drm_connector_helper_funcs mdp4_lvds_connector_helper_funcs = { .get_modes = mdp4_lvds_connector_get_modes, .mode_valid = mdp4_lvds_connector_mode_valid, - .best_encoder = mdp4_lvds_connector_best_encoder, }; /* initialize connector */ diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index b275ce11b..ca6ca3065 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h @@ -8,19 +8,11 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14) - -Copyright (C) 2013-2015 by the following authors: +- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-05-10 05:06:30) +- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54) +- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55) + +Copyright (C) 2013-2016 by the following authors: - Rob Clark (robclark) - Ilia Mirkin (imirkin) @@ -198,118 +190,109 @@ static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) #define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100 #define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000 -static inline uint32_t __offset_MDP(uint32_t idx) -{ - switch (idx) { - case 0: return (mdp5_cfg->mdp.base[0]); - default: return INVALID_IDX(idx); - } -} -static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } - -static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); } -#define MDP5_MDP_HW_VERSION_STEP__MASK 0x0000ffff -#define MDP5_MDP_HW_VERSION_STEP__SHIFT 0 -static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val) +#define REG_MDP5_HW_VERSION 0x00000000 +#define MDP5_HW_VERSION_STEP__MASK 0x0000ffff +#define MDP5_HW_VERSION_STEP__SHIFT 0 +static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) { - return ((val) << MDP5_MDP_HW_VERSION_STEP__SHIFT) & MDP5_MDP_HW_VERSION_STEP__MASK; + return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK; } -#define MDP5_MDP_HW_VERSION_MINOR__MASK 0x0fff0000 -#define MDP5_MDP_HW_VERSION_MINOR__SHIFT 16 -static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val) +#define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000 +#define MDP5_HW_VERSION_MINOR__SHIFT 16 +static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) { - return ((val) << MDP5_MDP_HW_VERSION_MINOR__SHIFT) & MDP5_MDP_HW_VERSION_MINOR__MASK; + return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK; } -#define MDP5_MDP_HW_VERSION_MAJOR__MASK 0xf0000000 -#define MDP5_MDP_HW_VERSION_MAJOR__SHIFT 28 -static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val) +#define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000 +#define MDP5_HW_VERSION_MAJOR__SHIFT 28 +static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) { - return ((val) << MDP5_MDP_HW_VERSION_MAJOR__SHIFT) & MDP5_MDP_HW_VERSION_MAJOR__MASK; + return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK; } -static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i0); } -#define MDP5_MDP_DISP_INTF_SEL_INTF0__MASK 0x000000ff -#define MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT 0 -static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) +#define REG_MDP5_DISP_INTF_SEL 0x00000004 +#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff +#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0 +static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) { - return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; + return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK; } -#define MDP5_MDP_DISP_INTF_SEL_INTF1__MASK 0x0000ff00 -#define MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT 8 -static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) +#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00 +#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8 +static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) { - return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; + return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK; } -#define MDP5_MDP_DISP_INTF_SEL_INTF2__MASK 0x00ff0000 -#define MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT 16 -static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) +#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000 +#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16 +static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) { - return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; + return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK; } -#define MDP5_MDP_DISP_INTF_SEL_INTF3__MASK 0xff000000 -#define MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT 24 -static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) +#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000 +#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24 +static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) { - return ((val) << MDP5_MDP_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; + return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK; } -static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); } +#define REG_MDP5_INTR_EN 0x00000010 -static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0); } +#define REG_MDP5_INTR_STATUS 0x00000014 -static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0); } +#define REG_MDP5_INTR_CLEAR 0x00000018 -static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0); } +#define REG_MDP5_HIST_INTR_EN 0x0000001c -static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MDP(i0); } +#define REG_MDP5_HIST_INTR_STATUS 0x00000020 -static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP(i0); } +#define REG_MDP5_HIST_INTR_CLEAR 0x00000024 -static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); } -#define MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001 +#define REG_MDP5_SPARE_0 0x00000028 +#define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001 -static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } +static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } -static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0 -static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) +static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } +#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff +#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0 +static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK; + return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; } -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00 -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8 -static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) +#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00 +#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8 +static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK; + return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; } -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000 -#define MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16 -static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) +#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000 +#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16 +static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK; + return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; } -static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } +static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } -static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0 -static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) +static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } +#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff +#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0 +static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0__MASK; + return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK; } -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00 -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8 -static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) +#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00 +#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8 +static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1__MASK; + return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK; } -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000 -#define MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16 -static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) +#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000 +#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16 +static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val) { - return ((val) << MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2__MASK; + return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK; } static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) @@ -322,35 +305,35 @@ static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) default: return INVALID_IDX(idx); } } -static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); } +static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } -static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } +static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } -static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } -#define MDP5_MDP_IGC_LUT_REG_VAL__MASK 0x00000fff -#define MDP5_MDP_IGC_LUT_REG_VAL__SHIFT 0 -static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val) +static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } +#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff +#define MDP5_IGC_LUT_REG_VAL__SHIFT 0 +static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) { - return ((val) << MDP5_MDP_IGC_LUT_REG_VAL__SHIFT) & MDP5_MDP_IGC_LUT_REG_VAL__MASK; + return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK; } -#define MDP5_MDP_IGC_LUT_REG_INDEX_UPDATE 0x02000000 -#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000 -#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 -#define MDP5_MDP_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 +#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000 +#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000 +#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 +#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 -static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_EN(uint32_t i0) { return 0x000002f4 + __offset_MDP(i0); } +#define REG_MDP5_SPLIT_DPL_EN 0x000002f4 -static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_UPPER(uint32_t i0) { return 0x000002f8 + __offset_MDP(i0); } -#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 -#define MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 -#define MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 -#define MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 +#define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8 +#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002 +#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004 +#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010 +#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100 -static inline uint32_t REG_MDP5_MDP_SPLIT_DPL_LOWER(uint32_t i0) { return 0x000003f0 + __offset_MDP(i0); } -#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 -#define MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 -#define MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 -#define MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 +#define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0 +#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002 +#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004 +#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010 +#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100 static inline uint32_t __offset_CTL(uint32_t idx) { diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index 57f73f0c1..ac9e4cde1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -26,7 +26,6 @@ const struct mdp5_cfg_hw msm8x74v1_config = { .name = "msm8x74v1", .mdp = { .count = 1, - .base = { 0x00100 }, .caps = MDP_CAP_SMP | 0, }, @@ -41,12 +40,12 @@ const struct mdp5_cfg_hw msm8x74v1_config = { }, .ctl = { .count = 5, - .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, .flush_hw_mask = 0x0003ffff, }, .pipe_vig = { .count = 3, - .base = { 0x01200, 0x01600, 0x01a00 }, + .base = { 0x01100, 0x01500, 0x01900 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | @@ -55,7 +54,7 @@ const struct mdp5_cfg_hw msm8x74v1_config = { }, .pipe_rgb = { .count = 3, - .base = { 0x01e00, 0x02200, 0x02600 }, + .base = { 0x01d00, 0x02100, 0x02500 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | @@ -63,26 +62,26 @@ const struct mdp5_cfg_hw msm8x74v1_config = { }, .pipe_dma = { .count = 2, - .base = { 0x02a00, 0x02e00 }, + .base = { 0x02900, 0x02d00 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | 0, }, .lm = { .count = 5, - .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 }, + .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, .nb_stages = 5, }, .dspp = { .count = 3, - .base = { 0x04600, 0x04a00, 0x04e00 }, + .base = { 0x04500, 0x04900, 0x04d00 }, }, .pp = { .count = 3, - .base = { 0x21b00, 0x21c00, 0x21d00 }, + .base = { 0x21a00, 0x21b00, 0x21c00 }, }, .intf = { - .base = { 0x21100, 0x21300, 0x21500, 0x21700 }, + .base = { 0x21000, 0x21200, 0x21400, 0x21600 }, .connect = { [0] = INTF_eDP, [1] = INTF_DSI, @@ -97,7 +96,6 @@ const struct mdp5_cfg_hw msm8x74v2_config = { .name = "msm8x74", .mdp = { .count = 1, - .base = { 0x00100 }, .caps = MDP_CAP_SMP | 0, }, @@ -112,48 +110,48 @@ const struct mdp5_cfg_hw msm8x74v2_config = { }, .ctl = { .count = 5, - .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, .flush_hw_mask = 0x0003ffff, }, .pipe_vig = { .count = 3, - .base = { 0x01200, 0x01600, 0x01a00 }, + .base = { 0x01100, 0x01500, 0x01900 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | MDP_PIPE_CAP_DECIMATION, }, .pipe_rgb = { .count = 3, - .base = { 0x01e00, 0x02200, 0x02600 }, + .base = { 0x01d00, 0x02100, 0x02500 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, }, .pipe_dma = { .count = 2, - .base = { 0x02a00, 0x02e00 }, + .base = { 0x02900, 0x02d00 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, }, .lm = { .count = 5, - .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 }, + .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, .nb_stages = 5, .max_width = 2048, .max_height = 0xFFFF, }, .dspp = { .count = 3, - .base = { 0x04600, 0x04a00, 0x04e00 }, + .base = { 0x04500, 0x04900, 0x04d00 }, }, .ad = { .count = 2, - .base = { 0x13100, 0x13300 }, + .base = { 0x13000, 0x13200 }, }, .pp = { .count = 3, - .base = { 0x12d00, 0x12e00, 0x12f00 }, + .base = { 0x12c00, 0x12d00, 0x12e00 }, }, .intf = { - .base = { 0x12500, 0x12700, 0x12900, 0x12b00 }, + .base = { 0x12400, 0x12600, 0x12800, 0x12a00 }, .connect = { [0] = INTF_eDP, [1] = INTF_DSI, @@ -168,7 +166,6 @@ const struct mdp5_cfg_hw apq8084_config = { .name = "apq8084", .mdp = { .count = 1, - .base = { 0x00100 }, .caps = MDP_CAP_SMP | 0, }, @@ -190,49 +187,49 @@ const struct mdp5_cfg_hw apq8084_config = { }, .ctl = { .count = 5, - .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, .flush_hw_mask = 0x003fffff, }, .pipe_vig = { .count = 4, - .base = { 0x01200, 0x01600, 0x01a00, 0x01e00 }, + .base = { 0x01100, 0x01500, 0x01900, 0x01d00 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | MDP_PIPE_CAP_DECIMATION, }, .pipe_rgb = { .count = 4, - .base = { 0x02200, 0x02600, 0x02a00, 0x02e00 }, + .base = { 0x02100, 0x02500, 0x02900, 0x02d00 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, }, .pipe_dma = { .count = 2, - .base = { 0x03200, 0x03600 }, + .base = { 0x03100, 0x03500 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, }, .lm = { .count = 6, - .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 }, + .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 }, .nb_stages = 5, .max_width = 2048, .max_height = 0xFFFF, }, .dspp = { .count = 4, - .base = { 0x05200, 0x05600, 0x05a00, 0x05e00 }, + .base = { 0x05100, 0x05500, 0x05900, 0x05d00 }, }, .ad = { .count = 3, - .base = { 0x13500, 0x13700, 0x13900 }, + .base = { 0x13400, 0x13600, 0x13800 }, }, .pp = { .count = 4, - .base = { 0x12f00, 0x13000, 0x13100, 0x13200 }, + .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 }, }, .intf = { - .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 }, + .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 }, .connect = { [0] = INTF_eDP, [1] = INTF_DSI, @@ -247,7 +244,7 @@ const struct mdp5_cfg_hw msm8x16_config = { .name = "msm8x16", .mdp = { .count = 1, - .base = { 0x01000 }, + .base = { 0x0 }, .caps = MDP_CAP_SMP | 0, }, @@ -261,41 +258,41 @@ const struct mdp5_cfg_hw msm8x16_config = { }, .ctl = { .count = 5, - .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 }, + .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, .flush_hw_mask = 0x4003ffff, }, .pipe_vig = { .count = 1, - .base = { 0x05000 }, + .base = { 0x04000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | MDP_PIPE_CAP_DECIMATION, }, .pipe_rgb = { .count = 2, - .base = { 0x15000, 0x17000 }, + .base = { 0x14000, 0x16000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, }, .pipe_dma = { .count = 1, - .base = { 0x25000 }, + .base = { 0x24000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, }, .lm = { .count = 2, /* LM0 and LM3 */ - .base = { 0x45000, 0x48000 }, + .base = { 0x44000, 0x47000 }, .nb_stages = 5, .max_width = 2048, .max_height = 0xFFFF, }, .dspp = { .count = 1, - .base = { 0x55000 }, + .base = { 0x54000 }, }, .intf = { - .base = { 0x00000, 0x6b800 }, + .base = { 0x00000, 0x6a800 }, .connect = { [0] = INTF_DISABLED, [1] = INTF_DSI, @@ -308,7 +305,6 @@ const struct mdp5_cfg_hw msm8x94_config = { .name = "msm8x94", .mdp = { .count = 1, - .base = { 0x01000 }, .caps = MDP_CAP_SMP | 0, }, @@ -330,49 +326,49 @@ const struct mdp5_cfg_hw msm8x94_config = { }, .ctl = { .count = 5, - .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 }, + .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, .flush_hw_mask = 0xf0ffffff, }, .pipe_vig = { .count = 4, - .base = { 0x05000, 0x07000, 0x09000, 0x0b000 }, + .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC | MDP_PIPE_CAP_DECIMATION, }, .pipe_rgb = { .count = 4, - .base = { 0x15000, 0x17000, 0x19000, 0x1b000 }, + .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION, }, .pipe_dma = { .count = 2, - .base = { 0x25000, 0x27000 }, + .base = { 0x24000, 0x26000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP, }, .lm = { .count = 6, - .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 }, + .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, .nb_stages = 8, .max_width = 2048, .max_height = 0xFFFF, }, .dspp = { .count = 4, - .base = { 0x55000, 0x57000, 0x59000, 0x5b000 }, + .base = { 0x54000, 0x56000, 0x58000, 0x5a000 }, }, .ad = { .count = 3, - .base = { 0x79000, 0x79800, 0x7a000 }, + .base = { 0x78000, 0x78800, 0x79000 }, }, .pp = { .count = 4, - .base = { 0x71000, 0x71800, 0x72000, 0x72800 }, + .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, }, .intf = { - .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 }, + .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, .connect = { [0] = INTF_DISABLED, [1] = INTF_DSI, @@ -387,19 +383,18 @@ const struct mdp5_cfg_hw msm8x96_config = { .name = "msm8x96", .mdp = { .count = 1, - .base = { 0x01000 }, .caps = MDP_CAP_DSC | MDP_CAP_CDM | 0, }, .ctl = { .count = 5, - .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 }, + .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 }, .flush_hw_mask = 0xf4ffffff, }, .pipe_vig = { .count = 4, - .base = { 0x05000, 0x07000, 0x09000, 0x0b000 }, + .base = { 0x04000, 0x06000, 0x08000, 0x0a000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | @@ -410,7 +405,7 @@ const struct mdp5_cfg_hw msm8x96_config = { }, .pipe_rgb = { .count = 4, - .base = { 0x15000, 0x17000, 0x19000, 0x1b000 }, + .base = { 0x14000, 0x16000, 0x18000, 0x1a000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SCALE | @@ -420,7 +415,7 @@ const struct mdp5_cfg_hw msm8x96_config = { }, .pipe_dma = { .count = 2, - .base = { 0x25000, 0x27000 }, + .base = { 0x24000, 0x26000 }, .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP | MDP_PIPE_CAP_SW_PIX_EXT | @@ -428,33 +423,33 @@ const struct mdp5_cfg_hw msm8x96_config = { }, .lm = { .count = 6, - .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 }, + .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 }, .nb_stages = 8, .max_width = 2560, .max_height = 0xFFFF, }, .dspp = { .count = 2, - .base = { 0x55000, 0x57000 }, + .base = { 0x54000, 0x56000 }, }, .ad = { .count = 3, - .base = { 0x79000, 0x79800, 0x7a000 }, + .base = { 0x78000, 0x78800, 0x79000 }, }, .pp = { .count = 4, - .base = { 0x71000, 0x71800, 0x72000, 0x72800 }, + .base = { 0x70000, 0x70800, 0x71000, 0x71800 }, }, .cdm = { .count = 1, - .base = { 0x7a200 }, + .base = { 0x79200 }, }, .dsc = { .count = 2, - .base = { 0x81000, 0x81400 }, + .base = { 0x80000, 0x80400 }, }, .intf = { - .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 }, + .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 }, .connect = { [0] = INTF_DISABLED, [1] = INTF_DSI, diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c index 69094cb28..c627ab6d0 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c @@ -272,22 +272,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, * start signal for the slave encoder */ if (intf_num == 1) - data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; + data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; else if (intf_num == 2) - data |= MDP5_MDP_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; + data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; else return -EINVAL; /* Smart Panel, Sync mode */ - data |= MDP5_MDP_SPLIT_DPL_UPPER_SMART_PANEL; + data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; /* Make sure clocks are on when connectors calling this function. */ mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), data); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), - MDP5_MDP_SPLIT_DPL_LOWER_SMART_PANEL); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, + MDP5_SPLIT_DPL_LOWER_SMART_PANEL); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_disable(mdp5_kms); return 0; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 88fe256c1..fa2be7ce9 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -374,6 +374,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct plane_state pstates[STAGE_MAX + 1]; const struct mdp5_cfg_hw *hw_cfg; + const struct drm_plane_state *pstate; int cnt = 0, i; DBG("%s: check", mdp5_crtc->name); @@ -382,20 +383,13 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, * and that we don't have conflicting mixer stages: */ hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); - drm_atomic_crtc_state_for_each_plane(plane, state) { - struct drm_plane_state *pstate; + drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { if (cnt >= (hw_cfg->lm.nb_stages)) { dev_err(dev->dev, "too many planes!\n"); return -EINVAL; } - pstate = state->state->plane_states[drm_plane_index(plane)]; - /* plane might not have changed, in which case take - * current state: - */ - if (!pstate) - pstate = plane->state; pstates[cnt].plane = plane; pstates[cnt].state = to_mdp5_plane_state(pstate); @@ -496,8 +490,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, struct mdp5_kms *mdp5_kms = get_kms(crtc); struct drm_gem_object *cursor_bo, *old_bo = NULL; uint32_t blendcfg, cursor_addr, stride; - int ret, bpp, lm; - unsigned int depth; + int ret, lm; enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); uint32_t roi_w, roi_h; @@ -527,8 +520,7 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, return -EINVAL; lm = mdp5_crtc->lm; - drm_fb_get_bpp_depth(DRM_FORMAT_ARGB8888, &depth, &bpp); - stride = width * (bpp >> 3); + stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0); spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); old_bo = mdp5_crtc->cursor.scanout_bo; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c index 4e81ca4f9..d021edc3b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c @@ -118,31 +118,31 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms, u32 intf_sel; spin_lock_irqsave(&mdp5_kms->resource_lock, flags); - intf_sel = mdp5_read(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0)); + intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); switch (intf->num) { case 0: - intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF0__MASK; - intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF0(intf->type); + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type); break; case 1: - intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF1__MASK; - intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF1(intf->type); + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type); break; case 2: - intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF2__MASK; - intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF2(intf->type); + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type); break; case 3: - intf_sel &= ~MDP5_MDP_DISP_INTF_SEL_INTF3__MASK; - intf_sel |= MDP5_MDP_DISP_INTF_SEL_INTF3(intf->type); + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type); break; default: BUG(); break; } - mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), intf_sel); + mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); } @@ -557,7 +557,7 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) if (!enable) { ctlx->pair = NULL; ctly->pair = NULL; - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), 0); + mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, 0); return 0; } else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) { dev_err(ctl_mgr->dev->dev, "CTLs already paired\n"); @@ -570,8 +570,8 @@ int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) ctlx->pair = ctly; ctly->pair = ctlx; - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), - MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); + mdp5_write(mdp5_kms, REG_MDP5_SPARE_0, + MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN); return 0; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index 1d95f9fd9..fe0c22230 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -322,18 +322,18 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder, * to use the master's enable signal for the slave encoder. */ if (intf_num == 1) - data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF2_TG_SYNC; + data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; else if (intf_num == 2) - data |= MDP5_MDP_SPLIT_DPL_LOWER_INTF1_TG_SYNC; + data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; else return -EINVAL; /* Make sure clocks are on when connectors calling this function. */ mdp5_enable(mdp5_kms); /* Dumb Panel, Sync mode */ - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); + mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c index 73bc3e312..d53e5510f 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c @@ -15,7 +15,6 @@ * this program. If not, see . */ -#include #include #include "msm_drv.h" @@ -24,9 +23,9 @@ void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, uint32_t old_irqmask) { - mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_CLEAR(0), - irqmask ^ (irqmask & old_irqmask)); - mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask); + mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_CLEAR, + irqmask ^ (irqmask & old_irqmask)); + mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); } static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) @@ -38,8 +37,8 @@ void mdp5_irq_preinstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), 0xffffffff); - mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); + mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, 0xffffffff); + mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_disable(mdp5_kms); } @@ -55,7 +54,9 @@ int mdp5_irq_postinstall(struct msm_kms *kms) MDP5_IRQ_INTF2_UNDER_RUN | MDP5_IRQ_INTF3_UNDER_RUN; + mdp5_enable(mdp5_kms); mdp_irq_register(mdp_kms, error_handler); + mdp5_disable(mdp5_kms); return 0; } @@ -64,21 +65,22 @@ void mdp5_irq_uninstall(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); mdp5_enable(mdp5_kms); - mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000); + mdp5_write(mdp5_kms, REG_MDP5_INTR_EN, 0x00000000); mdp5_disable(mdp5_kms); } -static void mdp5_irq_mdp(struct mdp_kms *mdp_kms) +irqreturn_t mdp5_irq(struct msm_kms *kms) { + struct mdp_kms *mdp_kms = to_mdp_kms(kms); struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); struct drm_device *dev = mdp5_kms->dev; struct msm_drm_private *priv = dev->dev_private; unsigned int id; uint32_t status, enable; - enable = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_EN(0)); - status = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_STATUS(0)) & enable; - mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), status); + enable = mdp5_read(mdp5_kms, REG_MDP5_INTR_EN); + status = mdp5_read(mdp5_kms, REG_MDP5_INTR_STATUS) & enable; + mdp5_write(mdp5_kms, REG_MDP5_INTR_CLEAR, status); VERB("status=%08x", status); @@ -87,29 +89,6 @@ static void mdp5_irq_mdp(struct mdp_kms *mdp_kms) for (id = 0; id < priv->num_crtcs; id++) if (status & mdp5_crtc_vblank(priv->crtcs[id])) drm_handle_vblank(dev, id); -} - -irqreturn_t mdp5_irq(struct msm_kms *kms) -{ - struct mdp_kms *mdp_kms = to_mdp_kms(kms); - struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms); - uint32_t intr; - - intr = mdp5_read(mdp5_kms, REG_MDSS_HW_INTR_STATUS); - - VERB("intr=%08x", intr); - - if (intr & MDSS_HW_INTR_STATUS_INTR_MDP) { - mdp5_irq_mdp(mdp_kms); - intr &= ~MDSS_HW_INTR_STATUS_INTR_MDP; - } - - while (intr) { - irq_hw_number_t hwirq = fls(intr) - 1; - generic_handle_irq(irq_find_mapping( - mdp5_kms->irqcontroller.domain, hwirq)); - intr &= ~(1 << hwirq); - } return IRQ_HANDLED; } @@ -135,81 +114,3 @@ void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) mdp5_crtc_vblank(crtc), false); mdp5_disable(mdp5_kms); } - -/* - * interrupt-controller implementation, so sub-blocks (hdmi/eDP/dsi/etc) - * can register to get their irq's delivered - */ - -#define VALID_IRQS (MDSS_HW_INTR_STATUS_INTR_DSI0 | \ - MDSS_HW_INTR_STATUS_INTR_DSI1 | \ - MDSS_HW_INTR_STATUS_INTR_HDMI | \ - MDSS_HW_INTR_STATUS_INTR_EDP) - -static void mdp5_hw_mask_irq(struct irq_data *irqd) -{ - struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd); - smp_mb__before_atomic(); - clear_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask); - smp_mb__after_atomic(); -} - -static void mdp5_hw_unmask_irq(struct irq_data *irqd) -{ - struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd); - smp_mb__before_atomic(); - set_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask); - smp_mb__after_atomic(); -} - -static struct irq_chip mdp5_hw_irq_chip = { - .name = "mdp5", - .irq_mask = mdp5_hw_mask_irq, - .irq_unmask = mdp5_hw_unmask_irq, -}; - -static int mdp5_hw_irqdomain_map(struct irq_domain *d, - unsigned int irq, irq_hw_number_t hwirq) -{ - struct mdp5_kms *mdp5_kms = d->host_data; - - if (!(VALID_IRQS & (1 << hwirq))) - return -EPERM; - - irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq); - irq_set_chip_data(irq, mdp5_kms); - - return 0; -} - -static struct irq_domain_ops mdp5_hw_irqdomain_ops = { - .map = mdp5_hw_irqdomain_map, - .xlate = irq_domain_xlate_onecell, -}; - - -int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms) -{ - struct device *dev = mdp5_kms->dev->dev; - struct irq_domain *d; - - d = irq_domain_add_linear(dev->of_node, 32, - &mdp5_hw_irqdomain_ops, mdp5_kms); - if (!d) { - dev_err(dev, "mdp5 irq domain add failed\n"); - return -ENXIO; - } - - mdp5_kms->irqcontroller.enabled_mask = 0; - mdp5_kms->irqcontroller.domain = d; - - return 0; -} - -void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms) -{ - if (mdp5_kms->irqcontroller.domain) { - irq_domain_remove(mdp5_kms->irqcontroller.domain); - mdp5_kms->irqcontroller.domain = NULL; - } -} diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 484b4d15e..ed7143d35 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -16,6 +16,7 @@ * this program. If not, see . */ +#include #include "msm_drv.h" #include "msm_mmu.h" @@ -28,10 +29,11 @@ static const char *iommu_ports[] = { static int mdp5_hw_init(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - struct drm_device *dev = mdp5_kms->dev; + struct platform_device *pdev = mdp5_kms->pdev; unsigned long flags; - pm_runtime_get_sync(dev->dev); + pm_runtime_get_sync(&pdev->dev); + mdp5_enable(mdp5_kms); /* Magic unknown register writes: * @@ -58,12 +60,13 @@ static int mdp5_hw_init(struct msm_kms *kms) */ spin_lock_irqsave(&mdp5_kms->resource_lock, flags); - mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); + mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); mdp5_ctlm_hw_reset(mdp5_kms->ctlm); - pm_runtime_put_sync(dev->dev); + mdp5_disable(mdp5_kms); + pm_runtime_put_sync(&pdev->dev); return 0; } @@ -78,17 +81,11 @@ static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *s { int i; struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); - int nplanes = mdp5_kms->dev->mode_config.num_total_plane; - - for (i = 0; i < nplanes; i++) { - struct drm_plane *plane = state->planes[i]; - struct drm_plane_state *plane_state = state->plane_states[i]; - - if (!plane) - continue; + struct drm_plane *plane; + struct drm_plane_state *plane_state; + for_each_plane_in_state(state, plane, plane_state, i) mdp5_plane_complete_commit(plane, plane_state); - } mdp5_disable(mdp5_kms); } @@ -117,26 +114,15 @@ static int mdp5_set_split_display(struct msm_kms *kms, return mdp5_encoder_set_split_display(encoder, slave_encoder); } -static void mdp5_destroy(struct msm_kms *kms) +static void mdp5_kms_destroy(struct msm_kms *kms) { struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); struct msm_mmu *mmu = mdp5_kms->mmu; - mdp5_irq_domain_fini(mdp5_kms); - if (mmu) { mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); mmu->funcs->destroy(mmu); } - - if (mdp5_kms->ctlm) - mdp5_ctlm_destroy(mdp5_kms->ctlm); - if (mdp5_kms->smp) - mdp5_smp_destroy(mdp5_kms->smp); - if (mdp5_kms->cfg) - mdp5_cfg_destroy(mdp5_kms->cfg); - - kfree(mdp5_kms); } static const struct mdp_kms_funcs kms_funcs = { @@ -154,7 +140,7 @@ static const struct mdp_kms_funcs kms_funcs = { .get_format = mdp_get_format, .round_pixclk = mdp5_round_pixclk, .set_split_display = mdp5_set_split_display, - .destroy = mdp5_destroy, + .destroy = mdp5_kms_destroy, }, .set_irqmask = mdp5_set_irqmask, }; @@ -351,13 +337,6 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); - /* register our interrupt-controller for hdmi/eDP/dsi/etc - * to use for irqs routed through mdp: - */ - ret = mdp5_irq_domain_init(mdp5_kms); - if (ret) - goto fail; - /* construct CRTCs and their private planes: */ for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { struct drm_plane *plane; @@ -425,17 +404,17 @@ fail: return ret; } -static void read_hw_revision(struct mdp5_kms *mdp5_kms, - uint32_t *major, uint32_t *minor) +static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, + u32 *major, u32 *minor) { - uint32_t version; + u32 version; mdp5_enable(mdp5_kms); - version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION); + version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); mdp5_disable(mdp5_kms); - *major = FIELD(version, MDSS_HW_VERSION_MAJOR); - *minor = FIELD(version, MDSS_HW_VERSION_MINOR); + *major = FIELD(version, MDP5_HW_VERSION_MAJOR); + *minor = FIELD(version, MDP5_HW_VERSION_MINOR); DBG("MDP5 version v%d.%d", *major, *minor); } @@ -580,51 +559,146 @@ static u32 mdp5_get_vblank_counter(struct drm_device *dev, unsigned int pipe) struct msm_kms *mdp5_kms_init(struct drm_device *dev) { - struct platform_device *pdev = dev->platformdev; - struct mdp5_cfg *config; + struct msm_drm_private *priv = dev->dev_private; + struct platform_device *pdev; struct mdp5_kms *mdp5_kms; - struct msm_kms *kms = NULL; + struct mdp5_cfg *config; + struct msm_kms *kms; struct msm_mmu *mmu; - uint32_t major, minor; - int i, ret; + int irq, i, ret; - mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); - if (!mdp5_kms) { - dev_err(dev->dev, "failed to allocate kms\n"); - ret = -ENOMEM; + /* priv->kms would have been populated by the MDP5 driver */ + kms = priv->kms; + if (!kms) + return NULL; + + mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); + + mdp_kms_init(&mdp5_kms->base, &kms_funcs); + + pdev = mdp5_kms->pdev; + + irq = irq_of_parse_and_map(pdev->dev.of_node, 0); + if (irq < 0) { + ret = irq; + dev_err(&pdev->dev, "failed to get irq: %d\n", ret); goto fail; } - spin_lock_init(&mdp5_kms->resource_lock); + kms->irq = irq; - mdp_kms_init(&mdp5_kms->base, &kms_funcs); + config = mdp5_cfg_get_config(mdp5_kms->cfg); - kms = &mdp5_kms->base.base; + /* make sure things are off before attaching iommu (bootloader could + * have left things on, in which case we'll start getting faults if + * we don't disable): + */ + mdp5_enable(mdp5_kms); + for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { + if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || + !config->hw->intf.base[i]) + continue; + mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); - mdp5_kms->dev = dev; + mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); + } + mdp5_disable(mdp5_kms); + mdelay(16); - /* mdp5_kms->mmio actually represents the MDSS base address */ - mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); - if (IS_ERR(mdp5_kms->mmio)) { - ret = PTR_ERR(mdp5_kms->mmio); + if (config->platform.iommu) { + mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); + if (IS_ERR(mmu)) { + ret = PTR_ERR(mmu); + dev_err(&pdev->dev, "failed to init iommu: %d\n", ret); + iommu_domain_free(config->platform.iommu); + goto fail; + } + + ret = mmu->funcs->attach(mmu, iommu_ports, + ARRAY_SIZE(iommu_ports)); + if (ret) { + dev_err(&pdev->dev, "failed to attach iommu: %d\n", + ret); + mmu->funcs->destroy(mmu); + goto fail; + } + } else { + dev_info(&pdev->dev, + "no iommu, fallback to phys contig buffers for scanout\n"); + mmu = NULL; + } + mdp5_kms->mmu = mmu; + + mdp5_kms->id = msm_register_mmu(dev, mmu); + if (mdp5_kms->id < 0) { + ret = mdp5_kms->id; + dev_err(&pdev->dev, "failed to register mdp5 iommu: %d\n", ret); goto fail; } - mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); - if (IS_ERR(mdp5_kms->vbif)) { - ret = PTR_ERR(mdp5_kms->vbif); + ret = modeset_init(mdp5_kms); + if (ret) { + dev_err(&pdev->dev, "modeset_init failed: %d\n", ret); goto fail; } - mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); - if (IS_ERR(mdp5_kms->vdd)) { - ret = PTR_ERR(mdp5_kms->vdd); + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + dev->mode_config.max_width = config->hw->lm.max_width; + dev->mode_config.max_height = config->hw->lm.max_height; + + dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; + dev->driver->get_scanout_position = mdp5_get_scanoutpos; + dev->driver->get_vblank_counter = mdp5_get_vblank_counter; + dev->max_vblank_count = 0xffffffff; + dev->vblank_disable_immediate = true; + + return kms; +fail: + if (kms) + mdp5_kms_destroy(kms); + return ERR_PTR(ret); +} + +static void mdp5_destroy(struct platform_device *pdev) +{ + struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); + + if (mdp5_kms->ctlm) + mdp5_ctlm_destroy(mdp5_kms->ctlm); + if (mdp5_kms->smp) + mdp5_smp_destroy(mdp5_kms->smp); + if (mdp5_kms->cfg) + mdp5_cfg_destroy(mdp5_kms->cfg); + + if (mdp5_kms->rpm_enabled) + pm_runtime_disable(&pdev->dev); +} + +static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) +{ + struct msm_drm_private *priv = dev->dev_private; + struct mdp5_kms *mdp5_kms; + struct mdp5_cfg *config; + u32 major, minor; + int ret; + + mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); + if (!mdp5_kms) { + ret = -ENOMEM; goto fail; } - ret = regulator_enable(mdp5_kms->vdd); - if (ret) { - dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); + platform_set_drvdata(pdev, mdp5_kms); + + spin_lock_init(&mdp5_kms->resource_lock); + + mdp5_kms->dev = dev; + mdp5_kms->pdev = pdev; + + mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); + if (IS_ERR(mdp5_kms->mmio)) { + ret = PTR_ERR(mdp5_kms->mmio); goto fail; } @@ -633,9 +707,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) if (ret) goto fail; ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); - if (ret) - goto fail; - ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true); if (ret) goto fail; ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); @@ -652,9 +723,12 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) * rate first, then figure out hw revision, and then set a * more optimal rate: */ - clk_set_rate(mdp5_kms->src_clk, 200000000); + clk_set_rate(mdp5_kms->core_clk, 200000000); - read_hw_revision(mdp5_kms, &major, &minor); + pm_runtime_enable(&pdev->dev); + mdp5_kms->rpm_enabled = true; + + read_mdp_hw_revision(mdp5_kms, &major, &minor); mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); if (IS_ERR(mdp5_kms->cfg)) { @@ -667,7 +741,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) mdp5_kms->caps = config->hw->mdp.caps; /* TODO: compute core clock rate at runtime */ - clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); + clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); /* * Some chipsets have a Shared Memory Pool (SMP), while others @@ -690,73 +764,76 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) goto fail; } - /* make sure things are off before attaching iommu (bootloader could - * have left things on, in which case we'll start getting faults if - * we don't disable): - */ - mdp5_enable(mdp5_kms); - for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { - if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || - !config->hw->intf.base[i]) - continue; - mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); + /* set uninit-ed kms */ + priv->kms = &mdp5_kms->base.base; - mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); - } - mdp5_disable(mdp5_kms); - mdelay(16); + return 0; +fail: + mdp5_destroy(pdev); + return ret; +} - if (config->platform.iommu) { - mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); - if (IS_ERR(mmu)) { - ret = PTR_ERR(mmu); - dev_err(dev->dev, "failed to init iommu: %d\n", ret); - iommu_domain_free(config->platform.iommu); - goto fail; - } +static int mdp5_bind(struct device *dev, struct device *master, void *data) +{ + struct drm_device *ddev = dev_get_drvdata(master); + struct platform_device *pdev = to_platform_device(dev); - ret = mmu->funcs->attach(mmu, iommu_ports, - ARRAY_SIZE(iommu_ports)); - if (ret) { - dev_err(dev->dev, "failed to attach iommu: %d\n", ret); - mmu->funcs->destroy(mmu); - goto fail; - } - } else { - dev_info(dev->dev, "no iommu, fallback to phys " - "contig buffers for scanout\n"); - mmu = NULL; - } - mdp5_kms->mmu = mmu; + DBG(""); - mdp5_kms->id = msm_register_mmu(dev, mmu); - if (mdp5_kms->id < 0) { - ret = mdp5_kms->id; - dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); - goto fail; - } + return mdp5_init(pdev, ddev); +} - ret = modeset_init(mdp5_kms); - if (ret) { - dev_err(dev->dev, "modeset_init failed: %d\n", ret); - goto fail; - } +static void mdp5_unbind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); - dev->mode_config.min_width = 0; - dev->mode_config.min_height = 0; - dev->mode_config.max_width = config->hw->lm.max_width; - dev->mode_config.max_height = config->hw->lm.max_height; + mdp5_destroy(pdev); +} - dev->driver->get_vblank_timestamp = mdp5_get_vblank_timestamp; - dev->driver->get_scanout_position = mdp5_get_scanoutpos; - dev->driver->get_vblank_counter = mdp5_get_vblank_counter; - dev->max_vblank_count = 0xffffffff; - dev->vblank_disable_immediate = true; +static const struct component_ops mdp5_ops = { + .bind = mdp5_bind, + .unbind = mdp5_unbind, +}; - return kms; +static int mdp5_dev_probe(struct platform_device *pdev) +{ + DBG(""); + return component_add(&pdev->dev, &mdp5_ops); +} -fail: - if (kms) - mdp5_destroy(kms); - return ERR_PTR(ret); +static int mdp5_dev_remove(struct platform_device *pdev) +{ + DBG(""); + component_del(&pdev->dev, &mdp5_ops); + return 0; +} + +static const struct of_device_id mdp5_dt_match[] = { + { .compatible = "qcom,mdp5", }, + /* to support downstream DT files */ + { .compatible = "qcom,mdss_mdp", }, + {} +}; +MODULE_DEVICE_TABLE(of, mdp5_dt_match); + +static struct platform_driver mdp5_driver = { + .probe = mdp5_dev_probe, + .remove = mdp5_dev_remove, + .driver = { + .name = "msm_mdp", + .of_match_table = mdp5_dt_match, + }, +}; + +void __init msm_mdp_register(void) +{ + DBG(""); + platform_driver_register(&mdp5_driver); +} + +void __exit msm_mdp_unregister(void) +{ + DBG(""); + platform_driver_unregister(&mdp5_driver); } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 9a2589823..03738927b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -31,6 +31,8 @@ struct mdp5_kms { struct drm_device *dev; + struct platform_device *pdev; + struct mdp5_cfg_handler *cfg; uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */ @@ -43,29 +45,23 @@ struct mdp5_kms { struct mdp5_ctl_manager *ctlm; /* io/register spaces: */ - void __iomem *mmio, *vbif; - - struct regulator *vdd; + void __iomem *mmio; struct clk *axi_clk; struct clk *ahb_clk; - struct clk *src_clk; struct clk *core_clk; struct clk *lut_clk; struct clk *vsync_clk; /* * lock to protect access to global resources: ie., following register: - * - REG_MDP5_MDP_DISP_INTF_SEL + * - REG_MDP5_DISP_INTF_SEL */ spinlock_t resource_lock; - struct mdp_irq error_handler; + bool rpm_enabled; - struct { - volatile unsigned long enabled_mask; - struct irq_domain *domain; - } irqcontroller; + struct mdp_irq error_handler; }; #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c new file mode 100644 index 000000000..d444a6901 --- /dev/null +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_mdss.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include + +#include "msm_drv.h" +#include "mdp5_kms.h" + +/* + * If needed, this can become more specific: something like struct mdp5_mdss, + * which contains a 'struct msm_mdss base' member. + */ +struct msm_mdss { + struct drm_device *dev; + + void __iomem *mmio, *vbif; + + struct regulator *vdd; + + struct { + volatile unsigned long enabled_mask; + struct irq_domain *domain; + } irqcontroller; +}; + +static inline void mdss_write(struct msm_mdss *mdss, u32 reg, u32 data) +{ + msm_writel(data, mdss->mmio + reg); +} + +static inline u32 mdss_read(struct msm_mdss *mdss, u32 reg) +{ + return msm_readl(mdss->mmio + reg); +} + +static irqreturn_t mdss_irq(int irq, void *arg) +{ + struct msm_mdss *mdss = arg; + u32 intr; + + intr = mdss_read(mdss, REG_MDSS_HW_INTR_STATUS); + + VERB("intr=%08x", intr); + + while (intr) { + irq_hw_number_t hwirq = fls(intr) - 1; + + generic_handle_irq(irq_find_mapping( + mdss->irqcontroller.domain, hwirq)); + intr &= ~(1 << hwirq); + } + + return IRQ_HANDLED; +} + +/* + * interrupt-controller implementation, so sub-blocks (MDP/HDMI/eDP/DSI/etc) + * can register to get their irq's delivered + */ + +#define VALID_IRQS (MDSS_HW_INTR_STATUS_INTR_MDP | \ + MDSS_HW_INTR_STATUS_INTR_DSI0 | \ + MDSS_HW_INTR_STATUS_INTR_DSI1 | \ + MDSS_HW_INTR_STATUS_INTR_HDMI | \ + MDSS_HW_INTR_STATUS_INTR_EDP) + +static void mdss_hw_mask_irq(struct irq_data *irqd) +{ + struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd); + + smp_mb__before_atomic(); + clear_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask); + smp_mb__after_atomic(); +} + +static void mdss_hw_unmask_irq(struct irq_data *irqd) +{ + struct msm_mdss *mdss = irq_data_get_irq_chip_data(irqd); + + smp_mb__before_atomic(); + set_bit(irqd->hwirq, &mdss->irqcontroller.enabled_mask); + smp_mb__after_atomic(); +} + +static struct irq_chip mdss_hw_irq_chip = { + .name = "mdss", + .irq_mask = mdss_hw_mask_irq, + .irq_unmask = mdss_hw_unmask_irq, +}; + +static int mdss_hw_irqdomain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct msm_mdss *mdss = d->host_data; + + if (!(VALID_IRQS & (1 << hwirq))) + return -EPERM; + + irq_set_chip_and_handler(irq, &mdss_hw_irq_chip, handle_level_irq); + irq_set_chip_data(irq, mdss); + + return 0; +} + +static struct irq_domain_ops mdss_hw_irqdomain_ops = { + .map = mdss_hw_irqdomain_map, + .xlate = irq_domain_xlate_onecell, +}; + + +static int mdss_irq_domain_init(struct msm_mdss *mdss) +{ + struct device *dev = mdss->dev->dev; + struct irq_domain *d; + + d = irq_domain_add_linear(dev->of_node, 32, &mdss_hw_irqdomain_ops, + mdss); + if (!d) { + dev_err(dev, "mdss irq domain add failed\n"); + return -ENXIO; + } + + mdss->irqcontroller.enabled_mask = 0; + mdss->irqcontroller.domain = d; + + return 0; +} + +void msm_mdss_destroy(struct drm_device *dev) +{ + struct msm_drm_private *priv = dev->dev_private; + struct msm_mdss *mdss = priv->mdss; + + if (!mdss) + return; + + irq_domain_remove(mdss->irqcontroller.domain); + mdss->irqcontroller.domain = NULL; + + regulator_disable(mdss->vdd); + + pm_runtime_put_sync(dev->dev); + + pm_runtime_disable(dev->dev); +} + +int msm_mdss_init(struct drm_device *dev) +{ + struct platform_device *pdev = dev->platformdev; + struct msm_drm_private *priv = dev->dev_private; + struct msm_mdss *mdss; + int ret; + + DBG(""); + + if (!of_device_is_compatible(dev->dev->of_node, "qcom,mdss")) + return 0; + + mdss = devm_kzalloc(dev->dev, sizeof(*mdss), GFP_KERNEL); + if (!mdss) { + ret = -ENOMEM; + goto fail; + } + + mdss->dev = dev; + + mdss->mmio = msm_ioremap(pdev, "mdss_phys", "MDSS"); + if (IS_ERR(mdss->mmio)) { + ret = PTR_ERR(mdss->mmio); + goto fail; + } + + mdss->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); + if (IS_ERR(mdss->vbif)) { + ret = PTR_ERR(mdss->vbif); + goto fail; + } + + /* Regulator to enable GDSCs in downstream kernels */ + mdss->vdd = devm_regulator_get(dev->dev, "vdd"); + if (IS_ERR(mdss->vdd)) { + ret = PTR_ERR(mdss->vdd); + goto fail; + } + + ret = regulator_enable(mdss->vdd); + if (ret) { + dev_err(dev->dev, "failed to enable regulator vdd: %d\n", + ret); + goto fail; + } + + ret = devm_request_irq(dev->dev, platform_get_irq(pdev, 0), + mdss_irq, 0, "mdss_isr", mdss); + if (ret) { + dev_err(dev->dev, "failed to init irq: %d\n", ret); + goto fail_irq; + } + + ret = mdss_irq_domain_init(mdss); + if (ret) { + dev_err(dev->dev, "failed to init sub-block irqs: %d\n", ret); + goto fail_irq; + } + + priv->mdss = mdss; + + pm_runtime_enable(dev->dev); + + /* + * TODO: This is needed as the MDSS GDSC is only tied to MDSS's power + * domain. Remove this once runtime PM is adapted for all the devices. + */ + pm_runtime_get_sync(dev->dev); + + return 0; +fail_irq: + regulator_disable(mdss->vdd); +fail: + return ret; +} diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c index 6f425c25d..27d7b55b5 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c @@ -42,7 +42,7 @@ * * configured: * The block is allocated to some client, and assigned to that - * client in MDP5_MDP_SMP_ALLOC registers. + * client in MDP5_SMP_ALLOC registers. * * inuse: * The block is being actively used by a client. @@ -59,7 +59,7 @@ * mdp5_smp_commit. * * 2) mdp5_smp_configure(): - * As hw is programmed, before FLUSH, MDP5_MDP_SMP_ALLOC registers + * As hw is programmed, before FLUSH, MDP5_SMP_ALLOC registers * are configured for the union(pending, inuse) * Current pending is copied to configured. * It is assumed that mdp5_smp_request and mdp5_smp_configure not run @@ -311,25 +311,25 @@ static void update_smp_state(struct mdp5_smp *smp, int idx = blk / 3; int fld = blk % 3; - val = mdp5_read(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx)); + val = mdp5_read(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx)); switch (fld) { case 0: - val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0__MASK; - val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(cid); + val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; + val |= MDP5_SMP_ALLOC_W_REG_CLIENT0(cid); break; case 1: - val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1__MASK; - val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(cid); + val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; + val |= MDP5_SMP_ALLOC_W_REG_CLIENT1(cid); break; case 2: - val &= ~MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2__MASK; - val |= MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(cid); + val &= ~MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; + val |= MDP5_SMP_ALLOC_W_REG_CLIENT2(cid); break; } - mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_W_REG(0, idx), val); - mdp5_write(mdp5_kms, REG_MDP5_MDP_SMP_ALLOC_R_REG(0, idx), val); + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_W_REG(idx), val); + mdp5_write(mdp5_kms, REG_MDP5_SMP_ALLOC_R_REG(idx), val); } } -- cgit v1.2.3-54-g00ecf