From 57f0f512b273f60d52568b8c6b77e17f5636edc0 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Wed, 5 Aug 2015 17:04:01 -0300 Subject: Initial import --- drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild | 4 + drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 144 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 219 +++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c | 50 +++++ drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 271 ++++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h | 30 +++ 6 files changed, 718 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h (limited to 'drivers/gpu/drm/nouveau/nvkm/subdev/bar') diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild new file mode 100644 index 000000000..1ab554a0b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/Kbuild @@ -0,0 +1,4 @@ +nvkm-y += nvkm/subdev/bar/base.o +nvkm-y += nvkm/subdev/bar/nv50.o +nvkm-y += nvkm/subdev/bar/gf100.o +nvkm-y += nvkm/subdev/bar/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c new file mode 100644 index 000000000..3502d0012 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -0,0 +1,144 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include + +struct nvkm_barobj { + struct nvkm_object base; + struct nvkm_vma vma; + void __iomem *iomem; +}; + +static int +nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct nvkm_bar *bar = nvkm_bar(device); + struct nvkm_mem *mem = data; + struct nvkm_barobj *barobj; + int ret; + + ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); + *pobject = nv_object(barobj); + if (ret) + return ret; + + ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma); + if (ret) + return ret; + + barobj->iomem = ioremap(nv_device_resource_start(device, 3) + + (u32)barobj->vma.offset, mem->size << 12); + if (!barobj->iomem) { + nv_warn(bar, "PRAMIN ioremap failed\n"); + return -ENOMEM; + } + + return 0; +} + +static void +nvkm_barobj_dtor(struct nvkm_object *object) +{ + struct nvkm_bar *bar = nvkm_bar(object); + struct nvkm_barobj *barobj = (void *)object; + if (barobj->vma.node) { + if (barobj->iomem) + iounmap(barobj->iomem); + bar->unmap(bar, &barobj->vma); + } + nvkm_object_destroy(&barobj->base); +} + +static u32 +nvkm_barobj_rd32(struct nvkm_object *object, u64 addr) +{ + struct nvkm_barobj *barobj = (void *)object; + return ioread32_native(barobj->iomem + addr); +} + +static void +nvkm_barobj_wr32(struct nvkm_object *object, u64 addr, u32 data) +{ + struct nvkm_barobj *barobj = (void *)object; + iowrite32_native(data, barobj->iomem + addr); +} + +static struct nvkm_oclass +nvkm_barobj_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nvkm_barobj_ctor, + .dtor = nvkm_barobj_dtor, + .init = nvkm_object_init, + .fini = nvkm_object_fini, + .rd32 = nvkm_barobj_rd32, + .wr32 = nvkm_barobj_wr32, + }, +}; + +int +nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent, + struct nvkm_mem *mem, struct nvkm_object **pobject) +{ + struct nvkm_object *gpuobj; + int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, + &nvkm_barobj_oclass, mem, 0, &gpuobj); + if (ret == 0) + *pobject = gpuobj; + return ret; +} + +int +nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) +{ + struct nvkm_bar *bar; + int ret; + + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", + "bar", length, pobject); + bar = *pobject; + if (ret) + return ret; + + return 0; +} + +void +nvkm_bar_destroy(struct nvkm_bar *bar) +{ + nvkm_subdev_destroy(&bar->base); +} + +void +_nvkm_bar_dtor(struct nvkm_object *object) +{ + struct nvkm_bar *bar = (void *)object; + nvkm_bar_destroy(bar); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c new file mode 100644 index 000000000..12a1aebd9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -0,0 +1,219 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include +#include + +struct gf100_bar_priv_vm { + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct gf100_bar_priv { + struct nvkm_bar base; + spinlock_t lock; + struct gf100_bar_priv_vm bar[2]; +}; + +static int +gf100_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static int +gf100_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct gf100_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar[1].vm, mem->size << 12, + mem->page_shift, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static void +gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) +{ + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); +} + +static int +gf100_bar_ctor_vm(struct gf100_bar_priv *priv, struct gf100_bar_priv_vm *bar_vm, + int bar_nr) +{ + struct nvkm_device *device = nv_device(&priv->base); + struct nvkm_vm *vm; + resource_size_t bar_len; + int ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, + &bar_vm->mem); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, + &bar_vm->pgd); + if (ret) + return ret; + + bar_len = nv_device_resource_len(device, bar_nr); + + ret = nvkm_vm_new(device, 0, bar_len, 0, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + + /* + * Bootstrap page table lookup. + */ + if (bar_nr == 3) { + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (bar_len >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, + &vm->pgt[0].obj[0]); + vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + } + + ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); + nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); + nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); + return 0; +} + +int +gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct gf100_bar_priv *priv; + bool has_bar3 = nv_device_resource_len(device, 3) != 0; + int ret; + + ret = nvkm_bar_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + /* BAR3 */ + if (has_bar3) { + ret = gf100_bar_ctor_vm(priv, &priv->bar[0], 3); + if (ret) + return ret; + } + + /* BAR1 */ + ret = gf100_bar_ctor_vm(priv, &priv->bar[1], 1); + if (ret) + return ret; + + if (has_bar3) { + priv->base.alloc = nvkm_bar_alloc; + priv->base.kmap = gf100_bar_kmap; + } + priv->base.umap = gf100_bar_umap; + priv->base.unmap = gf100_bar_unmap; + priv->base.flush = g84_bar_flush; + spin_lock_init(&priv->lock); + return 0; +} + +void +gf100_bar_dtor(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + + nvkm_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[1].mem); + + if (priv->bar[0].vm) { + nvkm_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); + } + nvkm_gpuobj_ref(NULL, &priv->bar[0].pgd); + nvkm_gpuobj_ref(NULL, &priv->bar[0].mem); + + nvkm_bar_destroy(&priv->base); +} + +int +gf100_bar_init(struct nvkm_object *object) +{ + struct gf100_bar_priv *priv = (void *)object; + int ret; + + ret = nvkm_bar_init(&priv->base); + if (ret) + return ret; + + nv_mask(priv, 0x000200, 0x00000100, 0x00000000); + nv_mask(priv, 0x000200, 0x00000100, 0x00000100); + + nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); + if (priv->bar[0].mem) + nv_wr32(priv, 0x001714, + 0xc0000000 | priv->bar[0].mem->addr >> 12); + return 0; +} + +struct nvkm_oclass +gf100_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_bar_ctor, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c new file mode 100644 index 000000000..148f739a2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "priv.h" + +int +gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_bar *bar; + int ret; + + ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); + if (ret) + return ret; + + bar = (struct nvkm_bar *)*pobject; + bar->iomap_uncached = true; + return 0; +} + +struct nvkm_oclass +gk20a_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0xea), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk20a_bar_ctor, + .dtor = gf100_bar_dtor, + .init = gf100_bar_init, + .fini = _nvkm_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c new file mode 100644 index 000000000..8548adb91 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -0,0 +1,271 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include +#include +#include +#include +#include + +struct nv50_bar_priv { + struct nvkm_bar base; + spinlock_t lock; + struct nvkm_gpuobj *mem; + struct nvkm_gpuobj *pad; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *bar1_vm; + struct nvkm_gpuobj *bar1; + struct nvkm_vm *bar3_vm; + struct nvkm_gpuobj *bar3; +}; + +static int +nv50_bar_kmap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct nv50_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static int +nv50_bar_umap(struct nvkm_bar *bar, struct nvkm_mem *mem, u32 flags, + struct nvkm_vma *vma) +{ + struct nv50_bar_priv *priv = (void *)bar; + int ret; + + ret = nvkm_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); + if (ret) + return ret; + + nvkm_vm_map(vma, mem); + return 0; +} + +static void +nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma) +{ + nvkm_vm_unmap(vma); + nvkm_vm_put(vma); +} + +static void +nv50_bar_flush(struct nvkm_bar *bar) +{ + struct nv50_bar_priv *priv = (void *)bar; + unsigned long flags; + spin_lock_irqsave(&priv->lock, flags); + nv_wr32(priv, 0x00330c, 0x00000001); + if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000)) + nv_warn(priv, "flush timeout\n"); + spin_unlock_irqrestore(&priv->lock, flags); +} + +void +g84_bar_flush(struct nvkm_bar *bar) +{ + struct nv50_bar_priv *priv = (void *)bar; + unsigned long flags; + spin_lock_irqsave(&priv->lock, flags); + nv_wr32(bar, 0x070000, 0x00000001); + if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000)) + nv_warn(priv, "flush timeout\n"); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int +nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_device(parent); + struct nvkm_object *heap; + struct nvkm_vm *vm; + struct nv50_bar_priv *priv; + u64 start, limit; + int ret; + + ret = nvkm_bar_create(parent, engine, oclass, &priv); + *pobject = nv_object(priv); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, + NVOBJ_FLAG_HEAP, &priv->mem); + heap = nv_object(priv->mem); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), heap, + (device->chipset == 0x50) ? 0x1400 : 0x0200, + 0, 0, &priv->pad); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), heap, 0x4000, 0, 0, &priv->pgd); + if (ret) + return ret; + + /* BAR3 */ + start = 0x0100000000ULL; + limit = start + nv_device_resource_len(device, 3); + + ret = nvkm_vm_new(device, start, limit, start, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + + ret = nvkm_gpuobj_new(nv_object(priv), heap, + ((limit-- - start) >> 12) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); + vm->pgt[0].refcount[0] = 1; + if (ret) + return ret; + + ret = nvkm_vm_ref(vm, &priv->bar3_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); + if (ret) + return ret; + + nv_wo32(priv->bar3, 0x00, 0x7fc00000); + nv_wo32(priv->bar3, 0x04, lower_32_bits(limit)); + nv_wo32(priv->bar3, 0x08, lower_32_bits(start)); + nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nv_wo32(priv->bar3, 0x10, 0x00000000); + nv_wo32(priv->bar3, 0x14, 0x00000000); + + /* BAR1 */ + start = 0x0000000000ULL; + limit = start + nv_device_resource_len(device, 1); + + ret = nvkm_vm_new(device, start, limit--, start, &vm); + if (ret) + return ret; + + atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + + ret = nvkm_vm_ref(vm, &priv->bar1_vm, priv->pgd); + nvkm_vm_ref(NULL, &vm, NULL); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); + if (ret) + return ret; + + nv_wo32(priv->bar1, 0x00, 0x7fc00000); + nv_wo32(priv->bar1, 0x04, lower_32_bits(limit)); + nv_wo32(priv->bar1, 0x08, lower_32_bits(start)); + nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nv_wo32(priv->bar1, 0x10, 0x00000000); + nv_wo32(priv->bar1, 0x14, 0x00000000); + + priv->base.alloc = nvkm_bar_alloc; + priv->base.kmap = nv50_bar_kmap; + priv->base.umap = nv50_bar_umap; + priv->base.unmap = nv50_bar_unmap; + if (device->chipset == 0x50) + priv->base.flush = nv50_bar_flush; + else + priv->base.flush = g84_bar_flush; + spin_lock_init(&priv->lock); + return 0; +} + +static void +nv50_bar_dtor(struct nvkm_object *object) +{ + struct nv50_bar_priv *priv = (void *)object; + nvkm_gpuobj_ref(NULL, &priv->bar1); + nvkm_vm_ref(NULL, &priv->bar1_vm, priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->bar3); + if (priv->bar3_vm) { + nvkm_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->bar3_vm, priv->pgd); + } + nvkm_gpuobj_ref(NULL, &priv->pgd); + nvkm_gpuobj_ref(NULL, &priv->pad); + nvkm_gpuobj_ref(NULL, &priv->mem); + nvkm_bar_destroy(&priv->base); +} + +static int +nv50_bar_init(struct nvkm_object *object) +{ + struct nv50_bar_priv *priv = (void *)object; + int ret, i; + + ret = nvkm_bar_init(&priv->base); + if (ret) + return ret; + + nv_mask(priv, 0x000200, 0x00000100, 0x00000000); + nv_mask(priv, 0x000200, 0x00000100, 0x00000100); + nv_wr32(priv, 0x100c80, 0x00060001); + if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) { + nv_error(priv, "vm flush timeout\n"); + return -EBUSY; + } + + nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12); + nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12); + nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4); + nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4); + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x001900 + (i * 4), 0x00000000); + return 0; +} + +static int +nv50_bar_fini(struct nvkm_object *object, bool suspend) +{ + struct nv50_bar_priv *priv = (void *)object; + return nvkm_bar_fini(&priv->base, suspend); +} + +struct nvkm_oclass +nv50_bar_oclass = { + .handle = NV_SUBDEV(BAR, 0x50), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_bar_ctor, + .dtor = nv50_bar_dtor, + .init = nv50_bar_init, + .fini = nv50_bar_fini, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h new file mode 100644 index 000000000..aa85f61b4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -0,0 +1,30 @@ +#ifndef __NVKM_BAR_PRIV_H__ +#define __NVKM_BAR_PRIV_H__ +#include + +#define nvkm_bar_create(p,e,o,d) \ + nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d) +#define nvkm_bar_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_bar_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void nvkm_bar_destroy(struct nvkm_bar *); + +void _nvkm_bar_dtor(struct nvkm_object *); +#define _nvkm_bar_init _nvkm_subdev_init +#define _nvkm_bar_fini _nvkm_subdev_fini + +int nvkm_bar_alloc(struct nvkm_bar *, struct nvkm_object *, + struct nvkm_mem *, struct nvkm_object **); + +void g84_bar_flush(struct nvkm_bar *); + +int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_bar_dtor(struct nvkm_object *); +int gf100_bar_init(struct nvkm_object *); +#endif -- cgit v1.2.3-54-g00ecf