From 8d91c1e411f55d7ea91b1183a2e9f8088fb4d5be Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Tue, 15 Dec 2015 14:52:16 -0300 Subject: Linux-libre 4.3.2-gnu --- drivers/staging/sm750fb/ddk750_display.c | 170 ++++++++++++++----------------- 1 file changed, 74 insertions(+), 96 deletions(-) (limited to 'drivers/staging/sm750fb/ddk750_display.c') diff --git a/drivers/staging/sm750fb/ddk750_display.c b/drivers/staging/sm750fb/ddk750_display.c index a3e672056..834811348 100644 --- a/drivers/staging/sm750fb/ddk750_display.c +++ b/drivers/staging/sm750fb/ddk750_display.c @@ -15,16 +15,14 @@ static void setDisplayControl(int ctrl, int dispState) cnt = 0; /* Set the primary display control */ - if (!ctrl) - { + if (!ctrl) { ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL); /* Turn on/off the Panel display control */ - if (dispState) - { + if (dispState) { /* Timing should be enabled first before enabling the plane * because changing at the same time does not guarantee that * the plane will also enabled or disabled. - */ + */ ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, PANEL_DISPLAY_CTRL, TIMING, ENABLE); POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); @@ -45,16 +43,13 @@ static void setDisplayControl(int ctrl, int dispState) * until a few delay. Need to write * and read it a couple times */ - do - { + do { cnt++; POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); - } while((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != + } while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulDisplayCtrlReg & ~ulReservedBits)); printk("Set Panel Plane enbit:after tried %d times\n", cnt); - } - else - { + } else { /* When turning off, there is no rule on the programming * sequence since whenever the clock is off, then it does not * matter whether the plane is enabled or disabled. @@ -71,14 +66,11 @@ static void setDisplayControl(int ctrl, int dispState) POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); } - } - /* Set the secondary display control */ - else - { + } else { + /* Set the secondary display control */ ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL); - if (dispState) - { + if (dispState) { /* Timing should be enabled first before enabling the plane because changing at the same time does not guarantee that the plane will also enabled or disabled. */ @@ -100,16 +92,13 @@ static void setDisplayControl(int ctrl, int dispState) FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) | FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE); - do - { + do { cnt++; POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg); - } while((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) != + } while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) != (ulDisplayCtrlReg & ~ulReservedBits)); printk("Set Crt Plane enbit:after tried %d times\n", cnt); - } - else - { + } else { /* When turning off, there is no rule on the programming * sequence since whenever the clock is off, then it does not * matter whether the plane is enabled or disabled. @@ -132,71 +121,60 @@ static void setDisplayControl(int ctrl, int dispState) static void waitNextVerticalSync(int ctrl, int delay) { unsigned int status; - if(!ctrl){ + + if (!ctrl) { /* primary controller */ - /* Do not wait when the Primary PLL is off or display control is already off. - This will prevent the software to wait forever. */ + /* Do not wait when the Primary PLL is off or display control is already off. + This will prevent the software to wait forever. */ if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) == PANEL_PLL_CTRL_POWER_OFF) || (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) == - PANEL_DISPLAY_CTRL_TIMING_DISABLE)) - { + PANEL_DISPLAY_CTRL_TIMING_DISABLE)) { return; } - while (delay-- > 0) - { - /* Wait for end of vsync. */ - do - { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - PANEL_VSYNC); - } - while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); - - /* Wait for start of vsync. */ - do - { - status = FIELD_GET(PEEK32(SYSTEM_CTRL), - SYSTEM_CTRL, - PANEL_VSYNC); - } - while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE); - } - - }else{ + while (delay-- > 0) { + /* Wait for end of vsync. */ + do { + status = FIELD_GET(PEEK32(SYSTEM_CTRL), + SYSTEM_CTRL, + PANEL_VSYNC); + } while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); + + /* Wait for start of vsync. */ + do { + status = FIELD_GET(PEEK32(SYSTEM_CTRL), + SYSTEM_CTRL, + PANEL_VSYNC); + } while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE); + } + + } else { /* Do not wait when the Primary PLL is off or display control is already off. This will prevent the software to wait forever. */ if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) == CRT_PLL_CTRL_POWER_OFF) || (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) == - CRT_DISPLAY_CTRL_TIMING_DISABLE)) - { + CRT_DISPLAY_CTRL_TIMING_DISABLE)) { return; } - while (delay-- > 0) - { + while (delay-- > 0) { /* Wait for end of vsync. */ - do - { + do { status = FIELD_GET(PEEK32(SYSTEM_CTRL), SYSTEM_CTRL, CRT_VSYNC); - } - while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE); + } while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE); /* Wait for start of vsync. */ - do - { + do { status = FIELD_GET(PEEK32(SYSTEM_CTRL), SYSTEM_CTRL, CRT_VSYNC); - } - while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE); + } while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE); } } } @@ -233,14 +211,15 @@ static void swPanelPowerSequence(int disp, int delay) void ddk750_setLogicalDispOut(disp_output_t output) { unsigned int reg; - if(output & PNL_2_USAGE){ + + if (output & PNL_2_USAGE) { /* set panel path controller select */ reg = PEEK32(PANEL_DISPLAY_CTRL); reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, SELECT, (output & PNL_2_MASK)>>PNL_2_OFFSET); POKE32(PANEL_DISPLAY_CTRL, reg); } - if(output & CRT_2_USAGE){ + if (output & CRT_2_USAGE) { /* set crt path controller select */ reg = PEEK32(CRT_DISPLAY_CTRL); reg = FIELD_VALUE(reg, CRT_DISPLAY_CTRL, SELECT, (output & CRT_2_MASK)>>CRT_2_OFFSET); @@ -250,58 +229,57 @@ void ddk750_setLogicalDispOut(disp_output_t output) } - if(output & PRI_TP_USAGE){ + if (output & PRI_TP_USAGE) { /* set primary timing and plane en_bit */ setDisplayControl(0, (output&PRI_TP_MASK)>>PRI_TP_OFFSET); } - if(output & SEC_TP_USAGE){ + if (output & SEC_TP_USAGE) { /* set secondary timing and plane en_bit*/ setDisplayControl(1, (output&SEC_TP_MASK)>>SEC_TP_OFFSET); } - if(output & PNL_SEQ_USAGE){ + if (output & PNL_SEQ_USAGE) { /* set panel sequence */ swPanelPowerSequence((output&PNL_SEQ_MASK)>>PNL_SEQ_OFFSET, 4); } - if(output & DAC_USAGE) + if (output & DAC_USAGE) setDAC((output & DAC_MASK)>>DAC_OFFSET); - if(output & DPMS_USAGE) + if (output & DPMS_USAGE) ddk750_setDPMS((output & DPMS_MASK) >> DPMS_OFFSET); } int ddk750_initDVIDisp(void) { - /* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are - not zeroed, then set the failure flag. If it is zeroe, it might mean - that the system is in Dual CRT Monitor configuration. */ - - /* De-skew enabled with default 111b value. - This will fix some artifacts problem in some mode on board 2.2. - Somehow this fix does not affect board 2.1. - */ - if ((dviInit(1, /* Select Rising Edge */ - 1, /* Select 24-bit bus */ - 0, /* Select Single Edge clock */ - 1, /* Enable HSync as is */ - 1, /* Enable VSync as is */ - 1, /* Enable De-skew */ - 7, /* Set the de-skew setting to maximum setup */ - 1, /* Enable continuous Sync */ - 1, /* Enable PLL Filter */ - 4 /* Use the recommended value for PLL Filter value */ - ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000)) - { - return (-1); - } - - /* TODO: Initialize other display component */ - - /* Success */ - return 0; + /* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are + not zeroed, then set the failure flag. If it is zeroe, it might mean + that the system is in Dual CRT Monitor configuration. */ + + /* De-skew enabled with default 111b value. + This will fix some artifacts problem in some mode on board 2.2. + Somehow this fix does not affect board 2.1. + */ + if ((dviInit(1, /* Select Rising Edge */ + 1, /* Select 24-bit bus */ + 0, /* Select Single Edge clock */ + 1, /* Enable HSync as is */ + 1, /* Enable VSync as is */ + 1, /* Enable De-skew */ + 7, /* Set the de-skew setting to maximum setup */ + 1, /* Enable continuous Sync */ + 1, /* Enable PLL Filter */ + 4 /* Use the recommended value for PLL Filter value */ + ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000)) { + return (-1); + } + + /* TODO: Initialize other display component */ + + /* Success */ + return 0; } -- cgit v1.2.3-54-g00ecf