From 57f0f512b273f60d52568b8c6b77e17f5636edc0 Mon Sep 17 00:00:00 2001 From: André Fabian Silva Delgado Date: Wed, 5 Aug 2015 17:04:01 -0300 Subject: Initial import --- include/dt-bindings/clock/stih418-clks.h | 34 ++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 include/dt-bindings/clock/stih418-clks.h (limited to 'include/dt-bindings/clock/stih418-clks.h') diff --git a/include/dt-bindings/clock/stih418-clks.h b/include/dt-bindings/clock/stih418-clks.h new file mode 100644 index 000000000..b62aa0b20 --- /dev/null +++ b/include/dt-bindings/clock/stih418-clks.h @@ -0,0 +1,34 @@ +/* + * This header provides constants clk index STMicroelectronics + * STiH418 SoC. + */ +#ifndef _DT_BINDINGS_CLK_STIH418 +#define _DT_BINDINGS_CLK_STIH418 + +#include "stih410-clks.h" + +/* STiH418 introduces new clock outputs compared to STiH410 */ + +/* CLOCKGEN C0 */ +#define CLK_PROC_BDISP_0 14 +#define CLK_PROC_BDISP_1 15 +#define CLK_TX_ICN_1 23 +#define CLK_ETH_PHYREF 27 +#define CLK_PP_HEVC 35 +#define CLK_CLUST_HEVC 36 +#define CLK_HWPE_HEVC 37 +#define CLK_FC_HEVC 38 +#define CLK_PROC_MIXER 39 +#define CLK_PROC_SC 40 +#define CLK_AVSP_HEVC 41 + +/* CLOCKGEN D2 */ +#undef CLK_PIX_PIP +#undef CLK_PIX_GDP1 +#undef CLK_PIX_GDP2 +#undef CLK_PIX_GDP3 +#undef CLK_PIX_GDP4 + +#define CLK_TMDS_HDMI_DIV2 5 +#define CLK_VP9 47 +#endif -- cgit v1.2.3-54-g00ecf