summaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/octeon/cvmx-fau.h
blob: dafeae300c970a4f1668637a528b3110f0fce8a9 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: support@caviumnetworks.com
 * This file is part of the OCTEON SDK
 *
 * Copyright (c) 2003-2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

/*
 * Interface to the hardware Fetch and Add Unit.
 */

#ifndef __CVMX_FAU_H__
#define __CVMX_FAU_H__

/*
 * Octeon Fetch and Add Unit (FAU)
 */

#define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
#define CVMX_FAU_BITS_SCRADDR	    63, 56
#define CVMX_FAU_BITS_LEN	    55, 48
#define CVMX_FAU_BITS_INEVAL	    35, 14
#define CVMX_FAU_BITS_TAGWAIT	    13, 13
#define CVMX_FAU_BITS_NOADD	    13, 13
#define CVMX_FAU_BITS_SIZE	    12, 11
#define CVMX_FAU_BITS_REGISTER	    10, 0

typedef enum {
	CVMX_FAU_OP_SIZE_8 = 0,
	CVMX_FAU_OP_SIZE_16 = 1,
	CVMX_FAU_OP_SIZE_32 = 2,
	CVMX_FAU_OP_SIZE_64 = 3
} cvmx_fau_op_size_t;

/**
 * Tagwait return definition. If a timeout occurs, the error
 * bit will be set. Otherwise the value of the register before
 * the update will be returned.
 */
typedef struct {
	uint64_t error:1;
	int64_t value:63;
} cvmx_fau_tagwait64_t;

/**
 * Tagwait return definition. If a timeout occurs, the error
 * bit will be set. Otherwise the value of the register before
 * the update will be returned.
 */
typedef struct {
	uint64_t error:1;
	int32_t value:31;
} cvmx_fau_tagwait32_t;

/**
 * Tagwait return definition. If a timeout occurs, the error
 * bit will be set. Otherwise the value of the register before
 * the update will be returned.
 */
typedef struct {
	uint64_t error:1;
	int16_t value:15;
} cvmx_fau_tagwait16_t;

/**
 * Tagwait return definition. If a timeout occurs, the error
 * bit will be set. Otherwise the value of the register before
 * the update will be returned.
 */
typedef struct {
	uint64_t error:1;
	int8_t value:7;
} cvmx_fau_tagwait8_t;

/**
 * Asynchronous tagwait return definition. If a timeout occurs,
 * the error bit will be set. Otherwise the value of the
 * register before the update will be returned.
 */
typedef union {
	uint64_t u64;
	struct {
		uint64_t invalid:1;
		uint64_t data:63;	/* unpredictable if invalid is set */
	} s;
} cvmx_fau_async_tagwait_result_t;

#ifdef __BIG_ENDIAN_BITFIELD
#define SWIZZLE_8  0
#define SWIZZLE_16 0
#define SWIZZLE_32 0
#else
#define SWIZZLE_8  0x7
#define SWIZZLE_16 0x6
#define SWIZZLE_32 0x4
#endif

/**
 * Builds a store I/O address for writing to the FAU
 *
 * @noadd:  0 = Store value is atomically added to the current value
 *		 1 = Store value is atomically written over the current value
 * @reg:    FAU atomic register to access. 0 <= reg < 2048.
 *		 - Step by 2 for 16 bit access.
 *		 - Step by 4 for 32 bit access.
 *		 - Step by 8 for 64 bit access.
 * Returns Address to store for atomic update
 */
static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
{
	return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
	       cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
	       cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
}

/**
 * Builds a I/O address for accessing the FAU
 *
 * @tagwait: Should the atomic add wait for the current tag switch
 *		  operation to complete.
 *		  - 0 = Don't wait
 *		  - 1 = Wait for tag switch to complete
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 *		  - Step by 4 for 32 bit access.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to add.
 *		  Note: When performing 32 and 64 bit access, only the low
 *		  22 bits are available.
 * Returns Address to read from for atomic update
 */
static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
						 int64_t value)
{
	return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
	       cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
	       cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
	       cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
}

/**
 * Perform an atomic 64 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Value of the register before the update
 */
static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
					       int64_t value)
{
	return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
}

/**
 * Perform an atomic 32 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 4 for 32 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Value of the register before the update
 */
static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
					       int32_t value)
{
	reg ^= SWIZZLE_32;
	return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
}

/**
 * Perform an atomic 16 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 * @value:   Signed value to add.
 * Returns Value of the register before the update
 */
static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
					       int16_t value)
{
	reg ^= SWIZZLE_16;
	return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
}

/**
 * Perform an atomic 8 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 * @value:   Signed value to add.
 * Returns Value of the register before the update
 */
static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
{
	reg ^= SWIZZLE_8;
	return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
}

/**
 * Perform an atomic 64 bit add after the current tag switch
 * completes
 *
 * @reg:    FAU atomic register to access. 0 <= reg < 2048.
 *		 - Step by 8 for 64 bit access.
 * @value:  Signed value to add.
 *		 Note: Only the low 22 bits are available.
 * Returns If a timeout occurs, the error bit will be set. Otherwise
 *	   the value of the register before the update will be
 *	   returned
 */
static inline cvmx_fau_tagwait64_t
cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
{
	union {
		uint64_t i64;
		cvmx_fau_tagwait64_t t;
	} result;
	result.i64 =
	    cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
	return result.t;
}

/**
 * Perform an atomic 32 bit add after the current tag switch
 * completes
 *
 * @reg:    FAU atomic register to access. 0 <= reg < 2048.
 *		 - Step by 4 for 32 bit access.
 * @value:  Signed value to add.
 *		 Note: Only the low 22 bits are available.
 * Returns If a timeout occurs, the error bit will be set. Otherwise
 *	   the value of the register before the update will be
 *	   returned
 */
static inline cvmx_fau_tagwait32_t
cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
{
	union {
		uint64_t i32;
		cvmx_fau_tagwait32_t t;
	} result;
	reg ^= SWIZZLE_32;
	result.i32 =
	    cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
	return result.t;
}

/**
 * Perform an atomic 16 bit add after the current tag switch
 * completes
 *
 * @reg:    FAU atomic register to access. 0 <= reg < 2048.
 *		 - Step by 2 for 16 bit access.
 * @value:  Signed value to add.
 * Returns If a timeout occurs, the error bit will be set. Otherwise
 *	   the value of the register before the update will be
 *	   returned
 */
static inline cvmx_fau_tagwait16_t
cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
{
	union {
		uint64_t i16;
		cvmx_fau_tagwait16_t t;
	} result;
	reg ^= SWIZZLE_16;
	result.i16 =
	    cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
	return result.t;
}

/**
 * Perform an atomic 8 bit add after the current tag switch
 * completes
 *
 * @reg:    FAU atomic register to access. 0 <= reg < 2048.
 * @value:  Signed value to add.
 * Returns If a timeout occurs, the error bit will be set. Otherwise
 *	   the value of the register before the update will be
 *	   returned
 */
static inline cvmx_fau_tagwait8_t
cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
{
	union {
		uint64_t i8;
		cvmx_fau_tagwait8_t t;
	} result;
	reg ^= SWIZZLE_8;
	result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
	return result.t;
}

/**
 * Builds I/O data for async operations
 *
 * @scraddr: Scratch pad byte address to write to.  Must be 8 byte aligned
 * @value:   Signed value to add.
 *		  Note: When performing 32 and 64 bit access, only the low
 *		  22 bits are available.
 * @tagwait: Should the atomic add wait for the current tag switch
 *		  operation to complete.
 *		  - 0 = Don't wait
 *		  - 1 = Wait for tag switch to complete
 * @size:    The size of the operation:
 *		  - CVMX_FAU_OP_SIZE_8	(0) = 8 bits
 *		  - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
 *		  - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
 *		  - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 *		  - Step by 4 for 32 bit access.
 *		  - Step by 8 for 64 bit access.
 * Returns Data to write using cvmx_send_single
 */
static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
					      uint64_t tagwait,
					      cvmx_fau_op_size_t size,
					      uint64_t reg)
{
	return CVMX_FAU_LOAD_IO_ADDRESS |
	       cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
	       cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
	       cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
	       cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
	       cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
	       cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
}

/**
 * Perform an async atomic 64 bit add. The old value is
 * placed in the scratch memory at byte address scraddr.
 *
 * @scraddr: Scratch memory byte address to put response in.
 *		  Must be 8 byte aligned.
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
						  cvmx_fau_reg_64_t reg,
						  int64_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
}

/**
 * Perform an async atomic 32 bit add. The old value is
 * placed in the scratch memory at byte address scraddr.
 *
 * @scraddr: Scratch memory byte address to put response in.
 *		  Must be 8 byte aligned.
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 4 for 32 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
						  cvmx_fau_reg_32_t reg,
						  int32_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
}

/**
 * Perform an async atomic 16 bit add. The old value is
 * placed in the scratch memory at byte address scraddr.
 *
 * @scraddr: Scratch memory byte address to put response in.
 *		  Must be 8 byte aligned.
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 * @value:   Signed value to add.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
						  cvmx_fau_reg_16_t reg,
						  int16_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
}

/**
 * Perform an async atomic 8 bit add. The old value is
 * placed in the scratch memory at byte address scraddr.
 *
 * @scraddr: Scratch memory byte address to put response in.
 *		  Must be 8 byte aligned.
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 * @value:   Signed value to add.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
						 cvmx_fau_reg_8_t reg,
						 int8_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
}

/**
 * Perform an async atomic 64 bit add after the current tag
 * switch completes.
 *
 * @scraddr: Scratch memory byte address to put response in.  Must be
 *	     8 byte aligned.  If a timeout occurs, the error bit (63)
 *	     will be set. Otherwise the value of the register before
 *	     the update will be returned
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
							  cvmx_fau_reg_64_t reg,
							  int64_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
}

/**
 * Perform an async atomic 32 bit add after the current tag
 * switch completes.
 *
 * @scraddr: Scratch memory byte address to put response in.  Must be
 *	     8 byte aligned.  If a timeout occurs, the error bit (63)
 *	     will be set. Otherwise the value of the register before
 *	     the update will be returned
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 4 for 32 bit access.
 * @value:   Signed value to add.
 *		  Note: Only the low 22 bits are available.
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
							  cvmx_fau_reg_32_t reg,
							  int32_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
}

/**
 * Perform an async atomic 16 bit add after the current tag
 * switch completes.
 *
 * @scraddr: Scratch memory byte address to put response in.  Must be
 *	     8 byte aligned.  If a timeout occurs, the error bit (63)
 *	     will be set. Otherwise the value of the register before
 *	     the update will be returned
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 * @value:   Signed value to add.
 *
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
							  cvmx_fau_reg_16_t reg,
							  int16_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
}

/**
 * Perform an async atomic 8 bit add after the current tag
 * switch completes.
 *
 * @scraddr: Scratch memory byte address to put response in.  Must be
 *	     8 byte aligned.  If a timeout occurs, the error bit (63)
 *	     will be set. Otherwise the value of the register before
 *	     the update will be returned
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 * @value:   Signed value to add.
 *
 * Returns Placed in the scratch pad register
 */
static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
							 cvmx_fau_reg_8_t reg,
							 int8_t value)
{
	cvmx_send_single(__cvmx_fau_iobdma_data
			 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
}

/**
 * Perform an atomic 64 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to add.
 */
static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
{
	cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
}

/**
 * Perform an atomic 32 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 4 for 32 bit access.
 * @value:   Signed value to add.
 */
static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
{
	reg ^= SWIZZLE_32;
	cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
}

/**
 * Perform an atomic 16 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 * @value:   Signed value to add.
 */
static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
{
	reg ^= SWIZZLE_16;
	cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
}

/**
 * Perform an atomic 8 bit add
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 * @value:   Signed value to add.
 */
static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
{
	reg ^= SWIZZLE_8;
	cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
}

/**
 * Perform an atomic 64 bit write
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 8 for 64 bit access.
 * @value:   Signed value to write.
 */
static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
{
	cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
}

/**
 * Perform an atomic 32 bit write
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 4 for 32 bit access.
 * @value:   Signed value to write.
 */
static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
{
	reg ^= SWIZZLE_32;
	cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
}

/**
 * Perform an atomic 16 bit write
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 *		  - Step by 2 for 16 bit access.
 * @value:   Signed value to write.
 */
static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
{
	reg ^= SWIZZLE_16;
	cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
}

/**
 * Perform an atomic 8 bit write
 *
 * @reg:     FAU atomic register to access. 0 <= reg < 2048.
 * @value:   Signed value to write.
 */
static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
{
	reg ^= SWIZZLE_8;
	cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
}

#endif /* __CVMX_FAU_H__ */