summaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/ge_imp3a.dts
blob: fefae416a097f26337e94cff8060d03f4b92fad8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
/*
 * GE IMP3A Device Tree Source
 *
 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Based on: P2020 DS Device Tree Source
 * Copyright 2009 Freescale Semiconductor Inc.
 */

/include/ "fsl/p2020si-pre.dtsi"

/ {
	model = "GE_IMP3A";
	compatible = "ge,imp3a";

	memory {
		device_type = "memory";
	};

	lbc: localbus@fef05000 {
		reg = <0 0xfef05000 0 0x1000>;

		ranges = <0x0 0x0 0x0 0xff000000 0x01000000
			  0x1 0x0 0x0 0xe0000000 0x08000000
			  0x2 0x0 0x0 0xe8000000 0x08000000
			  0x3 0x0 0x0 0xfc100000 0x00020000
			  0x4 0x0 0x0 0xfc000000 0x00008000
			  0x5 0x0 0x0 0xfc008000 0x00008000
			  0x6 0x0 0x0 0xfee00000 0x00040000
			  0x7 0x0 0x0 0xfee80000 0x00040000>;

		/* nor@0,0 is a mirror of part of the memory in nor@1,0
		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
			reg = <0x0 0x0 0x1000000>;
			bank-width = <2>;
			device-width = <1>;

			partition@0 {
				label = "firmware";
				reg = <0x0 0x1000000>;
				read-only;
			};
		};
		*/

		nor@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "ge,imp3a-paged-flash", "cfi-flash";
			reg = <0x1 0x0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;

			partition@0 {
				label = "user";
				reg = <0x0 0x7800000>;
			};

			partition@7800000 {
				label = "firmware";
				reg = <0x7800000 0x800000>;
				read-only;
			};
		};

		nvram@3,0 {
			device_type = "nvram";
			compatible = "simtek,stk14ca8";
			reg = <0x3 0x0 0x20000>;
		};

		fpga@4,0 {
			compatible = "ge,imp3a-fpga-regs";
			reg = <0x4 0x0 0x20>;
		};

		gef_pic: pic@4,20 {
			#interrupt-cells = <1>;
			interrupt-controller;
			device_type = "interrupt-controller";
			compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
			reg = <0x4 0x20 0x20>;
			interrupts = <6 7 0 0>;
		};

		gef_gpio: gpio@4,400 {
			#gpio-cells = <2>;
			compatible = "ge,imp3a-gpio";
			reg = <0x4 0x400 0x24>;
			gpio-controller;
		};

		wdt@4,800 {
			compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x800 0x8>;
			interrupts = <10 4>;
			interrupt-parent = <&gef_pic>;
		};

		/* Second watchdog available, driver currently supports one.
		wdt@4,808 {
			compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
				"gef,fpga-wdt";
			reg = <0x4 0x808 0x8>;
			interrupts = <9 4>;
			interrupt-parent = <&gef_pic>;
		};
		*/

		nand@6,0 {
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x6 0x0 0x40000>;
		};

		nand@7,0 {
			compatible = "fsl,elbc-fcm-nand";
			reg = <0x7 0x0 0x40000>;
		};
	};

	soc: soc@fef00000 {
		ranges = <0x0 0 0xfef00000 0x100000>;

		i2c@3000 {
			hwmon@48 {
				compatible = "national,lm92";
				reg = <0x48>;
			};

			hwmon@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};

			rtc@51 {
				compatible = "epson,rx8581";
				reg = <0x51>;
			};

			eti@6b {
				compatible = "dallas,ds1682";
				reg = <0x6b>;
			};
		};

		usb@22000 {
			phy_type = "ulpi";
			dr_mode = "host";
		};

		mdio@24520 {
			phy0: ethernet-phy@0 {
				interrupt-parent = <&gef_pic>;
				interrupts = <0xc 0x4>;
				reg = <0x1>;
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&gef_pic>;
				interrupts = <0xb 0x4>;
				reg = <0x2>;
			};
			tbi0: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@25520 {
			tbi1: tbi-phy@11 {
				reg = <0x11>;
				device_type = "tbi-phy";
			};
		};

		mdio@26520 {
			status = "disabled";
		};

		enet0: ethernet@24000 {
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "gmii";
		};

		enet1: ethernet@25000 {
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;
			phy-connection-type = "gmii";
		};

		enet2: ethernet@26000 {
			status = "disabled";
		};
	};

	pci0: pcie@fef08000 {
		ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
		reg = <0 0xfef08000 0 0x1000>;

		pcie@0 {
			ranges = <0x2000000 0x0 0xc0000000
				  0x2000000 0x0 0xc0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};

	pci1: pcie@fef09000 {
		reg = <0 0xfef09000 0 0x1000>;
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;

		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};

	};

	pci2: pcie@fef0a000 {
		reg = <0 0xfef0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;

		pcie@0 {
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x10000>;
		};
	};
};

/include/ "fsl/p2020si-post.dtsi"