summaryrefslogtreecommitdiff
path: root/include/linux/mfd/palmas.h
blob: c800dbc420795c37c78b2008b4cbe5991d90b881 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
/*
 * TI Palmas
 *
 * Copyright 2011-2013 Texas Instruments Inc.
 *
 * Author: Graeme Gregory <gg@slimlogic.co.uk>
 * Author: Ian Lartey <ian@slimlogic.co.uk>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under  the terms of the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the License, or (at your
 *  option) any later version.
 *
 */

#ifndef __LINUX_MFD_PALMAS_H
#define __LINUX_MFD_PALMAS_H

#include <linux/usb/otg.h>
#include <linux/leds.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/extcon.h>
#include <linux/of_gpio.h>
#include <linux/usb/phy_companion.h>

#define PALMAS_NUM_CLIENTS		3

/* The ID_REVISION NUMBERS */
#define PALMAS_CHIP_OLD_ID		0x0000
#define PALMAS_CHIP_ID			0xC035
#define PALMAS_CHIP_CHARGER_ID		0xC036

#define TPS65917_RESERVED		-1

#define is_palmas(a)	(((a) == PALMAS_CHIP_OLD_ID) || \
			((a) == PALMAS_CHIP_ID))
#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)

/**
 * Palmas PMIC feature types
 *
 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
 *	regulator.
 *
 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
 *	specific feature (above) or not. Return non-zero, if yes.
 */
#define PALMAS_PMIC_FEATURE_SMPS10_BOOST	BIT(0)
#define PALMAS_PMIC_HAS(b, f)			\
			((b)->features & PALMAS_PMIC_FEATURE_ ## f)

struct palmas_pmic;
struct palmas_gpadc;
struct palmas_resource;
struct palmas_usb;
struct palmas_pmic_driver_data;
struct palmas_pmic_platform_data;

enum palmas_usb_state {
	PALMAS_USB_STATE_DISCONNECT,
	PALMAS_USB_STATE_VBUS,
	PALMAS_USB_STATE_ID,
};

struct palmas {
	struct device *dev;

	struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
	struct regmap *regmap[PALMAS_NUM_CLIENTS];

	/* Stored chip id */
	int id;

	unsigned int features;
	/* IRQ Data */
	int irq;
	u32 irq_mask;
	struct mutex irq_lock;
	struct regmap_irq_chip_data *irq_data;

	struct palmas_pmic_driver_data *pmic_ddata;

	/* Child Devices */
	struct palmas_pmic *pmic;
	struct palmas_gpadc *gpadc;
	struct palmas_resource *resource;
	struct palmas_usb *usb;

	/* GPIO MUXing */
	u8 gpio_muxed;
	u8 led_muxed;
	u8 pwm_muxed;
};

#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 |	\
			PALMAS_EXT_CONTROL_ENABLE2 |	\
			PALMAS_EXT_CONTROL_NSLEEP)

struct palmas_sleep_requestor_info {
	int id;
	int reg_offset;
	int bit_pos;
};

struct palmas_regs_info {
	char	*name;
	char	*sname;
	u8	vsel_addr;
	u8	ctrl_addr;
	u8	tstep_addr;
	int	sleep_id;
};

struct palmas_pmic_driver_data {
	int smps_start;
	int smps_end;
	int ldo_begin;
	int ldo_end;
	int max_reg;
	bool has_regen3;
	struct palmas_regs_info *palmas_regs_info;
	struct of_regulator_match *palmas_matches;
	struct palmas_sleep_requestor_info *sleep_req_info;
	int (*smps_register)(struct palmas_pmic *pmic,
			     struct palmas_pmic_driver_data *ddata,
			     struct palmas_pmic_platform_data *pdata,
			     const char *pdev_name,
			     struct regulator_config config);
	int (*ldo_register)(struct palmas_pmic *pmic,
			    struct palmas_pmic_driver_data *ddata,
			    struct palmas_pmic_platform_data *pdata,
			    const char *pdev_name,
			    struct regulator_config config);
};

struct palmas_adc_wakeup_property {
	int adc_channel_number;
	int adc_high_threshold;
	int adc_low_threshold;
};

struct palmas_gpadc_platform_data {
	/* Channel 3 current source is only enabled during conversion */
	int ch3_current;	/* 0: off; 1: 10uA; 2: 400uA; 3: 800 uA */

	/* Channel 0 current source can be used for battery detection.
	 * If used for battery detection this will cause a permanent current
	 * consumption depending on current level set here.
	 */
	int ch0_current;	/* 0: off; 1: 5uA; 2: 15uA; 3: 20 uA */
	bool extended_delay;	/* use extended delay for conversion */

	/* default BAT_REMOVAL_DAT setting on device probe */
	int bat_removal;

	/* Sets the START_POLARITY bit in the RT_CTRL register */
	int start_polarity;

	int auto_conversion_period_ms;
	struct palmas_adc_wakeup_property *adc_wakeup1_data;
	struct palmas_adc_wakeup_property *adc_wakeup2_data;
};

struct palmas_reg_init {
	/* warm_rest controls the voltage levels after a warm reset
	 *
	 * 0: reload default values from OTP on warm reset
	 * 1: maintain voltage from VSEL on warm reset
	 */
	int warm_reset;

	/* roof_floor controls whether the regulator uses the i2c style
	 * of DVS or uses the method where a GPIO or other control method is
	 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
	 *
	 * For SMPS
	 *
	 * 0: i2c selection of voltage
	 * 1: pin selection of voltage.
	 *
	 * For LDO unused
	 */
	int roof_floor;

	/* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
	 * the data sheet.
	 *
	 * For SMPS
	 *
	 * 0: Off
	 * 1: AUTO
	 * 2: ECO
	 * 3: Forced PWM
	 *
	 * For LDO
	 *
	 * 0: Off
	 * 1: On
	 */
	int mode_sleep;

	/* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
	 * register. Set this is the default voltage set in OTP needs
	 * to be overridden.
	 */
	u8 vsel;

};

enum palmas_regulators {
	/* SMPS regulators */
	PALMAS_REG_SMPS12,
	PALMAS_REG_SMPS123,
	PALMAS_REG_SMPS3,
	PALMAS_REG_SMPS45,
	PALMAS_REG_SMPS457,
	PALMAS_REG_SMPS6,
	PALMAS_REG_SMPS7,
	PALMAS_REG_SMPS8,
	PALMAS_REG_SMPS9,
	PALMAS_REG_SMPS10_OUT2,
	PALMAS_REG_SMPS10_OUT1,
	/* LDO regulators */
	PALMAS_REG_LDO1,
	PALMAS_REG_LDO2,
	PALMAS_REG_LDO3,
	PALMAS_REG_LDO4,
	PALMAS_REG_LDO5,
	PALMAS_REG_LDO6,
	PALMAS_REG_LDO7,
	PALMAS_REG_LDO8,
	PALMAS_REG_LDO9,
	PALMAS_REG_LDOLN,
	PALMAS_REG_LDOUSB,
	/* External regulators */
	PALMAS_REG_REGEN1,
	PALMAS_REG_REGEN2,
	PALMAS_REG_REGEN3,
	PALMAS_REG_SYSEN1,
	PALMAS_REG_SYSEN2,
	/* Total number of regulators */
	PALMAS_NUM_REGS,
};

enum tps65917_regulators {
	/* SMPS regulators */
	TPS65917_REG_SMPS1,
	TPS65917_REG_SMPS2,
	TPS65917_REG_SMPS3,
	TPS65917_REG_SMPS4,
	TPS65917_REG_SMPS5,
	/* LDO regulators */
	TPS65917_REG_LDO1,
	TPS65917_REG_LDO2,
	TPS65917_REG_LDO3,
	TPS65917_REG_LDO4,
	TPS65917_REG_LDO5,
	TPS65917_REG_REGEN1,
	TPS65917_REG_REGEN2,
	TPS65917_REG_REGEN3,

	/* Total number of regulators */
	TPS65917_NUM_REGS,
};

/* External controll signal name */
enum {
	PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
	PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
	PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
};

/*
 * Palmas device resources can be controlled externally for
 * enabling/disabling it rather than register write through i2c.
 * Add the external controlled requestor ID for different resources.
 */
enum palmas_external_requestor_id {
	PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
	PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
	PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
	PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
	PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
	PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
	PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
	PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
	PALMAS_EXTERNAL_REQSTR_ID_LDO1,
	PALMAS_EXTERNAL_REQSTR_ID_LDO2,
	PALMAS_EXTERNAL_REQSTR_ID_LDO3,
	PALMAS_EXTERNAL_REQSTR_ID_LDO4,
	PALMAS_EXTERNAL_REQSTR_ID_LDO5,
	PALMAS_EXTERNAL_REQSTR_ID_LDO6,
	PALMAS_EXTERNAL_REQSTR_ID_LDO7,
	PALMAS_EXTERNAL_REQSTR_ID_LDO8,
	PALMAS_EXTERNAL_REQSTR_ID_LDO9,
	PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
	PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,

	/* Last entry */
	PALMAS_EXTERNAL_REQSTR_ID_MAX,
};

enum tps65917_external_requestor_id {
	TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
	TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
	TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
	TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
	TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
	TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
	TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
	TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
	TPS65917_EXTERNAL_REQSTR_ID_LDO1,
	TPS65917_EXTERNAL_REQSTR_ID_LDO2,
	TPS65917_EXTERNAL_REQSTR_ID_LDO3,
	TPS65917_EXTERNAL_REQSTR_ID_LDO4,
	TPS65917_EXTERNAL_REQSTR_ID_LDO5,
	/* Last entry */
	TPS65917_EXTERNAL_REQSTR_ID_MAX,
};

struct palmas_pmic_platform_data {
	/* An array of pointers to regulator init data indexed by regulator
	 * ID
	 */
	struct regulator_init_data *reg_data[PALMAS_NUM_REGS];

	/* An array of pointers to structures containing sleep mode and DVS
	 * configuration for regulators indexed by ID
	 */
	struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];

	/* use LDO6 for vibrator control */
	int ldo6_vibrator;

	/* Enable tracking mode of LDO8 */
	bool enable_ldo8_tracking;
};

struct palmas_usb_platform_data {
	/* Do we enable the wakeup comparator on probe */
	int wakeup;
};

struct palmas_resource_platform_data {
	int regen1_mode_sleep;
	int regen2_mode_sleep;
	int sysen1_mode_sleep;
	int sysen2_mode_sleep;

	/* bitfield to be loaded to NSLEEP_RES_ASSIGN */
	u8 nsleep_res;
	/* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
	u8 nsleep_smps;
	/* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
	u8 nsleep_ldo1;
	/* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
	u8 nsleep_ldo2;

	/* bitfield to be loaded to ENABLE1_RES_ASSIGN */
	u8 enable1_res;
	/* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
	u8 enable1_smps;
	/* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
	u8 enable1_ldo1;
	/* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
	u8 enable1_ldo2;

	/* bitfield to be loaded to ENABLE2_RES_ASSIGN */
	u8 enable2_res;
	/* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
	u8 enable2_smps;
	/* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
	u8 enable2_ldo1;
	/* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
	u8 enable2_ldo2;
};

struct palmas_clk_platform_data {
	int clk32kg_mode_sleep;
	int clk32kgaudio_mode_sleep;
};

struct palmas_platform_data {
	int irq_flags;
	int gpio_base;

	/* bit value to be loaded to the POWER_CTRL register */
	u8 power_ctrl;

	/*
	 * boolean to select if we want to configure muxing here
	 * then the two value to load into the registers if true
	 */
	int mux_from_pdata;
	u8 pad1, pad2;
	bool pm_off;

	struct palmas_pmic_platform_data *pmic_pdata;
	struct palmas_gpadc_platform_data *gpadc_pdata;
	struct palmas_usb_platform_data *usb_pdata;
	struct palmas_resource_platform_data *resource_pdata;
	struct palmas_clk_platform_data *clk_pdata;
};

struct palmas_gpadc_calibration {
	s32 gain;
	s32 gain_error;
	s32 offset_error;
};

#define PALMAS_DATASHEET_NAME(_name)	"palmas-gpadc-chan-"#_name

struct palmas_gpadc_result {
	s32 raw_code;
	s32 corrected_code;
	s32 result;
};

#define PALMAS_MAX_CHANNELS 16

/* Define the tps65917 IRQ numbers */
enum tps65917_irqs {
	/* INT1 registers */
	TPS65917_RESERVED1,
	TPS65917_PWRON_IRQ,
	TPS65917_LONG_PRESS_KEY_IRQ,
	TPS65917_RESERVED2,
	TPS65917_PWRDOWN_IRQ,
	TPS65917_HOTDIE_IRQ,
	TPS65917_VSYS_MON_IRQ,
	TPS65917_RESERVED3,
	/* INT2 registers */
	TPS65917_RESERVED4,
	TPS65917_OTP_ERROR_IRQ,
	TPS65917_WDT_IRQ,
	TPS65917_RESERVED5,
	TPS65917_RESET_IN_IRQ,
	TPS65917_FSD_IRQ,
	TPS65917_SHORT_IRQ,
	TPS65917_RESERVED6,
	/* INT3 registers */
	TPS65917_GPADC_AUTO_0_IRQ,
	TPS65917_GPADC_AUTO_1_IRQ,
	TPS65917_GPADC_EOC_SW_IRQ,
	TPS65917_RESREVED6,
	TPS65917_RESERVED7,
	TPS65917_RESERVED8,
	TPS65917_RESERVED9,
	TPS65917_VBUS_IRQ,
	/* INT4 registers */
	TPS65917_GPIO_0_IRQ,
	TPS65917_GPIO_1_IRQ,
	TPS65917_GPIO_2_IRQ,
	TPS65917_GPIO_3_IRQ,
	TPS65917_GPIO_4_IRQ,
	TPS65917_GPIO_5_IRQ,
	TPS65917_GPIO_6_IRQ,
	TPS65917_RESERVED10,
	/* Total Number IRQs */
	TPS65917_NUM_IRQ,
};

/* Define the palmas IRQ numbers */
enum palmas_irqs {
	/* INT1 registers */
	PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
	PALMAS_PWRON_IRQ,
	PALMAS_LONG_PRESS_KEY_IRQ,
	PALMAS_RPWRON_IRQ,
	PALMAS_PWRDOWN_IRQ,
	PALMAS_HOTDIE_IRQ,
	PALMAS_VSYS_MON_IRQ,
	PALMAS_VBAT_MON_IRQ,
	/* INT2 registers */
	PALMAS_RTC_ALARM_IRQ,
	PALMAS_RTC_TIMER_IRQ,
	PALMAS_WDT_IRQ,
	PALMAS_BATREMOVAL_IRQ,
	PALMAS_RESET_IN_IRQ,
	PALMAS_FBI_BB_IRQ,
	PALMAS_SHORT_IRQ,
	PALMAS_VAC_ACOK_IRQ,
	/* INT3 registers */
	PALMAS_GPADC_AUTO_0_IRQ,
	PALMAS_GPADC_AUTO_1_IRQ,
	PALMAS_GPADC_EOC_SW_IRQ,
	PALMAS_GPADC_EOC_RT_IRQ,
	PALMAS_ID_OTG_IRQ,
	PALMAS_ID_IRQ,
	PALMAS_VBUS_OTG_IRQ,
	PALMAS_VBUS_IRQ,
	/* INT4 registers */
	PALMAS_GPIO_0_IRQ,
	PALMAS_GPIO_1_IRQ,
	PALMAS_GPIO_2_IRQ,
	PALMAS_GPIO_3_IRQ,
	PALMAS_GPIO_4_IRQ,
	PALMAS_GPIO_5_IRQ,
	PALMAS_GPIO_6_IRQ,
	PALMAS_GPIO_7_IRQ,
	/* Total Number IRQs */
	PALMAS_NUM_IRQ,
};

/* Palmas GPADC Channels */
enum {
	PALMAS_ADC_CH_IN0,
	PALMAS_ADC_CH_IN1,
	PALMAS_ADC_CH_IN2,
	PALMAS_ADC_CH_IN3,
	PALMAS_ADC_CH_IN4,
	PALMAS_ADC_CH_IN5,
	PALMAS_ADC_CH_IN6,
	PALMAS_ADC_CH_IN7,
	PALMAS_ADC_CH_IN8,
	PALMAS_ADC_CH_IN9,
	PALMAS_ADC_CH_IN10,
	PALMAS_ADC_CH_IN11,
	PALMAS_ADC_CH_IN12,
	PALMAS_ADC_CH_IN13,
	PALMAS_ADC_CH_IN14,
	PALMAS_ADC_CH_IN15,
	PALMAS_ADC_CH_MAX,
};

/* Palmas GPADC Channel0 Current Source */
enum {
	PALMAS_ADC_CH0_CURRENT_SRC_0,
	PALMAS_ADC_CH0_CURRENT_SRC_5,
	PALMAS_ADC_CH0_CURRENT_SRC_15,
	PALMAS_ADC_CH0_CURRENT_SRC_20,
};

/* Palmas GPADC Channel3 Current Source */
enum {
	PALMAS_ADC_CH3_CURRENT_SRC_0,
	PALMAS_ADC_CH3_CURRENT_SRC_10,
	PALMAS_ADC_CH3_CURRENT_SRC_400,
	PALMAS_ADC_CH3_CURRENT_SRC_800,
};

struct palmas_pmic {
	struct palmas *palmas;
	struct device *dev;
	struct regulator_desc desc[PALMAS_NUM_REGS];
	struct regulator_dev *rdev[PALMAS_NUM_REGS];
	struct mutex mutex;

	int smps123;
	int smps457;
	int smps12;

	int range[PALMAS_REG_SMPS10_OUT1];
	unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
	unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
};

struct palmas_resource {
	struct palmas *palmas;
	struct device *dev;
};

struct palmas_usb {
	struct palmas *palmas;
	struct device *dev;

	struct extcon_dev *edev;

	int id_otg_irq;
	int id_irq;
	int vbus_otg_irq;
	int vbus_irq;

	int gpio_id_irq;
	struct gpio_desc *id_gpiod;
	unsigned long sw_debounce_jiffies;
	struct delayed_work wq_detectid;

	enum palmas_usb_state linkstat;
	int wakeup;
	bool enable_vbus_detection;
	bool enable_id_detection;
	bool enable_gpio_id_detection;
};

#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)

enum usb_irq_events {
	/* Wakeup events from INT3 */
	PALMAS_USB_ID_WAKEPUP,
	PALMAS_USB_VBUS_WAKEUP,

	/* ID_OTG_EVENTS */
	PALMAS_USB_ID_GND,
	N_PALMAS_USB_ID_GND,
	PALMAS_USB_ID_C,
	N_PALMAS_USB_ID_C,
	PALMAS_USB_ID_B,
	N_PALMAS_USB_ID_B,
	PALMAS_USB_ID_A,
	N_PALMAS_USB_ID_A,
	PALMAS_USB_ID_FLOAT,
	N_PALMAS_USB_ID_FLOAT,

	/* VBUS_OTG_EVENTS */
	PALMAS_USB_VB_SESS_END,
	N_PALMAS_USB_VB_SESS_END,
	PALMAS_USB_VB_SESS_VLD,
	N_PALMAS_USB_VB_SESS_VLD,
	PALMAS_USB_VA_SESS_VLD,
	N_PALMAS_USB_VA_SESS_VLD,
	PALMAS_USB_VA_VBUS_VLD,
	N_PALMAS_USB_VA_VBUS_VLD,
	PALMAS_USB_VADP_SNS,
	N_PALMAS_USB_VADP_SNS,
	PALMAS_USB_VADP_PRB,
	N_PALMAS_USB_VADP_PRB,
	PALMAS_USB_VOTG_SESS_VLD,
	N_PALMAS_USB_VOTG_SESS_VLD,
};

/* defines so we can store the mux settings */
#define PALMAS_GPIO_0_MUXED					(1 << 0)
#define PALMAS_GPIO_1_MUXED					(1 << 1)
#define PALMAS_GPIO_2_MUXED					(1 << 2)
#define PALMAS_GPIO_3_MUXED					(1 << 3)
#define PALMAS_GPIO_4_MUXED					(1 << 4)
#define PALMAS_GPIO_5_MUXED					(1 << 5)
#define PALMAS_GPIO_6_MUXED					(1 << 6)
#define PALMAS_GPIO_7_MUXED					(1 << 7)

#define PALMAS_LED1_MUXED					(1 << 0)
#define PALMAS_LED2_MUXED					(1 << 1)

#define PALMAS_PWM1_MUXED					(1 << 0)
#define PALMAS_PWM2_MUXED					(1 << 1)

/* helper macro to get correct slave number */
#define PALMAS_BASE_TO_SLAVE(x)		((x >> 8) - 1)
#define PALMAS_BASE_TO_REG(x, y)	((x & 0xFF) + y)

/* Base addresses of IP blocks in Palmas */
#define PALMAS_SMPS_DVS_BASE					0x020
#define PALMAS_RTC_BASE						0x100
#define PALMAS_VALIDITY_BASE					0x118
#define PALMAS_SMPS_BASE					0x120
#define PALMAS_LDO_BASE						0x150
#define PALMAS_DVFS_BASE					0x180
#define PALMAS_PMU_CONTROL_BASE					0x1A0
#define PALMAS_RESOURCE_BASE					0x1D4
#define PALMAS_PU_PD_OD_BASE					0x1F0
#define PALMAS_LED_BASE						0x200
#define PALMAS_INTERRUPT_BASE					0x210
#define PALMAS_USB_OTG_BASE					0x250
#define PALMAS_VIBRATOR_BASE					0x270
#define PALMAS_GPIO_BASE					0x280
#define PALMAS_USB_BASE						0x290
#define PALMAS_GPADC_BASE					0x2C0
#define PALMAS_TRIM_GPADC_BASE					0x3CD

/* Registers for function RTC */
#define PALMAS_SECONDS_REG					0x00
#define PALMAS_MINUTES_REG					0x01
#define PALMAS_HOURS_REG					0x02
#define PALMAS_DAYS_REG						0x03
#define PALMAS_MONTHS_REG					0x04
#define PALMAS_YEARS_REG					0x05
#define PALMAS_WEEKS_REG					0x06
#define PALMAS_ALARM_SECONDS_REG				0x08
#define PALMAS_ALARM_MINUTES_REG				0x09
#define PALMAS_ALARM_HOURS_REG					0x0A
#define PALMAS_ALARM_DAYS_REG					0x0B
#define PALMAS_ALARM_MONTHS_REG					0x0C
#define PALMAS_ALARM_YEARS_REG					0x0D
#define PALMAS_RTC_CTRL_REG					0x10
#define PALMAS_RTC_STATUS_REG					0x11
#define PALMAS_RTC_INTERRUPTS_REG				0x12
#define PALMAS_RTC_COMP_LSB_REG					0x13
#define PALMAS_RTC_COMP_MSB_REG					0x14
#define PALMAS_RTC_RES_PROG_REG					0x15
#define PALMAS_RTC_RESET_STATUS_REG				0x16

/* Bit definitions for SECONDS_REG */
#define PALMAS_SECONDS_REG_SEC1_MASK				0x70
#define PALMAS_SECONDS_REG_SEC1_SHIFT				0x04
#define PALMAS_SECONDS_REG_SEC0_MASK				0x0F
#define PALMAS_SECONDS_REG_SEC0_SHIFT				0x00

/* Bit definitions for MINUTES_REG */
#define PALMAS_MINUTES_REG_MIN1_MASK				0x70
#define PALMAS_MINUTES_REG_MIN1_SHIFT				0x04
#define PALMAS_MINUTES_REG_MIN0_MASK				0x0F
#define PALMAS_MINUTES_REG_MIN0_SHIFT				0x00

/* Bit definitions for HOURS_REG */
#define PALMAS_HOURS_REG_PM_NAM					0x80
#define PALMAS_HOURS_REG_PM_NAM_SHIFT				0x07
#define PALMAS_HOURS_REG_HOUR1_MASK				0x30
#define PALMAS_HOURS_REG_HOUR1_SHIFT				0x04
#define PALMAS_HOURS_REG_HOUR0_MASK				0x0F
#define PALMAS_HOURS_REG_HOUR0_SHIFT				0x00

/* Bit definitions for DAYS_REG */
#define PALMAS_DAYS_REG_DAY1_MASK				0x30
#define PALMAS_DAYS_REG_DAY1_SHIFT				0x04
#define PALMAS_DAYS_REG_DAY0_MASK				0x0F
#define PALMAS_DAYS_REG_DAY0_SHIFT				0x00

/* Bit definitions for MONTHS_REG */
#define PALMAS_MONTHS_REG_MONTH1				0x10
#define PALMAS_MONTHS_REG_MONTH1_SHIFT				0x04
#define PALMAS_MONTHS_REG_MONTH0_MASK				0x0F
#define PALMAS_MONTHS_REG_MONTH0_SHIFT				0x00

/* Bit definitions for YEARS_REG */
#define PALMAS_YEARS_REG_YEAR1_MASK				0xf0
#define PALMAS_YEARS_REG_YEAR1_SHIFT				0x04
#define PALMAS_YEARS_REG_YEAR0_MASK				0x0F
#define PALMAS_YEARS_REG_YEAR0_SHIFT				0x00

/* Bit definitions for WEEKS_REG */
#define PALMAS_WEEKS_REG_WEEK_MASK				0x07
#define PALMAS_WEEKS_REG_WEEK_SHIFT				0x00

/* Bit definitions for ALARM_SECONDS_REG */
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK		0x70
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT		0x04
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK		0x0F
#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT		0x00

/* Bit definitions for ALARM_MINUTES_REG */
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK		0x70
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT		0x04
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK		0x0F
#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT		0x00

/* Bit definitions for ALARM_HOURS_REG */
#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM			0x80
#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT		0x07
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK			0x30
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT		0x04
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK			0x0F
#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT		0x00

/* Bit definitions for ALARM_DAYS_REG */
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK			0x30
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT			0x04
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK			0x0F
#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT			0x00

/* Bit definitions for ALARM_MONTHS_REG */
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1			0x10
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT		0x04
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK		0x0F
#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT		0x00

/* Bit definitions for ALARM_YEARS_REG */
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK			0xf0
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT		0x04
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK			0x0F
#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT		0x00

/* Bit definitions for RTC_CTRL_REG */
#define PALMAS_RTC_CTRL_REG_RTC_V_OPT				0x80
#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT			0x07
#define PALMAS_RTC_CTRL_REG_GET_TIME				0x40
#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT			0x06
#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER			0x20
#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT		0x05
#define PALMAS_RTC_CTRL_REG_TEST_MODE				0x10
#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT			0x04
#define PALMAS_RTC_CTRL_REG_MODE_12_24				0x08
#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT			0x03
#define PALMAS_RTC_CTRL_REG_AUTO_COMP				0x04
#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT			0x02
#define PALMAS_RTC_CTRL_REG_ROUND_30S				0x02
#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT			0x01
#define PALMAS_RTC_CTRL_REG_STOP_RTC				0x01
#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT			0x00

/* Bit definitions for RTC_STATUS_REG */
#define PALMAS_RTC_STATUS_REG_POWER_UP				0x80
#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT			0x07
#define PALMAS_RTC_STATUS_REG_ALARM				0x40
#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT			0x06
#define PALMAS_RTC_STATUS_REG_EVENT_1D				0x20
#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT			0x05
#define PALMAS_RTC_STATUS_REG_EVENT_1H				0x10
#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT			0x04
#define PALMAS_RTC_STATUS_REG_EVENT_1M				0x08
#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT			0x03
#define PALMAS_RTC_STATUS_REG_EVENT_1S				0x04
#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT			0x02
#define PALMAS_RTC_STATUS_REG_RUN				0x02
#define PALMAS_RTC_STATUS_REG_RUN_SHIFT				0x01

/* Bit definitions for RTC_INTERRUPTS_REG */
#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN		0x10
#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT	0x04
#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM			0x08
#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT		0x03
#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER			0x04
#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT		0x02
#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK			0x03
#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT			0x00

/* Bit definitions for RTC_COMP_LSB_REG */
#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK		0xFF
#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT		0x00

/* Bit definitions for RTC_COMP_MSB_REG */
#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK		0xFF
#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT		0x00

/* Bit definitions for RTC_RES_PROG_REG */
#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK		0x3F
#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT		0x00

/* Bit definitions for RTC_RESET_STATUS_REG */
#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS		0x01
#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT		0x00

/* Registers for function BACKUP */
#define PALMAS_BACKUP0						0x00
#define PALMAS_BACKUP1						0x01
#define PALMAS_BACKUP2						0x02
#define PALMAS_BACKUP3						0x03
#define PALMAS_BACKUP4						0x04
#define PALMAS_BACKUP5						0x05
#define PALMAS_BACKUP6						0x06
#define PALMAS_BACKUP7						0x07

/* Bit definitions for BACKUP0 */
#define PALMAS_BACKUP0_BACKUP_MASK				0xFF
#define PALMAS_BACKUP0_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP1 */
#define PALMAS_BACKUP1_BACKUP_MASK				0xFF
#define PALMAS_BACKUP1_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP2 */
#define PALMAS_BACKUP2_BACKUP_MASK				0xFF
#define PALMAS_BACKUP2_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP3 */
#define PALMAS_BACKUP3_BACKUP_MASK				0xFF
#define PALMAS_BACKUP3_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP4 */
#define PALMAS_BACKUP4_BACKUP_MASK				0xFF
#define PALMAS_BACKUP4_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP5 */
#define PALMAS_BACKUP5_BACKUP_MASK				0xFF
#define PALMAS_BACKUP5_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP6 */
#define PALMAS_BACKUP6_BACKUP_MASK				0xFF
#define PALMAS_BACKUP6_BACKUP_SHIFT				0x00

/* Bit definitions for BACKUP7 */
#define PALMAS_BACKUP7_BACKUP_MASK				0xFF
#define PALMAS_BACKUP7_BACKUP_SHIFT				0x00

/* Registers for function SMPS */
#define PALMAS_SMPS12_CTRL					0x00
#define PALMAS_SMPS12_TSTEP					0x01
#define PALMAS_SMPS12_FORCE					0x02
#define PALMAS_SMPS12_VOLTAGE					0x03
#define PALMAS_SMPS3_CTRL					0x04
#define PALMAS_SMPS3_VOLTAGE					0x07
#define PALMAS_SMPS45_CTRL					0x08
#define PALMAS_SMPS45_TSTEP					0x09
#define PALMAS_SMPS45_FORCE					0x0A
#define PALMAS_SMPS45_VOLTAGE					0x0B
#define PALMAS_SMPS6_CTRL					0x0C
#define PALMAS_SMPS6_TSTEP					0x0D
#define PALMAS_SMPS6_FORCE					0x0E
#define PALMAS_SMPS6_VOLTAGE					0x0F
#define PALMAS_SMPS7_CTRL					0x10
#define PALMAS_SMPS7_VOLTAGE					0x13
#define PALMAS_SMPS8_CTRL					0x14
#define PALMAS_SMPS8_TSTEP					0x15
#define PALMAS_SMPS8_FORCE					0x16
#define PALMAS_SMPS8_VOLTAGE					0x17
#define PALMAS_SMPS9_CTRL					0x18
#define PALMAS_SMPS9_VOLTAGE					0x1B
#define PALMAS_SMPS10_CTRL					0x1C
#define PALMAS_SMPS10_STATUS					0x1F
#define PALMAS_SMPS_CTRL					0x24
#define PALMAS_SMPS_PD_CTRL					0x25
#define PALMAS_SMPS_DITHER_EN					0x26
#define PALMAS_SMPS_THERMAL_EN					0x27
#define PALMAS_SMPS_THERMAL_STATUS				0x28
#define PALMAS_SMPS_SHORT_STATUS				0x29
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN			0x2A
#define PALMAS_SMPS_POWERGOOD_MASK1				0x2B
#define PALMAS_SMPS_POWERGOOD_MASK2				0x2C

/* Bit definitions for SMPS12_CTRL */
#define PALMAS_SMPS12_CTRL_WR_S					0x80
#define PALMAS_SMPS12_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN			0x40
#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT			0x06
#define PALMAS_SMPS12_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS12_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS12_TSTEP */
#define PALMAS_SMPS12_TSTEP_TSTEP_MASK				0x03
#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT				0x00

/* Bit definitions for SMPS12_FORCE */
#define PALMAS_SMPS12_FORCE_CMD					0x80
#define PALMAS_SMPS12_FORCE_CMD_SHIFT				0x07
#define PALMAS_SMPS12_FORCE_VSEL_MASK				0x7F
#define PALMAS_SMPS12_FORCE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS12_VOLTAGE */
#define PALMAS_SMPS12_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS3_CTRL */
#define PALMAS_SMPS3_CTRL_WR_S					0x80
#define PALMAS_SMPS3_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS3_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS3_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS3_VOLTAGE */
#define PALMAS_SMPS3_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS45_CTRL */
#define PALMAS_SMPS45_CTRL_WR_S					0x80
#define PALMAS_SMPS45_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN			0x40
#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT			0x06
#define PALMAS_SMPS45_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS45_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS45_TSTEP */
#define PALMAS_SMPS45_TSTEP_TSTEP_MASK				0x03
#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT				0x00

/* Bit definitions for SMPS45_FORCE */
#define PALMAS_SMPS45_FORCE_CMD					0x80
#define PALMAS_SMPS45_FORCE_CMD_SHIFT				0x07
#define PALMAS_SMPS45_FORCE_VSEL_MASK				0x7F
#define PALMAS_SMPS45_FORCE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS45_VOLTAGE */
#define PALMAS_SMPS45_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS6_CTRL */
#define PALMAS_SMPS6_CTRL_WR_S					0x80
#define PALMAS_SMPS6_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN				0x40
#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT			0x06
#define PALMAS_SMPS6_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS6_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS6_TSTEP */
#define PALMAS_SMPS6_TSTEP_TSTEP_MASK				0x03
#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT				0x00

/* Bit definitions for SMPS6_FORCE */
#define PALMAS_SMPS6_FORCE_CMD					0x80
#define PALMAS_SMPS6_FORCE_CMD_SHIFT				0x07
#define PALMAS_SMPS6_FORCE_VSEL_MASK				0x7F
#define PALMAS_SMPS6_FORCE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS6_VOLTAGE */
#define PALMAS_SMPS6_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS7_CTRL */
#define PALMAS_SMPS7_CTRL_WR_S					0x80
#define PALMAS_SMPS7_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS7_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS7_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS7_VOLTAGE */
#define PALMAS_SMPS7_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS8_CTRL */
#define PALMAS_SMPS8_CTRL_WR_S					0x80
#define PALMAS_SMPS8_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN				0x40
#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT			0x06
#define PALMAS_SMPS8_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS8_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS8_TSTEP */
#define PALMAS_SMPS8_TSTEP_TSTEP_MASK				0x03
#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT				0x00

/* Bit definitions for SMPS8_FORCE */
#define PALMAS_SMPS8_FORCE_CMD					0x80
#define PALMAS_SMPS8_FORCE_CMD_SHIFT				0x07
#define PALMAS_SMPS8_FORCE_VSEL_MASK				0x7F
#define PALMAS_SMPS8_FORCE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS8_VOLTAGE */
#define PALMAS_SMPS8_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS9_CTRL */
#define PALMAS_SMPS9_CTRL_WR_S					0x80
#define PALMAS_SMPS9_CTRL_WR_S_SHIFT				0x07
#define PALMAS_SMPS9_CTRL_STATUS_MASK				0x30
#define PALMAS_SMPS9_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK			0x0c
#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK			0x03
#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS9_VOLTAGE */
#define PALMAS_SMPS9_VOLTAGE_RANGE				0x80
#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT			0x07
#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK				0x7F
#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for SMPS10_CTRL */
#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK			0xf0
#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT			0x04
#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK			0x0F
#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS10_STATUS */
#define PALMAS_SMPS10_STATUS_STATUS_MASK			0x0F
#define PALMAS_SMPS10_STATUS_STATUS_SHIFT			0x00

/* Bit definitions for SMPS_CTRL */
#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN			0x20
#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT		0x05
#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN			0x10
#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT		0x04
#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK			0x0c
#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT		0x02
#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK		0x03
#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT		0x00

/* Bit definitions for SMPS_PD_CTRL */
#define PALMAS_SMPS_PD_CTRL_SMPS9				0x40
#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT				0x06
#define PALMAS_SMPS_PD_CTRL_SMPS8				0x20
#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT				0x05
#define PALMAS_SMPS_PD_CTRL_SMPS7				0x10
#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT				0x04
#define PALMAS_SMPS_PD_CTRL_SMPS6				0x08
#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT				0x03
#define PALMAS_SMPS_PD_CTRL_SMPS45				0x04
#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT			0x02
#define PALMAS_SMPS_PD_CTRL_SMPS3				0x02
#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT				0x01
#define PALMAS_SMPS_PD_CTRL_SMPS12				0x01
#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT			0x00

/* Bit definitions for SMPS_THERMAL_EN */
#define PALMAS_SMPS_THERMAL_EN_SMPS9				0x40
#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT			0x06
#define PALMAS_SMPS_THERMAL_EN_SMPS8				0x20
#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT			0x05
#define PALMAS_SMPS_THERMAL_EN_SMPS6				0x08
#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT			0x03
#define PALMAS_SMPS_THERMAL_EN_SMPS457				0x04
#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT			0x02
#define PALMAS_SMPS_THERMAL_EN_SMPS123				0x01
#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT			0x00

/* Bit definitions for SMPS_THERMAL_STATUS */
#define PALMAS_SMPS_THERMAL_STATUS_SMPS9			0x40
#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT			0x06
#define PALMAS_SMPS_THERMAL_STATUS_SMPS8			0x20
#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT			0x05
#define PALMAS_SMPS_THERMAL_STATUS_SMPS6			0x08
#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT			0x03
#define PALMAS_SMPS_THERMAL_STATUS_SMPS457			0x04
#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT		0x02
#define PALMAS_SMPS_THERMAL_STATUS_SMPS123			0x01
#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT		0x00

/* Bit definitions for SMPS_SHORT_STATUS */
#define PALMAS_SMPS_SHORT_STATUS_SMPS10				0x80
#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT			0x07
#define PALMAS_SMPS_SHORT_STATUS_SMPS9				0x40
#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT			0x06
#define PALMAS_SMPS_SHORT_STATUS_SMPS8				0x20
#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT			0x05
#define PALMAS_SMPS_SHORT_STATUS_SMPS7				0x10
#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT			0x04
#define PALMAS_SMPS_SHORT_STATUS_SMPS6				0x08
#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT			0x03
#define PALMAS_SMPS_SHORT_STATUS_SMPS45				0x04
#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT			0x02
#define PALMAS_SMPS_SHORT_STATUS_SMPS3				0x02
#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT			0x01
#define PALMAS_SMPS_SHORT_STATUS_SMPS12				0x01
#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT			0x00

/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9		0x40
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT	0x06
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8		0x20
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT	0x05
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7		0x10
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT	0x04
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6		0x08
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT	0x03
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45		0x04
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT	0x02
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3		0x02
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT	0x01
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12		0x01
#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT	0x00

/* Bit definitions for SMPS_POWERGOOD_MASK1 */
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10			0x80
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT		0x07
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9			0x40
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT			0x06
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8			0x20
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT			0x05
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7			0x10
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT			0x04
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6			0x08
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT			0x03
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45			0x04
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT		0x02
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3			0x02
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT			0x01
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12			0x01
#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT		0x00

/* Bit definitions for SMPS_POWERGOOD_MASK2 */
#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT	0x80
#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT	0x07
#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7			0x04
#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT		0x02
#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS			0x02
#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT			0x01
#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK			0x01
#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT			0x00

/* Registers for function LDO */
#define PALMAS_LDO1_CTRL					0x00
#define PALMAS_LDO1_VOLTAGE					0x01
#define PALMAS_LDO2_CTRL					0x02
#define PALMAS_LDO2_VOLTAGE					0x03
#define PALMAS_LDO3_CTRL					0x04
#define PALMAS_LDO3_VOLTAGE					0x05
#define PALMAS_LDO4_CTRL					0x06
#define PALMAS_LDO4_VOLTAGE					0x07
#define PALMAS_LDO5_CTRL					0x08
#define PALMAS_LDO5_VOLTAGE					0x09
#define PALMAS_LDO6_CTRL					0x0A
#define PALMAS_LDO6_VOLTAGE					0x0B
#define PALMAS_LDO7_CTRL					0x0C
#define PALMAS_LDO7_VOLTAGE					0x0D
#define PALMAS_LDO8_CTRL					0x0E
#define PALMAS_LDO8_VOLTAGE					0x0F
#define PALMAS_LDO9_CTRL					0x10
#define PALMAS_LDO9_VOLTAGE					0x11
#define PALMAS_LDOLN_CTRL					0x12
#define PALMAS_LDOLN_VOLTAGE					0x13
#define PALMAS_LDOUSB_CTRL					0x14
#define PALMAS_LDOUSB_VOLTAGE					0x15
#define PALMAS_LDO_CTRL						0x1A
#define PALMAS_LDO_PD_CTRL1					0x1B
#define PALMAS_LDO_PD_CTRL2					0x1C
#define PALMAS_LDO_SHORT_STATUS1				0x1D
#define PALMAS_LDO_SHORT_STATUS2				0x1E

/* Bit definitions for LDO1_CTRL */
#define PALMAS_LDO1_CTRL_WR_S					0x80
#define PALMAS_LDO1_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO1_CTRL_STATUS					0x10
#define PALMAS_LDO1_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO1_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO1_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO1_VOLTAGE */
#define PALMAS_LDO1_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO2_CTRL */
#define PALMAS_LDO2_CTRL_WR_S					0x80
#define PALMAS_LDO2_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO2_CTRL_STATUS					0x10
#define PALMAS_LDO2_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO2_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO2_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO2_VOLTAGE */
#define PALMAS_LDO2_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO3_CTRL */
#define PALMAS_LDO3_CTRL_WR_S					0x80
#define PALMAS_LDO3_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO3_CTRL_STATUS					0x10
#define PALMAS_LDO3_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO3_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO3_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO3_VOLTAGE */
#define PALMAS_LDO3_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO4_CTRL */
#define PALMAS_LDO4_CTRL_WR_S					0x80
#define PALMAS_LDO4_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO4_CTRL_STATUS					0x10
#define PALMAS_LDO4_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO4_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO4_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO4_VOLTAGE */
#define PALMAS_LDO4_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO5_CTRL */
#define PALMAS_LDO5_CTRL_WR_S					0x80
#define PALMAS_LDO5_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO5_CTRL_STATUS					0x10
#define PALMAS_LDO5_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO5_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO5_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO5_VOLTAGE */
#define PALMAS_LDO5_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO6_CTRL */
#define PALMAS_LDO6_CTRL_WR_S					0x80
#define PALMAS_LDO6_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO6_CTRL_LDO_VIB_EN				0x40
#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT			0x06
#define PALMAS_LDO6_CTRL_STATUS					0x10
#define PALMAS_LDO6_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO6_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO6_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO6_VOLTAGE */
#define PALMAS_LDO6_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO7_CTRL */
#define PALMAS_LDO7_CTRL_WR_S					0x80
#define PALMAS_LDO7_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO7_CTRL_STATUS					0x10
#define PALMAS_LDO7_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO7_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO7_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO7_VOLTAGE */
#define PALMAS_LDO7_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO8_CTRL */
#define PALMAS_LDO8_CTRL_WR_S					0x80
#define PALMAS_LDO8_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN			0x40
#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT			0x06
#define PALMAS_LDO8_CTRL_STATUS					0x10
#define PALMAS_LDO8_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO8_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO8_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO8_VOLTAGE */
#define PALMAS_LDO8_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDO9_CTRL */
#define PALMAS_LDO9_CTRL_WR_S					0x80
#define PALMAS_LDO9_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN				0x40
#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT			0x06
#define PALMAS_LDO9_CTRL_STATUS					0x10
#define PALMAS_LDO9_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDO9_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDO9_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO9_VOLTAGE */
#define PALMAS_LDO9_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDOLN_CTRL */
#define PALMAS_LDOLN_CTRL_WR_S					0x80
#define PALMAS_LDOLN_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDOLN_CTRL_STATUS				0x10
#define PALMAS_LDOLN_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDOLN_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDOLN_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDOLN_VOLTAGE */
#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT				0x00

/* Bit definitions for LDOUSB_CTRL */
#define PALMAS_LDOUSB_CTRL_WR_S					0x80
#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT				0x07
#define PALMAS_LDOUSB_CTRL_STATUS				0x10
#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT				0x04
#define PALMAS_LDOUSB_CTRL_MODE_SLEEP				0x04
#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE				0x01
#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDOUSB_VOLTAGE */
#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK				0x3F
#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO_CTRL */
#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS			0x01
#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT		0x00

/* Bit definitions for LDO_PD_CTRL1 */
#define PALMAS_LDO_PD_CTRL1_LDO8				0x80
#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT				0x07
#define PALMAS_LDO_PD_CTRL1_LDO7				0x40
#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT				0x06
#define PALMAS_LDO_PD_CTRL1_LDO6				0x20
#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT				0x05
#define PALMAS_LDO_PD_CTRL1_LDO5				0x10
#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT				0x04
#define PALMAS_LDO_PD_CTRL1_LDO4				0x08
#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT				0x03
#define PALMAS_LDO_PD_CTRL1_LDO3				0x04
#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT				0x02
#define PALMAS_LDO_PD_CTRL1_LDO2				0x02
#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT				0x01
#define PALMAS_LDO_PD_CTRL1_LDO1				0x01
#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT				0x00

/* Bit definitions for LDO_PD_CTRL2 */
#define PALMAS_LDO_PD_CTRL2_LDOUSB				0x04
#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT			0x02
#define PALMAS_LDO_PD_CTRL2_LDOLN				0x02
#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT				0x01
#define PALMAS_LDO_PD_CTRL2_LDO9				0x01
#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT				0x00

/* Bit definitions for LDO_SHORT_STATUS1 */
#define PALMAS_LDO_SHORT_STATUS1_LDO8				0x80
#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT			0x07
#define PALMAS_LDO_SHORT_STATUS1_LDO7				0x40
#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT			0x06
#define PALMAS_LDO_SHORT_STATUS1_LDO6				0x20
#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT			0x05
#define PALMAS_LDO_SHORT_STATUS1_LDO5				0x10
#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT			0x04
#define PALMAS_LDO_SHORT_STATUS1_LDO4				0x08
#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT			0x03
#define PALMAS_LDO_SHORT_STATUS1_LDO3				0x04
#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT			0x02
#define PALMAS_LDO_SHORT_STATUS1_LDO2				0x02
#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT			0x01
#define PALMAS_LDO_SHORT_STATUS1_LDO1				0x01
#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT			0x00

/* Bit definitions for LDO_SHORT_STATUS2 */
#define PALMAS_LDO_SHORT_STATUS2_LDOVANA			0x08
#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT			0x03
#define PALMAS_LDO_SHORT_STATUS2_LDOUSB				0x04
#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT			0x02
#define PALMAS_LDO_SHORT_STATUS2_LDOLN				0x02
#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT			0x01
#define PALMAS_LDO_SHORT_STATUS2_LDO9				0x01
#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT			0x00

/* Registers for function PMU_CONTROL */
#define PALMAS_DEV_CTRL						0x00
#define PALMAS_POWER_CTRL					0x01
#define PALMAS_VSYS_LO						0x02
#define PALMAS_VSYS_MON						0x03
#define PALMAS_VBAT_MON						0x04
#define PALMAS_WATCHDOG						0x05
#define PALMAS_BOOT_STATUS					0x06
#define PALMAS_BATTERY_BOUNCE					0x07
#define PALMAS_BACKUP_BATTERY_CTRL				0x08
#define PALMAS_LONG_PRESS_KEY					0x09
#define PALMAS_OSC_THERM_CTRL					0x0A
#define PALMAS_BATDEBOUNCING					0x0B
#define PALMAS_SWOFF_HWRST					0x0F
#define PALMAS_SWOFF_COLDRST					0x10
#define PALMAS_SWOFF_STATUS					0x11
#define PALMAS_PMU_CONFIG					0x12
#define PALMAS_SPARE						0x14
#define PALMAS_PMU_SECONDARY_INT				0x15
#define PALMAS_SW_REVISION					0x17
#define PALMAS_EXT_CHRG_CTRL					0x18
#define PALMAS_PMU_SECONDARY_INT2				0x19

/* Bit definitions for DEV_CTRL */
#define PALMAS_DEV_CTRL_DEV_STATUS_MASK				0x0c
#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT			0x02
#define PALMAS_DEV_CTRL_SW_RST					0x02
#define PALMAS_DEV_CTRL_SW_RST_SHIFT				0x01
#define PALMAS_DEV_CTRL_DEV_ON					0x01
#define PALMAS_DEV_CTRL_DEV_ON_SHIFT				0x00

/* Bit definitions for POWER_CTRL */
#define PALMAS_POWER_CTRL_ENABLE2_MASK				0x04
#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT			0x02
#define PALMAS_POWER_CTRL_ENABLE1_MASK				0x02
#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT			0x01
#define PALMAS_POWER_CTRL_NSLEEP_MASK				0x01
#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT			0x00

/* Bit definitions for VSYS_LO */
#define PALMAS_VSYS_LO_THRESHOLD_MASK				0x1F
#define PALMAS_VSYS_LO_THRESHOLD_SHIFT				0x00

/* Bit definitions for VSYS_MON */
#define PALMAS_VSYS_MON_ENABLE					0x80
#define PALMAS_VSYS_MON_ENABLE_SHIFT				0x07
#define PALMAS_VSYS_MON_THRESHOLD_MASK				0x3F
#define PALMAS_VSYS_MON_THRESHOLD_SHIFT				0x00

/* Bit definitions for VBAT_MON */
#define PALMAS_VBAT_MON_ENABLE					0x80
#define PALMAS_VBAT_MON_ENABLE_SHIFT				0x07
#define PALMAS_VBAT_MON_THRESHOLD_MASK				0x3F
#define PALMAS_VBAT_MON_THRESHOLD_SHIFT				0x00

/* Bit definitions for WATCHDOG */
#define PALMAS_WATCHDOG_LOCK					0x20
#define PALMAS_WATCHDOG_LOCK_SHIFT				0x05
#define PALMAS_WATCHDOG_ENABLE					0x10
#define PALMAS_WATCHDOG_ENABLE_SHIFT				0x04
#define PALMAS_WATCHDOG_MODE					0x08
#define PALMAS_WATCHDOG_MODE_SHIFT				0x03
#define PALMAS_WATCHDOG_TIMER_MASK				0x07
#define PALMAS_WATCHDOG_TIMER_SHIFT				0x00

/* Bit definitions for BOOT_STATUS */
#define PALMAS_BOOT_STATUS_BOOT1				0x02
#define PALMAS_BOOT_STATUS_BOOT1_SHIFT				0x01
#define PALMAS_BOOT_STATUS_BOOT0				0x01
#define PALMAS_BOOT_STATUS_BOOT0_SHIFT				0x00

/* Bit definitions for BATTERY_BOUNCE */
#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK			0x3F
#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT			0x00

/* Bit definitions for BACKUP_BATTERY_CTRL */
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15			0x80
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT		0x07
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP			0x40
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT		0x06
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF			0x20
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT		0x05
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN			0x10
#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT		0x04
#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG		0x08
#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT	0x03
#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK			0x06
#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT			0x01
#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN			0x01
#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT		0x00

/* Bit definitions for LONG_PRESS_KEY */
#define PALMAS_LONG_PRESS_KEY_LPK_LOCK				0x80
#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT			0x07
#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR			0x10
#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT			0x04
#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK			0x0c
#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT			0x02
#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK		0x03
#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT		0x00

/* Bit definitions for OSC_THERM_CTRL */
#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP			0x80
#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT		0x07
#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP			0x40
#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT		0x06
#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP		0x20
#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT		0x05
#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP		0x10
#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT		0x04
#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK			0x0c
#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT		0x02
#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS			0x02
#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT			0x01
#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE			0x01
#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT			0x00

/* Bit definitions for BATDEBOUNCING */
#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS			0x80
#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT		0x07
#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK			0x78
#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT			0x03
#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK			0x07
#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT			0x00

/* Bit definitions for SWOFF_HWRST */
#define PALMAS_SWOFF_HWRST_PWRON_LPK				0x80
#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT			0x07
#define PALMAS_SWOFF_HWRST_PWRDOWN				0x40
#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT			0x06
#define PALMAS_SWOFF_HWRST_WTD					0x20
#define PALMAS_SWOFF_HWRST_WTD_SHIFT				0x05
#define PALMAS_SWOFF_HWRST_TSHUT				0x10
#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT				0x04
#define PALMAS_SWOFF_HWRST_RESET_IN				0x08
#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT			0x03
#define PALMAS_SWOFF_HWRST_SW_RST				0x04
#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT				0x02
#define PALMAS_SWOFF_HWRST_VSYS_LO				0x02
#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT			0x01
#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN			0x01
#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT			0x00

/* Bit definitions for SWOFF_COLDRST */
#define PALMAS_SWOFF_COLDRST_PWRON_LPK				0x80
#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT			0x07
#define PALMAS_SWOFF_COLDRST_PWRDOWN				0x40
#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT			0x06
#define PALMAS_SWOFF_COLDRST_WTD				0x20
#define PALMAS_SWOFF_COLDRST_WTD_SHIFT				0x05
#define PALMAS_SWOFF_COLDRST_TSHUT				0x10
#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT			0x04
#define PALMAS_SWOFF_COLDRST_RESET_IN				0x08
#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT			0x03
#define PALMAS_SWOFF_COLDRST_SW_RST				0x04
#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT			0x02
#define PALMAS_SWOFF_COLDRST_VSYS_LO				0x02
#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT			0x01
#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN			0x01
#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT		0x00

/* Bit definitions for SWOFF_STATUS */
#define PALMAS_SWOFF_STATUS_PWRON_LPK				0x80
#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT			0x07
#define PALMAS_SWOFF_STATUS_PWRDOWN				0x40
#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT			0x06
#define PALMAS_SWOFF_STATUS_WTD					0x20
#define PALMAS_SWOFF_STATUS_WTD_SHIFT				0x05
#define PALMAS_SWOFF_STATUS_TSHUT				0x10
#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT				0x04
#define PALMAS_SWOFF_STATUS_RESET_IN				0x08
#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT			0x03
#define PALMAS_SWOFF_STATUS_SW_RST				0x04
#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT			0x02
#define PALMAS_SWOFF_STATUS_VSYS_LO				0x02
#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT			0x01
#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN			0x01
#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT		0x00

/* Bit definitions for PMU_CONFIG */
#define PALMAS_PMU_CONFIG_MULTI_CELL_EN				0x40
#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT			0x06
#define PALMAS_PMU_CONFIG_SPARE_MASK				0x30
#define PALMAS_PMU_CONFIG_SPARE_SHIFT				0x04
#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK			0x0c
#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT			0x02
#define PALMAS_PMU_CONFIG_GATE_RESET_OUT			0x02
#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT			0x01
#define PALMAS_PMU_CONFIG_AUTODEVON				0x01
#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT			0x00

/* Bit definitions for SPARE */
#define PALMAS_SPARE_SPARE_MASK					0xf8
#define PALMAS_SPARE_SPARE_SHIFT				0x03
#define PALMAS_SPARE_REGEN3_OD					0x04
#define PALMAS_SPARE_REGEN3_OD_SHIFT				0x02
#define PALMAS_SPARE_REGEN2_OD					0x02
#define PALMAS_SPARE_REGEN2_OD_SHIFT				0x01
#define PALMAS_SPARE_REGEN1_OD					0x01
#define PALMAS_SPARE_REGEN1_OD_SHIFT				0x00

/* Bit definitions for PMU_SECONDARY_INT */
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC		0x80
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT		0x07
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC		0x40
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT	0x06
#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC			0x20
#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT		0x05
#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC			0x10
#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT		0x04
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK			0x08
#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT		0x03
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK		0x04
#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT		0x02
#define PALMAS_PMU_SECONDARY_INT_BB_MASK			0x02
#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT			0x01
#define PALMAS_PMU_SECONDARY_INT_FBI_MASK			0x01
#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT			0x00

/* Bit definitions for SW_REVISION */
#define PALMAS_SW_REVISION_SW_REVISION_MASK			0xFF
#define PALMAS_SW_REVISION_SW_REVISION_SHIFT			0x00

/* Bit definitions for EXT_CHRG_CTRL */
#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS			0x80
#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT		0x07
#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS			0x40
#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT		0x06
#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY		0x08
#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT		0x03
#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N				0x04
#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT			0x02
#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN			0x02
#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT			0x01
#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN			0x01
#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT		0x00

/* Bit definitions for PMU_SECONDARY_INT2 */
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC			0x20
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT		0x05
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC			0x10
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT		0x04
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK			0x02
#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT		0x01
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK			0x01
#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT		0x00

/* Registers for function RESOURCE */
#define PALMAS_CLK32KG_CTRL					0x00
#define PALMAS_CLK32KGAUDIO_CTRL				0x01
#define PALMAS_REGEN1_CTRL					0x02
#define PALMAS_REGEN2_CTRL					0x03
#define PALMAS_SYSEN1_CTRL					0x04
#define PALMAS_SYSEN2_CTRL					0x05
#define PALMAS_NSLEEP_RES_ASSIGN				0x06
#define PALMAS_NSLEEP_SMPS_ASSIGN				0x07
#define PALMAS_NSLEEP_LDO_ASSIGN1				0x08
#define PALMAS_NSLEEP_LDO_ASSIGN2				0x09
#define PALMAS_ENABLE1_RES_ASSIGN				0x0A
#define PALMAS_ENABLE1_SMPS_ASSIGN				0x0B
#define PALMAS_ENABLE1_LDO_ASSIGN1				0x0C
#define PALMAS_ENABLE1_LDO_ASSIGN2				0x0D
#define PALMAS_ENABLE2_RES_ASSIGN				0x0E
#define PALMAS_ENABLE2_SMPS_ASSIGN				0x0F
#define PALMAS_ENABLE2_LDO_ASSIGN1				0x10
#define PALMAS_ENABLE2_LDO_ASSIGN2				0x11
#define PALMAS_REGEN3_CTRL					0x12

/* Bit definitions for CLK32KG_CTRL */
#define PALMAS_CLK32KG_CTRL_STATUS				0x10
#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT			0x04
#define PALMAS_CLK32KG_CTRL_MODE_SLEEP				0x04
#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE				0x01
#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for CLK32KGAUDIO_CTRL */
#define PALMAS_CLK32KGAUDIO_CTRL_STATUS				0x10
#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT			0x04
#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3			0x08
#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT		0x03
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP			0x04
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT		0x02
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE			0x01
#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT		0x00

/* Bit definitions for REGEN1_CTRL */
#define PALMAS_REGEN1_CTRL_STATUS				0x10
#define PALMAS_REGEN1_CTRL_STATUS_SHIFT				0x04
#define PALMAS_REGEN1_CTRL_MODE_SLEEP				0x04
#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_REGEN1_CTRL_MODE_ACTIVE				0x01
#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for REGEN2_CTRL */
#define PALMAS_REGEN2_CTRL_STATUS				0x10
#define PALMAS_REGEN2_CTRL_STATUS_SHIFT				0x04
#define PALMAS_REGEN2_CTRL_MODE_SLEEP				0x04
#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_REGEN2_CTRL_MODE_ACTIVE				0x01
#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SYSEN1_CTRL */
#define PALMAS_SYSEN1_CTRL_STATUS				0x10
#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SYSEN1_CTRL_MODE_SLEEP				0x04
#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE				0x01
#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SYSEN2_CTRL */
#define PALMAS_SYSEN2_CTRL_STATUS				0x10
#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT				0x04
#define PALMAS_SYSEN2_CTRL_MODE_SLEEP				0x04
#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE				0x01
#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for NSLEEP_RES_ASSIGN */
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3				0x40
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT			0x06
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO			0x20
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT		0x05
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG			0x10
#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT			0x04
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2				0x08
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT			0x03
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1				0x04
#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT			0x02
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2				0x02
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT			0x01
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1				0x01
#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT			0x00

/* Bit definitions for NSLEEP_SMPS_ASSIGN */
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10			0x80
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT			0x07
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9				0x40
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT			0x06
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8				0x20
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT			0x05
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7				0x10
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT			0x04
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6				0x08
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT			0x03
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45			0x04
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT			0x02
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3				0x02
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT			0x01
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12			0x01
#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT			0x00

/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8				0x80
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT			0x07
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7				0x40
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT			0x06
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6				0x20
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT			0x05
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5				0x10
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT			0x04
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4				0x08
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT			0x03
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3				0x04
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT			0x02
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2				0x02
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT			0x01
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1				0x01
#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT			0x00

/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB			0x04
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT			0x02
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN				0x02
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT			0x01
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9				0x01
#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT			0x00

/* Bit definitions for ENABLE1_RES_ASSIGN */
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3			0x40
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT			0x06
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO			0x20
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT		0x05
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG			0x10
#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT			0x04
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2			0x08
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT			0x03
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1			0x04
#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT			0x02
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2			0x02
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT			0x01
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1			0x01
#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT			0x00

/* Bit definitions for ENABLE1_SMPS_ASSIGN */
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10			0x80
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT			0x07
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9			0x40
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT			0x06
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8			0x20
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT			0x05
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7			0x10
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT			0x04
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6			0x08
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT			0x03
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45			0x04
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT			0x02
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3			0x02
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT			0x01
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12			0x01
#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT			0x00

/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8				0x80
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT			0x07
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7				0x40
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT			0x06
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6				0x20
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT			0x05
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5				0x10
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT			0x04
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4				0x08
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT			0x03
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3				0x04
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT			0x02
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2				0x02
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT			0x01
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1				0x01
#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT			0x00

/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB			0x04
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT			0x02
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN			0x02
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT			0x01
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9				0x01
#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT			0x00

/* Bit definitions for ENABLE2_RES_ASSIGN */
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3			0x40
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT			0x06
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO			0x20
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT		0x05
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG			0x10
#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT			0x04
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2			0x08
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT			0x03
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1			0x04
#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT			0x02
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2			0x02
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT			0x01
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1			0x01
#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT			0x00

/* Bit definitions for ENABLE2_SMPS_ASSIGN */
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10			0x80
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT			0x07
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9			0x40
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT			0x06
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8			0x20
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT			0x05
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7			0x10
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT			0x04
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6			0x08
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT			0x03
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45			0x04
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT			0x02
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3			0x02
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT			0x01
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12			0x01
#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT			0x00

/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8				0x80
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT			0x07
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7				0x40
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT			0x06
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6				0x20
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT			0x05
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5				0x10
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT			0x04
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4				0x08
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT			0x03
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3				0x04
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT			0x02
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2				0x02
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT			0x01
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1				0x01
#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT			0x00

/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB			0x04
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT			0x02
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN			0x02
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT			0x01
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9				0x01
#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT			0x00

/* Bit definitions for REGEN3_CTRL */
#define PALMAS_REGEN3_CTRL_STATUS				0x10
#define PALMAS_REGEN3_CTRL_STATUS_SHIFT				0x04
#define PALMAS_REGEN3_CTRL_MODE_SLEEP				0x04
#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT			0x02
#define PALMAS_REGEN3_CTRL_MODE_ACTIVE				0x01
#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Registers for function PAD_CONTROL */
#define PALMAS_OD_OUTPUT_CTRL2					0x02
#define PALMAS_POLARITY_CTRL2					0x03
#define PALMAS_PU_PD_INPUT_CTRL1				0x04
#define PALMAS_PU_PD_INPUT_CTRL2				0x05
#define PALMAS_PU_PD_INPUT_CTRL3				0x06
#define PALMAS_PU_PD_INPUT_CTRL5				0x07
#define PALMAS_OD_OUTPUT_CTRL					0x08
#define PALMAS_POLARITY_CTRL					0x09
#define PALMAS_PRIMARY_SECONDARY_PAD1				0x0A
#define PALMAS_PRIMARY_SECONDARY_PAD2				0x0B
#define PALMAS_I2C_SPI						0x0C
#define PALMAS_PU_PD_INPUT_CTRL4				0x0D
#define PALMAS_PRIMARY_SECONDARY_PAD3				0x0E
#define PALMAS_PRIMARY_SECONDARY_PAD4				0x0F

/* Bit definitions for PU_PD_INPUT_CTRL1 */
#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD			0x40
#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT		0x06
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU			0x20
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT		0x05
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD			0x10
#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT		0x04
#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD			0x04
#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT		0x02
#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU			0x02
#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT		0x01

/* Bit definitions for PU_PD_INPUT_CTRL2 */
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU			0x20
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT		0x05
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD			0x10
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT		0x04
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU			0x08
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT		0x03
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD			0x04
#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT		0x02
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU			0x02
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT		0x01
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD			0x01
#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT		0x00

/* Bit definitions for PU_PD_INPUT_CTRL3 */
#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD			0x40
#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT			0x06
#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD			0x10
#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT		0x04
#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD			0x04
#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT		0x02
#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD			0x01
#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT		0x00

/* Bit definitions for OD_OUTPUT_CTRL */
#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD				0x80
#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT			0x07
#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD			0x40
#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT			0x06
#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD				0x20
#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT			0x05
#define PALMAS_OD_OUTPUT_CTRL_INT_OD				0x08
#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT			0x03

/* Bit definitions for POLARITY_CTRL */
#define PALMAS_POLARITY_CTRL_INT_POLARITY			0x80
#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT			0x07
#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY			0x40
#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT		0x06
#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY			0x20
#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT		0x05
#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY			0x10
#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT		0x04
#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY			0x08
#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT		0x03
#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY		0x04
#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT	0x02
#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY	0x02
#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT	0x01
#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY			0x01
#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT		0x00

/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3			0x80
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT		0x07
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK		0x60
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT		0x05
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK		0x18
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT		0x03
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0			0x04
#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT		0x02
#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC			0x02
#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT			0x01
#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD			0x01
#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT		0x00

/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK		0x30
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT		0x04
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6			0x08
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT		0x03
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK		0x06
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT		0x01
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4			0x01
#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT		0x00

/* Bit definitions for I2C_SPI */
#define PALMAS_I2C_SPI_I2C2OTP_EN				0x80
#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT				0x07
#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL				0x40
#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT			0x06
#define PALMAS_I2C_SPI_ID_I2C2					0x20
#define PALMAS_I2C_SPI_ID_I2C2_SHIFT				0x05
#define PALMAS_I2C_SPI_I2C_SPI					0x10
#define PALMAS_I2C_SPI_I2C_SPI_SHIFT				0x04
#define PALMAS_I2C_SPI_ID_I2C1_MASK				0x0F
#define PALMAS_I2C_SPI_ID_I2C1_SHIFT				0x00

/* Bit definitions for PU_PD_INPUT_CTRL4 */
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD			0x40
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT		0x06
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD			0x10
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT		0x04
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD			0x04
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT		0x02
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD			0x01
#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT		0x00

/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2			0x02
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT		0x01
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1			0x01
#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT		0x00

/* Registers for function LED_PWM */
#define PALMAS_LED_PERIOD_CTRL					0x00
#define PALMAS_LED_CTRL						0x01
#define PALMAS_PWM_CTRL1					0x02
#define PALMAS_PWM_CTRL2					0x03

/* Bit definitions for LED_PERIOD_CTRL */
#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK		0x38
#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT		0x03
#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK		0x07
#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT		0x00

/* Bit definitions for LED_CTRL */
#define PALMAS_LED_CTRL_LED_2_SEQ				0x20
#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT				0x05
#define PALMAS_LED_CTRL_LED_1_SEQ				0x10
#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT				0x04
#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK			0x0c
#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT			0x02
#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK			0x03
#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT			0x00

/* Bit definitions for PWM_CTRL1 */
#define PALMAS_PWM_CTRL1_PWM_FREQ_EN				0x02
#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT			0x01
#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL				0x01
#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT			0x00

/* Bit definitions for PWM_CTRL2 */
#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK			0xFF
#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT			0x00

/* Registers for function INTERRUPT */
#define PALMAS_INT1_STATUS					0x00
#define PALMAS_INT1_MASK					0x01
#define PALMAS_INT1_LINE_STATE					0x02
#define PALMAS_INT1_EDGE_DETECT1_RESERVED			0x03
#define PALMAS_INT1_EDGE_DETECT2_RESERVED			0x04
#define PALMAS_INT2_STATUS					0x05
#define PALMAS_INT2_MASK					0x06
#define PALMAS_INT2_LINE_STATE					0x07
#define PALMAS_INT2_EDGE_DETECT1_RESERVED			0x08
#define PALMAS_INT2_EDGE_DETECT2_RESERVED			0x09
#define PALMAS_INT3_STATUS					0x0A
#define PALMAS_INT3_MASK					0x0B
#define PALMAS_INT3_LINE_STATE					0x0C
#define PALMAS_INT3_EDGE_DETECT1_RESERVED			0x0D
#define PALMAS_INT3_EDGE_DETECT2_RESERVED			0x0E
#define PALMAS_INT4_STATUS					0x0F
#define PALMAS_INT4_MASK					0x10
#define PALMAS_INT4_LINE_STATE					0x11
#define PALMAS_INT4_EDGE_DETECT1				0x12
#define PALMAS_INT4_EDGE_DETECT2				0x13
#define PALMAS_INT_CTRL						0x14

/* Bit definitions for INT1_STATUS */
#define PALMAS_INT1_STATUS_VBAT_MON				0x80
#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT			0x07
#define PALMAS_INT1_STATUS_VSYS_MON				0x40
#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT			0x06
#define PALMAS_INT1_STATUS_HOTDIE				0x20
#define PALMAS_INT1_STATUS_HOTDIE_SHIFT				0x05
#define PALMAS_INT1_STATUS_PWRDOWN				0x10
#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT			0x04
#define PALMAS_INT1_STATUS_RPWRON				0x08
#define PALMAS_INT1_STATUS_RPWRON_SHIFT				0x03
#define PALMAS_INT1_STATUS_LONG_PRESS_KEY			0x04
#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT			0x02
#define PALMAS_INT1_STATUS_PWRON				0x02
#define PALMAS_INT1_STATUS_PWRON_SHIFT				0x01
#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV			0x01
#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT		0x00

/* Bit definitions for INT1_MASK */
#define PALMAS_INT1_MASK_VBAT_MON				0x80
#define PALMAS_INT1_MASK_VBAT_MON_SHIFT				0x07
#define PALMAS_INT1_MASK_VSYS_MON				0x40
#define PALMAS_INT1_MASK_VSYS_MON_SHIFT				0x06
#define PALMAS_INT1_MASK_HOTDIE					0x20
#define PALMAS_INT1_MASK_HOTDIE_SHIFT				0x05
#define PALMAS_INT1_MASK_PWRDOWN				0x10
#define PALMAS_INT1_MASK_PWRDOWN_SHIFT				0x04
#define PALMAS_INT1_MASK_RPWRON					0x08
#define PALMAS_INT1_MASK_RPWRON_SHIFT				0x03
#define PALMAS_INT1_MASK_LONG_PRESS_KEY				0x04
#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT			0x02
#define PALMAS_INT1_MASK_PWRON					0x02
#define PALMAS_INT1_MASK_PWRON_SHIFT				0x01
#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV			0x01
#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT		0x00

/* Bit definitions for INT1_LINE_STATE */
#define PALMAS_INT1_LINE_STATE_VBAT_MON				0x80
#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT			0x07
#define PALMAS_INT1_LINE_STATE_VSYS_MON				0x40
#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT			0x06
#define PALMAS_INT1_LINE_STATE_HOTDIE				0x20
#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT			0x05
#define PALMAS_INT1_LINE_STATE_PWRDOWN				0x10
#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT			0x04
#define PALMAS_INT1_LINE_STATE_RPWRON				0x08
#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT			0x03
#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY			0x04
#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT		0x02
#define PALMAS_INT1_LINE_STATE_PWRON				0x02
#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT			0x01
#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV		0x01
#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT	0x00

/* Bit definitions for INT2_STATUS */
#define PALMAS_INT2_STATUS_VAC_ACOK				0x80
#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT			0x07
#define PALMAS_INT2_STATUS_SHORT				0x40
#define PALMAS_INT2_STATUS_SHORT_SHIFT				0x06
#define PALMAS_INT2_STATUS_FBI_BB				0x20
#define PALMAS_INT2_STATUS_FBI_BB_SHIFT				0x05
#define PALMAS_INT2_STATUS_RESET_IN				0x10
#define PALMAS_INT2_STATUS_RESET_IN_SHIFT			0x04
#define PALMAS_INT2_STATUS_BATREMOVAL				0x08
#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT			0x03
#define PALMAS_INT2_STATUS_WDT					0x04
#define PALMAS_INT2_STATUS_WDT_SHIFT				0x02
#define PALMAS_INT2_STATUS_RTC_TIMER				0x02
#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT			0x01
#define PALMAS_INT2_STATUS_RTC_ALARM				0x01
#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT			0x00

/* Bit definitions for INT2_MASK */
#define PALMAS_INT2_MASK_VAC_ACOK				0x80
#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT				0x07
#define PALMAS_INT2_MASK_SHORT					0x40
#define PALMAS_INT2_MASK_SHORT_SHIFT				0x06
#define PALMAS_INT2_MASK_FBI_BB					0x20
#define PALMAS_INT2_MASK_FBI_BB_SHIFT				0x05
#define PALMAS_INT2_MASK_RESET_IN				0x10
#define PALMAS_INT2_MASK_RESET_IN_SHIFT				0x04
#define PALMAS_INT2_MASK_BATREMOVAL				0x08
#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT			0x03
#define PALMAS_INT2_MASK_WDT					0x04
#define PALMAS_INT2_MASK_WDT_SHIFT				0x02
#define PALMAS_INT2_MASK_RTC_TIMER				0x02
#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT			0x01
#define PALMAS_INT2_MASK_RTC_ALARM				0x01
#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT			0x00

/* Bit definitions for INT2_LINE_STATE */
#define PALMAS_INT2_LINE_STATE_VAC_ACOK				0x80
#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT			0x07
#define PALMAS_INT2_LINE_STATE_SHORT				0x40
#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT			0x06
#define PALMAS_INT2_LINE_STATE_FBI_BB				0x20
#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT			0x05
#define PALMAS_INT2_LINE_STATE_RESET_IN				0x10
#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT			0x04
#define PALMAS_INT2_LINE_STATE_BATREMOVAL			0x08
#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT			0x03
#define PALMAS_INT2_LINE_STATE_WDT				0x04
#define PALMAS_INT2_LINE_STATE_WDT_SHIFT			0x02
#define PALMAS_INT2_LINE_STATE_RTC_TIMER			0x02
#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT			0x01
#define PALMAS_INT2_LINE_STATE_RTC_ALARM			0x01
#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT			0x00

/* Bit definitions for INT3_STATUS */
#define PALMAS_INT3_STATUS_VBUS					0x80
#define PALMAS_INT3_STATUS_VBUS_SHIFT				0x07
#define PALMAS_INT3_STATUS_VBUS_OTG				0x40
#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT			0x06
#define PALMAS_INT3_STATUS_ID					0x20
#define PALMAS_INT3_STATUS_ID_SHIFT				0x05
#define PALMAS_INT3_STATUS_ID_OTG				0x10
#define PALMAS_INT3_STATUS_ID_OTG_SHIFT				0x04
#define PALMAS_INT3_STATUS_GPADC_EOC_RT				0x08
#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT			0x03
#define PALMAS_INT3_STATUS_GPADC_EOC_SW				0x04
#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT			0x02
#define PALMAS_INT3_STATUS_GPADC_AUTO_1				0x02
#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT			0x01
#define PALMAS_INT3_STATUS_GPADC_AUTO_0				0x01
#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT			0x00

/* Bit definitions for INT3_MASK */
#define PALMAS_INT3_MASK_VBUS					0x80
#define PALMAS_INT3_MASK_VBUS_SHIFT				0x07
#define PALMAS_INT3_MASK_VBUS_OTG				0x40
#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT				0x06
#define PALMAS_INT3_MASK_ID					0x20
#define PALMAS_INT3_MASK_ID_SHIFT				0x05
#define PALMAS_INT3_MASK_ID_OTG					0x10
#define PALMAS_INT3_MASK_ID_OTG_SHIFT				0x04
#define PALMAS_INT3_MASK_GPADC_EOC_RT				0x08
#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT			0x03
#define PALMAS_INT3_MASK_GPADC_EOC_SW				0x04
#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT			0x02
#define PALMAS_INT3_MASK_GPADC_AUTO_1				0x02
#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT			0x01
#define PALMAS_INT3_MASK_GPADC_AUTO_0				0x01
#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT			0x00

/* Bit definitions for INT3_LINE_STATE */
#define PALMAS_INT3_LINE_STATE_VBUS				0x80
#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT			0x07
#define PALMAS_INT3_LINE_STATE_VBUS_OTG				0x40
#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT			0x06
#define PALMAS_INT3_LINE_STATE_ID				0x20
#define PALMAS_INT3_LINE_STATE_ID_SHIFT				0x05
#define PALMAS_INT3_LINE_STATE_ID_OTG				0x10
#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT			0x04
#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT			0x08
#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT		0x03
#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW			0x04
#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT		0x02
#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1			0x02
#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT		0x01
#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0			0x01
#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT		0x00

/* Bit definitions for INT4_STATUS */
#define PALMAS_INT4_STATUS_GPIO_7				0x80
#define PALMAS_INT4_STATUS_GPIO_7_SHIFT				0x07
#define PALMAS_INT4_STATUS_GPIO_6				0x40
#define PALMAS_INT4_STATUS_GPIO_6_SHIFT				0x06
#define PALMAS_INT4_STATUS_GPIO_5				0x20
#define PALMAS_INT4_STATUS_GPIO_5_SHIFT				0x05
#define PALMAS_INT4_STATUS_GPIO_4				0x10
#define PALMAS_INT4_STATUS_GPIO_4_SHIFT				0x04
#define PALMAS_INT4_STATUS_GPIO_3				0x08
#define PALMAS_INT4_STATUS_GPIO_3_SHIFT				0x03
#define PALMAS_INT4_STATUS_GPIO_2				0x04
#define PALMAS_INT4_STATUS_GPIO_2_SHIFT				0x02
#define PALMAS_INT4_STATUS_GPIO_1				0x02
#define PALMAS_INT4_STATUS_GPIO_1_SHIFT				0x01
#define PALMAS_INT4_STATUS_GPIO_0				0x01
#define PALMAS_INT4_STATUS_GPIO_0_SHIFT				0x00

/* Bit definitions for INT4_MASK */
#define PALMAS_INT4_MASK_GPIO_7					0x80
#define PALMAS_INT4_MASK_GPIO_7_SHIFT				0x07
#define PALMAS_INT4_MASK_GPIO_6					0x40
#define PALMAS_INT4_MASK_GPIO_6_SHIFT				0x06
#define PALMAS_INT4_MASK_GPIO_5					0x20
#define PALMAS_INT4_MASK_GPIO_5_SHIFT				0x05
#define PALMAS_INT4_MASK_GPIO_4					0x10
#define PALMAS_INT4_MASK_GPIO_4_SHIFT				0x04
#define PALMAS_INT4_MASK_GPIO_3					0x08
#define PALMAS_INT4_MASK_GPIO_3_SHIFT				0x03
#define PALMAS_INT4_MASK_GPIO_2					0x04
#define PALMAS_INT4_MASK_GPIO_2_SHIFT				0x02
#define PALMAS_INT4_MASK_GPIO_1					0x02
#define PALMAS_INT4_MASK_GPIO_1_SHIFT				0x01
#define PALMAS_INT4_MASK_GPIO_0					0x01
#define PALMAS_INT4_MASK_GPIO_0_SHIFT				0x00

/* Bit definitions for INT4_LINE_STATE */
#define PALMAS_INT4_LINE_STATE_GPIO_7				0x80
#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT			0x07
#define PALMAS_INT4_LINE_STATE_GPIO_6				0x40
#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT			0x06
#define PALMAS_INT4_LINE_STATE_GPIO_5				0x20
#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT			0x05
#define PALMAS_INT4_LINE_STATE_GPIO_4				0x10
#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT			0x04
#define PALMAS_INT4_LINE_STATE_GPIO_3				0x08
#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT			0x03
#define PALMAS_INT4_LINE_STATE_GPIO_2				0x04
#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT			0x02
#define PALMAS_INT4_LINE_STATE_GPIO_1				0x02
#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT			0x01
#define PALMAS_INT4_LINE_STATE_GPIO_0				0x01
#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT			0x00

/* Bit definitions for INT4_EDGE_DETECT1 */
#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING			0x80
#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT		0x07
#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING			0x40
#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT		0x06
#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING			0x20
#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT		0x05
#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING			0x10
#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT		0x04
#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING			0x08
#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT		0x03
#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING			0x04
#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT		0x02
#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING			0x02
#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT		0x01
#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING			0x01
#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT		0x00

/* Bit definitions for INT4_EDGE_DETECT2 */
#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING			0x80
#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT		0x07
#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING			0x40
#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT		0x06
#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING			0x20
#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT		0x05
#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING			0x10
#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT		0x04
#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING			0x08
#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT		0x03
#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING			0x04
#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT		0x02
#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING			0x02
#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT		0x01
#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING			0x01
#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT		0x00

/* Bit definitions for INT_CTRL */
#define PALMAS_INT_CTRL_INT_PENDING				0x04
#define PALMAS_INT_CTRL_INT_PENDING_SHIFT			0x02
#define PALMAS_INT_CTRL_INT_CLEAR				0x01
#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT				0x00

/* Registers for function USB_OTG */
#define PALMAS_USB_WAKEUP					0x03
#define PALMAS_USB_VBUS_CTRL_SET				0x04
#define PALMAS_USB_VBUS_CTRL_CLR				0x05
#define PALMAS_USB_ID_CTRL_SET					0x06
#define PALMAS_USB_ID_CTRL_CLEAR				0x07
#define PALMAS_USB_VBUS_INT_SRC					0x08
#define PALMAS_USB_VBUS_INT_LATCH_SET				0x09
#define PALMAS_USB_VBUS_INT_LATCH_CLR				0x0A
#define PALMAS_USB_VBUS_INT_EN_LO_SET				0x0B
#define PALMAS_USB_VBUS_INT_EN_LO_CLR				0x0C
#define PALMAS_USB_VBUS_INT_EN_HI_SET				0x0D
#define PALMAS_USB_VBUS_INT_EN_HI_CLR				0x0E
#define PALMAS_USB_ID_INT_SRC					0x0F
#define PALMAS_USB_ID_INT_LATCH_SET				0x10
#define PALMAS_USB_ID_INT_LATCH_CLR				0x11
#define PALMAS_USB_ID_INT_EN_LO_SET				0x12
#define PALMAS_USB_ID_INT_EN_LO_CLR				0x13
#define PALMAS_USB_ID_INT_EN_HI_SET				0x14
#define PALMAS_USB_ID_INT_EN_HI_CLR				0x15
#define PALMAS_USB_OTG_ADP_CTRL					0x16
#define PALMAS_USB_OTG_ADP_HIGH					0x17
#define PALMAS_USB_OTG_ADP_LOW					0x18
#define PALMAS_USB_OTG_ADP_RISE					0x19
#define PALMAS_USB_OTG_REVISION					0x1A

/* Bit definitions for USB_WAKEUP */
#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP				0x01
#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT			0x00

/* Bit definitions for USB_VBUS_CTRL_SET */
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS			0x80
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT		0x07
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG			0x20
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT		0x05
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC			0x10
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT		0x04
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK			0x08
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT		0x03
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP			0x04
#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT		0x02

/* Bit definitions for USB_VBUS_CTRL_CLR */
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS			0x80
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT		0x07
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG			0x20
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT		0x05
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC			0x10
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT		0x04
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK			0x08
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT		0x03
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP			0x04
#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT		0x02

/* Bit definitions for USB_ID_CTRL_SET */
#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K			0x80
#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT			0x07
#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K			0x40
#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT			0x06
#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV			0x20
#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT			0x05
#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U			0x10
#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT			0x04
#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U			0x08
#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT			0x03
#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP			0x04
#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT		0x02

/* Bit definitions for USB_ID_CTRL_CLEAR */
#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K			0x80
#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT		0x07
#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K			0x40
#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT		0x06
#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV			0x20
#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT		0x05
#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U			0x10
#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT		0x04
#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U			0x08
#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT		0x03
#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP			0x04
#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT		0x02

/* Bit definitions for USB_VBUS_INT_SRC */
#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD			0x80
#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT		0x07
#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT			0x06
#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT			0x05
#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD			0x08
#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD			0x04
#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD			0x02
#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END			0x01
#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_LATCH_SET */
#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP			0x10
#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT			0x04
#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP			0x10
#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT			0x04
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP			0x10
#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT			0x04
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD		0x80
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT	0x07
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB			0x40
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT		0x06
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS			0x20
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT		0x05
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP			0x10
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT			0x04
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD		0x08
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT		0x03
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD		0x04
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT		0x02
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD		0x02
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT		0x01
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END		0x01
#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT		0x00

/* Bit definitions for USB_ID_INT_SRC */
#define PALMAS_USB_ID_INT_SRC_ID_FLOAT				0x10
#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT			0x04
#define PALMAS_USB_ID_INT_SRC_ID_A				0x08
#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_SRC_ID_B				0x04
#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_SRC_ID_C				0x02
#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_SRC_ID_GND				0x01
#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT			0x00

/* Bit definitions for USB_ID_INT_LATCH_SET */
#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_LATCH_SET_ID_A			0x08
#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_LATCH_SET_ID_B			0x04
#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_LATCH_SET_ID_C			0x02
#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND			0x01
#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT		0x00

/* Bit definitions for USB_ID_INT_LATCH_CLR */
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A			0x08
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B			0x04
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C			0x02
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND			0x01
#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT		0x00

/* Bit definitions for USB_ID_INT_EN_LO_SET */
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A			0x08
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B			0x04
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C			0x02
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND			0x01
#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT		0x00

/* Bit definitions for USB_ID_INT_EN_LO_CLR */
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A			0x08
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B			0x04
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C			0x02
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND			0x01
#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT		0x00

/* Bit definitions for USB_ID_INT_EN_HI_SET */
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A			0x08
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B			0x04
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C			0x02
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND			0x01
#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT		0x00

/* Bit definitions for USB_ID_INT_EN_HI_CLR */
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT			0x10
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT		0x04
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A			0x08
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT			0x03
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B			0x04
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT			0x02
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C			0x02
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT			0x01
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND			0x01
#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT		0x00

/* Bit definitions for USB_OTG_ADP_CTRL */
#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN				0x04
#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT			0x02
#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK			0x03
#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT			0x00

/* Bit definitions for USB_OTG_ADP_HIGH */
#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK			0xFF
#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT		0x00

/* Bit definitions for USB_OTG_ADP_LOW */
#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK			0xFF
#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT			0x00

/* Bit definitions for USB_OTG_ADP_RISE */
#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK			0xFF
#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT		0x00

/* Bit definitions for USB_OTG_REVISION */
#define PALMAS_USB_OTG_REVISION_OTG_REV				0x01
#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT			0x00

/* Registers for function VIBRATOR */
#define PALMAS_VIBRA_CTRL					0x00

/* Bit definitions for VIBRA_CTRL */
#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK			0x06
#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT			0x01
#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL				0x01
#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT			0x00

/* Registers for function GPIO */
#define PALMAS_GPIO_DATA_IN					0x00
#define PALMAS_GPIO_DATA_DIR					0x01
#define PALMAS_GPIO_DATA_OUT					0x02
#define PALMAS_GPIO_DEBOUNCE_EN					0x03
#define PALMAS_GPIO_CLEAR_DATA_OUT				0x04
#define PALMAS_GPIO_SET_DATA_OUT				0x05
#define PALMAS_PU_PD_GPIO_CTRL1					0x06
#define PALMAS_PU_PD_GPIO_CTRL2					0x07
#define PALMAS_OD_OUTPUT_GPIO_CTRL				0x08
#define PALMAS_GPIO_DATA_IN2					0x09
#define PALMAS_GPIO_DATA_DIR2					0x0A
#define PALMAS_GPIO_DATA_OUT2					0x0B
#define PALMAS_GPIO_DEBOUNCE_EN2				0x0C
#define PALMAS_GPIO_CLEAR_DATA_OUT2				0x0D
#define PALMAS_GPIO_SET_DATA_OUT2				0x0E
#define PALMAS_PU_PD_GPIO_CTRL3					0x0F
#define PALMAS_PU_PD_GPIO_CTRL4					0x10
#define PALMAS_OD_OUTPUT_GPIO_CTRL2				0x11

/* Bit definitions for GPIO_DATA_IN */
#define PALMAS_GPIO_DATA_IN_GPIO_7_IN				0x80
#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT			0x07
#define PALMAS_GPIO_DATA_IN_GPIO_6_IN				0x40
#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT			0x06
#define PALMAS_GPIO_DATA_IN_GPIO_5_IN				0x20
#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT			0x05
#define PALMAS_GPIO_DATA_IN_GPIO_4_IN				0x10
#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT			0x04
#define PALMAS_GPIO_DATA_IN_GPIO_3_IN				0x08
#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT			0x03
#define PALMAS_GPIO_DATA_IN_GPIO_2_IN				0x04
#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT			0x02
#define PALMAS_GPIO_DATA_IN_GPIO_1_IN				0x02
#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT			0x01
#define PALMAS_GPIO_DATA_IN_GPIO_0_IN				0x01
#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT			0x00

/* Bit definitions for GPIO_DATA_DIR */
#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR				0x80
#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT			0x07
#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR				0x40
#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT			0x06
#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR				0x20
#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT			0x05
#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR				0x10
#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT			0x04
#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR				0x08
#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT			0x03
#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR				0x04
#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT			0x02
#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR				0x02
#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT			0x01
#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR				0x01
#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT			0x00

/* Bit definitions for GPIO_DATA_OUT */
#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT				0x80
#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT			0x07
#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT				0x40
#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT			0x06
#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT				0x20
#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT			0x05
#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT				0x10
#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT			0x04
#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT				0x08
#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT			0x03
#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT				0x04
#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT			0x02
#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT				0x02
#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT			0x01
#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT				0x01
#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT			0x00

/* Bit definitions for GPIO_DEBOUNCE_EN */
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN		0x80
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT	0x07
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN		0x40
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT	0x06
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN		0x20
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT	0x05
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN		0x10
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT	0x04
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN		0x08
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT	0x03
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN		0x04
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT	0x02
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN		0x02
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT	0x01
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN		0x01
#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT	0x00

/* Bit definitions for GPIO_CLEAR_DATA_OUT */
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT	0x80
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT	0x07
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT	0x40
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT	0x06
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT	0x20
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT	0x05
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT	0x10
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT	0x04
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT	0x08
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT	0x03
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT	0x04
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT	0x02
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT	0x02
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT	0x01
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT	0x01
#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT	0x00

/* Bit definitions for GPIO_SET_DATA_OUT */
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT		0x80
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT	0x07
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT		0x40
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT	0x06
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT		0x20
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT	0x05
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT		0x10
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT	0x04
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT		0x08
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT	0x03
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT		0x04
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT	0x02
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT		0x02
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT	0x01
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT		0x01
#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT	0x00

/* Bit definitions for PU_PD_GPIO_CTRL1 */
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD			0x40
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT			0x06
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU			0x20
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT			0x05
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD			0x10
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT			0x04
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU			0x08
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT			0x03
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD			0x04
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT			0x02
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD			0x01
#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT			0x00

/* Bit definitions for PU_PD_GPIO_CTRL2 */
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD			0x40
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT			0x06
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU			0x20
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT			0x05
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD			0x10
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT			0x04
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU			0x08
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT			0x03
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD			0x04
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT			0x02
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU			0x02
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT			0x01
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD			0x01
#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT			0x00

/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD			0x20
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT		0x05
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD			0x04
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT		0x02
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD			0x02
#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT		0x01

/* Registers for function GPADC */
#define PALMAS_GPADC_CTRL1					0x00
#define PALMAS_GPADC_CTRL2					0x01
#define PALMAS_GPADC_RT_CTRL					0x02
#define PALMAS_GPADC_AUTO_CTRL					0x03
#define PALMAS_GPADC_STATUS					0x04
#define PALMAS_GPADC_RT_SELECT					0x05
#define PALMAS_GPADC_RT_CONV0_LSB				0x06
#define PALMAS_GPADC_RT_CONV0_MSB				0x07
#define PALMAS_GPADC_AUTO_SELECT				0x08
#define PALMAS_GPADC_AUTO_CONV0_LSB				0x09
#define PALMAS_GPADC_AUTO_CONV0_MSB				0x0A
#define PALMAS_GPADC_AUTO_CONV1_LSB				0x0B
#define PALMAS_GPADC_AUTO_CONV1_MSB				0x0C
#define PALMAS_GPADC_SW_SELECT					0x0D
#define PALMAS_GPADC_SW_CONV0_LSB				0x0E
#define PALMAS_GPADC_SW_CONV0_MSB				0x0F
#define PALMAS_GPADC_THRES_CONV0_LSB				0x10
#define PALMAS_GPADC_THRES_CONV0_MSB				0x11
#define PALMAS_GPADC_THRES_CONV1_LSB				0x12
#define PALMAS_GPADC_THRES_CONV1_MSB				0x13
#define PALMAS_GPADC_SMPS_ILMONITOR_EN				0x14
#define PALMAS_GPADC_SMPS_VSEL_MONITORING			0x15

/* Bit definitions for GPADC_CTRL1 */
#define PALMAS_GPADC_CTRL1_RESERVED_MASK			0xc0
#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT			0x06
#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK			0x30
#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT		0x04
#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK			0x0c
#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT		0x02
#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET			0x02
#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT		0x01
#define PALMAS_GPADC_CTRL1_GPADC_FORCE				0x01
#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT			0x00

/* Bit definitions for GPADC_CTRL2 */
#define PALMAS_GPADC_CTRL2_RESERVED_MASK			0x06
#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT			0x01

/* Bit definitions for GPADC_RT_CTRL */
#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY			0x02
#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT			0x01
#define PALMAS_GPADC_RT_CTRL_START_POLARITY			0x01
#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT		0x00

/* Bit definitions for GPADC_AUTO_CTRL */
#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1			0x80
#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT		0x07
#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0			0x40
#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT		0x06
#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN			0x20
#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT		0x05
#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN			0x10
#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT		0x04
#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK		0x0F
#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT		0x00

/* Bit definitions for GPADC_STATUS */
#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE			0x10
#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT		0x04

/* Bit definitions for GPADC_RT_SELECT */
#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN			0x80
#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT			0x07
#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK		0x0F
#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT		0x00

/* Bit definitions for GPADC_RT_CONV0_LSB */
#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK		0xFF
#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT		0x00

/* Bit definitions for GPADC_RT_CONV0_MSB */
#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK		0x0F
#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT		0x00

/* Bit definitions for GPADC_AUTO_SELECT */
#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK		0xF0
#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT		0x04
#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK		0x0F
#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT		0x00

/* Bit definitions for GPADC_AUTO_CONV0_LSB */
#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK		0xFF
#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT	0x00

/* Bit definitions for GPADC_AUTO_CONV0_MSB */
#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK		0x0F
#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT	0x00

/* Bit definitions for GPADC_AUTO_CONV1_LSB */
#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK		0xFF
#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT	0x00

/* Bit definitions for GPADC_AUTO_CONV1_MSB */
#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK		0x0F
#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT	0x00

/* Bit definitions for GPADC_SW_SELECT */
#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN			0x80
#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT			0x07
#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0			0x10
#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT		0x04
#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK		0x0F
#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT		0x00

/* Bit definitions for GPADC_SW_CONV0_LSB */
#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK		0xFF
#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT		0x00

/* Bit definitions for GPADC_SW_CONV0_MSB */
#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK		0x0F
#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT		0x00

/* Bit definitions for GPADC_THRES_CONV0_LSB */
#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK	0xFF
#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT	0x00

/* Bit definitions for GPADC_THRES_CONV0_MSB */
#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL		0x80
#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT	0x07
#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK	0x0F
#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT	0x00

/* Bit definitions for GPADC_THRES_CONV1_LSB */
#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK	0xFF
#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT	0x00

/* Bit definitions for GPADC_THRES_CONV1_MSB */
#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL		0x80
#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT	0x07
#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK	0x0F
#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT	0x00

/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN		0x20
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT	0x05
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT		0x10
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT	0x04
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK	0x0F
#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT	0x00

/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE		0x80
#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT	0x07
#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK	0x7F
#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT	0x00

/* Registers for function GPADC */
#define PALMAS_GPADC_TRIM1					0x00
#define PALMAS_GPADC_TRIM2					0x01
#define PALMAS_GPADC_TRIM3					0x02
#define PALMAS_GPADC_TRIM4					0x03
#define PALMAS_GPADC_TRIM5					0x04
#define PALMAS_GPADC_TRIM6					0x05
#define PALMAS_GPADC_TRIM7					0x06
#define PALMAS_GPADC_TRIM8					0x07
#define PALMAS_GPADC_TRIM9					0x08
#define PALMAS_GPADC_TRIM10					0x09
#define PALMAS_GPADC_TRIM11					0x0A
#define PALMAS_GPADC_TRIM12					0x0B
#define PALMAS_GPADC_TRIM13					0x0C
#define PALMAS_GPADC_TRIM14					0x0D
#define PALMAS_GPADC_TRIM15					0x0E
#define PALMAS_GPADC_TRIM16					0x0F

/* TPS659038 regen2_ctrl offset iss different from palmas */
#define TPS659038_REGEN2_CTRL					0x12

/* TPS65917 Interrupt registers */

/* Registers for function INTERRUPT */
#define TPS65917_INT1_STATUS					0x00
#define TPS65917_INT1_MASK					0x01
#define TPS65917_INT1_LINE_STATE				0x02
#define TPS65917_INT2_STATUS					0x05
#define TPS65917_INT2_MASK					0x06
#define TPS65917_INT2_LINE_STATE				0x07
#define TPS65917_INT3_STATUS					0x0A
#define TPS65917_INT3_MASK					0x0B
#define TPS65917_INT3_LINE_STATE				0x0C
#define TPS65917_INT4_STATUS					0x0F
#define TPS65917_INT4_MASK					0x10
#define TPS65917_INT4_LINE_STATE				0x11
#define TPS65917_INT4_EDGE_DETECT1				0x12
#define TPS65917_INT4_EDGE_DETECT2				0x13
#define TPS65917_INT_CTRL					0x14

/* Bit definitions for INT1_STATUS */
#define TPS65917_INT1_STATUS_VSYS_MON				0x40
#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT			0x06
#define TPS65917_INT1_STATUS_HOTDIE				0x20
#define TPS65917_INT1_STATUS_HOTDIE_SHIFT			0x05
#define TPS65917_INT1_STATUS_PWRDOWN				0x10
#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT			0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY			0x04
#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT		0x02
#define TPS65917_INT1_STATUS_PWRON				0x02
#define TPS65917_INT1_STATUS_PWRON_SHIFT			0x01

/* Bit definitions for INT1_MASK */
#define TPS65917_INT1_MASK_VSYS_MON				0x40
#define TPS65917_INT1_MASK_VSYS_MON_SHIFT			0x06
#define TPS65917_INT1_MASK_HOTDIE				0x20
#define TPS65917_INT1_MASK_HOTDIE_SHIFT			0x05
#define TPS65917_INT1_MASK_PWRDOWN				0x10
#define TPS65917_INT1_MASK_PWRDOWN_SHIFT			0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY			0x04
#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT		0x02
#define TPS65917_INT1_MASK_PWRON				0x02
#define TPS65917_INT1_MASK_PWRON_SHIFT				0x01

/* Bit definitions for INT1_LINE_STATE */
#define TPS65917_INT1_LINE_STATE_VSYS_MON			0x40
#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT		0x06
#define TPS65917_INT1_LINE_STATE_HOTDIE			0x20
#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT			0x05
#define TPS65917_INT1_LINE_STATE_PWRDOWN			0x10
#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT			0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY		0x04
#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT		0x02
#define TPS65917_INT1_LINE_STATE_PWRON				0x02
#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT			0x01

/* Bit definitions for INT2_STATUS */
#define TPS65917_INT2_STATUS_SHORT				0x40
#define TPS65917_INT2_STATUS_SHORT_SHIFT			0x06
#define TPS65917_INT2_STATUS_FSD				0x20
#define TPS65917_INT2_STATUS_FSD_SHIFT				0x05
#define TPS65917_INT2_STATUS_RESET_IN				0x10
#define TPS65917_INT2_STATUS_RESET_IN_SHIFT			0x04
#define TPS65917_INT2_STATUS_WDT				0x04
#define TPS65917_INT2_STATUS_WDT_SHIFT				0x02
#define TPS65917_INT2_STATUS_OTP_ERROR				0x02
#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT			0x01

/* Bit definitions for INT2_MASK */
#define TPS65917_INT2_MASK_SHORT				0x40
#define TPS65917_INT2_MASK_SHORT_SHIFT				0x06
#define TPS65917_INT2_MASK_FSD					0x20
#define TPS65917_INT2_MASK_FSD_SHIFT				0x05
#define TPS65917_INT2_MASK_RESET_IN				0x10
#define TPS65917_INT2_MASK_RESET_IN_SHIFT			0x04
#define TPS65917_INT2_MASK_WDT					0x04
#define TPS65917_INT2_MASK_WDT_SHIFT				0x02
#define TPS65917_INT2_MASK_OTP_ERROR_TIMER			0x02
#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT			0x01

/* Bit definitions for INT2_LINE_STATE */
#define TPS65917_INT2_LINE_STATE_SHORT				0x40
#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT			0x06
#define TPS65917_INT2_LINE_STATE_FSD				0x20
#define TPS65917_INT2_LINE_STATE_FSD_SHIFT			0x05
#define TPS65917_INT2_LINE_STATE_RESET_IN			0x10
#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT		0x04
#define TPS65917_INT2_LINE_STATE_WDT				0x04
#define TPS65917_INT2_LINE_STATE_WDT_SHIFT			0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR			0x02
#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT		0x01

/* Bit definitions for INT3_STATUS */
#define TPS65917_INT3_STATUS_VBUS				0x80
#define TPS65917_INT3_STATUS_VBUS_SHIFT			0x07
#define TPS65917_INT3_STATUS_GPADC_EOC_SW			0x04
#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT		0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1			0x02
#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT		0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0			0x01
#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT		0x00

/* Bit definitions for INT3_MASK */
#define TPS65917_INT3_MASK_VBUS				0x80
#define TPS65917_INT3_MASK_VBUS_SHIFT				0x07
#define TPS65917_INT3_MASK_GPADC_EOC_SW			0x04
#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT			0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1			0x02
#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT			0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0			0x01
#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT			0x00

/* Bit definitions for INT3_LINE_STATE */
#define TPS65917_INT3_LINE_STATE_VBUS				0x80
#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT			0x07
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW			0x04
#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT		0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1			0x02
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT		0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0			0x01
#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT		0x00

/* Bit definitions for INT4_STATUS */
#define TPS65917_INT4_STATUS_GPIO_6				0x40
#define TPS65917_INT4_STATUS_GPIO_6_SHIFT			0x06
#define TPS65917_INT4_STATUS_GPIO_5				0x20
#define TPS65917_INT4_STATUS_GPIO_5_SHIFT			0x05
#define TPS65917_INT4_STATUS_GPIO_4				0x10
#define TPS65917_INT4_STATUS_GPIO_4_SHIFT			0x04
#define TPS65917_INT4_STATUS_GPIO_3				0x08
#define TPS65917_INT4_STATUS_GPIO_3_SHIFT			0x03
#define TPS65917_INT4_STATUS_GPIO_2				0x04
#define TPS65917_INT4_STATUS_GPIO_2_SHIFT			0x02
#define TPS65917_INT4_STATUS_GPIO_1				0x02
#define TPS65917_INT4_STATUS_GPIO_1_SHIFT			0x01
#define TPS65917_INT4_STATUS_GPIO_0				0x01
#define TPS65917_INT4_STATUS_GPIO_0_SHIFT			0x00

/* Bit definitions for INT4_MASK */
#define TPS65917_INT4_MASK_GPIO_6				0x40
#define TPS65917_INT4_MASK_GPIO_6_SHIFT			0x06
#define TPS65917_INT4_MASK_GPIO_5				0x20
#define TPS65917_INT4_MASK_GPIO_5_SHIFT			0x05
#define TPS65917_INT4_MASK_GPIO_4				0x10
#define TPS65917_INT4_MASK_GPIO_4_SHIFT			0x04
#define TPS65917_INT4_MASK_GPIO_3				0x08
#define TPS65917_INT4_MASK_GPIO_3_SHIFT			0x03
#define TPS65917_INT4_MASK_GPIO_2				0x04
#define TPS65917_INT4_MASK_GPIO_2_SHIFT			0x02
#define TPS65917_INT4_MASK_GPIO_1				0x02
#define TPS65917_INT4_MASK_GPIO_1_SHIFT			0x01
#define TPS65917_INT4_MASK_GPIO_0				0x01
#define TPS65917_INT4_MASK_GPIO_0_SHIFT			0x00

/* Bit definitions for INT4_LINE_STATE */
#define TPS65917_INT4_LINE_STATE_GPIO_6			0x40
#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT			0x06
#define TPS65917_INT4_LINE_STATE_GPIO_5			0x20
#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT			0x05
#define TPS65917_INT4_LINE_STATE_GPIO_4			0x10
#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT			0x04
#define TPS65917_INT4_LINE_STATE_GPIO_3			0x08
#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT			0x03
#define TPS65917_INT4_LINE_STATE_GPIO_2			0x04
#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT			0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1			0x02
#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT			0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0			0x01
#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT			0x00

/* Bit definitions for INT4_EDGE_DETECT1 */
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING		0x80
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT		0x07
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING		0x40
#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT	0x06
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING		0x20
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT		0x05
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING		0x10
#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT	0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING		0x08
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT		0x03
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING		0x04
#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT	0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING		0x02
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT		0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING		0x01
#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT	0x00

/* Bit definitions for INT4_EDGE_DETECT2 */
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING		0x20
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT		0x05
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING		0x10
#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT	0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING		0x08
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT		0x03
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING		0x04
#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT	0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING		0x02
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT		0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING		0x01
#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT	0x00

/* Bit definitions for INT_CTRL */
#define TPS65917_INT_CTRL_INT_PENDING				0x04
#define TPS65917_INT_CTRL_INT_PENDING_SHIFT			0x02
#define TPS65917_INT_CTRL_INT_CLEAR				0x01
#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT			0x00

/* TPS65917 SMPS Registers */

/* Registers for function SMPS */
#define TPS65917_SMPS1_CTRL					0x00
#define TPS65917_SMPS1_FORCE					0x02
#define TPS65917_SMPS1_VOLTAGE					0x03
#define TPS65917_SMPS2_CTRL					0x04
#define TPS65917_SMPS2_FORCE					0x06
#define TPS65917_SMPS2_VOLTAGE					0x07
#define TPS65917_SMPS3_CTRL					0x0C
#define TPS65917_SMPS3_FORCE					0x0E
#define TPS65917_SMPS3_VOLTAGE					0x0F
#define TPS65917_SMPS4_CTRL					0x10
#define TPS65917_SMPS4_VOLTAGE					0x13
#define TPS65917_SMPS5_CTRL					0x18
#define TPS65917_SMPS5_VOLTAGE					0x1B
#define TPS65917_SMPS_CTRL					0x24
#define TPS65917_SMPS_PD_CTRL					0x25
#define TPS65917_SMPS_THERMAL_EN				0x27
#define TPS65917_SMPS_THERMAL_STATUS				0x28
#define TPS65917_SMPS_SHORT_STATUS				0x29
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN		0x2A
#define TPS65917_SMPS_POWERGOOD_MASK1				0x2B
#define TPS65917_SMPS_POWERGOOD_MASK2				0x2C

/* Bit definitions for SMPS1_CTRL */
#define TPS65917_SMPS1_CTRL_WR_S				0x80
#define TPS65917_SMPS1_CTRL_WR_S_SHIFT				0x07
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN			0x40
#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT		0x06
#define TPS65917_SMPS1_CTRL_STATUS_MASK			0x30
#define TPS65917_SMPS1_CTRL_STATUS_SHIFT			0x04
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK			0x0C
#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK			0x03
#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS1_FORCE */
#define TPS65917_SMPS1_FORCE_CMD				0x80
#define TPS65917_SMPS1_FORCE_CMD_SHIFT				0x07
#define TPS65917_SMPS1_FORCE_VSEL_MASK				0x7F
#define TPS65917_SMPS1_FORCE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS1_VOLTAGE */
#define TPS65917_SMPS1_VOLTAGE_RANGE				0x80
#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT			0x07
#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK			0x7F
#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS2_CTRL */
#define TPS65917_SMPS2_CTRL_WR_S				0x80
#define TPS65917_SMPS2_CTRL_WR_S_SHIFT				0x07
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN			0x40
#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT		0x06
#define TPS65917_SMPS2_CTRL_STATUS_MASK			0x30
#define TPS65917_SMPS2_CTRL_STATUS_SHIFT			0x04
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK			0x0C
#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK			0x03
#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS2_FORCE */
#define TPS65917_SMPS2_FORCE_CMD				0x80
#define TPS65917_SMPS2_FORCE_CMD_SHIFT				0x07
#define TPS65917_SMPS2_FORCE_VSEL_MASK				0x7F
#define TPS65917_SMPS2_FORCE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS2_VOLTAGE */
#define TPS65917_SMPS2_VOLTAGE_RANGE				0x80
#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT			0x07
#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK			0x7F
#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS3_CTRL */
#define TPS65917_SMPS3_CTRL_WR_S				0x80
#define TPS65917_SMPS3_CTRL_WR_S_SHIFT				0x07
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN			0x40
#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT		0x06
#define TPS65917_SMPS3_CTRL_STATUS_MASK			0x30
#define TPS65917_SMPS3_CTRL_STATUS_SHIFT			0x04
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK			0x0C
#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK			0x03
#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS3_FORCE */
#define TPS65917_SMPS3_FORCE_CMD				0x80
#define TPS65917_SMPS3_FORCE_CMD_SHIFT				0x07
#define TPS65917_SMPS3_FORCE_VSEL_MASK				0x7F
#define TPS65917_SMPS3_FORCE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS3_VOLTAGE */
#define TPS65917_SMPS3_VOLTAGE_RANGE				0x80
#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT			0x07
#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK			0x7F
#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS4_CTRL */
#define TPS65917_SMPS4_CTRL_WR_S				0x80
#define TPS65917_SMPS4_CTRL_WR_S_SHIFT				0x07
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN			0x40
#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT		0x06
#define TPS65917_SMPS4_CTRL_STATUS_MASK			0x30
#define TPS65917_SMPS4_CTRL_STATUS_SHIFT			0x04
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK			0x0C
#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK			0x03
#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS4_VOLTAGE */
#define TPS65917_SMPS4_VOLTAGE_RANGE				0x80
#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT			0x07
#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK			0x7F
#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS5_CTRL */
#define TPS65917_SMPS5_CTRL_WR_S				0x80
#define TPS65917_SMPS5_CTRL_WR_S_SHIFT				0x07
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN			0x40
#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT		0x06
#define TPS65917_SMPS5_CTRL_STATUS_MASK			0x30
#define TPS65917_SMPS5_CTRL_STATUS_SHIFT			0x04
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK			0x0C
#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK			0x03
#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for SMPS5_VOLTAGE */
#define TPS65917_SMPS5_VOLTAGE_RANGE				0x80
#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT			0x07
#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK			0x7F
#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for SMPS_CTRL */
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN			0x10
#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT		0x04
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL			0x03
#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT		0x00

/* Bit definitions for SMPS_PD_CTRL */
#define TPS65917_SMPS_PD_CTRL_SMPS5				0x40
#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT			0x06
#define TPS65917_SMPS_PD_CTRL_SMPS4				0x10
#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT			0x04
#define TPS65917_SMPS_PD_CTRL_SMPS3				0x08
#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT			0x03
#define TPS65917_SMPS_PD_CTRL_SMPS2				0x02
#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT			0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1				0x01
#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT			0x00

/* Bit definitions for SMPS_THERMAL_EN */
#define TPS65917_SMPS_THERMAL_EN_SMPS5				0x40
#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT			0x06
#define TPS65917_SMPS_THERMAL_EN_SMPS3				0x08
#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT			0x03
#define TPS65917_SMPS_THERMAL_EN_SMPS12			0x01
#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT			0x00

/* Bit definitions for SMPS_THERMAL_STATUS */
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5			0x40
#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT		0x06
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3			0x08
#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT		0x03
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12			0x01
#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT		0x00

/* Bit definitions for SMPS_SHORT_STATUS */
#define TPS65917_SMPS_SHORT_STATUS_SMPS5			0x40
#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT			0x06
#define TPS65917_SMPS_SHORT_STATUS_SMPS4			0x10
#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT			0x04
#define TPS65917_SMPS_SHORT_STATUS_SMPS3			0x08
#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT			0x03
#define TPS65917_SMPS_SHORT_STATUS_SMPS2			0x02
#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT			0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1			0x01
#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT			0x00

/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5		0x40
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT	0x06
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4		0x10
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT	0x04
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3		0x08
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT	0x03
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2		0x02
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT	0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1		0x01
#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT	0x00

/* Bit definitions for SMPS_POWERGOOD_MASK1 */
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5			0x40
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT		0x06
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4			0x10
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT		0x04
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3			0x08
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT		0x03
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2			0x02
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT		0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1			0x01
#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT		0x00

/* Bit definitions for SMPS_POWERGOOD_MASK2 */
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT		0x80
#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT	0x07
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT			0x10
#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM			0x04

/* Bit definitions for SMPS_PLL_CTRL */

#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT		0x08
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS		0x03
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT	0x04
#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK		0x02

/* Registers for function LDO */
#define TPS65917_LDO1_CTRL					0x00
#define TPS65917_LDO1_VOLTAGE					0x01
#define TPS65917_LDO2_CTRL					0x02
#define TPS65917_LDO2_VOLTAGE					0x03
#define TPS65917_LDO3_CTRL					0x04
#define TPS65917_LDO3_VOLTAGE					0x05
#define TPS65917_LDO4_CTRL					0x0E
#define TPS65917_LDO4_VOLTAGE					0x0F
#define TPS65917_LDO5_CTRL					0x12
#define TPS65917_LDO5_VOLTAGE					0x13
#define TPS65917_LDO_PD_CTRL1					0x1B
#define TPS65917_LDO_PD_CTRL2					0x1C
#define TPS65917_LDO_SHORT_STATUS1				0x1D
#define TPS65917_LDO_SHORT_STATUS2				0x1E
#define TPS65917_LDO_PD_CTRL3					0x2D
#define TPS65917_LDO_SHORT_STATUS3				0x2E

/* Bit definitions for LDO1_CTRL */
#define TPS65917_LDO1_CTRL_WR_S				0x80
#define TPS65917_LDO1_CTRL_WR_S_SHIFT				0x07
#define TPS65917_LDO1_CTRL_BYPASS_EN				0x40
#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT			0x06
#define TPS65917_LDO1_CTRL_STATUS				0x10
#define TPS65917_LDO1_CTRL_STATUS_SHIFT			0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP				0x04
#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_LDO1_CTRL_MODE_ACTIVE				0x01
#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO1_VOLTAGE */
#define TPS65917_LDO1_VOLTAGE_VSEL_MASK			0x2F
#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO2_CTRL */
#define TPS65917_LDO2_CTRL_WR_S				0x80
#define TPS65917_LDO2_CTRL_WR_S_SHIFT				0x07
#define TPS65917_LDO2_CTRL_BYPASS_EN				0x40
#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT			0x06
#define TPS65917_LDO2_CTRL_STATUS				0x10
#define TPS65917_LDO2_CTRL_STATUS_SHIFT			0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP				0x04
#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_LDO2_CTRL_MODE_ACTIVE				0x01
#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO2_VOLTAGE */
#define TPS65917_LDO2_VOLTAGE_VSEL_MASK			0x2F
#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO3_CTRL */
#define TPS65917_LDO3_CTRL_WR_S				0x80
#define TPS65917_LDO3_CTRL_WR_S_SHIFT				0x07
#define TPS65917_LDO3_CTRL_STATUS				0x10
#define TPS65917_LDO3_CTRL_STATUS_SHIFT			0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP				0x04
#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_LDO3_CTRL_MODE_ACTIVE				0x01
#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO3_VOLTAGE */
#define TPS65917_LDO3_VOLTAGE_VSEL_MASK			0x2F
#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO4_CTRL */
#define TPS65917_LDO4_CTRL_WR_S				0x80
#define TPS65917_LDO4_CTRL_WR_S_SHIFT				0x07
#define TPS65917_LDO4_CTRL_STATUS				0x10
#define TPS65917_LDO4_CTRL_STATUS_SHIFT			0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP				0x04
#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_LDO4_CTRL_MODE_ACTIVE				0x01
#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO4_VOLTAGE */
#define TPS65917_LDO4_VOLTAGE_VSEL_MASK			0x2F
#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO5_CTRL */
#define TPS65917_LDO5_CTRL_WR_S				0x80
#define TPS65917_LDO5_CTRL_WR_S_SHIFT				0x07
#define TPS65917_LDO5_CTRL_STATUS				0x10
#define TPS65917_LDO5_CTRL_STATUS_SHIFT			0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP				0x04
#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_LDO5_CTRL_MODE_ACTIVE				0x01
#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for LDO5_VOLTAGE */
#define TPS65917_LDO5_VOLTAGE_VSEL_MASK			0x2F
#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT			0x00

/* Bit definitions for LDO_PD_CTRL1 */
#define TPS65917_LDO_PD_CTRL1_LDO4				0x80
#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT			0x07
#define TPS65917_LDO_PD_CTRL1_LDO2				0x02
#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT			0x01
#define TPS65917_LDO_PD_CTRL1_LDO1				0x01
#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT			0x00

/* Bit definitions for LDO_PD_CTRL2 */
#define TPS65917_LDO_PD_CTRL2_LDO3				0x04
#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT			0x02
#define TPS65917_LDO_PD_CTRL2_LDO5				0x02
#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT			0x01

/* Bit definitions for LDO_PD_CTRL3 */
#define TPS65917_LDO_PD_CTRL2_LDOVANA				0x80
#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT			0x07

/* Bit definitions for LDO_SHORT_STATUS1 */
#define TPS65917_LDO_SHORT_STATUS1_LDO4			0x80
#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT			0x07
#define TPS65917_LDO_SHORT_STATUS1_LDO2			0x02
#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT			0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1			0x01
#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT			0x00

/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDO3			0x04
#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT			0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5			0x02
#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT			0x01

/* Bit definitions for LDO_SHORT_STATUS2 */
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA			0x80
#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT		0x07

/* Bit definitions for REGEN1_CTRL */
#define TPS65917_REGEN1_CTRL_STATUS				0x10
#define TPS65917_REGEN1_CTRL_STATUS_SHIFT			0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP			0x04
#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE			0x01
#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for PLLEN_CTRL */
#define TPS65917_PLLEN_CTRL_STATUS				0x10
#define TPS65917_PLLEN_CTRL_STATUS_SHIFT			0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP				0x04
#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE			0x01
#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for REGEN2_CTRL */
#define TPS65917_REGEN2_CTRL_STATUS				0x10
#define TPS65917_REGEN2_CTRL_STATUS_SHIFT			0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP			0x04
#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE			0x01
#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Bit definitions for NSLEEP_RES_ASSIGN */
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN			0x08
#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT		0x03
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3			0x04
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT		0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2			0x02
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT		0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1			0x01
#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT		0x00

/* Bit definitions for NSLEEP_SMPS_ASSIGN */
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5			0x40
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT		0x06
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4			0x10
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT		0x04
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3			0x08
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT		0x03
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2			0x02
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT		0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1			0x01
#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT		0x00

/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4			0x80
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT			0x07
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2			0x02
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT			0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1			0x01
#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT			0x00

/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3			0x04
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT			0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5			0x02
#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT			0x01

/* Bit definitions for ENABLE1_RES_ASSIGN */
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN			0x08
#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT		0x03
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3			0x04
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT		0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2			0x02
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT		0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1			0x01
#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT		0x00

/* Bit definitions for ENABLE1_SMPS_ASSIGN */
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5			0x40
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT		0x06
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4			0x10
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT		0x04
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3			0x08
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT		0x03
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2			0x02
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT		0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1			0x01
#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT		0x00

/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4			0x80
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT		0x07
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2			0x02
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT		0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1			0x01
#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT		0x00

/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3			0x04
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT		0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5			0x02
#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT		0x01

/* Bit definitions for ENABLE2_RES_ASSIGN */
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN			0x08
#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT		0x03
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3			0x04
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT		0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2			0x02
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT		0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1			0x01
#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT		0x00

/* Bit definitions for ENABLE2_SMPS_ASSIGN */
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5			0x40
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT		0x06
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4			0x10
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT		0x04
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3			0x08
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT		0x03
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2			0x02
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT		0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1			0x01
#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT		0x00

/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4			0x80
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT		0x07
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2			0x02
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT		0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1			0x01
#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT		0x00

/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3			0x04
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT		0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5			0x02
#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT		0x01

/* Bit definitions for REGEN3_CTRL */
#define TPS65917_REGEN3_CTRL_STATUS				0x10
#define TPS65917_REGEN3_CTRL_STATUS_SHIFT			0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP			0x04
#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT			0x02
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE			0x01
#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT			0x00

/* Registers for function RESOURCE */
#define TPS65917_REGEN1_CTRL					0x2
#define TPS65917_PLLEN_CTRL					0x3
#define TPS65917_NSLEEP_RES_ASSIGN				0x6
#define TPS65917_NSLEEP_SMPS_ASSIGN				0x7
#define TPS65917_NSLEEP_LDO_ASSIGN1				0x8
#define TPS65917_NSLEEP_LDO_ASSIGN2				0x9
#define TPS65917_ENABLE1_RES_ASSIGN				0xA
#define TPS65917_ENABLE1_SMPS_ASSIGN				0xB
#define TPS65917_ENABLE1_LDO_ASSIGN1				0xC
#define TPS65917_ENABLE1_LDO_ASSIGN2				0xD
#define TPS65917_ENABLE2_RES_ASSIGN				0xE
#define TPS65917_ENABLE2_SMPS_ASSIGN				0xF
#define TPS65917_ENABLE2_LDO_ASSIGN1				0x10
#define TPS65917_ENABLE2_LDO_ASSIGN2				0x11
#define TPS65917_REGEN2_CTRL					0x12
#define TPS65917_REGEN3_CTRL					0x13

static inline int palmas_read(struct palmas *palmas, unsigned int base,
		unsigned int reg, unsigned int *val)
{
	unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
	int slave_id = PALMAS_BASE_TO_SLAVE(base);

	return regmap_read(palmas->regmap[slave_id], addr, val);
}

static inline int palmas_write(struct palmas *palmas, unsigned int base,
		unsigned int reg, unsigned int value)
{
	unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
	int slave_id = PALMAS_BASE_TO_SLAVE(base);

	return regmap_write(palmas->regmap[slave_id], addr, value);
}

static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
	unsigned int reg, const void *val, size_t val_count)
{
	unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
	int slave_id = PALMAS_BASE_TO_SLAVE(base);

	return regmap_bulk_write(palmas->regmap[slave_id], addr,
			val, val_count);
}

static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
		unsigned int reg, void *val, size_t val_count)
{
	unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
	int slave_id = PALMAS_BASE_TO_SLAVE(base);

	return regmap_bulk_read(palmas->regmap[slave_id], addr,
		val, val_count);
}

static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
	unsigned int reg, unsigned int mask, unsigned int val)
{
	unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
	int slave_id = PALMAS_BASE_TO_SLAVE(base);

	return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
}

static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
{
	return regmap_irq_get_virq(palmas->irq_data, irq);
}


int palmas_ext_control_req_config(struct palmas *palmas,
	enum palmas_external_requestor_id ext_control_req_id,
	int ext_ctrl, bool enable);

#endif /*  __LINUX_MFD_PALMAS_H */