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authorAndré Fabian Silva Delgado <emulatorman@parabola.nu>2015-08-05 17:04:01 -0300
committerAndré Fabian Silva Delgado <emulatorman@parabola.nu>2015-08-05 17:04:01 -0300
commit57f0f512b273f60d52568b8c6b77e17f5636edc0 (patch)
tree5e910f0e82173f4ef4f51111366a3f1299037a7b /include/linux/can/platform
Initial import
Diffstat (limited to 'include/linux/can/platform')
-rw-r--r--include/linux/can/platform/cc770.h33
-rw-r--r--include/linux/can/platform/mcp251x.h21
-rw-r--r--include/linux/can/platform/rcar_can.h17
-rw-r--r--include/linux/can/platform/sja1000.h35
-rw-r--r--include/linux/can/platform/ti_hecc.h44
5 files changed, 150 insertions, 0 deletions
diff --git a/include/linux/can/platform/cc770.h b/include/linux/can/platform/cc770.h
new file mode 100644
index 000000000..78b2d44f0
--- /dev/null
+++ b/include/linux/can/platform/cc770.h
@@ -0,0 +1,33 @@
+#ifndef _CAN_PLATFORM_CC770_H
+#define _CAN_PLATFORM_CC770_H
+
+/* CPU Interface Register (0x02) */
+#define CPUIF_CEN 0x01 /* Clock Out Enable */
+#define CPUIF_MUX 0x04 /* Multiplex */
+#define CPUIF_SLP 0x08 /* Sleep */
+#define CPUIF_PWD 0x10 /* Power Down Mode */
+#define CPUIF_DMC 0x20 /* Divide Memory Clock */
+#define CPUIF_DSC 0x40 /* Divide System Clock */
+#define CPUIF_RST 0x80 /* Hardware Reset Status */
+
+/* Clock Out Register (0x1f) */
+#define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */
+#define CLKOUT_SL_MASK 0x30 /* Slew Rate mask */
+#define CLKOUT_SL_SHIFT 4
+
+/* Bus Configuration Register (0x2f) */
+#define BUSCFG_DR0 0x01 /* Disconnect RX0 Input / Select RX input */
+#define BUSCFG_DR1 0x02 /* Disconnect RX1 Input / Silent mode */
+#define BUSCFG_DT1 0x08 /* Disconnect TX1 Output */
+#define BUSCFG_POL 0x20 /* Polarity dominant or recessive */
+#define BUSCFG_CBY 0x40 /* Input Comparator Bypass */
+
+struct cc770_platform_data {
+ u32 osc_freq; /* CAN bus oscillator frequency in Hz */
+
+ u8 cir; /* CPU Interface Register */
+ u8 cor; /* Clock Out Register */
+ u8 bcr; /* Bus Configuration Register */
+};
+
+#endif /* !_CAN_PLATFORM_CC770_H */
diff --git a/include/linux/can/platform/mcp251x.h b/include/linux/can/platform/mcp251x.h
new file mode 100644
index 000000000..d44fcae27
--- /dev/null
+++ b/include/linux/can/platform/mcp251x.h
@@ -0,0 +1,21 @@
+#ifndef _CAN_PLATFORM_MCP251X_H
+#define _CAN_PLATFORM_MCP251X_H
+
+/*
+ *
+ * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
+ *
+ */
+
+#include <linux/spi/spi.h>
+
+/*
+ * struct mcp251x_platform_data - MCP251X SPI CAN controller platform data
+ * @oscillator_frequency: - oscillator frequency in Hz
+ */
+
+struct mcp251x_platform_data {
+ unsigned long oscillator_frequency;
+};
+
+#endif /* !_CAN_PLATFORM_MCP251X_H */
diff --git a/include/linux/can/platform/rcar_can.h b/include/linux/can/platform/rcar_can.h
new file mode 100644
index 000000000..0f4a2f3df
--- /dev/null
+++ b/include/linux/can/platform/rcar_can.h
@@ -0,0 +1,17 @@
+#ifndef _CAN_PLATFORM_RCAR_CAN_H_
+#define _CAN_PLATFORM_RCAR_CAN_H_
+
+#include <linux/types.h>
+
+/* Clock Select Register settings */
+enum CLKR {
+ CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */
+ CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */
+ CLKR_CLKEXT = 3 /* Externally input clock */
+};
+
+struct rcar_can_platform_data {
+ enum CLKR clock_select; /* Clock source select */
+};
+
+#endif /* !_CAN_PLATFORM_RCAR_CAN_H_ */
diff --git a/include/linux/can/platform/sja1000.h b/include/linux/can/platform/sja1000.h
new file mode 100644
index 000000000..93570b61e
--- /dev/null
+++ b/include/linux/can/platform/sja1000.h
@@ -0,0 +1,35 @@
+#ifndef _CAN_PLATFORM_SJA1000_H
+#define _CAN_PLATFORM_SJA1000_H
+
+/* clock divider register */
+#define CDR_CLKOUT_MASK 0x07
+#define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
+#define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */
+#define CDR_CBP 0x40 /* CAN input comparator bypass */
+#define CDR_PELICAN 0x80 /* PeliCAN mode */
+
+/* output control register */
+#define OCR_MODE_BIPHASE 0x00
+#define OCR_MODE_TEST 0x01
+#define OCR_MODE_NORMAL 0x02
+#define OCR_MODE_CLOCK 0x03
+#define OCR_MODE_MASK 0x07
+#define OCR_TX0_INVERT 0x04
+#define OCR_TX0_PULLDOWN 0x08
+#define OCR_TX0_PULLUP 0x10
+#define OCR_TX0_PUSHPULL 0x18
+#define OCR_TX1_INVERT 0x20
+#define OCR_TX1_PULLDOWN 0x40
+#define OCR_TX1_PULLUP 0x80
+#define OCR_TX1_PUSHPULL 0xc0
+#define OCR_TX_MASK 0xfc
+#define OCR_TX_SHIFT 2
+
+struct sja1000_platform_data {
+ u32 osc_freq; /* CAN bus oscillator frequency in Hz */
+
+ u8 ocr; /* output control register */
+ u8 cdr; /* clock divider register */
+};
+
+#endif /* !_CAN_PLATFORM_SJA1000_H */
diff --git a/include/linux/can/platform/ti_hecc.h b/include/linux/can/platform/ti_hecc.h
new file mode 100644
index 000000000..a52f47ca6
--- /dev/null
+++ b/include/linux/can/platform/ti_hecc.h
@@ -0,0 +1,44 @@
+#ifndef _CAN_PLATFORM_TI_HECC_H
+#define _CAN_PLATFORM_TI_HECC_H
+
+/*
+ * TI HECC (High End CAN Controller) driver platform header
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/**
+ * struct hecc_platform_data - HECC Platform Data
+ *
+ * @scc_hecc_offset: mostly 0 - should really never change
+ * @scc_ram_offset: SCC RAM offset
+ * @hecc_ram_offset: HECC RAM offset
+ * @mbx_offset: Mailbox RAM offset
+ * @int_line: Interrupt line to use - 0 or 1
+ * @version: version for future use
+ * @transceiver_switch: platform specific callback fn for transceiver control
+ *
+ * Platform data structure to get all platform specific settings.
+ * this structure also accounts the fact that the IP may have different
+ * RAM and mailbox offsets for different SOC's
+ */
+struct ti_hecc_platform_data {
+ u32 scc_hecc_offset;
+ u32 scc_ram_offset;
+ u32 hecc_ram_offset;
+ u32 mbx_offset;
+ u32 int_line;
+ u32 version;
+ void (*transceiver_switch) (int);
+};
+#endif /* !_CAN_PLATFORM_TI_HECC_H */