diff options
Diffstat (limited to 'arch/arm')
23 files changed, 0 insertions, 3870 deletions
diff --git a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi deleted file mode 100644 index 3e4c4ad96..000000000 --- a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Device tree sources for Exynos5422 thermal zone - * - * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com> - * Anand Moon <linux.amoon@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <dt-bindings/thermal/thermal.h> - -/ { - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmu_cpu0 0>; - polling-delay-passive = <250>; - polling-delay = <0>; - trips { - cpu_alert0: cpu-alert-0 { - temperature = <50000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert1: cpu-alert-1 { - temperature = <60000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_alert2: cpu-alert-2 { - temperature = <70000>; /* millicelsius */ - hysteresis = <5000>; /* millicelsius */ - type = "active"; - }; - cpu_crit0: cpu-crit-0 { - temperature = <120000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - /* - * Exyunos542x support only 4 trip-points - * so for these polling mode is required. - * Start polling at temperature level of last - * interrupt-driven trip: cpu_alert2 - */ - cpu_alert3: cpu-alert-3 { - temperature = <70000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert4: cpu-alert-4 { - temperature = <85000>; /* millicelsius */ - hysteresis = <10000>; /* millicelsius */ - type = "passive"; - }; - - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&fan0 1 2>; - }; - map2 { - trip = <&cpu_alert2>; - cooling-device = <&fan0 2 3>; - }; - /* - * When reaching cpu_alert3, reduce CPU - * by 2 steps. On Exynos5422/5800 that would - * be: 1500 MHz and 1100 MHz. - */ - map3 { - trip = <&cpu_alert3>; - cooling-device = <&cpu0 0 2>; - }; - map4 { - trip = <&cpu_alert3>; - cooling-device = <&cpu4 0 2>; - }; - - /* - * When reaching cpu_alert4, reduce CPU - * further, down to 600 MHz (11 steps for big, - * 7 steps for LITTLE). - */ - map5 { - trip = <&cpu_alert4>; - cooling-device = <&cpu0 3 7>; - }; - map6 { - trip = <&cpu_alert4>; - cooling-device = <&cpu4 3 11>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi deleted file mode 100644 index a3efb9704..000000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -&tlmm_pinmux { - card_detect: card-detect { - mux { - pins = "gpio26"; - function = "gpio"; - bias-disable; - }; - }; - - pcie_pins: pcie-pinmux { - mux { - pins = "gpio27"; - function = "gpio"; - }; - conf { - pins = "gpio27"; - drive-strength = <12>; - bias-disable; - }; - }; - - user_leds: user-leds { - mux { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - }; - - conf { - pins = "gpio3", "gpio7", "gpio10", "gpio11"; - function = "gpio"; - output-low; - }; - }; - - magneto_pins: magneto-pins { - mux { - pins = "gpio31", "gpio48"; - function = "gpio"; - bias-disable; - }; - }; -}; - -&pm8921_mpps { - mpp_leds: mpp-leds { - pinconf { - pins = "mpp7", "mpp8"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts deleted file mode 100644 index e01b27ea7..000000000 --- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts +++ /dev/null @@ -1,349 +0,0 @@ -#include "qcom-apq8064-v2.0.dtsi" -#include "qcom-apq8064-arrow-db600c-pins.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Arrow Electronics, APQ8064 DB600c"; - compatible = "arrow,db600c", "qcom,apq8064"; - - aliases { - serial0 = &gsbi7_serial; - serial1 = &gsbi1_serial; - i2c0 = &gsbi2_i2c; - i2c1 = &gsbi3_i2c; - i2c2 = &gsbi4_i2c; - i2c3 = &gsbi7_i2c; - spi0 = &gsbi5_spi; - }; - - regulators { - compatible = "simple-bus"; - vph: regulator-fixed@1 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <4500000>; - regulator-max-microvolt = <4500000>; - regulator-name = "VPH"; - regulator-type = "voltage"; - regulator-boot-on; - }; - - /* on board fixed 3.3v supply */ - vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - }; - - soc { - rpm@108000 { - regulators { - vdd_s1-supply = <&vph>; - vdd_s2-supply = <&vph>; - vdd_s3-supply = <&vph>; - vdd_s4-supply = <&vph>; - vdd_s5-supply = <&vph>; - vdd_s6-supply = <&vph>; - vdd_s7-supply = <&vph>; - vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; - vdd_l3_l15_l17-supply = <&vph>; - vdd_l4_l14-supply = <&vph>; - vdd_l5_l8_l16-supply = <&vph>; - vdd_l6_l7-supply = <&vph>; - vdd_l9_l11-supply = <&vph>; - vdd_l10_l22-supply = <&vph>; - vdd_l21_l23_l29-supply = <&vph>; - vdd_l24-supply = <&pm8921_s1>; - vdd_l25-supply = <&pm8921_s1>; - vdd_l26-supply = <&pm8921_s7>; - vdd_l27-supply = <&pm8921_s7>; - vdd_l28-supply = <&pm8921_s7>; - vin_lvs1_3_6-supply = <&pm8921_s4>; - vin_lvs2-supply = <&pm8921_s1>; - vin_lvs4_5_7-supply = <&pm8921_s4>; - - s1 { - regulator-always-on; - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - }; - - s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - qcom,switch-mode-frequency = <4800000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - qcom,switch-mode-frequency = <3200000>; - bias-pull-down; - regulator-always-on; - }; - - s7 { - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1300000>; - qcom,switch-mode-frequency = <3200000>; - }; - - l3 { - regulator-min-microvolt = <3050000>; - regulator-max-microvolt = <3300000>; - bias-pull-down; - }; - - l4 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1800000>; - bias-pull-down; - }; - - l5 { - regulator-min-microvolt = <2750000>; - regulator-max-microvolt = <3000000>; - bias-pull-down; - regulator-boot-on; - regulator-always-on; - }; - - l6 { - regulator-min-microvolt = <2950000>; - regulator-max-microvolt = <2950000>; - bias-pull-down; - }; - - l23 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - bias-pull-down; - }; - - lvs6 { - bias-pull-down; - }; - - lvs7 { - bias-pull-down; - }; - }; - }; - - gsbi@12440000 { - status = "okay"; - qcom,mode = <GSBI_PROT_UART_W_FC>; - serial@12450000 { - label = "LS-UART1"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi1_uart_4pins>; - }; - }; - - gsbi@12480000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C>; - i2c@124a0000 { - /* On Low speed expansion and Sensors */ - label = "LS-I2C0"; - status = "okay"; - lis3mdl_mag@1e { - compatible = "st,lis3mdl-magn"; - reg = <0x1e>; - vdd-supply = <&vcc3v3>; - vddio-supply = <&pm8921_s4>; - pinctrl-names = "default"; - pinctrl-0 = <&magneto_pins>; - interrupt-parent = <&tlmm_pinmux>; - - st,drdy-int-pin = <2>; - interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ - <31 IRQ_TYPE_EDGE_RISING>; /* INT */ - }; - }; - }; - - gsbi@16200000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C>; - i2c@16280000 { - /* On Low speed expansion */ - status = "okay"; - label = "LS-I2C1"; - clock-frequency = <200000>; - eeprom@52 { - compatible = "atmel,24c128"; - reg = <0x52>; - pagesize = <64>; - }; - }; - }; - - gsbi@16300000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C>; - i2c@16380000 { - /* On High speed expansion */ - label = "HS-CAM-I2C3"; - status = "okay"; - }; - }; - - gsbi@1a200000 { - status = "okay"; - spi@1a280000 { - /* On Low speed expansion */ - label = "LS-SPI0"; - status = "okay"; - }; - }; - - /* DEBUG UART */ - gsbi@16600000 { - status = "okay"; - qcom,mode = <GSBI_PROT_I2C_UART>; - serial@16640000 { - label = "LS-UART0"; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&gsbi7_uart_2pins>; - }; - - i2c@16680000 { - /* On High speed expansion */ - status = "okay"; - label = "HS-CAM-I2C2"; - }; - }; - - leds { - pinctrl-names = "default"; - pinctrl-0 = <&user_leds>, <&mpp_leds>; - - compatible = "gpio-leds"; - - user-led0 { - label = "user0-led"; - gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - user-led1 { - label = "user1-led"; - gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - user-led2 { - label = "user2-led"; - gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - user-led3 { - label = "user3-led"; - gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - }; - - wifi-led { - label = "WiFi-led"; - gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - bt-led { - label = "BT-led"; - gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - pci@1b500000 { - status = "okay"; - vdda-supply = <&pm8921_s3>; - vdda_phy-supply = <&pm8921_lvs6>; - vdda_refclk-supply = <&vcc3v3>; - pinctrl-0 = <&pcie_pins>; - pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; - }; - - phy@1b400000 { - status = "okay"; - }; - - sata@29000000 { - status = "okay"; - target-supply = <&pm8921_lvs7>; - }; - - /* OTG */ - phy@12500000 { - status = "okay"; - dr_mode = "peripheral"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l4>; - }; - - phy@12520000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - phy@12530000 { - status = "okay"; - vddcx-supply = <&pm8921_s3>; - v3p3-supply = <&pm8921_l3>; - v1p8-supply = <&pm8921_l23>; - }; - - gadget@12500000 { - status = "okay"; - }; - - /* OTG */ - usb@12500000 { - status = "okay"; - }; - - usb@12520000 { - status = "okay"; - }; - - usb@12530000 { - status = "okay"; - }; - - amba { - /* eMMC */ - sdcc@12400000 { - status = "okay"; - vmmc-supply = <&pm8921_l5>; - vqmmc-supply = <&pm8921_s4>; - }; - - /* External micro SD card */ - sdcc@12180000 { - status = "okay"; - vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi deleted file mode 100644 index e23a22e29..000000000 --- a/arch/arm/boot/dts/rk3228.dtsi +++ /dev/null @@ -1,591 +0,0 @@ -/* - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include <dt-bindings/clock/rk3228-cru.h> -#include <dt-bindings/thermal/thermal.h> -#include "skeleton.dtsi" - -/ { - compatible = "rockchip,rk3228"; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points = < - /* KHz uV */ - 816000 1000000 - >; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - }; - }; - - amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - grf: syscon@11000000 { - compatible = "syscon"; - reg = <0x11000000 0x1000>; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - clock-names = "pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&xin24m>, <&cru PCLK_TIMER>; - clock-names = "timer", "pclk"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = <&cru PLL_GPLL>; - assigned-clock-rates = <594000000>; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_gpio>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_gpio>; - #thermal-sensor-cells = <0>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - emmc: dwmmc@30020000 { - compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <37500000>; - clock-freq-min-max = <400000 37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; - bus-width = <8>; - default-sample-phase = <158>; - num-slots = <1>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - status = "disabled"; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x1000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio0@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio1@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio2@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio3@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, - <2 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_gpio: otp-gpio { - rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, - <2 27 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>, - <1 10 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-q8-common.dtsi deleted file mode 100644 index a78e189f6..000000000 --- a/arch/arm/boot/dts/sun5i-q8-common.dtsi +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#include "sunxi-q8-common.dtsi" - -#include <dt-bindings/pwm/pwm.h> - -/ { - aliases { - serial0 = &uart1; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - /* TODO: backlight uses axp gpio1 as enable pin */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -&i2c1 { - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>; - vmmc-supply = <®_vcc3v0>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_q8: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - usb0_vbus_pin_a: usb0_vbus_pin@0 { - allwinner,pins = "PG12"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sunxi-q8-common.dtsi b/arch/arm/boot/dts/sunxi-q8-common.dtsi deleted file mode 100644 index b8241462f..000000000 --- a/arch/arm/boot/dts/sunxi-q8-common.dtsi +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> -#include "sunxi-common-regulators.dtsi" - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig deleted file mode 100644 index 909049a28..000000000 --- a/arch/arm/configs/bcm_defconfig +++ /dev/null @@ -1,141 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=19 -CONFIG_CGROUPS=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_SCHED=y -CONFIG_BLK_CGROUP=y -CONFIG_NAMESPACES=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_EMBEDDED=y -# CONFIG_COMPAT_BRK is not set -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_PARTITION_ADVANCED=y -CONFIG_ARCH_BCM=y -CONFIG_ARCH_BCM_21664=y -CONFIG_ARCH_BCM_281XX=y -CONFIG_ARM_THUMBEE=y -CONFIG_SMP=y -CONFIG_PREEMPT=y -CONFIG_AEABI=y -# CONFIG_COMPACTION is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttyS0,115200n8 mem=128M" -CONFIG_CPU_IDLE=y -CONFIG_VFP=y -CONFIG_NEON=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=y -CONFIG_UNIX=y -CONFIG_UNIX_DIAG=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_SYN_COOKIES=y -CONFIG_TCP_MD5SIG=y -CONFIG_IPV6=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_PROC_DEVICETREE=y -# CONFIG_BLK_DEV is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DW=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -# CONFIG_HWMON is not set -CONFIG_MFD_BCM590XX=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_USERSPACE_CONSUMER=y -CONFIG_REGULATOR_BCM590XX=y - -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_TEST=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_BCM_KONA=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_PWM=y -CONFIG_PWM_BCM_KONA=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=y -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110 -CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y -# CONFIG_FTRACE is not set -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC7=y -CONFIG_XZ_DEC=y -CONFIG_AVERAGE=y -CONFIG_PINCTRL_BCM281XX=y -CONFIG_WATCHDOG=y -CONFIG_BCM_KONA_WDT=y -CONFIG_BCM_KONA_WDT_DEBUG=y diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h deleted file mode 100644 index eb052a11a..000000000 --- a/arch/arm/mach-clps711x/include/mach/clps711x.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This file contains the hardware definitions of the Cirrus Logic - * ARM7 CLPS711X internal registers. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __MACH_CLPS711X_H -#define __MACH_CLPS711X_H - -#include <linux/mfd/syscon/clps711x.h> - -#define CLPS711X_PHYS_BASE (0x80000000) - -#define PADR (0x0000) -#define PBDR (0x0001) -#define PCDR (0x0002) -#define PDDR (0x0003) -#define PADDR (0x0040) -#define PBDDR (0x0041) -#define PCDDR (0x0042) -#define PDDDR (0x0043) -#define PEDR (0x0083) -#define PEDDR (0x00c3) -#define SYSCON1 (0x0100) -#define SYSFLG1 (0x0140) -#define MEMCFG1 (0x0180) -#define MEMCFG2 (0x01c0) -#define DRFPR (0x0200) -#define LCDCON (0x02c0) -#define TC1D (0x0300) -#define TC2D (0x0340) -#define RTCDR (0x0380) -#define RTCMR (0x03c0) -#define PMPCON (0x0400) -#define CODR (0x0440) -#define UARTDR1 (0x0480) -#define UBRLCR1 (0x04c0) -#define SYNCIO (0x0500) -#define PALLSW (0x0540) -#define PALMSW (0x0580) -#define STFCLR (0x05c0) -#define HALT (0x0800) -#define STDBY (0x0840) - -#define FBADDR (0x1000) -#define SYSCON2 (0x1100) -#define SYSFLG2 (0x1140) -#define UARTDR2 (0x1480) -#define UBRLCR2 (0x14c0) -#define SS2DR (0x1500) -#define SS2POP (0x16c0) - -#define DAIR (0x2000) -#define DAIDR0 (0x2040) -#define DAIDR1 (0x2080) -#define DAIDR2 (0x20c0) -#define DAISR (0x2100) -#define SYSCON3 (0x2200) -#define LEDFLSH (0x22c0) -#define SDCONF (0x2300) -#define SDRFPR (0x2340) -#define UNIQID (0x2440) -#define DAI64FS (0x2600) -#define PLLW (0x2610) -#define PLLR (0xa5a8) -#define RANDID0 (0x2700) -#define RANDID1 (0x2704) -#define RANDID2 (0x2708) -#define RANDID3 (0x270c) - -#define LCDCON_GSEN (1 << 30) -#define LCDCON_GSMD (1 << 31) - -/* common bits: UARTDR1 / UARTDR2 */ -#define UARTDR_FRMERR (1 << 8) -#define UARTDR_PARERR (1 << 9) -#define UARTDR_OVERR (1 << 10) - -/* common bits: UBRLCR1 / UBRLCR2 */ -#define UBRLCR_BAUD_MASK ((1 << 12) - 1) -#define UBRLCR_BREAK (1 << 12) -#define UBRLCR_PRTEN (1 << 13) -#define UBRLCR_EVENPRT (1 << 14) -#define UBRLCR_XSTOP (1 << 15) -#define UBRLCR_FIFOEN (1 << 16) -#define UBRLCR_WRDLEN5 (0 << 17) -#define UBRLCR_WRDLEN6 (1 << 17) -#define UBRLCR_WRDLEN7 (2 << 17) -#define UBRLCR_WRDLEN8 (3 << 17) -#define UBRLCR_WRDLEN_MASK (3 << 17) - -#define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) -#define SYNCIO_SMCKEN (1 << 13) -#define SYNCIO_TXFRMEN (1 << 14) - -#define DAIR_RESERVED (0x0404) -#define DAIR_DAIEN (1 << 16) -#define DAIR_ECS (1 << 17) -#define DAIR_LCTM (1 << 19) -#define DAIR_LCRM (1 << 20) -#define DAIR_RCTM (1 << 21) -#define DAIR_RCRM (1 << 22) -#define DAIR_LBM (1 << 23) - -#define DAIDR2_FIFOEN (1 << 15) -#define DAIDR2_FIFOLEFT (0x0d << 16) -#define DAIDR2_FIFORIGHT (0x11 << 16) - -#define DAISR_RCTS (1 << 0) -#define DAISR_RCRS (1 << 1) -#define DAISR_LCTS (1 << 2) -#define DAISR_LCRS (1 << 3) -#define DAISR_RCTU (1 << 4) -#define DAISR_RCRO (1 << 5) -#define DAISR_LCTU (1 << 6) -#define DAISR_LCRO (1 << 7) -#define DAISR_RCNF (1 << 8) -#define DAISR_RCNE (1 << 9) -#define DAISR_LCNF (1 << 10) -#define DAISR_LCNE (1 << 11) -#define DAISR_FIFO (1 << 12) - -#define DAI64FS_I2SF64 (1 << 0) -#define DAI64FS_AUDIOCLKEN (1 << 1) -#define DAI64FS_AUDIOCLKSRC (1 << 2) -#define DAI64FS_MCLK256EN (1 << 3) -#define DAI64FS_LOOPBACK (1 << 5) - -#define SDCONF_ACTIVE (1 << 10) -#define SDCONF_CLKCTL (1 << 9) -#define SDCONF_WIDTH_4 (0 << 7) -#define SDCONF_WIDTH_8 (1 << 7) -#define SDCONF_WIDTH_16 (2 << 7) -#define SDCONF_WIDTH_32 (3 << 7) -#define SDCONF_SIZE_16 (0 << 5) -#define SDCONF_SIZE_64 (1 << 5) -#define SDCONF_SIZE_128 (2 << 5) -#define SDCONF_SIZE_256 (3 << 5) -#define SDCONF_CASLAT_2 (2) -#define SDCONF_CASLAT_3 (3) - -#define MEMCFG_BUS_WIDTH_32 (1) -#define MEMCFG_BUS_WIDTH_16 (0) -#define MEMCFG_BUS_WIDTH_8 (3) - -#define MEMCFG_SQAEN (1 << 6) -#define MEMCFG_CLKENB (1 << 7) - -#define MEMCFG_WAITSTATE_8_3 (0 << 2) -#define MEMCFG_WAITSTATE_7_3 (1 << 2) -#define MEMCFG_WAITSTATE_6_3 (2 << 2) -#define MEMCFG_WAITSTATE_5_3 (3 << 2) -#define MEMCFG_WAITSTATE_4_2 (4 << 2) -#define MEMCFG_WAITSTATE_3_2 (5 << 2) -#define MEMCFG_WAITSTATE_2_2 (6 << 2) -#define MEMCFG_WAITSTATE_1_2 (7 << 2) -#define MEMCFG_WAITSTATE_8_1 (8 << 2) -#define MEMCFG_WAITSTATE_7_1 (9 << 2) -#define MEMCFG_WAITSTATE_6_1 (10 << 2) -#define MEMCFG_WAITSTATE_5_1 (11 << 2) -#define MEMCFG_WAITSTATE_4_0 (12 << 2) -#define MEMCFG_WAITSTATE_3_0 (13 << 2) -#define MEMCFG_WAITSTATE_2_0 (14 << 2) -#define MEMCFG_WAITSTATE_1_0 (15 << 2) - -/* INTSR1 Interrupts */ -#define IRQ_CSINT (4) -#define IRQ_EINT1 (5) -#define IRQ_EINT2 (6) -#define IRQ_EINT3 (7) -#define IRQ_TC1OI (8) -#define IRQ_TC2OI (9) -#define IRQ_RTCMI (10) -#define IRQ_TINT (11) -#define IRQ_UTXINT1 (12) -#define IRQ_URXINT1 (13) -#define IRQ_UMSINT (14) -#define IRQ_SSEOTI (15) - -/* INTSR2 Interrupts */ -#define IRQ_KBDINT (16 + 0) -#define IRQ_SS2RX (16 + 1) -#define IRQ_SS2TX (16 + 2) -#define IRQ_UTXINT2 (16 + 12) -#define IRQ_URXINT2 (16 + 13) - -/* INTSR3 Interrupts */ -#define IRQ_DAIINT (32 + 0) - -#endif /* __MACH_CLPS711X_H */ diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h deleted file mode 100644 index 833129c9f..000000000 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/hardware.h - * - * This file contains the hardware definitions of the Prospector P720T. - * - * Copyright (C) 2000 Deep Blue Solutions Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __MACH_HARDWARE_H -#define __MACH_HARDWARE_H - -#include <mach/clps711x.h> - -#define CLPS711X_VIRT_BASE IOMEM(0xfeff0000) - -#ifndef __ASSEMBLY__ -#define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) -#define clps_readw(off) readw(CLPS711X_VIRT_BASE + (off)) -#define clps_readl(off) readl(CLPS711X_VIRT_BASE + (off)) -#define clps_writeb(val,off) writeb(val, CLPS711X_VIRT_BASE + (off)) -#define clps_writew(val,off) writew(val, CLPS711X_VIRT_BASE + (off)) -#define clps_writel(val,off) writel(val, CLPS711X_VIRT_BASE + (off)) -#endif - -#define CS0_PHYS_BASE (0x00000000) -#define CS1_PHYS_BASE (0x10000000) -#define CS2_PHYS_BASE (0x20000000) -#define CS3_PHYS_BASE (0x30000000) -#define CS4_PHYS_BASE (0x40000000) -#define CS5_PHYS_BASE (0x50000000) -#define CS6_PHYS_BASE (0x60000000) -#define CS7_PHYS_BASE (0x70000000) - -#define CLPS711X_SRAM_BASE CS6_PHYS_BASE -#define CLPS711X_SRAM_SIZE (48 * 1024) - -#define CLPS711X_SDRAM0_BASE (0xc0000000) -#define CLPS711X_SDRAM1_BASE (0xd0000000) - -#endif diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h deleted file mode 100644 index 5f02d06dc..000000000 --- a/arch/arm/mach-clps711x/include/mach/uncompress.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * arch/arm/mach-clps711x/include/mach/uncompress.h - * - * Copyright (C) 2000 Deep Blue Solutions Ltd - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include <mach/clps711x.h> - -#ifdef CONFIG_DEBUG_CLPS711X_UART2 -#define SYSFLGx SYSFLG2 -#define UARTDRx UARTDR2 -#else -#define SYSFLGx SYSFLG1 -#define UARTDRx UARTDR1 -#endif - -#define phys_reg(x) (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x))) - -/* - * The following code assumes the serial port has already been - * initialized by the bootloader. If you didn't setup a port in - * your bootloader then nothing will appear (which might be desired). - * - * This does not append a newline - */ -static inline void putc(int c) -{ - while (phys_reg(SYSFLGx) & SYSFLG_UTXFF) - barrier(); - phys_reg(UARTDRx) = c; -} - -static inline void flush(void) -{ - while (phys_reg(SYSFLGx) & SYSFLG_UBUSY) - barrier(); -} - -/* - * nothing to do - */ -#define arch_decomp_setup() diff --git a/arch/arm/mach-exynos/mfc.h b/arch/arm/mach-exynos/mfc.h deleted file mode 100644 index dec93cd5b..000000000 --- a/arch/arm/mach-exynos/mfc.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (C) 2013 Samsung Electronics Co.Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __MACH_EXYNOS_MFC_H -#define __MACH_EXYNOS_MFC_H __FILE__ - -int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, - int depth, void *data); - -#endif /* __MACH_EXYNOS_MFC_H */ diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c deleted file mode 100644 index 875a2bab6..000000000 --- a/arch/arm/mach-exynos/pm_domains.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Exynos Generic power domain support. - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Implementation of Exynos specific power domain control which is used in - * conjunction with runtime-pm. Support for both device-tree and non-device-tree - * based power domain support is included. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include <linux/io.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/pm_domain.h> -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/of_address.h> -#include <linux/of_platform.h> -#include <linux/sched.h> - -#define INT_LOCAL_PWR_EN 0x7 -#define MAX_CLK_PER_DOMAIN 4 - -/* - * Exynos specific wrapper around the generic power domain - */ -struct exynos_pm_domain { - void __iomem *base; - char const *name; - bool is_off; - struct generic_pm_domain pd; - struct clk *oscclk; - struct clk *clk[MAX_CLK_PER_DOMAIN]; - struct clk *pclk[MAX_CLK_PER_DOMAIN]; - struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; -}; - -static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) -{ - struct exynos_pm_domain *pd; - void __iomem *base; - u32 timeout, pwr; - char *op; - int i; - - pd = container_of(domain, struct exynos_pm_domain, pd); - base = pd->base; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_prepare_enable(pd->asb_clk[i]); - } - - /* Set oscclk before powering off a domain*/ - if (!power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - pd->pclk[i] = clk_get_parent(pd->clk[i]); - if (clk_set_parent(pd->clk[i], pd->oscclk)) - pr_err("%s: error setting oscclk as parent to clock %d\n", - pd->name, i); - } - } - - pwr = power_on ? INT_LOCAL_PWR_EN : 0; - __raw_writel(pwr, base); - - /* Wait max 1ms */ - timeout = 10; - - while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) { - if (!timeout) { - op = (power_on) ? "enable" : "disable"; - pr_err("Power domain %s %s failed\n", domain->name, op); - return -ETIMEDOUT; - } - timeout--; - cpu_relax(); - usleep_range(80, 100); - } - - /* Restore clocks after powering on a domain*/ - if (power_on) { - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->clk[i])) - break; - - if (IS_ERR(pd->pclk[i])) - continue; /* Skip on first power up */ - if (clk_set_parent(pd->clk[i], pd->pclk[i])) - pr_err("%s: error setting parent to clock%d\n", - pd->name, i); - } - } - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - if (IS_ERR(pd->asb_clk[i])) - break; - clk_disable_unprepare(pd->asb_clk[i]); - } - - return 0; -} - -static int exynos_pd_power_on(struct generic_pm_domain *domain) -{ - return exynos_pd_power(domain, true); -} - -static int exynos_pd_power_off(struct generic_pm_domain *domain) -{ - return exynos_pd_power(domain, false); -} - -static __init int exynos4_pm_init_power_domain(void) -{ - struct device_node *np; - - for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { - struct exynos_pm_domain *pd; - int on, i; - - pd = kzalloc(sizeof(*pd), GFP_KERNEL); - if (!pd) { - pr_err("%s: failed to allocate memory for domain\n", - __func__); - of_node_put(np); - return -ENOMEM; - } - pd->pd.name = kstrdup_const(strrchr(np->full_name, '/') + 1, - GFP_KERNEL); - if (!pd->pd.name) { - kfree(pd); - of_node_put(np); - return -ENOMEM; - } - - pd->name = pd->pd.name; - pd->base = of_iomap(np, 0); - if (!pd->base) { - pr_warn("%s: failed to map memory\n", __func__); - kfree_const(pd->pd.name); - kfree(pd); - continue; - } - - pd->pd.power_off = exynos_pd_power_off; - pd->pd.power_on = exynos_pd_power_on; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "asb%d", i); - pd->asb_clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->asb_clk[i])) - break; - } - - pd->oscclk = of_clk_get_by_name(np, "oscclk"); - if (IS_ERR(pd->oscclk)) - goto no_clk; - - for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { - char clk_name[8]; - - snprintf(clk_name, sizeof(clk_name), "clk%d", i); - pd->clk[i] = of_clk_get_by_name(np, clk_name); - if (IS_ERR(pd->clk[i])) - break; - /* - * Skip setting parent on first power up. - * The parent at this time may not be useful at all. - */ - pd->pclk[i] = ERR_PTR(-EINVAL); - } - - if (IS_ERR(pd->clk[0])) - clk_put(pd->oscclk); - -no_clk: - on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN; - - pm_genpd_init(&pd->pd, NULL, !on); - of_genpd_add_provider_simple(np, &pd->pd); - } - - /* Assign the child power domains to their parents */ - for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { - struct generic_pm_domain *child_domain, *parent_domain; - struct of_phandle_args args; - - args.np = np; - args.args_count = 0; - child_domain = of_genpd_get_from_provider(&args); - if (IS_ERR(child_domain)) - continue; - - if (of_parse_phandle_with_args(np, "power-domains", - "#power-domain-cells", 0, &args) != 0) - continue; - - parent_domain = of_genpd_get_from_provider(&args); - if (IS_ERR(parent_domain)) - continue; - - if (pm_genpd_add_subdomain(parent_domain, child_domain)) - pr_warn("%s failed to add subdomain: %s\n", - parent_domain->name, child_domain->name); - else - pr_info("%s has as child subdomain: %s.\n", - parent_domain->name, child_domain->name); - } - - return 0; -} -core_initcall(exynos4_pm_init_power_domain); diff --git a/arch/arm/mach-exynos/s5p-dev-mfc.c b/arch/arm/mach-exynos/s5p-dev-mfc.c deleted file mode 100644 index 8ef1f3ee4..000000000 --- a/arch/arm/mach-exynos/s5p-dev-mfc.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd - * - * Base S5P MFC resource and device definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/memblock.h> -#include <linux/ioport.h> -#include <linux/of_fdt.h> -#include <linux/of.h> - -static struct platform_device s5p_device_mfc_l; -static struct platform_device s5p_device_mfc_r; - -struct s5p_mfc_dt_meminfo { - unsigned long loff; - unsigned long lsize; - unsigned long roff; - unsigned long rsize; - char *compatible; -}; - -struct s5p_mfc_reserved_mem { - phys_addr_t base; - unsigned long size; - struct device *dev; -}; - -static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata; - - -static void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize, - phys_addr_t lbase, unsigned int lsize) -{ - int i; - - s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev; - s5p_mfc_mem[0].base = rbase; - s5p_mfc_mem[0].size = rsize; - - s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev; - s5p_mfc_mem[1].base = lbase; - s5p_mfc_mem[1].size = lsize; - - for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) { - struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i]; - if (memblock_remove(area->base, area->size)) { - printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n", - area->size, (unsigned long) area->base); - area->base = 0; - } - } -} - -int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname, - int depth, void *data) -{ - const __be32 *prop; - int len; - struct s5p_mfc_dt_meminfo mfc_mem; - - if (!data) - return 0; - - if (!of_flat_dt_is_compatible(node, data)) - return 0; - - prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len); - if (!prop || (len != 2 * sizeof(unsigned long))) - return 0; - - mfc_mem.loff = be32_to_cpu(prop[0]); - mfc_mem.lsize = be32_to_cpu(prop[1]); - - prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len); - if (!prop || (len != 2 * sizeof(unsigned long))) - return 0; - - mfc_mem.roff = be32_to_cpu(prop[0]); - mfc_mem.rsize = be32_to_cpu(prop[1]); - - s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, - mfc_mem.loff, mfc_mem.lsize); - - return 1; -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_rnga.c b/arch/arm/mach-imx/devices/platform-mxc_rnga.c deleted file mode 100644 index 851fbc8af..000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_rnga.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ -#include "../hardware.h" -#include "devices-common.h" - -struct imx_mxc_rnga_data { - resource_size_t iobase; -}; - -#define imx_mxc_rnga_data_entry_single(soc) \ - { \ - .iobase = soc ## _RNGA_BASE_ADDR, \ - } - -#ifdef CONFIG_SOC_IMX31 -static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst = - imx_mxc_rnga_data_entry_single(MX31); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -static struct platform_device *__init imx_add_mxc_rnga( - const struct imx_mxc_rnga_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device("mxc_rnga", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - -static int __init imxXX_add_mxc_rnga(void) -{ - struct platform_device *ret; - -#if defined(CONFIG_SOC_IMX31) - if (cpu_is_mx31()) - ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data); - else -#endif /* if defined(CONFIG_SOC_IMX31) */ - ret = ERR_PTR(-ENODEV); - - return PTR_ERR_OR_ZERO(ret); -} -arch_initcall(imxXX_add_mxc_rnga); diff --git a/arch/arm/mach-imx/eukrea-baseboards.h b/arch/arm/mach-imx/eukrea-baseboards.h deleted file mode 100644 index bb2c90d65..000000000 --- a/arch/arm/mach-imx/eukrea-baseboards.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2010 Eric Benard - eric@eukrea.com - * - * Based on board-pcm038.h which is : - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __MACH_EUKREA_BASEBOARDS_H__ -#define __MACH_EUKREA_BASEBOARDS_H__ - -#ifndef __ASSEMBLY__ -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls baseboard's init function. - * TODO: Add your own baseboard init function and call it from - * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init() - * - * This example here is for the development board. Refer - * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 - * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 - */ - -extern void eukrea_mbimxsd25_baseboard_init(void); -extern void eukrea_mbimxsd35_baseboard_init(void); - -#endif - -#endif /* __MACH_EUKREA_BASEBOARDS_H__ */ diff --git a/arch/arm/mach-imx/pm-imx3.c b/arch/arm/mach-imx/pm-imx3.c deleted file mode 100644 index 94c089875..000000000 --- a/arch/arm/mach-imx/pm-imx3.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include <linux/io.h> - -#include "common.h" -#include "crmregs-imx3.h" -#include "devices/devices-common.h" -#include "hardware.h" - -/* - * Set cpu low power mode before WFI instruction. This function is called - * mx3 because it can be used for mx31 and mx35. - * Currently only WAIT_MODE is supported. - */ -void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode) -{ - int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); - reg &= ~MXC_CCM_CCMR_LPM_MASK; - - switch (mode) { - case MX3_WAIT: - if (cpu_is_mx35()) - reg |= MXC_CCM_CCMR_LPM_WAIT_MX35; - imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); - break; - default: - pr_err("Unknown cpu power mode: %d\n", mode); - return; - } -} diff --git a/arch/arm/mach-uniphier/uniphier.c b/arch/arm/mach-uniphier/uniphier.c deleted file mode 100644 index 9be10efac..000000000 --- a/arch/arm/mach-uniphier/uniphier.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <asm/mach/arch.h> - -static const char * const uniphier_dt_compat[] __initconst = { - "socionext,ph1-sld3", - "socionext,ph1-ld4", - "socionext,ph1-pro4", - "socionext,ph1-sld8", - "socionext,ph1-pro5", - "socionext,proxstream2", - "socionext,ph1-ld6b", - NULL, -}; - -DT_MACHINE_START(UNIPHIER, "Socionext UniPhier") - .dt_compat = uniphier_dt_compat, -MACHINE_END diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c deleted file mode 100644 index 32d744e91..000000000 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ /dev/null @@ -1,1065 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * - * Authors: Sundar Iyer <sundar.iyer@stericsson.com> - * Bengt Jonsson <bengt.g.jonsson@stericsson.com> - * Daniel Willerud <daniel.willerud@stericsson.com> - * - * MOP500 board specific initialization for regulators - */ -#include <linux/kernel.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/ab8500.h> -#include "board-mop500-regulators.h" -#include "id.h" - -static struct regulator_consumer_supply gpio_en_3v3_consumers[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), -}; - -struct regulator_init_data gpio_en_3v3_regulator = { - .constraints = { - .name = "EN-3V3", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(gpio_en_3v3_consumers), - .consumer_supplies = gpio_en_3v3_consumers, -}; - -/* - * TPS61052 regulator - */ -static struct regulator_consumer_supply tps61052_vaudio_consumers[] = { - /* - * Boost converter supply to raise voltage on audio speaker, this - * is actually connected to three pins, VInVhfL (left amplifier) - * VInVhfR (right amplifier) and VIntDClassInt - all three must - * be connected to the same voltage. - */ - REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"), -}; - -struct regulator_init_data tps61052_regulator = { - .constraints = { - .name = "vaudio-hf", - .min_uV = 4500000, - .max_uV = 4500000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers), - .consumer_supplies = tps61052_vaudio_consumers, -}; - -static struct regulator_consumer_supply ab8500_vaux1_consumers[] = { - /* Main display, u8500 R3 uib */ - REGULATOR_SUPPLY("vddi", "mcde_disp_sony_acx424akp.0"), - /* Main display, u8500 uib and ST uib */ - REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.0"), - /* Secondary display, ST uib */ - REGULATOR_SUPPLY("vdd1", "samsung_s6d16d0.1"), - /* SFH7741 proximity sensor */ - REGULATOR_SUPPLY("vcc", "gpio-keys.0"), - /* BH1780GLS ambient light sensor */ - REGULATOR_SUPPLY("vcc", "2-0029"), - /* lsm303dlh accelerometer */ - REGULATOR_SUPPLY("vdd", "2-0018"), - /* lsm303dlhc accelerometer */ - REGULATOR_SUPPLY("vdd", "2-0019"), - /* lsm303dlh magnetometer */ - REGULATOR_SUPPLY("vdd", "2-001e"), - /* Rohm BU21013 Touchscreen devices */ - REGULATOR_SUPPLY("avdd", "3-005c"), - REGULATOR_SUPPLY("avdd", "3-005d"), - /* Synaptics RMI4 Touchscreen device */ - REGULATOR_SUPPLY("vdd", "3-004b"), - /* L3G4200D Gyroscope device */ - REGULATOR_SUPPLY("vdd", "2-0068"), - /* Ambient light sensor device */ - REGULATOR_SUPPLY("vdd", "3-0029"), - /* Pressure sensor device */ - REGULATOR_SUPPLY("vdd", "2-005c"), - /* Cypress TrueTouch Touchscreen device */ - REGULATOR_SUPPLY("vcpin", "spi8.0"), - /* Camera device */ - REGULATOR_SUPPLY("vaux12v5", "mmio_camera"), -}; - -static struct regulator_consumer_supply ab8500_vaux2_consumers[] = { - /* On-board eMMC power */ - REGULATOR_SUPPLY("vmmc", "sdi4"), - /* AB8500 audio codec */ - REGULATOR_SUPPLY("vcc-N2158", "ab8500-codec.0"), - /* AB8500 accessory detect 1 */ - REGULATOR_SUPPLY("vcc-N2158", "ab8500-acc-det.0"), - /* AB8500 Tv-out device */ - REGULATOR_SUPPLY("vcc-N2158", "mcde_tv_ab8500.4"), - /* AV8100 HDMI device */ - REGULATOR_SUPPLY("vcc-N2158", "av8100_hdmi.3"), -}; - -static struct regulator_consumer_supply ab8500_vaux3_consumers[] = { - REGULATOR_SUPPLY("v-SD-STM", "stm"), - /* External MMC slot power */ - REGULATOR_SUPPLY("vmmc", "sdi0"), -}; - -static struct regulator_consumer_supply ab8505_vaux4_consumers[] = { -}; - -static struct regulator_consumer_supply ab8505_vaux5_consumers[] = { -}; - -static struct regulator_consumer_supply ab8505_vaux6_consumers[] = { -}; - -static struct regulator_consumer_supply ab8505_vaux8_consumers[] = { - /* AB8500 audio codec device */ - REGULATOR_SUPPLY("v-aux8", NULL), -}; - -static struct regulator_consumer_supply ab8505_vadc_consumers[] = { - /* Internal general-purpose ADC */ - REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"), - /* ADC for charger */ - REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"), -}; - -static struct regulator_consumer_supply ab8500_vtvout_consumers[] = { - /* TV-out DENC supply */ - REGULATOR_SUPPLY("vtvout", "ab8500-denc.0"), - /* Internal general-purpose ADC */ - REGULATOR_SUPPLY("vddadc", "ab8500-gpadc.0"), - /* ADC for charger */ - REGULATOR_SUPPLY("vddadc", "ab8500-charger.0"), - /* AB8500 Tv-out device */ - REGULATOR_SUPPLY("vtvout", "mcde_tv_ab8500.4"), -}; - -static struct regulator_consumer_supply ab8500_vaud_consumers[] = { - /* AB8500 audio-codec main supply */ - REGULATOR_SUPPLY("vaud", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vamic1_consumers[] = { - /* AB8500 audio-codec Mic1 supply */ - REGULATOR_SUPPLY("vamic1", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vamic2_consumers[] = { - /* AB8500 audio-codec Mic2 supply */ - REGULATOR_SUPPLY("vamic2", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vdmic_consumers[] = { - /* AB8500 audio-codec DMic supply */ - REGULATOR_SUPPLY("vdmic", "ab8500-codec.0"), -}; - -static struct regulator_consumer_supply ab8500_vintcore_consumers[] = { - /* SoC core supply, no device */ - REGULATOR_SUPPLY("v-intcore", NULL), - /* USB Transceiver */ - REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"), - /* Handled by abx500 clk driver */ - REGULATOR_SUPPLY("v-intcore", "abx500-clk.0"), -}; - -static struct regulator_consumer_supply ab8505_usb_consumers[] = { - /* HS USB OTG physical interface */ - REGULATOR_SUPPLY("v-ape", NULL), -}; - -static struct regulator_consumer_supply ab8500_vana_consumers[] = { - /* DB8500 DSI */ - REGULATOR_SUPPLY("vdddsi1v2", "mcde"), - REGULATOR_SUPPLY("vdddsi1v2", "b2r2_core"), - REGULATOR_SUPPLY("vdddsi1v2", "b2r2_1_core"), - REGULATOR_SUPPLY("vdddsi1v2", "dsilink.0"), - REGULATOR_SUPPLY("vdddsi1v2", "dsilink.1"), - REGULATOR_SUPPLY("vdddsi1v2", "dsilink.2"), - /* DB8500 CSI */ - REGULATOR_SUPPLY("vddcsi1v2", "mmio_camera"), -}; - -/* ab8500 regulator register initialization */ -static struct ab8500_regulator_reg_init ab8500_reg_init[] = { - /* - * VanaRequestCtrl = HP/LP depending on VxRequest - * VextSupply1RequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0xf0, 0x00), - /* - * VextSupply2RequestCtrl = HP/LP depending on VxRequest - * VextSupply3RequestCtrl = HP/LP depending on VxRequest - * Vaux1RequestCtrl = HP/LP depending on VxRequest - * Vaux2RequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0xff, 0x00), - /* - * Vaux3RequestCtrl = HP/LP depending on VxRequest - * SwHPReq = Control through SWValid disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x07, 0x00), - /* - * VanaSysClkReq1HPValid = disabled - * Vaux1SysClkReq1HPValid = disabled - * Vaux2SysClkReq1HPValid = disabled - * Vaux3SysClkReq1HPValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00), - /* - * VextSupply1SysClkReq1HPValid = disabled - * VextSupply2SysClkReq1HPValid = disabled - * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x70, 0x40), - /* - * VanaHwHPReq1Valid = disabled - * Vaux1HwHPreq1Valid = disabled - * Vaux2HwHPReq1Valid = disabled - * Vaux3HwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0xe8, 0x00), - /* - * VextSupply1HwHPReq1Valid = disabled - * VextSupply2HwHPReq1Valid = disabled - * VextSupply3HwHPReq1Valid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x07, 0x00), - /* - * VanaHwHPReq2Valid = disabled - * Vaux1HwHPReq2Valid = disabled - * Vaux2HwHPReq2Valid = disabled - * Vaux3HwHPReq2Valid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0xe8, 0x00), - /* - * VextSupply1HwHPReq2Valid = disabled - * VextSupply2HwHPReq2Valid = disabled - * VextSupply3HwHPReq2Valid = HWReq2 controlled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x07, 0x04), - /* - * VanaSwHPReqValid = disabled - * Vaux1SwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0xa0, 0x00), - /* - * Vaux2SwHPReqValid = disabled - * Vaux3SwHPReqValid = disabled - * VextSupply1SwHPReqValid = disabled - * VextSupply2SwHPReqValid = disabled - * VextSupply3SwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x1f, 0x00), - /* - * SysClkReq2Valid1 = SysClkReq2 controlled - * SysClkReq3Valid1 = disabled - * SysClkReq4Valid1 = SysClkReq4 controlled - * SysClkReq5Valid1 = disabled - * SysClkReq6Valid1 = SysClkReq6 controlled - * SysClkReq7Valid1 = disabled - * SysClkReq8Valid1 = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0xfe, 0x2a), - /* - * SysClkReq2Valid2 = disabled - * SysClkReq3Valid2 = disabled - * SysClkReq4Valid2 = disabled - * SysClkReq5Valid2 = disabled - * SysClkReq6Valid2 = SysClkReq6 controlled - * SysClkReq7Valid2 = disabled - * SysClkReq8Valid2 = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0xfe, 0x20), - /* - * VTVoutEna = disabled - * Vintcore12Ena = disabled - * Vintcore12Sel = 1.25 V - * Vintcore12LP = inactive (HP) - * VTVoutLP = inactive (HP) - */ - INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0xfe, 0x10), - /* - * VaudioEna = disabled - * VdmicEna = disabled - * Vamic1Ena = disabled - * Vamic2Ena = disabled - */ - INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x1e, 0x00), - /* - * Vamic1_dzout = high-Z when Vamic1 is disabled - * Vamic2_dzout = high-Z when Vamic2 is disabled - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x03, 0x00), - /* - * VPll = Hw controlled (NOTE! PRCMU bits) - * VanaRegu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x0f, 0x02), - /* - * VrefDDREna = disabled - * VrefDDRSleepMode = inactive (no pulldown) - */ - INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x03, 0x00), - /* - * VextSupply1Regu = force LP - * VextSupply2Regu = force OFF - * VextSupply3Regu = force HP (-> STBB2=LP and TPS=LP) - * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 - * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 - */ - INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0xff, 0x13), - /* - * Vaux1Regu = force HP - * Vaux2Regu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x0f, 0x01), - /* - * Vaux3Regu = force off - */ - INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x03, 0x00), - /* - * Vaux1Sel = 2.8 V - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x0f, 0x0C), - /* - * Vaux2Sel = 2.9 V - */ - INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0f, 0x0d), - /* - * Vaux3Sel = 2.91 V - */ - INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07, 0x07), - /* - * VextSupply12LP = disabled (no LP) - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x01, 0x00), - /* - * Vaux1Disch = short discharge time - * Vaux2Disch = short discharge time - * Vaux3Disch = short discharge time - * Vintcore12Disch = short discharge time - * VTVoutDisch = short discharge time - * VaudioDisch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0xfc, 0x00), - /* - * VanaDisch = short discharge time - * VdmicPullDownEna = pulldown disabled when Vdmic is disabled - * VdmicDisch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x16, 0x00), -}; - -/* AB8500 regulators */ -static struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = { - /* supplies to the display/camera */ - [AB8500_LDO_AUX1] = { - .supply_regulator = "ab8500-ext-supply3", - .constraints = { - .name = "V-DISPLAY", - .min_uV = 2800000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, /* display is on at boot */ - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), - .consumer_supplies = ab8500_vaux1_consumers, - }, - /* supplies to the on-board eMMC */ - [AB8500_LDO_AUX2] = { - .supply_regulator = "ab8500-ext-supply3", - .constraints = { - .name = "V-eMMC1", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers), - .consumer_supplies = ab8500_vaux2_consumers, - }, - /* supply for VAUX3, supplies to SDcard slots */ - [AB8500_LDO_AUX3] = { - .supply_regulator = "ab8500-ext-supply3", - .constraints = { - .name = "V-MMC-SD", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers), - .consumer_supplies = ab8500_vaux3_consumers, - }, - /* supply for tvout, gpadc, TVOUT LDO */ - [AB8500_LDO_TVOUT] = { - .constraints = { - .name = "V-TVOUT", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers), - .consumer_supplies = ab8500_vtvout_consumers, - }, - /* supply for ab8500-vaudio, VAUDIO LDO */ - [AB8500_LDO_AUDIO] = { - .constraints = { - .name = "V-AUD", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers), - .consumer_supplies = ab8500_vaud_consumers, - }, - /* supply for v-anamic1 VAMic1-LDO */ - [AB8500_LDO_ANAMIC1] = { - .constraints = { - .name = "V-AMIC1", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers), - .consumer_supplies = ab8500_vamic1_consumers, - }, - /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */ - [AB8500_LDO_ANAMIC2] = { - .constraints = { - .name = "V-AMIC2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers), - .consumer_supplies = ab8500_vamic2_consumers, - }, - /* supply for v-dmic, VDMIC LDO */ - [AB8500_LDO_DMIC] = { - .constraints = { - .name = "V-DMIC", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers), - .consumer_supplies = ab8500_vdmic_consumers, - }, - /* supply for v-intcore12, VINTCORE12 LDO */ - [AB8500_LDO_INTCORE] = { - .constraints = { - .name = "V-INTCORE", - .min_uV = 1250000, - .max_uV = 1350000, - .input_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE | - REGULATOR_CHANGE_DRMS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers), - .consumer_supplies = ab8500_vintcore_consumers, - }, - /* supply for U8500 CSI-DSI, VANA LDO */ - [AB8500_LDO_ANA] = { - .constraints = { - .name = "V-CSI-DSI", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers), - .consumer_supplies = ab8500_vana_consumers, - }, -}; - -/* supply for VextSupply3 */ -static struct regulator_consumer_supply ab8500_ext_supply3_consumers[] = { - /* SIM supply for 3 V SIM cards */ - REGULATOR_SUPPLY("vinvsim", "sim-detect.0"), -}; - -/* extended configuration for VextSupply2, only used for HREFP_V20 boards */ -static struct ab8500_ext_regulator_cfg ab8500_ext_supply2 = { - .hwreq = true, -}; - -/* - * AB8500 external regulators - */ -static struct regulator_init_data ab8500_ext_regulators[] = { - /* fixed Vbat supplies VSMPS1_EXT_1V8 */ - [AB8500_EXT_SUPPLY1] = { - .constraints = { - .name = "ab8500-ext-supply1", - .min_uV = 1800000, - .max_uV = 1800000, - .initial_mode = REGULATOR_MODE_IDLE, - .boot_on = 1, - .always_on = 1, - }, - }, - /* fixed Vbat supplies VSMPS2_EXT_1V36 and VSMPS5_EXT_1V15 */ - [AB8500_EXT_SUPPLY2] = { - .constraints = { - .name = "ab8500-ext-supply2", - .min_uV = 1360000, - .max_uV = 1360000, - }, - }, - /* fixed Vbat supplies VSMPS3_EXT_3V4 and VSMPS4_EXT_3V4 */ - [AB8500_EXT_SUPPLY3] = { - .constraints = { - .name = "ab8500-ext-supply3", - .min_uV = 3400000, - .max_uV = 3400000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = - ARRAY_SIZE(ab8500_ext_supply3_consumers), - .consumer_supplies = ab8500_ext_supply3_consumers, - }, -}; - -/* ab8505 regulator register initialization */ -static struct ab8500_regulator_reg_init ab8505_reg_init[] = { - /* - * VarmRequestCtrl - * VsmpsCRequestCtrl - * VsmpsARequestCtrl - * VsmpsBRequestCtrl - */ - INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL1, 0x00, 0x00), - /* - * VsafeRequestCtrl - * VpllRequestCtrl - * VanaRequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL2, 0x30, 0x00), - /* - * Vaux1RequestCtrl = HP/LP depending on VxRequest - * Vaux2RequestCtrl = HP/LP depending on VxRequest - */ - INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL3, 0xf0, 0x00), - /* - * Vaux3RequestCtrl = HP/LP depending on VxRequest - * SwHPReq = Control through SWValid disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUREQUESTCTRL4, 0x07, 0x00), - /* - * VsmpsASysClkReq1HPValid - * VsmpsBSysClkReq1HPValid - * VsafeSysClkReq1HPValid - * VanaSysClkReq1HPValid = disabled - * VpllSysClkReq1HPValid - * Vaux1SysClkReq1HPValid = disabled - * Vaux2SysClkReq1HPValid = disabled - * Vaux3SysClkReq1HPValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID1, 0xe8, 0x00), - /* - * VsmpsCSysClkReq1HPValid - * VarmSysClkReq1HPValid - * VbbSysClkReq1HPValid - * VsmpsMSysClkReq1HPValid - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQ1HPVALID2, 0x00, 0x00), - /* - * VsmpsAHwHPReq1Valid - * VsmpsBHwHPReq1Valid - * VsafeHwHPReq1Valid - * VanaHwHPReq1Valid = disabled - * VpllHwHPReq1Valid - * Vaux1HwHPreq1Valid = disabled - * Vaux2HwHPReq1Valid = disabled - * Vaux3HwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID1, 0xe8, 0x00), - /* - * VsmpsMHwHPReq1Valid - */ - INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ1VALID2, 0x00, 0x00), - /* - * VsmpsAHwHPReq2Valid - * VsmpsBHwHPReq2Valid - * VsafeHwHPReq2Valid - * VanaHwHPReq2Valid = disabled - * VpllHwHPReq2Valid - * Vaux1HwHPReq2Valid = disabled - * Vaux2HwHPReq2Valid = disabled - * Vaux3HwHPReq2Valid = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID1, 0xe8, 0x00), - /* - * VsmpsMHwHPReq2Valid - */ - INIT_REGULATOR_REGISTER(AB8505_REGUHWHPREQ2VALID2, 0x00, 0x00), - /** - * VsmpsCSwHPReqValid - * VarmSwHPReqValid - * VsmpsASwHPReqValid - * VsmpsBSwHPReqValid - * VsafeSwHPReqValid - * VanaSwHPReqValid - * VanaSwHPReqValid = disabled - * VpllSwHPReqValid - * Vaux1SwHPReqValid = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID1, 0xa0, 0x00), - /* - * Vaux2SwHPReqValid = disabled - * Vaux3SwHPReqValid = disabled - * VsmpsMSwHPReqValid - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSWHPREQVALID2, 0x03, 0x00), - /* - * SysClkReq2Valid1 = SysClkReq2 controlled - * SysClkReq3Valid1 = disabled - * SysClkReq4Valid1 = SysClkReq4 controlled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID1, 0x0e, 0x0a), - /* - * SysClkReq2Valid2 = disabled - * SysClkReq3Valid2 = disabled - * SysClkReq4Valid2 = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUSYSCLKREQVALID2, 0x0e, 0x00), - /* - * Vaux4SwHPReqValid - * Vaux4HwHPReq2Valid - * Vaux4HwHPReq1Valid - * Vaux4SysClkReq1HPValid - */ - INIT_REGULATOR_REGISTER(AB8505_REGUVAUX4REQVALID, 0x00, 0x00), - /* - * VadcEna = disabled - * VintCore12Ena = disabled - * VintCore12Sel = 1.25 V - * VintCore12LP = inactive (HP) - * VadcLP = inactive (HP) - */ - INIT_REGULATOR_REGISTER(AB8505_REGUMISC1, 0xfe, 0x10), - /* - * VaudioEna = disabled - * Vaux8Ena = disabled - * Vamic1Ena = disabled - * Vamic2Ena = disabled - */ - INIT_REGULATOR_REGISTER(AB8505_VAUDIOSUPPLY, 0x1e, 0x00), - /* - * Vamic1_dzout = high-Z when Vamic1 is disabled - * Vamic2_dzout = high-Z when Vamic2 is disabled - */ - INIT_REGULATOR_REGISTER(AB8505_REGUCTRL1VAMIC, 0x03, 0x00), - /* - * VsmpsARegu - * VsmpsASelCtrl - * VsmpsAAutoMode - * VsmpsAPWMMode - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSAREGU, 0x00, 0x00), - /* - * VsmpsBRegu - * VsmpsBSelCtrl - * VsmpsBAutoMode - * VsmpsBPWMMode - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSBREGU, 0x00, 0x00), - /* - * VsafeRegu - * VsafeSelCtrl - * VsafeAutoMode - * VsafePWMMode - */ - INIT_REGULATOR_REGISTER(AB8505_VSAFEREGU, 0x00, 0x00), - /* - * VPll = Hw controlled (NOTE! PRCMU bits) - * VanaRegu = force off - */ - INIT_REGULATOR_REGISTER(AB8505_VPLLVANAREGU, 0x0f, 0x02), - /* - * VextSupply1Regu = force OFF (OTP_ExtSupply12LPnPolarity 1) - * VextSupply2Regu = force OFF (OTP_ExtSupply12LPnPolarity 1) - * VextSupply3Regu = force OFF (OTP_ExtSupply3LPnPolarity 0) - * ExtSupply2Bypass = ExtSupply12LPn ball is 0 when Ena is 0 - * ExtSupply3Bypass = ExtSupply3LPn ball is 0 when Ena is 0 - */ - INIT_REGULATOR_REGISTER(AB8505_EXTSUPPLYREGU, 0xff, 0x30), - /* - * Vaux1Regu = force HP - * Vaux2Regu = force off - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX12REGU, 0x0f, 0x01), - /* - * Vaux3Regu = force off - */ - INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3REGU, 0x03, 0x00), - /* - * VsmpsASel1 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL1, 0x00, 0x00), - /* - * VsmpsASel2 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL2, 0x00, 0x00), - /* - * VsmpsASel3 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSASEL3, 0x00, 0x00), - /* - * VsmpsBSel1 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL1, 0x00, 0x00), - /* - * VsmpsBSel2 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL2, 0x00, 0x00), - /* - * VsmpsBSel3 - */ - INIT_REGULATOR_REGISTER(AB8505_VSMPSBSEL3, 0x00, 0x00), - /* - * VsafeSel1 - */ - INIT_REGULATOR_REGISTER(AB8505_VSAFESEL1, 0x00, 0x00), - /* - * VsafeSel2 - */ - INIT_REGULATOR_REGISTER(AB8505_VSAFESEL2, 0x00, 0x00), - /* - * VsafeSel3 - */ - INIT_REGULATOR_REGISTER(AB8505_VSAFESEL3, 0x00, 0x00), - /* - * Vaux1Sel = 2.8 V - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX1SEL, 0x0f, 0x0C), - /* - * Vaux2Sel = 2.9 V - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX2SEL, 0x0f, 0x0d), - /* - * Vaux3Sel = 2.91 V - */ - INIT_REGULATOR_REGISTER(AB8505_VRF1VAUX3SEL, 0x07, 0x07), - /* - * Vaux4RequestCtrl - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX4REQCTRL, 0x00, 0x00), - /* - * Vaux4Regu - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX4REGU, 0x00, 0x00), - /* - * Vaux4Sel - */ - INIT_REGULATOR_REGISTER(AB8505_VAUX4SEL, 0x00, 0x00), - /* - * Vaux1Disch = short discharge time - * Vaux2Disch = short discharge time - * Vaux3Disch = short discharge time - * Vintcore12Disch = short discharge time - * VTVoutDisch = short discharge time - * VaudioDisch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH, 0xfc, 0x00), - /* - * VanaDisch = short discharge time - * Vaux8PullDownEna = pulldown disabled when Vaux8 is disabled - * Vaux8Disch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH2, 0x16, 0x00), - /* - * Vaux4Disch = short discharge time - */ - INIT_REGULATOR_REGISTER(AB8505_REGUCTRLDISCH3, 0x01, 0x00), - /* - * Vaux5Sel - * Vaux5LP - * Vaux5Ena - * Vaux5Disch - * Vaux5DisSfst - * Vaux5DisPulld - */ - INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX5, 0x00, 0x00), - /* - * Vaux6Sel - * Vaux6LP - * Vaux6Ena - * Vaux6DisPulld - */ - INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6, 0x00, 0x00), -}; - -static struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = { - /* supplies to the display/camera */ - [AB8505_LDO_AUX1] = { - .constraints = { - .name = "V-DISPLAY", - .min_uV = 2800000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, /* display is on at boot */ - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers), - .consumer_supplies = ab8500_vaux1_consumers, - }, - /* supplies to the on-board eMMC */ - [AB8505_LDO_AUX2] = { - .constraints = { - .name = "V-eMMC1", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers), - .consumer_supplies = ab8500_vaux2_consumers, - }, - /* supply for VAUX3, supplies to SDcard slots */ - [AB8505_LDO_AUX3] = { - .constraints = { - .name = "V-MMC-SD", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers), - .consumer_supplies = ab8500_vaux3_consumers, - }, - /* supply for VAUX4, supplies to NFC and standalone secure element */ - [AB8505_LDO_AUX4] = { - .constraints = { - .name = "V-NFC-SE", - .min_uV = 1100000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux4_consumers), - .consumer_supplies = ab8505_vaux4_consumers, - }, - /* supply for VAUX5, supplies to TBD */ - [AB8505_LDO_AUX5] = { - .constraints = { - .name = "V-AUX5", - .min_uV = 1050000, - .max_uV = 2790000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux5_consumers), - .consumer_supplies = ab8505_vaux5_consumers, - }, - /* supply for VAUX6, supplies to TBD */ - [AB8505_LDO_AUX6] = { - .constraints = { - .name = "V-AUX6", - .min_uV = 1050000, - .max_uV = 2790000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux6_consumers), - .consumer_supplies = ab8505_vaux6_consumers, - }, - /* supply for gpadc, ADC LDO */ - [AB8505_LDO_ADC] = { - .constraints = { - .name = "V-ADC", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_vadc_consumers), - .consumer_supplies = ab8505_vadc_consumers, - }, - /* supply for ab8500-vaudio, VAUDIO LDO */ - [AB8505_LDO_AUDIO] = { - .constraints = { - .name = "V-AUD", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vaud_consumers), - .consumer_supplies = ab8500_vaud_consumers, - }, - /* supply for v-anamic1 VAMic1-LDO */ - [AB8505_LDO_ANAMIC1] = { - .constraints = { - .name = "V-AMIC1", - .valid_ops_mask = REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers), - .consumer_supplies = ab8500_vamic1_consumers, - }, - /* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */ - [AB8505_LDO_ANAMIC2] = { - .constraints = { - .name = "V-AMIC2", - .valid_ops_mask = REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers), - .consumer_supplies = ab8500_vamic2_consumers, - }, - /* supply for v-aux8, VAUX8 LDO */ - [AB8505_LDO_AUX8] = { - .constraints = { - .name = "V-AUX8", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_vaux8_consumers), - .consumer_supplies = ab8505_vaux8_consumers, - }, - /* supply for v-intcore12, VINTCORE12 LDO */ - [AB8505_LDO_INTCORE] = { - .constraints = { - .name = "V-INTCORE", - .min_uV = 1250000, - .max_uV = 1350000, - .input_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE | - REGULATOR_CHANGE_DRMS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers), - .consumer_supplies = ab8500_vintcore_consumers, - }, - /* supply for LDO USB */ - [AB8505_LDO_USB] = { - .constraints = { - .name = "V-USB", - .valid_ops_mask = REGULATOR_CHANGE_STATUS | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_IDLE, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8505_usb_consumers), - .consumer_supplies = ab8505_usb_consumers, - }, - /* supply for U8500 CSI-DSI, VANA LDO */ - [AB8505_LDO_ANA] = { - .constraints = { - .name = "V-CSI-DSI", - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers), - .consumer_supplies = ab8500_vana_consumers, - }, -}; - -struct ab8500_regulator_platform_data ab8500_regulator_plat_data = { - .reg_init = ab8500_reg_init, - .num_reg_init = ARRAY_SIZE(ab8500_reg_init), - .regulator = ab8500_regulators, - .num_regulator = ARRAY_SIZE(ab8500_regulators), - .ext_regulator = ab8500_ext_regulators, - .num_ext_regulator = ARRAY_SIZE(ab8500_ext_regulators), -}; - -struct ab8500_regulator_platform_data ab8505_regulator_plat_data = { - .reg_init = ab8505_reg_init, - .num_reg_init = ARRAY_SIZE(ab8505_reg_init), - .regulator = ab8505_regulators, - .num_regulator = ARRAY_SIZE(ab8505_regulators), -}; - -static void ab8500_modify_reg_init(int id, u8 mask, u8 value) -{ - int i; - - if (cpu_is_u8520()) { - for (i = ARRAY_SIZE(ab8505_reg_init) - 1; i >= 0; i--) { - if (ab8505_reg_init[i].id == id) { - u8 initval = ab8505_reg_init[i].value; - initval = (initval & ~mask) | (value & mask); - ab8505_reg_init[i].value = initval; - - BUG_ON(mask & ~ab8505_reg_init[i].mask); - return; - } - } - } else { - for (i = ARRAY_SIZE(ab8500_reg_init) - 1; i >= 0; i--) { - if (ab8500_reg_init[i].id == id) { - u8 initval = ab8500_reg_init[i].value; - initval = (initval & ~mask) | (value & mask); - ab8500_reg_init[i].value = initval; - - BUG_ON(mask & ~ab8500_reg_init[i].mask); - return; - } - } - } - - BUG_ON(1); -} - -void mop500_regulator_init(void) -{ - struct regulator_init_data *regulator; - - /* - * Temporarily turn on Vaux2 on 8520 machine - */ - if (cpu_is_u8520()) { - /* Vaux2 initialized to be on */ - ab8500_modify_reg_init(AB8505_VAUX12REGU, 0x0f, 0x05); - } - - /* - * Handle AB8500_EXT_SUPPLY2 on HREFP_V20_V50 boards (do it for - * all HREFP_V20 boards) - */ - if (cpu_is_u8500v20()) { - /* VextSupply2RequestCtrl = HP/OFF depending on VxRequest */ - ab8500_modify_reg_init(AB8500_REGUREQUESTCTRL3, 0x01, 0x01); - - /* VextSupply2SysClkReq1HPValid = SysClkReq1 controlled */ - ab8500_modify_reg_init(AB8500_REGUSYSCLKREQ1HPVALID2, - 0x20, 0x20); - - /* VextSupply2 = force HP at initialization */ - ab8500_modify_reg_init(AB8500_EXTSUPPLYREGU, 0x0c, 0x04); - - /* enable VextSupply2 during platform active */ - regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2]; - regulator->constraints.always_on = 1; - - /* disable VextSupply2 in suspend */ - regulator = &ab8500_ext_regulators[AB8500_EXT_SUPPLY2]; - regulator->constraints.state_mem.disabled = 1; - regulator->constraints.state_standby.disabled = 1; - - /* enable VextSupply2 HW control (used in suspend) */ - regulator->driver_data = (void *)&ab8500_ext_supply2; - } -} diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h deleted file mode 100644 index 9bece38fe..000000000 --- a/arch/arm/mach-ux500/board-mop500-regulators.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * License Terms: GNU General Public License v2 - * - * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson - * - * MOP500 board specific initialization for regulators - */ - -#ifndef __BOARD_MOP500_REGULATORS_H -#define __BOARD_MOP500_REGULATORS_H - -#include <linux/regulator/machine.h> -#include <linux/regulator/ab8500.h> - -extern struct ab8500_regulator_platform_data ab8500_regulator_plat_data; -extern struct ab8500_regulator_platform_data ab8505_regulator_plat_data; -extern struct regulator_init_data tps61052_regulator; -extern struct regulator_init_data gpio_en_3v3_regulator; - -void mop500_regulator_init(void); - -#endif diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c deleted file mode 100644 index 780bd13cd..000000000 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2011 - * - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> - -#include <asm/outercache.h> -#include <asm/hardware/cache-l2x0.h> - -#include "db8500-regs.h" -#include "id.h" - -static int __init ux500_l2x0_unlock(void) -{ - int i; - struct device_node *np; - void __iomem *l2x0_base; - - np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); - l2x0_base = of_iomap(np, 0); - of_node_put(np); - if (!l2x0_base) - return -ENODEV; - - /* - * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions - * apparently locks both caches before jumping to the kernel. The - * l2x0 core will not touch the unlock registers if the l2x0 is - * already enabled, so we do it right here instead. The PL310 has - * 8 sets of registers, one per possible CPU. - */ - for (i = 0; i < 8; i++) { - writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + - i * L2X0_LOCKDOWN_STRIDE); - writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + - i * L2X0_LOCKDOWN_STRIDE); - } - iounmap(l2x0_base); - return 0; -} - -static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) -{ - /* - * We can't write to secure registers as we are in non-secure - * mode, until we have some SMI service available. - */ -} - -static int __init ux500_l2x0_init(void) -{ - /* Multiplatform guard */ - if (!((cpu_is_u8500_family() || cpu_is_ux540_family()))) - return -ENODEV; - - /* Unlock before init */ - ux500_l2x0_unlock(); - outer_cache.write_sec = ux500_l2c310_write_sec; - l2x0_of_init(0, ~0); - - return 0; -} -early_initcall(ux500_l2x0_init); diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c deleted file mode 100644 index 82156cbc2..000000000 --- a/arch/arm/mach-ux500/cpu.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/mfd/dbx500-prcmu.h> -#include <linux/sys_soc.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/stat.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <linux/of_address.h> -#include <linux/irq.h> -#include <linux/irqchip.h> -#include <linux/irqchip/arm-gic.h> -#include <linux/platform_data/clk-ux500.h> -#include <linux/platform_data/arm-ux500-pm.h> - -#include <asm/mach/map.h> - -#include "setup.h" - -#include "board-mop500.h" -#include "db8500-regs.h" -#include "id.h" - -void ux500_restart(enum reboot_mode mode, const char *cmd) -{ - local_irq_disable(); - local_fiq_disable(); - - prcmu_system_reset(0); -} - -/* - * FIXME: Should we set up the GPIO domain here? - * - * The problem is that we cannot put the interrupt resources into the platform - * device until the irqdomain has been added. Right now, we set the GIC interrupt - * domain from init_irq(), then load the gpio driver from - * core_initcall(nmk_gpio_init) and add the platform devices from - * arch_initcall(customize_machine). - * - * This feels fragile because it depends on the gpio device getting probed - * _before_ any device uses the gpio interrupts. -*/ -void __init ux500_init_irq(void) -{ - struct device_node *np; - struct resource r; - - irqchip_init(); - np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu"); - of_address_to_resource(np, 0, &r); - of_node_put(np); - if (!r.start) { - pr_err("could not find PRCMU base resource\n"); - return; - } - prcmu_early_init(r.start, r.end-r.start); - ux500_pm_init(r.start, r.end-r.start); - - /* - * Init clocks here so that they are available for system timer - * initialization. - */ - if (cpu_is_u8500_family()) - u8500_clk_init(); - else if (cpu_is_u9540()) - u9540_clk_init(); - else if (cpu_is_u8540()) - u8540_clk_init(); -} - -static const char * __init ux500_get_machine(void) -{ - return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber()); -} - -static const char * __init ux500_get_family(void) -{ - return kasprintf(GFP_KERNEL, "ux500"); -} - -static const char * __init ux500_get_revision(void) -{ - unsigned int rev = dbx500_revision(); - - if (rev == 0x01) - return kasprintf(GFP_KERNEL, "%s", "ED"); - else if (rev >= 0xA0) - return kasprintf(GFP_KERNEL, "%d.%d", - (rev >> 4) - 0xA + 1, rev & 0xf); - - return kasprintf(GFP_KERNEL, "%s", "Unknown"); -} - -static ssize_t ux500_get_process(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - if (dbx500_id.process == 0x00) - return sprintf(buf, "Standard\n"); - - return sprintf(buf, "%02xnm\n", dbx500_id.process); -} - -static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr, - const char *soc_id) -{ - soc_dev_attr->soc_id = soc_id; - soc_dev_attr->machine = ux500_get_machine(); - soc_dev_attr->family = ux500_get_family(); - soc_dev_attr->revision = ux500_get_revision(); -} - -static const struct device_attribute ux500_soc_attr = - __ATTR(process, S_IRUGO, ux500_get_process, NULL); - -struct device * __init ux500_soc_device_init(const char *soc_id) -{ - struct device *parent; - struct soc_device *soc_dev; - struct soc_device_attribute *soc_dev_attr; - - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return ERR_PTR(-ENOMEM); - - soc_info_populate(soc_dev_attr, soc_id); - - soc_dev = soc_device_register(soc_dev_attr); - if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr); - return NULL; - } - - parent = soc_device_to_device(soc_dev); - device_create_file(parent, &ux500_soc_attr); - - return parent; -} diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c deleted file mode 100644 index 1e81e9900..000000000 --- a/arch/arm/mach-ux500/id.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> - -#include <asm/cputype.h> -#include <asm/tlbflush.h> -#include <asm/cacheflush.h> -#include <asm/mach/map.h> - -#include "setup.h" - -#include "db8500-regs.h" -#include "id.h" - -struct dbx500_asic_id dbx500_id; - -static unsigned int __init ux500_read_asicid(phys_addr_t addr) -{ - phys_addr_t base = addr & ~0xfff; - struct map_desc desc = { - .virtual = (unsigned long)UX500_VIRT_ROM, - .pfn = __phys_to_pfn(base), - .length = SZ_16K, - .type = MT_DEVICE, - }; - - iotable_init(&desc, 1); - - /* As in devicemaps_init() */ - local_flush_tlb_all(); - flush_cache_all(); - - return readl(UX500_VIRT_ROM + (addr & 0xfff)); -} - -static void ux500_print_soc_info(unsigned int asicid) -{ - unsigned int rev = dbx500_revision(); - - pr_info("DB%4x ", dbx500_partnumber()); - - if (rev == 0x01) - pr_cont("Early Drop"); - else if (rev >= 0xA0) - pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf); - else - pr_cont("Unknown"); - - pr_cont(" [%#010x]\n", asicid); -} - -static unsigned int partnumber(unsigned int asicid) -{ - return (asicid >> 8) & 0xffff; -} - -/* - * SOC MIDR ASICID ADDRESS ASICID VALUE - * DB8500ed 0x410fc090 0x9001FFF4 0x00850001 - * DB8500v1 0x411fc091 0x9001FFF4 0x008500A0 - * DB8500v1.1 0x411fc091 0x9001FFF4 0x008500A1 - * DB8500v2 0x412fc091 0x9001DBF4 0x008500B0 - * DB8520v2.2 0x412fc091 0x9001DBF4 0x008500B2 - * DB5500v1 0x412fc091 0x9001FFF4 0x005500A0 - * DB9540 0x413fc090 0xFFFFDBF4 0x009540xx - */ - -void __init ux500_setup_id(void) -{ - unsigned int cpuid = read_cpuid_id(); - unsigned int asicid = 0; - phys_addr_t addr = 0; - - switch (cpuid) { - case 0x410fc090: /* DB8500ed */ - case 0x411fc091: /* DB8500v1 */ - addr = 0x9001FFF4; - break; - - case 0x412fc091: /* DB8520 / DB8500v2 / DB5500v1 */ - asicid = ux500_read_asicid(0x9001DBF4); - if (partnumber(asicid) == 0x8500 || - partnumber(asicid) == 0x8520) - /* DB8500v2 */ - break; - - /* DB5500v1 */ - addr = 0x9001FFF4; - break; - - case 0x413fc090: /* DB9540 */ - addr = 0xFFFFDBF4; - break; - } - - if (addr) - asicid = ux500_read_asicid(addr); - - if (!asicid) { - pr_err("Unable to identify SoC\n"); - ux500_unknown_soc(); - } - - dbx500_id.process = asicid >> 24; - dbx500_id.partnumber = partnumber(asicid); - dbx500_id.revision = asicid & 0xff; - - ux500_print_soc_info(asicid); -} diff --git a/arch/arm/mach-ux500/id.h b/arch/arm/mach-ux500/id.h deleted file mode 100644 index bcc58a8cc..000000000 --- a/arch/arm/mach-ux500/id.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - */ - -#ifndef __MACH_UX500_ID -#define __MACH_UX500_ID - -/** - * struct dbx500_asic_id - fields of the ASIC ID - * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard" - * @partnumber: hithereto 0x8500 for DB8500 - * @revision: version code in the series - */ -struct dbx500_asic_id { - u16 partnumber; - u8 revision; - u8 process; -}; - -extern struct dbx500_asic_id dbx500_id; - -static inline unsigned int __attribute_const__ dbx500_partnumber(void) -{ - return dbx500_id.partnumber; -} - -static inline unsigned int __attribute_const__ dbx500_revision(void) -{ - return dbx500_id.revision; -} - -/* - * SOCs - */ - -static inline bool __attribute_const__ cpu_is_u8500(void) -{ - return dbx500_partnumber() == 0x8500; -} - -static inline bool __attribute_const__ cpu_is_u8520(void) -{ - return dbx500_partnumber() == 0x8520; -} - -static inline bool cpu_is_u8500_family(void) -{ - return cpu_is_u8500() || cpu_is_u8520(); -} - -static inline bool __attribute_const__ cpu_is_u9540(void) -{ - return dbx500_partnumber() == 0x9540; -} - -static inline bool __attribute_const__ cpu_is_u8540(void) -{ - return dbx500_partnumber() == 0x8540; -} - -static inline bool __attribute_const__ cpu_is_u8580(void) -{ - return dbx500_partnumber() == 0x8580; -} - -static inline bool cpu_is_ux540_family(void) -{ - return cpu_is_u9540() || cpu_is_u8540() || cpu_is_u8580(); -} - -/* - * 8500 revisions - */ - -static inline bool __attribute_const__ cpu_is_u8500ed(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0x00; -} - -static inline bool __attribute_const__ cpu_is_u8500v1(void) -{ - return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u8500v10(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u8500v11(void) -{ - return cpu_is_u8500() && dbx500_revision() == 0xA1; -} - -static inline bool __attribute_const__ cpu_is_u8500v2(void) -{ - return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0); -} - -static inline bool cpu_is_u8500v20(void) -{ - return cpu_is_u8500() && (dbx500_revision() == 0xB0); -} - -static inline bool cpu_is_u8500v21(void) -{ - return cpu_is_u8500() && (dbx500_revision() == 0xB1); -} - -static inline bool cpu_is_u8500v22(void) -{ - return cpu_is_u8500() && (dbx500_revision() == 0xB2); -} - -static inline bool cpu_is_u8500v20_or_later(void) -{ - return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11()); -} - -/* - * 8540 revisions - */ - -static inline bool __attribute_const__ cpu_is_u8540v10(void) -{ - return cpu_is_u8540() && dbx500_revision() == 0xA0; -} - -static inline bool __attribute_const__ cpu_is_u8580v10(void) -{ - return cpu_is_u8580() && dbx500_revision() == 0xA0; -} - -static inline bool ux500_is_svp(void) -{ - return false; -} - -#define ux500_unknown_soc() BUG() - -#endif |