diff options
Diffstat (limited to 'drivers/pinctrl/pinctrl-rockchip.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-rockchip.c | 75 |
1 files changed, 63 insertions, 12 deletions
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a0651128e..183545a06 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -224,11 +224,6 @@ static struct regmap_config rockchip_regmap_config = { .reg_stride = 4, }; -static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) -{ - return container_of(gc, struct rockchip_pin_bank, gpio_chip); -} - static const inline struct rockchip_pin_group *pinctrl_name_to_group( const struct rockchip_pinctrl *info, const char *name) @@ -614,6 +609,40 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, } } +#define RK3228_PULL_OFFSET 0x100 + +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_PULL_OFFSET; + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3188_PULL_PINS_PER_REG); + *bit *= RK3188_PULL_BITS_PER_PIN; +} + +#define RK3228_DRV_GRF_OFFSET 0x200 + +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + *regmap = info->regmap_base; + *reg = RK3228_DRV_GRF_OFFSET; + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); + + *bit = (pin_num % RK3288_DRV_PINS_PER_REG); + *bit *= RK3288_DRV_BITS_PER_PIN; +} + #define RK3368_PULL_GRF_OFFSET 0x100 #define RK3368_PULL_PMU_OFFSET 0x10 @@ -939,7 +968,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, unsigned long flags; u32 data; - bank = gc_to_pin_bank(chip); + bank = gpiochip_get_data(chip); ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); if (ret < 0) @@ -1258,8 +1287,10 @@ static int rockchip_pinctrl_parse_functions(struct device_node *np, func->groups[i] = child->name; grp = &info->groups[grp_index++]; ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); - if (ret) + if (ret) { + of_node_put(child); return ret; + } } return 0; @@ -1304,6 +1335,7 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, ret = rockchip_pinctrl_parse_functions(child, info, i++); if (ret) { dev_err(&pdev->dev, "failed to parse function\n"); + of_node_put(child); return ret; } } @@ -1376,7 +1408,7 @@ static int rockchip_pinctrl_register(struct platform_device *pdev, static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) { - struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; unsigned long flags; u32 data; @@ -1400,7 +1432,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) */ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) { - struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); u32 data; clk_enable(bank->clk); @@ -1439,7 +1471,7 @@ static int rockchip_gpio_direction_output(struct gpio_chip *gc, */ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) { - struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); unsigned int virq; if (!bank->domain) @@ -1754,11 +1786,11 @@ static int rockchip_gpiolib_register(struct platform_device *pdev, gc = &bank->gpio_chip; gc->base = bank->pin_base; gc->ngpio = bank->nr_pins; - gc->dev = &pdev->dev; + gc->parent = &pdev->dev; gc->of_node = bank->of_node; gc->label = bank->name; - ret = gpiochip_add(gc); + ret = gpiochip_add_data(gc, bank); if (ret) { dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", gc->label, ret); @@ -2143,6 +2175,23 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pull_calc_reg = rk3188_calc_pull_reg_and_bit, }; +static struct rockchip_pin_bank rk3228_pin_banks[] = { + PIN_BANK(0, 32, "gpio0"), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; + +static struct rockchip_pin_ctrl rk3228_pin_ctrl = { + .pin_banks = rk3228_pin_banks, + .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .label = "RK3228-GPIO", + .type = RK3288, + .grf_mux_offset = 0x0, + .pull_calc_reg = rk3228_calc_pull_reg_and_bit, + .drv_calc_reg = rk3228_calc_drv_reg_and_bit, +}; + static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -2220,6 +2269,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { .data = (void *)&rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", .data = (void *)&rk3188_pin_ctrl }, + { .compatible = "rockchip,rk3228-pinctrl", + .data = (void *)&rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", .data = (void *)&rk3288_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", |