summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
blob: f64de95a8e8b78481a92f79063fa4b0df973e362 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver

Required properties:
 - compatible: value should be one of the following:
   "atmel,sama5d3-hlcdc"
 - reg: base address and size of the HLCDC device registers.
 - clock-names: the name of the 3 clocks requested by the HLCDC device.
   Should contain "periph_clk", "sys_clk" and "slow_clk".
 - clocks: should contain the 3 clocks requested by the HLCDC device.
 - interrupts: should contain the description of the HLCDC interrupt line

The HLCDC IP exposes two subdevices:
 - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
 - a Display Controller: see ../drm/atmel-hlcdc-dc.txt

Example:

	hlcdc: hlcdc@f0030000 {
		compatible = "atmel,sama5d3-hlcdc";
		reg = <0xf0030000 0x2000>;
		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
		clock-names = "periph_clk","sys_clk", "slow_clk";
		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
		status = "disabled";

		hlcdc-display-controller {
			compatible = "atmel,hlcdc-display-controller";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>;

				hlcdc_panel_output: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&panel_input>;
				};
			};
		};

		hlcdc_pwm: hlcdc-pwm {
			compatible = "atmel,hlcdc-pwm";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_lcd_pwm>;
			#pwm-cells = <3>;
		};
	};